/*- * Copyright (c) 2008, 2009, 2010 Nikolay Denev * Copyright (c) 2007, 2008 Alexander Pohoyda * Copyright (c) 1997, 1998, 1999 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD: src/sys/dev/sge/if_sgereg.h,v 1.7 2010/07/08 18:22:49 yongari Exp $ */ #ifndef _IF_SGEREG_H #define _IF_SGEREG_H /* * SiS PCI vendor ID. */ #define SIS_VENDORID 0x1039 /* * SiS PCI device IDs */ #define SIS_DEVICEID_190 0x0190 #define SIS_DEVICEID_191 0x0191 #define TX_CTL 0x00 #define TX_DESC 0x04 #define Reserved0 0x08 #define TX_NEXT 0x0C #define RX_CTL 0x10 #define RX_DESC 0x14 #define Reserved1 0x18 #define RX_NEXT 0x1C #define INTR_STATUS 0x20 #define INTR_MASK 0x24 #define INTR_CTL 0x28 #define INTR_TIMER 0x2C #define PMControl 0x30 #define Reserved2 0x34 #define ROMControl 0x38 #define ROMInterface 0x3C #define StationControl 0x40 #define GMIIControl 0x44 #define GMacIOCR 0x48 #define GMacIOCTL 0x4C #define TXMAC_CTL 0x50 #define TXMAC_TMR_RTCNT 0x54 #define RGMIIDelay 0x58 #define Reserved3 0x5C #define RXMAC_CTL 0x60 /* 1 WORD */ #define RxMacAddr 0x62 /* 6x BYTE */ #define RxHashTable 0x68 /* 1 LONG */ #define RxHashTable2 0x6C /* 1 LONG */ #define RxWakeOnLan 0x70 #define RxWakeOnLanData 0x74 #define RxMPSControl 0x78 #define RX_PKT_LOST_CTL 0x7A #define Reserved4 0x7c /* * IntrStatus Register Content */ #define INTR_RX_PKT_LOST 0x80000000 #define INTR_SOFT 0x40000000 #define INTR_TIMEOUT 0x20000000 #define INTR_PAUSE_FRAME 0x00080000 #define INTR_MAGIC_FRAME 0x00040000 #define INTR_WAKE_FRAME 0x00020000 #define INTR_LINK 0x00010000 #define INTR_RX_EMPTY 0x00000080 #define INTR_RX_DONE 0x00000040 #define INTR_TXQ1_EMPTY 0x00000020 #define INTR_TXQ1_DONE 0x00000010 #define INTR_TXQ0_EMPTY 0x00000008 #define INTR_TXQ0_DONE 0x00000004 #define INTR_RX_HALT 0x00000002 #define INTR_TX_HALT 0x00000001 #define SGE_INTRS \ (INTR_RX_EMPTY | INTR_RX_DONE | INTR_TXQ0_DONE | \ INTR_TX_HALT | INTR_RX_HALT | INTR_RX_PKT_LOST) /* * RxStatusDesc Register Content */ #define RxRES 0x00200000 #define RxCRC 0x00080000 #define RxRUNT 0x00100000 #define RxRWT 0x00400000 /* * RX control register */ #define RX_CTL_FIFO_FTHRESH_128T 0x03000000 #define RX_CTL_FIFO_FTHRESH_64T 0x02000000 #define RX_CTL_FIFO_FTHRESH_32T 0x01000000 #define RX_CTL_FIFO_FTHRESH_16T 0x00000000 #define RX_CTL_ACCEPT_MAGIC_ENB 0x00040000 #define RX_CTL_ACCEPT_PAUSE_ENB 0x00020000 #define RX_CTL_DISCARD_ERR 0x00010000 #define RX_CTL_DMA_BURST 0x00001000 #define RX_CTL_DMA_REQ_8QW 0x00000C00 #define RX_CTL_DMA_REQ_4QW 0x00000800 #define RX_CTL_DMA_REQ_2QW 0x00000400 #define RX_CTL_DMA_REQ_1QW 0x00000000 #define RX_CTL_FIFO_THRESH_128QW 0x00000300 #define RX_CTL_FIFO_THRESH_64QW 0x00000200 #define RX_CTL_FIFO_THRESH_32QW 0x00000100 #define RX_CTL_FIFO_THRESH_16QW 0x00000000 #define RX_CTL_QUEUE_ENB 0x00000010 #define RX_CTL_SUSPEND 0x00000002 #define RX_CTL_ENB 0x00000001 /* * TX control register */ #define TX_CTL_SEL_QUEUE1 0x00010000 #define TX_CTL_SEL_QUEUE0 0x00000000 #define TX_CTL_DMA_BURST 0x00001000 #define TX_CTL_DMA_REQ_8QW 0x00000C00 #define TX_CTL_DMA_REQ_4QW 0x00000800 #define TX_CTL_DMA_REQ_2QW 0x00000400 #define TX_CTL_DMA_REQ_1QW 0x00000000 #define TX_CTL_FIFO_THRESH_16QW 0x00000300 #define TX_CTL_FIFO_THRESH_12QW 0x00000200 #define TX_CTL_FIFO_THRESH_8QW 0x00000100 #define TX_CTL_FIFO_THRESH_4QW 0x00000000 #define TX_CTL_QUEUE1_ENB 0x00000020 #define TX_CTL_QUEUE0_ENB 0x00000010 #define TX_CTL_TIMER_ENB 0x00000008 #define TX_CTL_RTCNT_ENB 0x00000004 #define TX_CTL_SUSPEND 0x00000002 #define TX_CTL_ENB 0x00000001 /* * Interrupt control register */ #define INTR_CTL_TIMER_COAL_MASK 0xF0000000 #define INTR_CTL_RX_COAL_MASK 0x0F000000 #define INTR_CTL_TXQ1_COAL_MASK 0x00F00000 #define INTR_CTL_TXQ0_COAL_MASK 0x000F0000 #define INTR_CTL_SW_RESET 0x00008000 #define INTR_CTL_SRC_RD_CLR 0x00000001 #define INTR_CTL_TIMER_COAL_SHIFT 28 #define INTR_CTL_RX_COAL_SHIFT 24 #define INTR_CTL_TXQ1_COAL_SHIFT 20 #define INTR_CTL_TXQ0_COAL_SHIFT 16 /* * Controller supports time-based interrupt coalescing from 16 * predefined tables. These values apply to RX queue, TX queue 0 * and TX queue 1 interrupts. The time value is computed by the * following formula. 0 means no interrupt coalescing. * interrupt interval = 0.48us * (2 ** (n - 1)) * where n is 0 ~ 15. */ #define INTR_CTL_TX_COAL_DEFAULT 8 /* 61.44us */ #define INTR_CTL_RX_COAL_DEFAULT 8 /* 61.44us */ /* * Timer interrupt coalescing has different ranges and it's * represented by by the following formula. 0 means no * interrupt coalescing. * timer interrupt interval = 491.52us * (2 ** (n - 1)) * where n is 0 ~ 15. */ /* * TX MAC control register */ #define TXMAC_PAUSE_DEF 0x00002000 #define TXMAC_PAUSE_CRC 0x00000200 #define TXMAC_PAUSE_AUTOPAD 0x00000100 #define TXMAC_IFG2_DEF 0x00000040 #define TXMAC_IFG1_DEF 0x00000020 #define TXMAC_PAUSE_ENB 0x00000001 /* * TX MAC Timer/TryLimit register */ #define TXMAC_TIMER_MASK 0xFFFFFF0 #define TXMAC_RTCNT__MASK 0x000000F #define TXMAC_RTCNT_SHIFT 0 #define TXMAC_RTCNT_DEFAULT 8 /* * RX MAC control register */ #define RXMAC_BROADCAST 0x0800 #define RXMAC_MULTICAST 0x0400 #define RXMAC_UNICAST 0x0200 #define RXMAC_PROMISC 0x0100 #define RXMAC_STRIP_VLAN 0x0020 #define RXMAC_STRIP_FCS 0x0010 #define RXMAC_COL_DET 0x0008 #define RXMAC_PAD_ENB 0x0004 #define RXMAC_CSUM_ENB 0x0002 #define RXMAC_PAUSE_ENB 0x0001 #define SGE_RX_PAD_BYTES 10 /* Station control register. */ #define SC_LOOPBACK 0x80000000 #define SC_RGMII 0x00008000 #define SC_FDX 0x00001000 #define SC_SPEED_MASK 0x00000c00 #define SC_SPEED_10 0x00000400 #define SC_SPEED_100 0x00000800 #define SC_SPEED_1000 0x00000c00 /* * Gigabit Media Independent Interface CTL register */ #define GMI_DATA 0xffff0000 #define GMI_DATA_SHIFT 16 #define GMI_REG 0x0000f800 #define GMI_REG_SHIFT 11 #define GMI_PHY 0x000007c0 #define GMI_PHY_SHIFT 6 #define GMI_OP_WR 0x00000020 #define GMI_OP_RD 0x00000000 #define GMI_REQ 0x00000010 #define GMI_MDIO 0x00000008 #define GMI_MDDIR 0x00000004 #define GMI_MDC 0x00000002 #define GMI_MDEN 0x00000001 /* * RX packet lost indication control */ #define RX_PKT_LOST_NPKT_MASK 0xFF00 #define RX_PKT_LOST_INTR_MASK 0x00FF #define RX_PKT_LOST_INTR_THRESH 32 /* Tx descriptor command bits. */ #define TDC_OWN 0x80000000 #define TDC_INS_VLAN 0x80000000 #define TDC_INTR 0x40000000 #define TDC_THOL3 0x30000000 #define TDC_THOL2 0x20000000 #define TDC_THOL1 0x10000000 #define TDC_THOL0 0x00000000 #define TDC_LS 0x08000000 #define TDC_IP_CSUM 0x04000000 #define TDC_TCP_CSUM 0x02000000 #define TDC_UDP_CSUM 0x01000000 #define TDC_BST 0x00800000 #define TDC_EXT 0x00400000 #define TDC_DEF 0x00200000 #define TDC_BKF 0x00100000 #define TDC_CRS 0x00080000 #define TDC_COL 0x00040000 #define TDC_CRC 0x00020000 #define TDC_PAD 0x00010000 #define TDC_VLAN_MASK 0x0000FFFF #define SGE_TX_INTR_FRAMES 32 /* * TX descriptor status bits. */ #define TDS_RETRY_EXP 0x00080000 #define TDS_TIMEOUT 0x00040000 #define TDS_UNDERRUN 0x00020000 #define TDS_COLON 0x00010000 #define TDS_COLON_MASK 0x0000FFFF #define SGE_TX_ERROR(x) \ ((x) & (TDS_RETRY_EXP | TDS_TIMEOUT | TDS_UNDERRUN)) #define TX_ERR_BITS "\20" \ "\21COLON\22UNDERRUN\23TIMEOUT\24RETRY_EXP" /* Rx descriptor command bits. */ #define RDC_OWN 0x80000000 #define RDC_INTR 0x40000000 #define RDC_IP_CSUM 0x20000000 #define RDC_TCP_CSUM 0x10000000 #define RDC_UDP_CSUM 0x08000000 #define RDC_IP_CSUM_OK 0x04000000 #define RDC_TCP_CSUM_OK 0x02000000 #define RDC_UDP_CSUM_OK 0x01000000 #define RDC_WAKEUP 0x00400000 #define RDC_MAGIC 0x00200000 #define RDC_PAUSE 0x00100000 #define RDC_BCAST 0x000c0000 #define RDC_MCAST 0x00080000 #define RDC_UCAST 0x00040000 #define RDC_CRCOFF 0x00020000 #define RDC_PREADD 0x00010000 #define RDC_VLAN_MASK 0x0000FFFF /* * RX descriptor status bits */ #define RDS_VLAN 0x80000000 #define RDS_DESCS 0x3F000000 #define RDS_ABORT 0x00800000 #define RDS_SHORT 0x00400000 #define RDS_LIMIT 0x00200000 #define RDS_MIIER 0x00100000 #define RDS_OVRUN 0x00080000 #define RDS_NIBON 0x00040000 #define RDS_COLON 0x00020000 #define RDS_CRCOK 0x00010000 #define SGE_RX_ERROR(x) \ ((x) & (RDS_COLON | RDS_NIBON | RDS_OVRUN | RDS_MIIER | \ RDS_LIMIT | RDS_SHORT | RDS_ABORT)) #define SGE_RX_NSEGS(x) (((x) & RDS_DESCS) >> 24) #define RX_ERR_BITS "\20" \ "\21CRCOK\22COLON\23NIBON\24OVRUN" \ "\25MIIER\26LIMIT\27SHORT\30ABORT" \ "\40VLAN" #define RING_END 0x80000000 #define SGE_RX_BYTES(x) ((x) & 0xFFFF) #define SGE_INC(x, y) (x) = (((x) + 1) % y) /* Taken from Solaris driver */ #define EI_DATA 0xffff0000 #define EI_DATA_SHIFT 16 #define EI_OFFSET 0x0000fc00 #define EI_OFFSET_SHIFT 10 #define EI_OP 0x00000300 #define EI_OP_SHIFT 8 #define EI_OP_RD (2 << EI_OP_SHIFT) #define EI_OP_WR (1 << EI_OP_SHIFT) #define EI_REQ 0x00000080 #define EI_DO 0x00000008 #define EI_DI 0x00000004 #define EI_CLK 0x00000002 #define EI_CS 0x00000001 /* * EEPROM Addresses */ #define EEPROMSignature 0x00 #define EEPROMCLK 0x01 #define EEPROMInfo 0x02 #define EEPROMMACAddr 0x03 struct sge_desc { uint32_t sge_sts_size; uint32_t sge_cmdsts; uint32_t sge_ptr; uint32_t sge_flags; }; #define SGE_RX_RING_CNT 256 /* [8, 1024] */ #define SGE_TX_RING_CNT 256 /* [8, 8192] */ #define SGE_DESC_ALIGN 16 #define SGE_MAXTXSEGS 32 #define SGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) #define SGE_TSO_MAXSEGSIZE 4096 #define SGE_RX_BUF_ALIGN sizeof(uint64_t) #define SGE_RX_RING_SZ (SGE_RX_RING_CNT * sizeof(struct sge_desc)) #define SGE_TX_RING_SZ (SGE_TX_RING_CNT * sizeof(struct sge_desc)) #define SGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) /* * It seems sge(4) controller can send 9K jumbo frame on TX path and * can receive 65535 bytes. */ #define SGE_JUMBO_FRAMELEN (1024 * 9) #define SGE_JUMBO_MTU \ (SGE_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - \ ETHER_HDR_LEN - ETHER_CRC_LEN) #define SGE_MAX_MTU \ (ETHER_MAX_LEN + sizeof(struct ether_vlan_header) - \ ETHER_HDR_LEN - ETHER_CRC_LEN) struct sge_list_data { struct sge_desc *sge_rx_ring; struct sge_desc *sge_tx_ring; /* physical bus addresses of sge_rx_ring/sge_tx_ring */ bus_addr_t sge_rx_paddr; bus_addr_t sge_tx_paddr; }; struct sge_txdesc { struct mbuf *tx_m; bus_dmamap_t tx_dmamap; int tx_ndesc; }; struct sge_rxdesc { struct mbuf *rx_m; bus_dmamap_t rx_dmamap; }; struct sge_chain_data { bus_dma_tag_t sge_tag; bus_dma_tag_t sge_rx_tag; bus_dma_tag_t sge_tx_tag; bus_dmamap_t sge_rx_dmamap; bus_dmamap_t sge_tx_dmamap; bus_dma_tag_t sge_txmbuf_tag; bus_dma_tag_t sge_rxmbuf_tag; struct sge_txdesc sge_txdesc[SGE_TX_RING_CNT]; struct sge_rxdesc sge_rxdesc[SGE_RX_RING_CNT]; bus_dmamap_t sge_rx_spare_map; int sge_rx_cons; int sge_tx_prod; int sge_tx_cons; int sge_tx_cnt; int sge_rxlen; struct mbuf *sge_rxhead; struct mbuf *sge_rxtail; }; struct sge_type { uint16_t sge_vid; uint16_t sge_did; char *sge_name; }; struct sge_softc { struct ifnet *sge_ifp; /* interface info */ struct resource *sge_res; int sge_res_id; int sge_res_type; struct resource *sge_irq; void *sge_intrhand; device_t sge_dev; device_t sge_miibus; uint8_t sge_rev; struct sge_list_data sge_ldata; struct sge_chain_data sge_cdata; struct callout sge_stat_ch; int sge_timer; int sge_flags; #define SGE_FLAG_FASTETHER 0x0001 #define SGE_FLAG_SIS190 0x0002 #define SGE_FLAG_RGMII 0x0010 #define SGE_FLAG_JUMBO 0x0020 #define SGE_FLAG_SPEED_1000 0x2000 #define SGE_FLAG_FDX 0x4000 #define SGE_FLAG_LINK 0x8000 int sge_if_flags; uint32_t sge_rxctl; uint32_t sge_txctl; struct mtx sge_mtx; }; #define SGE_LOCK(_sc) mtx_lock(&(_sc)->sge_mtx) #define SGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sge_mtx) #define SGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sge_mtx, MA_OWNED) #define SGE_TIMEOUT 1000 #define SGE_RXCHAIN_RESET(_sc) \ do { \ (_sc)->sge_cdata.sge_rxhead = NULL; \ (_sc)->sge_cdata.sge_rxtail = NULL; \ (_sc)->sge_cdata.sge_rxlen = 0; \ } while (0) #endif /* _IF_SGEREG_H */