--- sys/dev/mii/miidevs.orig 2008-10-23 10:27:15.000000000 +0900 +++ sys/dev/mii/miidevs 2008-12-13 13:11:21.000000000 +0900 @@ -243,6 +243,7 @@ model MARVELL E1116 0x0021 Marvell 88E1116 Gigabit PHY model MARVELL E1116R 0x0024 Marvell 88E1116R Gigabit PHY model MARVELL E1118 0x0022 Marvell 88E1118 Gigabit PHY +model MARVELL E3016 0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY model xxMARVELL E1000 0x0005 Marvell 88E1000 Gigabit PHY model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY --- sys/dev/mii/e1000phy.c.orig 2008-10-28 19:30:16.000000000 +0900 +++ sys/dev/mii/e1000phy.c 2008-12-15 19:08:00.000000000 +0900 @@ -107,6 +107,7 @@ MII_PHY_DESC(MARVELL, E1116), MII_PHY_DESC(MARVELL, E1116R), MII_PHY_DESC(MARVELL, E1118), + MII_PHY_DESC(MARVELL, E3016), MII_PHY_DESC(xxMARVELL, E1000), MII_PHY_DESC(xxMARVELL, E1011), MII_PHY_DESC(xxMARVELL, E1000_3), @@ -129,7 +130,6 @@ struct mii_softc *sc; struct mii_attach_args *ma; struct mii_data *mii; - int fast_ether; esc = device_get_softc(dev); sc = &esc->mii_sc; @@ -145,7 +145,6 @@ sc->mii_anegticks = MII_ANEGTICKS_GIGE; mii->mii_instance++; - fast_ether = 0; esc->mii_model = MII_MODEL(ma->mii_id2); switch (esc->mii_model) { case MII_MODEL_MARVELL_E1011: @@ -168,53 +167,20 @@ PHY_WRITE(sc, E1000_EADR, 0); break; case MII_MODEL_MARVELL_E3082: + case MII_MODEL_MARVELL_E3016: /* 88E3082 10/100 Fast Ethernet PHY. */ sc->mii_anegticks = MII_ANEGTICKS; - fast_ether = 1; break; } e1000phy_reset(sc); + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); device_printf(dev, " "); - -#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), - E1000_CR_ISOLATE); - if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), - E1000_CR_SPEED_10); - printf("10baseT, "); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), - E1000_CR_SPEED_10 | E1000_CR_FULL_DUPLEX); - printf("10baseT-FDX, "); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), - E1000_CR_SPEED_100); - printf("100baseTX, "); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), - E1000_CR_SPEED_100 | E1000_CR_FULL_DUPLEX); - printf("100baseTX-FDX, "); - if (fast_ether == 0) { - /* - * 1000BT-simplex not supported; driver must ignore - * this entry, but it must be present in order to - * manually set full-duplex. - */ - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, - sc->mii_inst), E1000_CR_SPEED_1000); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, - sc->mii_inst), - E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX); - printf("1000baseTX-FDX, "); - } - } else { - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), - E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX); - printf("1000baseSX-FDX, "); - } - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); - printf("auto\n"); -#undef ADD + mii_phy_add_media(sc); + printf("\n"); MIIBUS_MEDIAINIT(sc->mii_dev); return (0); @@ -253,16 +219,23 @@ reg |= E1000_SCR_AUTO_X_MODE; if (esc->mii_model == MII_MODEL_MARVELL_E1116) reg &= ~E1000_SCR_POWER_DOWN; + reg |= E1000_SCR_ASSERT_CRS_ON_TX; break; case MII_MODEL_MARVELL_E3082: reg |= (E1000_SCR_AUTO_X_MODE >> 1); + reg |= E1000_SCR_ASSERT_CRS_ON_TX; + break; + case MII_MODEL_MARVELL_E3016: + reg |= (E1000_SCR_AUTO_X_MODE >> 1); + reg &= ~(E1000_SCR_EN_DETECT | + E1000_SCR_SCRAMBLER_DISABLE); + reg |= E1000_SCR_LPNP; break; default: reg &= ~E1000_SCR_AUTO_X_MODE; + reg |= E1000_SCR_ASSERT_CRS_ON_TX; break; } - /* Enable CRS on TX. */ - reg |= E1000_SCR_ASSERT_CRS_ON_TX; /* Auto correction for reversed cable polarity. */ reg &= ~E1000_SCR_POLARITY_REVERSAL; PHY_WRITE(sc, E1000_SCR, reg); @@ -283,6 +256,12 @@ case MII_MODEL_MARVELL_E1118: case MII_MODEL_MARVELL_E1149: break; + case MII_MODEL_MARVELL_E3016: + /* XXX Yukon FE+ A0 */ + reg = PHY_READ(sc, 0x1C); + reg |= 0x0001; + PHY_WRITE(sc, 0x1C, reg); + break; default: /* Force TX_CLK to 25MHz clock. */ reg = PHY_READ(sc, E1000_ESCR); @@ -339,12 +318,14 @@ speed = 0; switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_1000_T: - if (esc->mii_model == MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & + (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) return (EINVAL); speed = E1000_CR_SPEED_1000; break; case IFM_1000_SX: - if (esc->mii_model == MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & + (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) return (EINVAL); speed = E1000_CR_SPEED_1000; break; @@ -390,7 +371,8 @@ PHY_WRITE(sc, E1000_1GCR, gig | E1000_1GCR_MS_ENABLE); } else { - if (esc->mii_model != MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & + (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) PHY_WRITE(sc, E1000_1GCR, 0); } PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); @@ -452,18 +434,14 @@ e1000phy_status(struct mii_softc *sc) { struct mii_data *mii = sc->mii_pdata; - int bmsr, bmcr, esr, gsr, ssr, isr, ar, lpar; + int bmcr, bmsr, gsr, ssr, ar, lpar; mii->mii_media_status = IFM_AVALID; mii->mii_media_active = IFM_ETHER; bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); - esr = PHY_READ(sc, E1000_ESR); bmcr = PHY_READ(sc, E1000_CR); ssr = PHY_READ(sc, E1000_SSR); - isr = PHY_READ(sc, E1000_ISR); - ar = PHY_READ(sc, E1000_AR); - lpar = PHY_READ(sc, E1000_LPAR); if (bmsr & E1000_SR_LINK_STATUS) mii->mii_media_status |= IFM_ACTIVE; @@ -481,23 +459,34 @@ } if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { - if (ssr & E1000_SSR_1000MBS) + switch (ssr & E1000_SSR_SPEED) { + case E1000_SSR_1000MBS: mii->mii_media_active |= IFM_1000_T; - else if (ssr & E1000_SSR_100MBS) + break; + case E1000_SSR_100MBS: mii->mii_media_active |= IFM_100_TX; - else + break; + case E1000_SSR_10MBS: mii->mii_media_active |= IFM_10_T; + break; + default: + mii->mii_media_active |= IFM_NONE; + return; + } } else { if (ssr & E1000_SSR_1000MBS) mii->mii_media_active |= IFM_1000_SX; } + sc->mii_ticks = 0; if (ssr & E1000_SSR_DUPLEX) mii->mii_media_active |= IFM_FDX; else mii->mii_media_active |= IFM_HDX; if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + ar = PHY_READ(sc, E1000_AR); + lpar = PHY_READ(sc, E1000_LPAR); /* FLAG0==rx-flow-control FLAG1==tx-flow-control */ if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) { mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; @@ -529,11 +518,12 @@ if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) PHY_WRITE(sc, E1000_AR, E1000_AR_10T | E1000_AR_10T_FD | E1000_AR_100TX | E1000_AR_100TX_FD | - E1000_AR_PAUSE | E1000_AR_ASM_DIR); + E1000_AR_PAUSE | E1000_AR_ASM_DIR | + E1000_AR_SELECTOR_FIELD); else PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X | E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE); - if (esc->mii_model != MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) PHY_WRITE(sc, E1000_1GCR, E1000_1GCR_1000T_FD | E1000_1GCR_1000T); PHY_WRITE(sc, E1000_CR, --- sys/dev/mii/e1000phyreg.h.orig 2007-10-30 11:42:22.000000000 +0900 +++ sys/dev/mii/e1000phyreg.h 2008-12-13 13:11:21.000000000 +0900 @@ -236,6 +236,16 @@ #define E1000_SCR_TX_FIFO_DEPTH_10 0x8000 #define E1000_SCR_TX_FIFO_DEPTH_12 0xC000 +/* 88E3016 only */ +#define E1000_SCR_AUTO_MDIX 0x0020 +#define E1000_SCR_SIGDET_POLARITY 0x0040 +#define E1000_SCR_EXT_DISTANCE 0x0080 +#define E1000_SCR_FEFI_DISABLE 0x0100 +#define E1000_SCR_NLP_GEN_DISABLE 0x0800 +#define E1000_SCR_LPNP 0x1000 +#define E1000_SCR_NLP_CHK_DISABLE 0x2000 +#define E1000_SCR_EN_DETECT 0x4000 + #define E1000_SCR_EN_DETECT_MASK 0x0300 /* 88E1112 page 2 */ --- sys/dev/msk/if_msk.c.orig 2008-12-04 11:39:27.000000000 +0900 +++ sys/dev/msk/if_msk.c 2008-12-13 15:00:13.000000000 +0900 @@ -195,6 +195,8 @@ "Marvell Yukon 88E8038 Gigabit Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_8039, "Marvell Yukon 88E8039 Gigabit Ethernet" }, + { VENDORID_MARVELL, DEVICEID_MRVL_8040, + "Marvell Yukon 88E8040 Fast Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_4361, "Marvell Yukon 88E8050 Gigabit Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_4360, @@ -218,7 +220,8 @@ "Yukon EC Ultra", "Yukon Unknown", "Yukon EC", - "Yukon FE" + "Yukon FE", + "Yukon FE+" }; static int mskc_probe(device_t); @@ -480,11 +483,30 @@ return; } - if (mii->mii_media_status & IFM_ACTIVE) { - if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) + sc_if->msk_link = 0; + if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == + (IFM_AVALID | IFM_ACTIVE)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: sc_if->msk_link = 1; - } else - sc_if->msk_link = 0; + break; + case IFM_1000_T: + case IFM_1000_SX: + case IFM_1000_LX: + case IFM_1000_CX: + switch (sc_if->msk_softc->msk_hw_id) { + case CHIP_ID_YUKON_FE: + case CHIP_ID_YUKON_FE_P: + break; + default: + sc_if->msk_link = 1; + } + break; + default: + break; + } + } if (sc_if->msk_link != 0) { /* Enable Tx FIFO Underrun. */ @@ -940,12 +962,32 @@ error = EINVAL; break; } - if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && - ifr->ifr_mtu > MSK_MAX_FRAMELEN) { - error = EINVAL; - break; - } MSK_IF_LOCK(sc_if); + if (ifr->ifr_mtu > MSK_MAX_FRAMELEN) { + switch (sc_if->msk_softc->msk_hw_id) { + case CHIP_ID_YUKON_FE: + case CHIP_ID_YUKON_FE_P: + error = EINVAL; + break; + case CHIP_ID_YUKON_EC_U: + /* + * In Yukon EC Ultra, TSO & checksum offload + * is not supported for jumbo frame. + */ + ifp->if_hwassist &= + ~(MSK_CSUM_FEATURES | CSUM_TSO); + ifp->if_capenable &= + ~(IFCAP_TSO4 | IFCAP_TXCSUM); + VLAN_CAPABILITIES(ifp); + break; + default: + break; + } + } + if (error != 0) { + MSK_IF_UNLOCK(sc_if); + break; + } ifp->if_mtu = ifr->ifr_mtu; if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) msk_init_locked(sc_if); @@ -986,23 +1028,24 @@ case SIOCSIFCAP: MSK_IF_LOCK(sc_if); mask = ifr->ifr_reqcap ^ ifp->if_capenable; - if ((mask & IFCAP_TXCSUM) != 0) { + if ((mask & IFCAP_TXCSUM) != 0 && + (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_TXCSUM; - if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && - (IFCAP_TXCSUM & ifp->if_capabilities) != 0) + if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) ifp->if_hwassist |= MSK_CSUM_FEATURES; else ifp->if_hwassist &= ~MSK_CSUM_FEATURES; } - if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { + if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && + (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; msk_setvlan(sc_if, ifp); } - if ((mask & IFCAP_TSO4) != 0) { + if ((mask & IFCAP_TSO4) != 0 && + (IFCAP_TSO4 & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_TSO4; - if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && - (IFCAP_TSO4 & ifp->if_capabilities) != 0) + if ((IFCAP_TSO4 & ifp->if_capenable) != 0) ifp->if_hwassist |= CSUM_TSO; else ifp->if_hwassist &= ~CSUM_TSO; @@ -1096,7 +1139,7 @@ static void msk_phy_power(struct msk_softc *sc, int mode) { - uint32_t val; + uint32_t our, val; int i; switch (mode) { @@ -1122,16 +1165,18 @@ val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); - if (sc->msk_hw_id == CHIP_ID_YUKON_XL && - sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { - /* Deassert Low Power for 1st PHY. */ - val |= PCI_Y2_PHY1_COMA; - if (sc->msk_num_port > 1) - val |= PCI_Y2_PHY2_COMA; - } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { - uint32_t our; - - CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); + switch (sc->msk_hw_id) { + case CHIP_ID_YUKON_XL: + if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { + /* Deassert Low Power for 1st PHY. */ + val |= PCI_Y2_PHY1_COMA; + if (sc->msk_num_port > 1) + val |= PCI_Y2_PHY2_COMA; + } + break; + case CHIP_ID_YUKON_EC_U: + case CHIP_ID_YUKON_FE_P: + CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); /* Enable all clocks. */ pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); @@ -1142,6 +1187,9 @@ pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); /* Set to default value. */ pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); + break; + default: + break; } /* Release PHY from PowerDown/COMA mode. */ pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); @@ -1502,14 +1550,24 @@ ether_ifattach(ifp, eaddr); MSK_IF_LOCK(sc_if); - /* - * VLAN capability setup - * Due to Tx checksum offload hardware bugs, msk(4) manually - * computes checksum for short frames. For VLAN tagged frames - * this workaround does not work so disable checksum offload - * for VLAN interface. - */ - ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; + /* VLAN capability setup */ + if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P && + sc_if->msk_softc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { + /* + * Due to the FE+'s status writeback bug, msk(4) ignores + * status word in msk_rxeof(). So msk(4) can't take + * advantage of VLAN hardware assistance. + */ + ifp->if_capabilities |= IFCAP_VLAN_MTU; + } else { + /* + * Due to Tx checksum offload hardware bugs, msk(4) manually + * computes checksum for short frames. For VLAN tagged frames + * this workaround does not work so disable checksum offload + * for VLAN interface. + */ + ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; + } ifp->if_capenable = ifp->if_capabilities; /* @@ -1593,7 +1651,7 @@ sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; /* Bail out if chip is not recognized. */ if (sc->msk_hw_id < CHIP_ID_YUKON_XL || - sc->msk_hw_id > CHIP_ID_YUKON_FE) { + sc->msk_hw_id > CHIP_ID_YUKON_FE_P) { device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", sc->msk_hw_id, sc->msk_hw_rev); mtx_destroy(&sc->msk_mtx); @@ -1650,6 +1708,9 @@ case CHIP_ID_YUKON_FE: sc->msk_clock = 100; /* 100 Mhz */ break; + case CHIP_ID_YUKON_FE_P: + sc->msk_clock = 50; /* 50 Mhz */ + break; case CHIP_ID_YUKON_XL: sc->msk_clock = 156; /* 156 Mhz */ break; @@ -2545,7 +2606,8 @@ tcp_offset = offset = 0; m = *m_head; - if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { + if ((sc_if->msk_softc->msk_hw_id != CHIP_ID_YUKON_FE_P) && + (m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { /* * Since mbuf has no protocol specific structure information * in it we have to inspect protocol information here to @@ -2675,11 +2737,19 @@ /* Check TSO support. */ if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { - tso_mtu = offset + m->m_pkthdr.tso_segsz; + /* FE+ uses different Op code and format. */ + if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P) + tso_mtu = m->m_pkthdr.tso_segsz; + else + tso_mtu = offset + m->m_pkthdr.tso_segsz; if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; tx_le->msk_addr = htole32(tso_mtu); - tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); + if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P) + tx_le->msk_control = htole32(OP_MSS | HW_OWNER); + else + tx_le->msk_control = + htole32(OP_LRGLEN | HW_OWNER); sc_if->msk_cdata.msk_tx_cnt++; MSK_INC(prod, MSK_TX_RING_CNT); sc_if->msk_cdata.msk_tso_mtu = tso_mtu; @@ -2703,15 +2773,22 @@ } /* Check if we have to handle checksum offload. */ if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { - tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; - tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) - & 0xffff) | ((uint32_t)tcp_offset << 16)); - tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); - control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; - if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) - control |= UDPTCP; - sc_if->msk_cdata.msk_tx_cnt++; - MSK_INC(prod, MSK_TX_RING_CNT); + /* FE+ uses different checksum offload format. */ + if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P) { + control |= CALSUM; + } else { + tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; + tx_le->msk_addr = htole32(((tcp_offset + + m->m_pkthdr.csum_data) & 0xffff) | + ((uint32_t)tcp_offset << 16)); + tx_le->msk_control = htole32(1 << 16 | + (OP_TCPLISW | HW_OWNER)); + control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; + if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) + control |= UDPTCP; + sc_if->msk_cdata.msk_tx_cnt++; + MSK_INC(prod, MSK_TX_RING_CNT); + } } si = prod; @@ -2994,11 +3071,28 @@ if (len > sc_if->msk_framesize || ((status & GMR_FS_ANY_ERR) != 0) || ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { - /* Don't count flow-control packet as errors. */ - if ((status & GMR_FS_GOOD_FC) == 0) - ifp->if_ierrors++; - msk_discard_rxbuf(sc_if, cons); - break; + if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P && + sc_if->msk_softc->msk_hw_rev == + CHIP_REV_YU_FE_P_A0) { + /* + * XXX + * According to Linux, this FE+ generates + * bogus status LEs so it cannot rely on + * hardware status. Let upper layer handle + * recevied frame with minimal check. + */ + if (rxlen > MSK_MAX_FRAMELEN) { + ifp->if_ierrors++; + msk_discard_rxbuf(sc_if, cons); + } + } else { + /* Don't count flow-control packet as errors. */ + if ((status & GMR_FS_GOOD_FC) == 0) + ifp->if_ierrors++; + msk_discard_rxbuf(sc_if, cons); + break; + } + } rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; m = rxd->rx_m; @@ -3624,6 +3718,7 @@ struct mii_data *mii; uint16_t eaddr[ETHER_ADDR_LEN / 2]; uint16_t gmac; + uint32_t reg; int error, i; MSK_IF_LOCK_ASSERT(sc_if); @@ -3648,6 +3743,14 @@ ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); } + /* GPHY Control reset. */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GPHY_CTRL), GPC_RST_SET); + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GPHY_CTRL), GPC_RST_CLR); + /* GMAC Control reset. */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); + /* * Initialize GMAC first. * Without this initialization, Rx MAC did not work as expected @@ -3658,7 +3761,12 @@ * I've spent almost 2 months to fix this issue. If I have had * datasheet for Yukon II I wouldn't have encountered this. :-( */ - gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; + if (sc->msk_hw_id == CHIP_ID_YUKON_FE || + sc->msk_hw_id == CHIP_ID_YUKON_FE_P) + gmac = GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; + else + gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | + GM_GPCR_DUP_FULL; GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); /* Dummy read the Interrupt Source Register. */ @@ -3712,8 +3820,10 @@ /* Configure Rx MAC FIFO. */ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); - CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), - GMF_OPER_ON | GMF_RX_F_FL_ON); + reg = GMF_OPER_ON | GMF_RX_F_FL_ON; + if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P) + reg |= GMF_RX_OVER_ON; + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); /* Set promiscuous mode. */ msk_setpromisc(sc_if); @@ -3729,8 +3839,12 @@ * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word * due to hardware hang on receipt of pause frames. */ - CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), - RX_GMF_FL_THR_DEF + 1); + reg = RX_GMF_FL_THR_DEF + 1; + /* Another magic for Yukon FE+ - From Linux. */ + if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && + sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) + reg = 0x178; + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); /* Configure Tx MAC FIFO. */ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); @@ -3746,22 +3860,43 @@ MSK_ECU_LLPP); CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), MSK_ECU_ULPP); - if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { - /* - * Set Tx GMAC FIFO Almost Empty Threshold. - */ - CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), - MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); - /* Disable Store & Forward mode for Tx. */ - CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), - TX_JUMBO_ENA | TX_STFW_DIS); - } else { - /* Enable Store & Forward mode for Tx. */ - CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), - TX_JUMBO_DIS | TX_STFW_ENA); + switch (sc->msk_hw_id) { + case CHIP_ID_YUKON_FE_P: + if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, + TX_GMF_CTRL_T), TX_JUMBO_ENA | TX_STFW_ENA); + else + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, + TX_GMF_CTRL_T), TX_JUMBO_DIS | TX_STFW_ENA); + break; + default: + if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { + /* + * Set Tx GMAC FIFO Almost Empty Threshold. + */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, + TX_GMF_AE_THR), + MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); + /* Disable Store & Forward mode for Tx. */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, + TX_GMF_CTRL_T), TX_JUMBO_ENA | TX_STFW_DIS); + } else { + /* Enable Store & Forward mode for Tx. */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, + TX_GMF_CTRL_T), TX_STFW_ENA); + } + break; } } + if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && + sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { + /* Disable dynamic watermark - from Linux. */ + reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); + reg &= ~0x03; + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); + } + /* * Disable Force Sync bit and Alloc bit in Tx RAM interface * arbiter as we don't use Sync Tx queue. --- sys/dev/msk/if_mskreg.h.orig 2008-09-30 18:01:10.000000000 +0900 +++ sys/dev/msk/if_mskreg.h 2008-12-13 13:11:21.000000000 +0900 @@ -130,7 +130,8 @@ #define DEVICEID_MRVL_8035 0x4350 #define DEVICEID_MRVL_8036 0x4351 #define DEVICEID_MRVL_8038 0x4352 -#define DEVICEID_MRVL_8039 0X4353 +#define DEVICEID_MRVL_8039 0x4353 +#define DEVICEID_MRVL_8040 0x4354 #define DEVICEID_MRVL_4360 0x4360 #define DEVICEID_MRVL_4361 0x4361 #define DEVICEID_MRVL_4362 0x4362 @@ -828,6 +829,7 @@ #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ +#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ @@ -841,6 +843,8 @@ #define CHIP_REV_YU_EC_U_A0 1 #define CHIP_REV_YU_EC_U_A1 2 +#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ + /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ @@ -1847,6 +1851,10 @@ #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ +#define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ +#define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ +#define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ +#define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ #define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ #define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ #define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ @@ -2114,6 +2122,8 @@ #define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) #define OP_LRGLEN 0x24000000 #define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) +#define OP_MSS 0x28000000 +#define OP_MSSVLAN (OP_MSS | OP_VLAN) #define OP_BUFFER 0x40000000 #define OP_PACKET 0x41000000 #define OP_LARGESEND 0x43000000