--- sys/conf/files.orig 2008-07-31 19:11:54.000000000 +0900 +++ sys/conf/files 2008-07-31 19:11:20.000000000 +0900 @@ -695,6 +695,7 @@ dev/ixgb/if_ixgb.c optional ixgb dev/ixgb/ixgb_ee.c optional ixgb dev/ixgb/ixgb_hw.c optional ixgb +dev/jme/if_jme.c optional jme pci dev/joy/joy.c optional joy dev/joy/joy_isa.c optional joy isa dev/joy/joy_pccard.c optional joy pccard @@ -740,6 +741,8 @@ dev/mii/inphy.c optional inphy dev/mii/ip1000phy.c optional miibus dev/mii/ip1000phy.c optional ip1000phy +dev/mii/jmphy.c optional miibus +dev/mii/jmphy.c optional jmphy dev/mii/lxtphy.c optional miibus dev/mii/lxtphy.c optional lxtphy dev/mii/mii.c optional miibus --- sys/dev/mii/miidevs.orig 2007-11-05 11:09:31.000000000 +0900 +++ sys/dev/mii/miidevs 2008-07-31 19:05:51.000000000 +0900 @@ -58,6 +58,7 @@ oui ICS 0x00a0be Integrated Circuit Systems oui INTEL 0x00aa00 Intel oui JATO 0x00e083 Jato Technologies +oui JMICRON 0x001b8c JMicron Technologies oui LEVEL1 0x00207b Level 1 oui NATSEMI 0x080017 National Semiconductor oui QUALSEMI 0x006051 Quality Semiconductor @@ -160,6 +161,10 @@ /* Jato Technologies PHYs */ model JATO BASEX 0x0000 Jato 1000baseX media interface +/* JMicron Technologies PHYs */ +model JMICRON JMP211 0x0021 JMP211 10/100/1000 media interface +model JMICRON JMP202 0x0022 JMP202 10/100 media interface + /* Level 1 PHYs */ model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface --- /dev/null 2008-07-31 19:33:03.000000000 +0900 +++ sys/dev/mii/jmphy.c 2008-07-24 09:49:20.000000000 +0900 @@ -0,0 +1,379 @@ +/*- + * Copyright (c) 2008, Pyun YongHyeon + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: stable/6/sys/dev/mii/jmphy.c 180773 2008-07-24 00:50:50Z yongari $"); + +/* + * Driver for the JMicron JMP211 10/100/1000, JMP202 10/100 PHY. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "miidevs.h" + +#include + +#include "miibus_if.h" + +static int jmphy_probe(device_t); +static int jmphy_attach(device_t); +static void jmphy_reset(struct mii_softc *); +static uint16_t jmphy_anar(struct ifmedia_entry *); +static int jmphy_auto(struct mii_softc *, struct ifmedia_entry *); + +struct jmphy_softc { + struct mii_softc mii_sc; + int mii_oui; + int mii_model; + int mii_rev; +}; + +static device_method_t jmphy_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, jmphy_probe), + DEVMETHOD(device_attach, jmphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { NULL, NULL } +}; + +static devclass_t jmphy_devclass; +static driver_t jmphy_driver = { + "jmphy", + jmphy_methods, + sizeof(struct jmphy_softc) +}; + +DRIVER_MODULE(jmphy, miibus, jmphy_driver, jmphy_devclass, 0, 0); + +static int jmphy_service(struct mii_softc *, struct mii_data *, int); +static void jmphy_status(struct mii_softc *); + +static const struct mii_phydesc jmphys[] = { + MII_PHY_DESC(JMICRON, JMP202), + MII_PHY_DESC(JMICRON, JMP211), + MII_PHY_END +}; + +static int +jmphy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, jmphys, BUS_PROBE_DEFAULT)); +} + +static int +jmphy_attach(device_t dev) +{ + struct jmphy_softc *jsc; + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + jsc = device_get_softc(dev); + sc = &jsc->mii_sc; + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = device_get_softc(sc->mii_dev); + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_inst = mii->mii_instance; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = jmphy_service; + sc->mii_pdata = mii; + + mii->mii_instance++; + + jsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); + jsc->mii_model = MII_MODEL(ma->mii_id2); + jsc->mii_rev = MII_REV(ma->mii_id2); + if (bootverbose) + device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", + jsc->mii_oui, jsc->mii_model, jsc->mii_rev); + + jmphy_reset(sc); + + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return(0); +} + +static int +jmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + uint16_t bmcr; + + switch (cmd) { + case MII_POLLSTAT: + /* + * If we're not polling our PHY instance, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + break; + + case MII_MEDIACHG: + /* + * If the media indicates a different PHY instance, + * isolate ourselves. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) { + bmcr = PHY_READ(sc, MII_BMCR); + PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); + return (0); + } + + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + if (jmphy_auto(sc, ife) != EJUSTRETURN) + return (EINVAL); + break; + + case MII_TICK: + /* + * If we're not currently selected, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + /* + * Only used for autonegotiation. + */ + if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { + sc->mii_ticks = 0; + break; + } + + /* Check for link. */ + if ((PHY_READ(sc, JMPHY_SSR) & JMPHY_SSR_LINK_UP) != 0) { + sc->mii_ticks = 0; + break; + } + + /* Announce link loss right after it happens. */ + if (sc->mii_ticks++ == 0) + break; + if (sc->mii_ticks <= sc->mii_anegticks) + return (0); + + sc->mii_ticks = 0; + jmphy_auto(sc, ife); + break; + } + + /* Update the media status. */ + jmphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +jmphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + int bmcr, ssr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + ssr = PHY_READ(sc, JMPHY_SSR); + if ((ssr & JMPHY_SSR_LINK_UP) != 0) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(sc, MII_BMCR); + if ((bmcr & BMCR_ISO) != 0) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if ((bmcr & BMCR_LOOP) != 0) + mii->mii_media_active |= IFM_LOOP; + + if ((ssr & JMPHY_SSR_SPD_DPLX_RESOLVED) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + switch ((ssr & JMPHY_SSR_SPEED_MASK)) { + case JMPHY_SSR_SPEED_1000: + mii->mii_media_active |= IFM_1000_T; + /* + * jmphy(4) got a valid link so reset mii_ticks. + * Resetting mii_ticks is needed in order to + * detect link loss after auto-negotiation. + */ + sc->mii_ticks = 0; + break; + case JMPHY_SSR_SPEED_100: + mii->mii_media_active |= IFM_100_TX; + sc->mii_ticks = 0; + break; + case JMPHY_SSR_SPEED_10: + mii->mii_media_active |= IFM_10_T; + sc->mii_ticks = 0; + break; + default: + mii->mii_media_active |= IFM_NONE; + return; + } + + if ((ssr & JMPHY_SSR_DUPLEX) != 0) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + /* XXX Flow-control. */ +#ifdef notyet + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { + if ((PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0) + mii->mii_media_active |= IFM_ETH_MASTER; + } +#endif +} + +static void +jmphy_reset(struct mii_softc *sc) +{ + struct jmphy_softc *jsc; + int i; + + jsc = (struct jmphy_softc *)sc; + + /* Disable sleep mode. */ + PHY_WRITE(sc, JMPHY_TMCTL, + PHY_READ(sc, JMPHY_TMCTL) & ~JMPHY_TMCTL_SLEEP_ENB); + PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN); + + for (i = 0; i < 1000; i++) { + DELAY(1); + if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) + break; + } +} + +static uint16_t +jmphy_anar(struct ifmedia_entry *ife) +{ + uint16_t anar; + + anar = 0; + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; + break; + case IFM_1000_T: + break; + case IFM_100_TX: + anar |= ANAR_TX | ANAR_TX_FD; + break; + case IFM_10_T: + anar |= ANAR_10 | ANAR_10_FD; + break; + default: + break; + } + + return (anar); +} + +static int +jmphy_auto(struct mii_softc *sc, struct ifmedia_entry *ife) +{ + uint16_t anar, bmcr, gig; + + gig = 0; + bmcr = PHY_READ(sc, MII_BMCR); + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; + break; + case IFM_1000_T: + gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; + break; + case IFM_100_TX: + case IFM_10_T: + break; + case IFM_NONE: + PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO | BMCR_PDOWN); + return (EJUSTRETURN); + default: + return (EINVAL); + } + + if ((ife->ifm_media & IFM_LOOP) != 0) + bmcr |= BMCR_LOOP; + + anar = jmphy_anar(ife); + /* XXX Always advertise pause capability. */ + anar |= (3 << 10); + + if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) { +#ifdef notyet + struct mii_data *mii; + + mii = sc->mii_pdata; + if ((mii->mii_media.ifm_media & IFM_ETH_MASTER) != 0) + gig |= GTCR_MAN_MS | GTCR_MAN_ADV; +#endif + PHY_WRITE(sc, MII_100T2CR, gig); + } + PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA); + PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG); + + return (EJUSTRETURN); +} --- /dev/null 2008-07-31 19:33:03.000000000 +0900 +++ sys/dev/mii/jmphyreg.h 2008-07-24 09:49:20.000000000 +0900 @@ -0,0 +1,108 @@ +/*- + * Copyright (c) 2008, Pyun YongHyeon + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: stable/6/sys/dev/mii/jmphyreg.h 180773 2008-07-24 00:50:50Z yongari $ + */ + +#ifndef _DEV_MII_JMPHYREG_H_ +#define _DEV_MII_JMPHYREG_H_ + +/* + * Registers for the JMicron JMC250 Gigabit PHY. + */ + +/* PHY specific status register. */ +#define JMPHY_SSR 0x11 +#define JMPHY_SSR_SPEED_1000 0x8000 +#define JMPHY_SSR_SPEED_100 0x4000 +#define JMPHY_SSR_SPEED_10 0x0000 +#define JMPHY_SSR_SPEED_MASK 0xC000 +#define JMPHY_SSR_DUPLEX 0x2000 +#define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800 +#define JMPHY_SSR_LINK_UP 0x0400 +#define JMPHY_SSR_MDI_XOVER 0x0040 +#define JMPHY_SSR_INV_POLARITY 0x0002 + +/* PHY specific cable length status register. */ +#define JMPHY_SCL 0x17 +#define JMPHY_SCL_CHAN_D_MASK 0xF000 +#define JMPHY_SCL_CHAN_C_MASK 0x0F00 +#define JMPHY_SCL_CHAN_B_MASK 0x00F0 +#define JMPHY_SCL_CHAN_A_MASK 0x000F +#define JMPHY_SCL_LEN_35 0 +#define JMPHY_SCL_LEN_40 1 +#define JMPHY_SCL_LEN_50 2 +#define JMPHY_SCL_LEN_60 3 +#define JMPHY_SCL_LEN_70 4 +#define JMPHY_SCL_LEN_80 5 +#define JMPHY_SCL_LEN_90 6 +#define JMPHY_SCL_LEN_100 7 +#define JMPHY_SCL_LEN_110 8 +#define JMPHY_SCL_LEN_120 9 +#define JMPHY_SCL_LEN_130 10 +#define JMPHY_SCL_LEN_140 11 +#define JMPHY_SCL_LEN_150 12 +#define JMPHY_SCL_LEN_160 13 +#define JMPHY_SCL_LEN_170 14 +#define JMPHY_SCL_RSVD 15 + +/* PHY specific LED control register 1. */ +#define JMPHY_LED_CTL1 0x18 +#define JMPHY_LED_BLINK_42MS 0x0000 +#define JMPHY_LED_BLINK_84MS 0x2000 +#define JMPHY_LED_BLINK_170MS 0x4000 +#define JMPHY_LED_BLINK_340MS 0x6000 +#define JMPHY_LED_BLINK_670MS 0x8000 +#define JMPHY_LED_BLINK_MASK 0xE000 +#define JMPHY_LED_FLP_GAP_MASK 0x1F00 +#define JMPHY_LED_FLP_GAP_DEFULT 0x1000 +#define JMPHY_LED2_POLARITY_MASK 0x0030 +#define JMPHY_LED1_POLARITY_MASK 0x000C +#define JMPHY_LED0_POLARITY_MASK 0x0003 +#define JMPHY_LED_ON_LO_OFF_HI 0 +#define JMPHY_LED_ON_HI_OFF_HI 1 +#define JMPHY_LED_ON_LO_OFF_TS 2 +#define JMPHY_LED_ON_HI_OFF_TS 3 + +/* PHY specific LED control register 2. */ +#define JMPHY_LED_CTL2 0x19 +#define JMPHY_LED_NO_STRETCH 0x0000 +#define JMPHY_LED_STRETCH_42MS 0x2000 +#define JMPHY_LED_STRETCH_84MS 0x4000 +#define JMPHY_LED_STRETCH_170MS 0x6000 +#define JMPHY_LED_STRETCH_340MS 0x8000 +#define JMPHY_LED_STRETCH_670MS 0xB000 +#define JMPHY_LED_STRETCH_1300MS 0xC000 +#define JMPHY_LED_STRETCH_2700MS 0xE000 +#define JMPHY_LED2_MODE_MASK 0x0F00 +#define JMPHY_LED1_MODE_MASK 0x00F0 +#define JMPHY_LED0_MODE_MASK 0x000F + +/* PHY specific test mode control register. */ +#define JMPHY_TMCTL 0x1A +#define JMPHY_TMCTL_SLEEP_ENB 0x1000 + +#endif /* _DEV_MII_JMPHYREG_H_ */ --- /dev/null 2008-07-31 19:33:03.000000000 +0900 +++ sys/dev/jme/if_jme.c 2008-07-31 10:20:52.000000000 +0900 @@ -0,0 +1,3146 @@ +/*- + * Copyright (c) 2008, Pyun YongHyeon + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: stable/6/sys/dev/jme/if_jme.c 181038 2008-07-31 01:22:24Z yongari $"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +/* "device miibus" required. See GENERIC if you get errors here. */ +#include "miibus_if.h" + +#ifndef IFCAP_WOL +#define IFCAP_WOL 0 +#define IFCAP_WOL_MAGIC 0 +#endif +#ifndef IFCAP_TSO4 +#define IFCAP_TSO4 0 +#define CSUM_TSO 0 +#endif +#ifndef IFCAP_VLAN_HWCSUM +#define IFCAP_VLAN_HWCSUM 0 +#endif +#ifndef VLAN_CAPABILITIES +#define VLAN_CAPABILITIES(x) +#endif +#if __FreeBSD_version < 700000 +#define FILTER_STRAY +#define FILTER_HANDLED +#define m_collapse(x, y, z) m_defrag(x, y) +#endif + +/* Define the following to disable printing Rx errors. */ +#undef JME_SHOW_ERRORS + +#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) + +MODULE_DEPEND(jme, pci, 1, 1, 1); +MODULE_DEPEND(jme, ether, 1, 1, 1); +MODULE_DEPEND(jme, miibus, 1, 1, 1); + +/* Tunables. */ +static int msi_disable = 0; +static int msix_disable = 0; +TUNABLE_INT("hw.jme.msi_disable", &msi_disable); +TUNABLE_INT("hw.jme.msix_disable", &msix_disable); + +/* + * Devices supported by this driver. + */ +static struct jme_dev { + uint16_t jme_vendorid; + uint16_t jme_deviceid; + const char *jme_name; +} jme_devs[] = { + { VENDORID_JMICRON, DEVICEID_JMC250, + "JMicron Inc, JMC250 Gigabit Ethernet" }, + { VENDORID_JMICRON, DEVICEID_JMC260, + "JMicron Inc, JMC260 Fast Ethernet" }, +}; + +static int jme_miibus_readreg(device_t, int, int); +static int jme_miibus_writereg(device_t, int, int, int); +static void jme_miibus_statchg(device_t); +static void jme_mediastatus(struct ifnet *, struct ifmediareq *); +static int jme_mediachange(struct ifnet *); +static int jme_probe(device_t); +static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); +static int jme_eeprom_macaddr(struct jme_softc *); +static void jme_reg_macaddr(struct jme_softc *); +static void jme_map_intr_vector(struct jme_softc *); +static int jme_attach(device_t); +static int jme_detach(device_t); +static void jme_sysctl_node(struct jme_softc *); +static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); +static int jme_dma_alloc(struct jme_softc *); +static void jme_dma_free(struct jme_softc *); +static int jme_shutdown(device_t); +static void jme_setlinkspeed(struct jme_softc *); +static void jme_setwol(struct jme_softc *); +static int jme_suspend(device_t); +static int jme_resume(device_t); +static int jme_encap(struct jme_softc *, struct mbuf **); +static void jme_tx_task(void *, int); +static void jme_start(struct ifnet *); +static void jme_watchdog(struct jme_softc *); +static int jme_ioctl(struct ifnet *, u_long, caddr_t); +static void jme_mac_config(struct jme_softc *); +static void jme_link_task(void *, int); +#if __FreeBSD_version < 700000 +static void jme_intr(void *); +#else +static int jme_intr(void *); +#endif +static void jme_int_task(void *, int); +static void jme_txeof(struct jme_softc *); +static __inline void jme_discard_rxbuf(struct jme_softc *, int); +static void jme_rxeof(struct jme_softc *); +static int jme_rxintr(struct jme_softc *, int); +static void jme_tick(void *); +static void jme_reset(struct jme_softc *); +static void jme_init(void *); +static void jme_init_locked(struct jme_softc *); +static void jme_stop(struct jme_softc *); +static void jme_stop_tx(struct jme_softc *); +static void jme_stop_rx(struct jme_softc *); +static int jme_init_rx_ring(struct jme_softc *); +static void jme_init_tx_ring(struct jme_softc *); +static void jme_init_ssb(struct jme_softc *); +static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); +static void jme_set_vlan(struct jme_softc *); +static void jme_set_filter(struct jme_softc *); +static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); +static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); +static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); +static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); +static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); +static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); + + +static device_method_t jme_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, jme_probe), + DEVMETHOD(device_attach, jme_attach), + DEVMETHOD(device_detach, jme_detach), + DEVMETHOD(device_shutdown, jme_shutdown), + DEVMETHOD(device_suspend, jme_suspend), + DEVMETHOD(device_resume, jme_resume), + + /* MII interface. */ + DEVMETHOD(miibus_readreg, jme_miibus_readreg), + DEVMETHOD(miibus_writereg, jme_miibus_writereg), + DEVMETHOD(miibus_statchg, jme_miibus_statchg), + + { NULL, NULL } +}; + +static driver_t jme_driver = { + "jme", + jme_methods, + sizeof(struct jme_softc) +}; + +static devclass_t jme_devclass; + +DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0); +DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0); + +static struct resource_spec jme_res_spec_mem[] = { + { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, + { -1, 0, 0 } +}; + +static struct resource_spec jme_irq_spec_legacy[] = { + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0, 0 } +}; + +static struct resource_spec jme_irq_spec_msi[] = { + { SYS_RES_IRQ, 1, RF_ACTIVE }, + { SYS_RES_IRQ, 2, RF_ACTIVE }, + { SYS_RES_IRQ, 3, RF_ACTIVE }, + { SYS_RES_IRQ, 4, RF_ACTIVE }, + { SYS_RES_IRQ, 5, RF_ACTIVE }, + { SYS_RES_IRQ, 6, RF_ACTIVE }, + { SYS_RES_IRQ, 7, RF_ACTIVE }, + { SYS_RES_IRQ, 8, RF_ACTIVE }, + { -1, 0, 0 } +}; + +/* + * Read a PHY register on the MII of the JMC250. + */ +static int +jme_miibus_readreg(device_t dev, int phy, int reg) +{ + struct jme_softc *sc; + uint32_t val; + int i; + + sc = device_get_softc(dev); + + /* For FPGA version, PHY address 0 should be ignored. */ + if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { + if (phy == 0) + return (0); + } else { + if (sc->jme_phyaddr != phy) + return (0); + } + + CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | + SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); + for (i = JME_PHY_TIMEOUT; i > 0; i--) { + DELAY(1); + if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) + break; + } + + if (i == 0) { + device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); + return (0); + } + + return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); +} + +/* + * Write a PHY register on the MII of the JMC250. + */ +static int +jme_miibus_writereg(device_t dev, int phy, int reg, int val) +{ + struct jme_softc *sc; + int i; + + sc = device_get_softc(dev); + + /* For FPGA version, PHY address 0 should be ignored. */ + if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { + if (phy == 0) + return (0); + } else { + if (sc->jme_phyaddr != phy) + return (0); + } + + CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | + ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | + SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); + for (i = JME_PHY_TIMEOUT; i > 0; i--) { + DELAY(1); + if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) + break; + } + + if (i == 0) + device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); + + return (0); +} + +/* + * Callback from MII layer when media changes. + */ +static void +jme_miibus_statchg(device_t dev) +{ + struct jme_softc *sc; + + sc = device_get_softc(dev); + taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); +} + +/* + * Get the current interface media status. + */ +static void +jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct jme_softc *sc; + struct mii_data *mii; + + sc = ifp->if_softc; + JME_LOCK(sc); + mii = device_get_softc(sc->jme_miibus); + + mii_pollstat(mii); + ifmr->ifm_status = mii->mii_media_status; + ifmr->ifm_active = mii->mii_media_active; + JME_UNLOCK(sc); +} + +/* + * Set hardware to newly-selected media. + */ +static int +jme_mediachange(struct ifnet *ifp) +{ + struct jme_softc *sc; + struct mii_data *mii; + struct mii_softc *miisc; + int error; + + sc = ifp->if_softc; + JME_LOCK(sc); + mii = device_get_softc(sc->jme_miibus); + if (mii->mii_instance != 0) { + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + mii_phy_reset(miisc); + } + error = mii_mediachg(mii); + JME_UNLOCK(sc); + + return (error); +} + +static int +jme_probe(device_t dev) +{ + struct jme_dev *sp; + int i; + uint16_t vendor, devid; + + vendor = pci_get_vendor(dev); + devid = pci_get_device(dev); + sp = jme_devs; + for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]); + i++, sp++) { + if (vendor == sp->jme_vendorid && + devid == sp->jme_deviceid) { + device_set_desc(dev, sp->jme_name); + return (BUS_PROBE_DEFAULT); + } + } + + return (ENXIO); +} + +static int +jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) +{ + uint32_t reg; + int i; + + *val = 0; + for (i = JME_TIMEOUT; i > 0; i--) { + reg = CSR_READ_4(sc, JME_SMBCSR); + if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) + break; + DELAY(1); + } + + if (i == 0) { + device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); + return (ETIMEDOUT); + } + + reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; + CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); + for (i = JME_TIMEOUT; i > 0; i--) { + DELAY(1); + reg = CSR_READ_4(sc, JME_SMBINTF); + if ((reg & SMBINTF_CMD_TRIGGER) == 0) + break; + } + + if (i == 0) { + device_printf(sc->jme_dev, "EEPROM read timeout!\n"); + return (ETIMEDOUT); + } + + reg = CSR_READ_4(sc, JME_SMBINTF); + *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; + + return (0); +} + +static int +jme_eeprom_macaddr(struct jme_softc *sc) +{ + uint8_t eaddr[ETHER_ADDR_LEN]; + uint8_t fup, reg, val; + uint32_t offset; + int match; + + offset = 0; + if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || + fup != JME_EEPROM_SIG0) + return (ENOENT); + if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || + fup != JME_EEPROM_SIG1) + return (ENOENT); + match = 0; + do { + if (jme_eeprom_read_byte(sc, offset, &fup) != 0) + break; + /* Check for the end of EEPROM descriptor. */ + if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) + break; + if ((uint8_t)JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, + JME_EEPROM_PAGE_BAR1) == fup) { + if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) + break; + if (reg >= JME_PAR0 && + reg < JME_PAR0 + ETHER_ADDR_LEN) { + if (jme_eeprom_read_byte(sc, offset + 2, + &val) != 0) + break; + eaddr[reg - JME_PAR0] = val; + match++; + } + } + /* Try next eeprom descriptor. */ + offset += JME_EEPROM_DESC_BYTES; + } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); + + if (match == ETHER_ADDR_LEN) { + bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); + return (0); + } + + return (ENOENT); +} + +static void +jme_reg_macaddr(struct jme_softc *sc) +{ + uint32_t par0, par1; + + /* Read station address. */ + par0 = CSR_READ_4(sc, JME_PAR0); + par1 = CSR_READ_4(sc, JME_PAR1); + par1 &= 0xFFFF; + if ((par0 == 0 && par1 == 0) || + (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { + device_printf(sc->jme_dev, + "generating fake ethernet address.\n"); + par0 = arc4random(); + /* Set OUI to JMicron. */ + sc->jme_eaddr[0] = 0x00; + sc->jme_eaddr[1] = 0x1B; + sc->jme_eaddr[2] = 0x8C; + sc->jme_eaddr[3] = (par0 >> 16) & 0xff; + sc->jme_eaddr[4] = (par0 >> 8) & 0xff; + sc->jme_eaddr[5] = par0 & 0xff; + } else { + sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; + sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; + sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; + sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; + sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; + sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; + } +} + +static void +jme_map_intr_vector(struct jme_softc *sc) +{ + uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; + + bzero(map, sizeof(map)); + + /* Map Tx interrupts source to MSI/MSIX vector 2. */ + map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = + MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); + map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); + map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= + MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); + + /* Map Rx interrupts source to MSI/MSIX vector 1. */ + map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); + map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); + map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); + map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); + map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); + map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); + map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); + map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); + map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); + map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); + map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); + map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); + map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); + map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); + map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); + map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = + MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); + + /* Map all other interrupts source to MSI/MSIX vector 0. */ + CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); + CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); + CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); + CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); +} + +static int +jme_attach(device_t dev) +{ + struct jme_softc *sc; + struct ifnet *ifp; + struct mii_softc *miisc; + struct mii_data *mii; + uint32_t reg; + uint16_t burst; + int error, i, msic, msixc, pmc; + + error = 0; + sc = device_get_softc(dev); + sc->jme_dev = dev; + + mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF); + callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); + TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); + TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); + + /* + * Map the device. JMC250 supports both memory mapped and I/O + * register space access. Because I/O register access should + * use different BARs to access registers it's waste of time + * to use I/O register spce access. JMC250 uses 16K to map + * entire memory space. + */ + pci_enable_busmaster(dev); + sc->jme_res_spec = jme_res_spec_mem; + sc->jme_irq_spec = jme_irq_spec_legacy; + error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); + if (error != 0) { + device_printf(dev, "cannot allocate memory resources.\n"); + goto fail; + } + + /* Allocate IRQ resources. */ + msixc = pci_msix_count(dev); + msic = pci_msi_count(dev); + if (bootverbose) { + device_printf(dev, "MSIX count : %d\n", msixc); + device_printf(dev, "MSI count : %d\n", msic); + } + + /* Prefer MSIX over MSI. */ + if (msix_disable == 0 || msi_disable == 0) { + if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES && + pci_alloc_msix(dev, &msixc) == 0) { + if (msic == JME_MSIX_MESSAGES) { + device_printf(dev, "Using %d MSIX messages.\n", + msixc); + sc->jme_flags |= JME_FLAG_MSIX; + sc->jme_irq_spec = jme_irq_spec_msi; + } else + pci_release_msi(dev); + } + if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && + msic == JME_MSI_MESSAGES && + pci_alloc_msi(dev, &msic) == 0) { + if (msic == JME_MSI_MESSAGES) { + device_printf(dev, "Using %d MSI messages.\n", + msic); + sc->jme_flags |= JME_FLAG_MSI; + sc->jme_irq_spec = jme_irq_spec_msi; + } else + pci_release_msi(dev); + } + /* Map interrupt vector 0, 1 and 2. */ + if ((sc->jme_flags & JME_FLAG_MSI) != 0 || + (sc->jme_flags & JME_FLAG_MSIX) != 0) + jme_map_intr_vector(sc); + } + + error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); + if (error != 0) { + device_printf(dev, "cannot allocate IRQ resources.\n"); + goto fail; + } + + sc->jme_rev = pci_get_revid(dev); + if (sc->jme_rev == DEVICEREVID_JMC260) { + sc->jme_flags |= JME_FLAG_FASTETH; + sc->jme_flags |= JME_FLAG_NOJUMBO; + } + reg = CSR_READ_4(sc, JME_CHIPMODE); + sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; + if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != + CHIPMODE_NOT_FPGA) + sc->jme_flags |= JME_FLAG_FPGA; + if (bootverbose) { + device_printf(dev, "PCI device revision : 0x%04x\n", + sc->jme_rev); + device_printf(dev, "Chip revision : 0x%02x\n", + sc->jme_chip_rev); + if ((sc->jme_flags & JME_FLAG_FPGA) != 0) + device_printf(dev, "FPGA revision : 0x%04x\n", + (reg & CHIPMODE_FPGA_REV_MASK) >> + CHIPMODE_FPGA_REV_SHIFT); + } + if (sc->jme_chip_rev == 0xFF) { + device_printf(dev, "Unknown chip revision : 0x%02x\n", + sc->jme_rev); + error = ENXIO; + goto fail; + } + + /* Reset the ethernet controller. */ + jme_reset(sc); + + /* Get station address. */ + reg = CSR_READ_4(sc, JME_SMBCSR); + if ((reg & SMBCSR_EEPROM_PRESENT) != 0) + error = jme_eeprom_macaddr(sc); + if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { + if (error != 0 && (bootverbose)) + device_printf(sc->jme_dev, + "ethernet hardware address not found in EEPROM.\n"); + jme_reg_macaddr(sc); + } + + /* + * Save PHY address. + * Integrated JR0211 has fixed PHY address whereas FPGA version + * requires PHY probing to get correct PHY address. + */ + if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { + sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & + GPREG0_PHY_ADDR_MASK; + if (bootverbose) + device_printf(dev, "PHY is at address %d.\n", + sc->jme_phyaddr); + } else + sc->jme_phyaddr = 0; + + /* Set max allowable DMA size. */ + if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { + sc->jme_flags |= JME_FLAG_PCIE; + burst = pci_read_config(dev, i + 0x08, 2); + if (bootverbose) { + device_printf(dev, "Read request size : %d bytes.\n", + 128 << ((burst >> 12) & 0x07)); + device_printf(dev, "TLP payload size : %d bytes.\n", + 128 << ((burst >> 5) & 0x07)); + } + switch ((burst >> 12) & 0x07) { + case 0: + sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; + break; + case 1: + sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; + break; + default: + sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; + break; + } + sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; + } else { + sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; + sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; + } + /* Create coalescing sysctl node. */ + jme_sysctl_node(sc); + if ((error = jme_dma_alloc(sc) != 0)) + goto fail; + + ifp = sc->jme_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "cannot allocate ifnet structure.\n"); + error = ENXIO; + goto fail; + } + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = jme_ioctl; + ifp->if_start = jme_start; + ifp->if_init = jme_init; + ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1; + IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); + IFQ_SET_READY(&ifp->if_snd); + /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ + ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; + ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; + if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { + sc->jme_flags |= JME_FLAG_PMCAP; + ifp->if_capabilities |= IFCAP_WOL_MAGIC; + } + ifp->if_capenable = ifp->if_capabilities; + + /* Set up MII bus. */ + if ((error = mii_phy_probe(dev, &sc->jme_miibus, jme_mediachange, + jme_mediastatus)) != 0) { + device_printf(dev, "no PHY found!\n"); + goto fail; + } + + /* + * Force PHY to FPGA mode. + */ + if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { + mii = device_get_softc(sc->jme_miibus); + if (mii->mii_instance != 0) { + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { + if (miisc->mii_phy != 0) { + sc->jme_phyaddr = miisc->mii_phy; + break; + } + } + if (sc->jme_phyaddr != 0) { + device_printf(sc->jme_dev, + "FPGA PHY is at %d\n", sc->jme_phyaddr); + /* vendor magic. */ + jme_miibus_writereg(dev, sc->jme_phyaddr, 27, + 0x0004); + } + } + } + + ether_ifattach(ifp, sc->jme_eaddr); + + /* VLAN capability setup */ + ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_HWCSUM; + ifp->if_capenable = ifp->if_capabilities; + + /* Tell the upper layer(s) we support long frames. */ + ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); + + /* Create local taskq. */ + TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp); + sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, + taskqueue_thread_enqueue, &sc->jme_tq); + if (sc->jme_tq == NULL) { + device_printf(dev, "could not create taskqueue.\n"); + ether_ifdetach(ifp); + error = ENXIO; + goto fail; + } + taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", + device_get_nameunit(sc->jme_dev)); + + if ((sc->jme_flags & JME_FLAG_MSIX) != 0) + msic = JME_MSIX_MESSAGES; + else if ((sc->jme_flags & JME_FLAG_MSI) != 0) + msic = JME_MSI_MESSAGES; + else + msic = 1; + for (i = 0; i < msic; i++) { +#if __FreeBSD_version > 700000 + error = bus_setup_intr(dev, sc->jme_irq[i], + INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, + &sc->jme_intrhand[i]); +#else + error = bus_setup_intr(dev, sc->jme_irq[i], + INTR_TYPE_NET | INTR_MPSAFE, jme_intr, sc, + &sc->jme_intrhand[i]); +#endif + if (error != 0) + break; + } + + if (error != 0) { + device_printf(dev, "could not set up interrupt handler.\n"); + taskqueue_free(sc->jme_tq); + sc->jme_tq = NULL; + ether_ifdetach(ifp); + goto fail; + } + +fail: + if (error != 0) + jme_detach(dev); + + return (error); +} + +static int +jme_detach(device_t dev) +{ + struct jme_softc *sc; + struct ifnet *ifp; + int i, msic; + + sc = device_get_softc(dev); + + ifp = sc->jme_ifp; + if (device_is_attached(dev)) { + JME_LOCK(sc); + sc->jme_flags |= JME_FLAG_DETACH; + jme_stop(sc); + JME_UNLOCK(sc); + callout_drain(&sc->jme_tick_ch); + taskqueue_drain(sc->jme_tq, &sc->jme_int_task); + taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); + taskqueue_drain(taskqueue_swi, &sc->jme_link_task); + ether_ifdetach(ifp); + } + + if (sc->jme_tq != NULL) { + taskqueue_drain(sc->jme_tq, &sc->jme_int_task); + taskqueue_free(sc->jme_tq); + sc->jme_tq = NULL; + } + + if (sc->jme_miibus != NULL) { + device_delete_child(dev, sc->jme_miibus); + sc->jme_miibus = NULL; + } + bus_generic_detach(dev); + jme_dma_free(sc); + + if (ifp != NULL) { + if_free(ifp); + sc->jme_ifp = NULL; + } + + msic = 1; + if ((sc->jme_flags & JME_FLAG_MSIX) != 0) + msic = JME_MSIX_MESSAGES; + else if ((sc->jme_flags & JME_FLAG_MSI) != 0) + msic = JME_MSI_MESSAGES; + else + msic = 1; + for (i = 0; i < msic; i++) { + if (sc->jme_intrhand[i] != NULL) { + bus_teardown_intr(dev, sc->jme_irq[i], + sc->jme_intrhand[i]); + sc->jme_intrhand[i] = NULL; + } + } + + bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); + if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) + pci_release_msi(dev); + bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); + mtx_destroy(&sc->jme_mtx); + + return (0); +} + +static void +jme_sysctl_node(struct jme_softc *sc) +{ + int error; + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, + "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, + 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, + "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, + 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, + "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, + 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, + "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, + 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, + "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, + 0, sysctl_hw_jme_proc_limit, "I", + "max number of Rx events to process"); + + /* Pull in device tunables. */ + sc->jme_process_limit = JME_PROC_DEFAULT; + error = resource_int_value(device_get_name(sc->jme_dev), + device_get_unit(sc->jme_dev), "process_limit", + &sc->jme_process_limit); + if (error == 0) { + if (sc->jme_process_limit < JME_PROC_MIN || + sc->jme_process_limit > JME_PROC_MAX) { + device_printf(sc->jme_dev, + "process_limit value out of range; " + "using default: %d\n", JME_PROC_DEFAULT); + sc->jme_process_limit = JME_PROC_DEFAULT; + } + } + + sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; + error = resource_int_value(device_get_name(sc->jme_dev), + device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); + if (error == 0) { + if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || + sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { + device_printf(sc->jme_dev, + "tx_coal_to value out of range; " + "using default: %d\n", PCCTX_COAL_TO_DEFAULT); + sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; + } + } + + sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; + error = resource_int_value(device_get_name(sc->jme_dev), + device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); + if (error == 0) { + if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || + sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { + device_printf(sc->jme_dev, + "tx_coal_pkt value out of range; " + "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); + sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; + } + } + + sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; + error = resource_int_value(device_get_name(sc->jme_dev), + device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); + if (error == 0) { + if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || + sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { + device_printf(sc->jme_dev, + "rx_coal_to value out of range; " + "using default: %d\n", PCCRX_COAL_TO_DEFAULT); + sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; + } + } + + sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; + error = resource_int_value(device_get_name(sc->jme_dev), + device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); + if (error == 0) { + if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || + sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { + device_printf(sc->jme_dev, + "tx_coal_pkt value out of range; " + "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); + sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; + } + } +} + +struct jme_dmamap_arg { + bus_addr_t jme_busaddr; +}; + +static void +jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + struct jme_dmamap_arg *ctx; + + if (error != 0) + return; + + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); + + ctx = (struct jme_dmamap_arg *)arg; + ctx->jme_busaddr = segs[0].ds_addr; +} + +static int +jme_dma_alloc(struct jme_softc *sc) +{ + struct jme_dmamap_arg ctx; + struct jme_txdesc *txd; + struct jme_rxdesc *rxd; + bus_addr_t lowaddr, rx_ring_end, tx_ring_end; + int error, i; + + lowaddr = BUS_SPACE_MAXADDR; + +again: + /* Create parent ring tag. */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ + 1, 0, /* algnmnt, boundary */ + lowaddr, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ + 0, /* nsegments */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->jme_cdata.jme_ring_tag); + if (error != 0) { + device_printf(sc->jme_dev, + "could not create parent ring DMA tag.\n"); + goto fail; + } + /* Create tag for Tx ring. */ + error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ + JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + JME_TX_RING_SIZE, /* maxsize */ + 1, /* nsegments */ + JME_TX_RING_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->jme_cdata.jme_tx_ring_tag); + if (error != 0) { + device_printf(sc->jme_dev, + "could not allocate Tx ring DMA tag.\n"); + goto fail; + } + + /* Create tag for Rx ring. */ + error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ + JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ + lowaddr, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + JME_RX_RING_SIZE, /* maxsize */ + 1, /* nsegments */ + JME_RX_RING_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->jme_cdata.jme_rx_ring_tag); + if (error != 0) { + device_printf(sc->jme_dev, + "could not allocate Rx ring DMA tag.\n"); + goto fail; + } + + /* Allocate DMA'able memory and load the DMA map for Tx ring. */ + error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, + (void **)&sc->jme_rdata.jme_tx_ring, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->jme_cdata.jme_tx_ring_map); + if (error != 0) { + device_printf(sc->jme_dev, + "could not allocate DMA'able memory for Tx ring.\n"); + goto fail; + } + + ctx.jme_busaddr = 0; + error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, + sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, + JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); + if (error != 0 || ctx.jme_busaddr == 0) { + device_printf(sc->jme_dev, + "could not load DMA'able memory for Tx ring.\n"); + goto fail; + } + sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; + + /* Allocate DMA'able memory and load the DMA map for Rx ring. */ + error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, + (void **)&sc->jme_rdata.jme_rx_ring, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->jme_cdata.jme_rx_ring_map); + if (error != 0) { + device_printf(sc->jme_dev, + "could not allocate DMA'able memory for Rx ring.\n"); + goto fail; + } + + ctx.jme_busaddr = 0; + error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, + sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, + JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); + if (error != 0 || ctx.jme_busaddr == 0) { + device_printf(sc->jme_dev, + "could not load DMA'able memory for Rx ring.\n"); + goto fail; + } + sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; + + /* Tx/Rx descriptor queue should reside within 4GB boundary. */ + tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + JME_TX_RING_SIZE; + rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + JME_RX_RING_SIZE; + if ((JME_ADDR_HI(tx_ring_end) != + JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || + (JME_ADDR_HI(rx_ring_end) != + JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { + device_printf(sc->jme_dev, "4GB boundary crossed, " + "switching to 32bit DMA address mode.\n"); + jme_dma_free(sc); + /* Limit DMA address space to 32bit and try again. */ + lowaddr = BUS_SPACE_MAXADDR_32BIT; + goto again; + } + + /* Create parent buffer tag. */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ + 1, 0, /* algnmnt, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ + 0, /* nsegments */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->jme_cdata.jme_buffer_tag); + if (error != 0) { + device_printf(sc->jme_dev, + "could not create parent buffer DMA tag.\n"); + goto fail; + } + + /* Create shadow status block tag. */ + error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ + JME_SSB_ALIGN, 0, /* algnmnt, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + JME_SSB_SIZE, /* maxsize */ + 1, /* nsegments */ + JME_SSB_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->jme_cdata.jme_ssb_tag); + if (error != 0) { + device_printf(sc->jme_dev, + "could not create shared status block DMA tag.\n"); + goto fail; + } + + /* Create tag for Tx buffers. */ + error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ + 1, 0, /* algnmnt, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + JME_TSO_MAXSIZE, /* maxsize */ + JME_MAXTXSEGS, /* nsegments */ + JME_TSO_MAXSEGSIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->jme_cdata.jme_tx_tag); + if (error != 0) { + device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); + goto fail; + } + + /* Create tag for Rx buffers. */ + error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ + JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MCLBYTES, /* maxsize */ + 1, /* nsegments */ + MCLBYTES, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->jme_cdata.jme_rx_tag); + if (error != 0) { + device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); + goto fail; + } + + /* + * Allocate DMA'able memory and load the DMA map for shared + * status block. + */ + error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, + (void **)&sc->jme_rdata.jme_ssb_block, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->jme_cdata.jme_ssb_map); + if (error != 0) { + device_printf(sc->jme_dev, "could not allocate DMA'able " + "memory for shared status block.\n"); + goto fail; + } + + ctx.jme_busaddr = 0; + error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, + sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, + JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); + if (error != 0 || ctx.jme_busaddr == 0) { + device_printf(sc->jme_dev, "could not load DMA'able memory " + "for shared status block.\n"); + goto fail; + } + sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; + + /* Create DMA maps for Tx buffers. */ + for (i = 0; i < JME_TX_RING_CNT; i++) { + txd = &sc->jme_cdata.jme_txdesc[i]; + txd->tx_m = NULL; + txd->tx_dmamap = NULL; + error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, + &txd->tx_dmamap); + if (error != 0) { + device_printf(sc->jme_dev, + "could not create Tx dmamap.\n"); + goto fail; + } + } + /* Create DMA maps for Rx buffers. */ + if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, + &sc->jme_cdata.jme_rx_sparemap)) != 0) { + device_printf(sc->jme_dev, + "could not create spare Rx dmamap.\n"); + goto fail; + } + for (i = 0; i < JME_RX_RING_CNT; i++) { + rxd = &sc->jme_cdata.jme_rxdesc[i]; + rxd->rx_m = NULL; + rxd->rx_dmamap = NULL; + error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, + &rxd->rx_dmamap); + if (error != 0) { + device_printf(sc->jme_dev, + "could not create Rx dmamap.\n"); + goto fail; + } + } + +fail: + return (error); +} + +static void +jme_dma_free(struct jme_softc *sc) +{ + struct jme_txdesc *txd; + struct jme_rxdesc *rxd; + int i; + + /* Tx ring */ + if (sc->jme_cdata.jme_tx_ring_tag != NULL) { + if (sc->jme_cdata.jme_tx_ring_map) + bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, + sc->jme_cdata.jme_tx_ring_map); + if (sc->jme_cdata.jme_tx_ring_map && + sc->jme_rdata.jme_tx_ring) + bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, + sc->jme_rdata.jme_tx_ring, + sc->jme_cdata.jme_tx_ring_map); + sc->jme_rdata.jme_tx_ring = NULL; + sc->jme_cdata.jme_tx_ring_map = NULL; + bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); + sc->jme_cdata.jme_tx_ring_tag = NULL; + } + /* Rx ring */ + if (sc->jme_cdata.jme_rx_ring_tag != NULL) { + if (sc->jme_cdata.jme_rx_ring_map) + bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, + sc->jme_cdata.jme_rx_ring_map); + if (sc->jme_cdata.jme_rx_ring_map && + sc->jme_rdata.jme_rx_ring) + bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, + sc->jme_rdata.jme_rx_ring, + sc->jme_cdata.jme_rx_ring_map); + sc->jme_rdata.jme_rx_ring = NULL; + sc->jme_cdata.jme_rx_ring_map = NULL; + bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); + sc->jme_cdata.jme_rx_ring_tag = NULL; + } + /* Tx buffers */ + if (sc->jme_cdata.jme_tx_tag != NULL) { + for (i = 0; i < JME_TX_RING_CNT; i++) { + txd = &sc->jme_cdata.jme_txdesc[i]; + if (txd->tx_dmamap != NULL) { + bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, + txd->tx_dmamap); + txd->tx_dmamap = NULL; + } + } + bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); + sc->jme_cdata.jme_tx_tag = NULL; + } + /* Rx buffers */ + if (sc->jme_cdata.jme_rx_tag != NULL) { + for (i = 0; i < JME_RX_RING_CNT; i++) { + rxd = &sc->jme_cdata.jme_rxdesc[i]; + if (rxd->rx_dmamap != NULL) { + bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, + rxd->rx_dmamap); + rxd->rx_dmamap = NULL; + } + } + if (sc->jme_cdata.jme_rx_sparemap != NULL) { + bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, + sc->jme_cdata.jme_rx_sparemap); + sc->jme_cdata.jme_rx_sparemap = NULL; + } + bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); + sc->jme_cdata.jme_rx_tag = NULL; + } + + /* Shared status block. */ + if (sc->jme_cdata.jme_ssb_tag != NULL) { + if (sc->jme_cdata.jme_ssb_map) + bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, + sc->jme_cdata.jme_ssb_map); + if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block) + bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, + sc->jme_rdata.jme_ssb_block, + sc->jme_cdata.jme_ssb_map); + sc->jme_rdata.jme_ssb_block = NULL; + sc->jme_cdata.jme_ssb_map = NULL; + bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); + sc->jme_cdata.jme_ssb_tag = NULL; + } + + if (sc->jme_cdata.jme_buffer_tag != NULL) { + bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); + sc->jme_cdata.jme_buffer_tag = NULL; + } + if (sc->jme_cdata.jme_ring_tag != NULL) { + bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); + sc->jme_cdata.jme_ring_tag = NULL; + } +} + +/* + * Make sure the interface is stopped at reboot time. + */ +static int +jme_shutdown(device_t dev) +{ + + return (jme_suspend(dev)); +} + +/* + * Unlike other ethernet controllers, JMC250 requires + * explicit resetting link speed to 10/100Mbps as gigabit + * link will cunsume more power than 375mA. + * Note, we reset the link speed to 10/100Mbps with + * auto-negotiation but we don't know whether that operation + * would succeed or not as we have no control after powering + * off. If the renegotiation fail WOL may not work. Running + * at 1Gbps draws more power than 375mA at 3.3V which is + * specified in PCI specification and that would result in + * complete shutdowning power to ethernet controller. + * + * TODO + * Save current negotiated media speed/duplex/flow-control + * to softc and restore the same link again after resuming. + * PHY handling such as power down/resetting to 100Mbps + * may be better handled in suspend method in phy driver. + */ +static void +jme_setlinkspeed(struct jme_softc *sc) +{ + struct mii_data *mii; + int aneg, i; + + JME_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->jme_miibus); + mii_pollstat(mii); + aneg = 0; + if ((mii->mii_media_status & IFM_AVALID) != 0) { + switch IFM_SUBTYPE(mii->mii_media_active) { + case IFM_10_T: + case IFM_100_TX: + return; + case IFM_1000_T: + aneg++; + default: + break; + } + } + jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); + jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, + ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); + jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, + BMCR_AUTOEN | BMCR_STARTNEG); + DELAY(1000); + if (aneg != 0) { + /* Poll link state until jme(4) get a 10/100 link. */ + for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { + mii_pollstat(mii); + if ((mii->mii_media_status & IFM_AVALID) != 0) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + jme_mac_config(sc); + return; + default: + break; + } + } +#if __FreeBSD_version < 700000 + msleep(sc, &sc->jme_mtx, PPAUSE, "jmelnk", hz); +#else + JME_UNLOCK(sc); + pause("jmelnk", hz); + JME_LOCK(sc); +#endif + } + if (i == MII_ANEGTICKS_GIGE) + device_printf(sc->jme_dev, "establishing link failed, " + "WOL may not work!"); + } + /* + * No link, force MAC to have 100Mbps, full-duplex link. + * This is the last resort and may/may not work. + */ + mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; + mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; + jme_mac_config(sc); +} + +static void +jme_setwol(struct jme_softc *sc) +{ + struct ifnet *ifp; + uint32_t gpr, pmcs; + uint16_t pmstat; + int pmc; + + JME_LOCK_ASSERT(sc); + + if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { + /* No PME capability, PHY power down. */ + jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, + MII_BMCR, BMCR_PDOWN); + return; + } + + ifp = sc->jme_ifp; + gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; + pmcs = CSR_READ_4(sc, JME_PMCS); + pmcs &= ~PMCS_WOL_ENB_MASK; + if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { + pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; + /* Enable PME message. */ + gpr |= GPREG0_PME_ENB; + /* For gigabit controllers, reset link speed to 10/100. */ + if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) + jme_setlinkspeed(sc); + } + + CSR_WRITE_4(sc, JME_PMCS, pmcs); + CSR_WRITE_4(sc, JME_GPREG0, gpr); + + /* Request PME. */ + pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); + pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); + if ((ifp->if_capenable & IFCAP_WOL) != 0) + pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; + pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); + if ((ifp->if_capenable & IFCAP_WOL) == 0) { + /* No WOL, PHY power down. */ + jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, + MII_BMCR, BMCR_PDOWN); + } +} + +static int +jme_suspend(device_t dev) +{ + struct jme_softc *sc; + + sc = device_get_softc(dev); + + JME_LOCK(sc); + jme_stop(sc); + jme_setwol(sc); + JME_UNLOCK(sc); + + return (0); +} + +static int +jme_resume(device_t dev) +{ + struct jme_softc *sc; + struct ifnet *ifp; + uint16_t pmstat; + int pmc; + + sc = device_get_softc(dev); + + JME_LOCK(sc); + if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { + pmstat = pci_read_config(sc->jme_dev, + pmc + PCIR_POWER_STATUS, 2); + /* Disable PME clear PME status. */ + pmstat &= ~PCIM_PSTAT_PMEENABLE; + pci_write_config(sc->jme_dev, + pmc + PCIR_POWER_STATUS, pmstat, 2); + } + ifp = sc->jme_ifp; + if ((ifp->if_flags & IFF_UP) != 0) + jme_init_locked(sc); + + JME_UNLOCK(sc); + + return (0); +} + +static int +jme_encap(struct jme_softc *sc, struct mbuf **m_head) +{ + struct jme_txdesc *txd; + struct jme_desc *desc; + struct mbuf *m; +#if __FreeBSD_version < 700000 + struct m_tag *mtag; +#endif + bus_dma_segment_t txsegs[JME_MAXTXSEGS]; + int error, i, nsegs, prod; + uint32_t cflags, tso_segsz; + + JME_LOCK_ASSERT(sc); + + M_ASSERTPKTHDR((*m_head)); + + if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { + /* + * Due to the adherence to NDIS specification JMC250 + * assumes upper stack computed TCP pseudo checksum + * without including payload length. This breaks + * checksum offload for TSO case so recompute TCP + * pseudo checksum for JMC250. Hopefully this wouldn't + * be much burden on modern CPUs. + */ + struct ether_header *eh; + struct ip *ip; + struct tcphdr *tcp; + uint32_t ip_off, poff; + + if (M_WRITABLE(*m_head) == 0) { + /* Get a writable copy. */ + m = m_dup(*m_head, M_DONTWAIT); + m_freem(*m_head); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + *m_head = m; + } + ip_off = sizeof(struct ether_header); + m = m_pullup(*m_head, ip_off); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + eh = mtod(m, struct ether_header *); + /* Check the existence of VLAN tag. */ + if (eh->ether_type == htons(ETHERTYPE_VLAN)) { + ip_off = sizeof(struct ether_vlan_header); + m = m_pullup(m, ip_off); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + } + m = m_pullup(m, ip_off + sizeof(struct ip)); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + ip = (struct ip *)(mtod(m, char *) + ip_off); + poff = ip_off + (ip->ip_hl << 2); + m = m_pullup(m, poff + sizeof(struct tcphdr)); + if (m == NULL) { + *m_head = NULL; + return (ENOBUFS); + } + tcp = (struct tcphdr *)(mtod(m, char *) + poff); + /* + * Reset IP checksum and recompute TCP pseudo + * checksum that NDIS specification requires. + */ + ip->ip_sum = 0; + if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { + tcp->th_sum = in_pseudo(ip->ip_src.s_addr, + ip->ip_dst.s_addr, + htons((tcp->th_off << 2) + IPPROTO_TCP)); + /* No need to TSO, force IP checksum offload. */ + (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; + (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; + } else + tcp->th_sum = in_pseudo(ip->ip_src.s_addr, + ip->ip_dst.s_addr, htons(IPPROTO_TCP)); + *m_head = m; + } + + prod = sc->jme_cdata.jme_tx_prod; + txd = &sc->jme_cdata.jme_txdesc[prod]; + + error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, + txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); + if (error == EFBIG) { + m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOMEM); + } + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, + txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); + if (error != 0) { + m_freem(*m_head); + *m_head = NULL; + return (error); + } + } else if (error != 0) + return (error); + if (nsegs == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + /* + * Check descriptor overrun. Leave one free descriptor. + * Since we always use 64bit address mode for transmitting, + * each Tx request requires one more dummy descriptor. + */ + if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { + bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); + return (ENOBUFS); + } + + m = *m_head; + cflags = 0; + tso_segsz = 0; + /* Configure checksum offload and TSO. */ + if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { +#if __FreeBSD_version >= 700000 + tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz << + JME_TD_MSS_SHIFT; +#endif + cflags |= JME_TD_TSO; + } else { + if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) + cflags |= JME_TD_IPCSUM; + if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) + cflags |= JME_TD_TCPCSUM; + if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) + cflags |= JME_TD_UDPCSUM; + } + /* Configure VLAN. */ +#if __FreeBSD_version < 700000 + mtag = VLAN_OUTPUT_TAG(sc->jme_ifp, m); + if (mtag != NULL) { + cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK); + cflags |= JME_TD_VLAN_TAG; + } +#else + if ((m->m_flags & M_VLANTAG) != 0) { + cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); + cflags |= JME_TD_VLAN_TAG; + } +#endif + + desc = &sc->jme_rdata.jme_tx_ring[prod]; + desc->flags = htole32(cflags); + desc->buflen = htole32(tso_segsz); + desc->addr_hi = htole32(m->m_pkthdr.len); + desc->addr_lo = 0; + sc->jme_cdata.jme_tx_cnt++; + JME_DESC_INC(prod, JME_TX_RING_CNT); + for (i = 0; i < nsegs; i++) { + desc = &sc->jme_rdata.jme_tx_ring[prod]; + desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); + desc->buflen = htole32(txsegs[i].ds_len); + desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); + desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); + sc->jme_cdata.jme_tx_cnt++; + JME_DESC_INC(prod, JME_TX_RING_CNT); + } + + /* Update producer index. */ + sc->jme_cdata.jme_tx_prod = prod; + /* + * Finally request interrupt and give the first descriptor + * owenership to hardware. + */ + desc = txd->tx_desc; + desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); + + txd->tx_m = m; + txd->tx_ndesc = nsegs + 1; + + /* Sync descriptors. */ + bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, + sc->jme_cdata.jme_tx_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (0); +} + +static void +jme_tx_task(void *arg, int pending) +{ + struct ifnet *ifp; + + ifp = (struct ifnet *)arg; + jme_start(ifp); +} + +static void +jme_start(struct ifnet *ifp) +{ + struct jme_softc *sc; + struct mbuf *m_head; + int enq; + + sc = ifp->if_softc; + + JME_LOCK(sc); + + if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) + jme_txeof(sc); + + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) { + JME_UNLOCK(sc); + return; + } + + for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + /* + * Pack the data into the transmit ring. If we + * don't have room, set the OACTIVE flag and wait + * for the NIC to drain the ring. + */ + if (jme_encap(sc, &m_head)) { + if (m_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + + enq++; + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + ETHER_BPF_MTAP(ifp, m_head); + } + + if (enq > 0) { + /* + * Reading TXCSR takes very long time under heavy load + * so cache TXCSR value and writes the ORed value with + * the kick command to the TXCSR. This saves one register + * access cycle. + */ + CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | + TXCSR_TXQ_N_START(TXCSR_TXQ0)); + /* Set a timeout in case the chip goes out to lunch. */ + sc->jme_watchdog_timer = JME_TX_TIMEOUT; + } + + JME_UNLOCK(sc); +} + +static void +jme_watchdog(struct jme_softc *sc) +{ + struct ifnet *ifp; + + JME_LOCK_ASSERT(sc); + + if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) + return; + + ifp = sc->jme_ifp; + if ((sc->jme_flags & JME_FLAG_LINK) == 0) { + if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); + ifp->if_oerrors++; + jme_init_locked(sc); + return; + } + jme_txeof(sc); + if (sc->jme_cdata.jme_tx_cnt == 0) { + if_printf(sc->jme_ifp, + "watchdog timeout (missed Tx interrupts) -- recovering\n"); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); + return; + } + + if_printf(sc->jme_ifp, "watchdog timeout\n"); + ifp->if_oerrors++; + jme_init_locked(sc); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); +} + +static int +jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct jme_softc *sc; + struct ifreq *ifr; + struct mii_data *mii; + uint32_t reg; + int error, mask; + + sc = ifp->if_softc; + ifr = (struct ifreq *)data; + error = 0; + switch (cmd) { + case SIOCSIFMTU: + if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || + ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && + ifr->ifr_mtu > JME_MAX_MTU)) { + error = EINVAL; + break; + } + + if (ifp->if_mtu != ifr->ifr_mtu) { + /* + * No special configuration is required when interface + * MTU is changed but availability of TSO/Tx checksum + * offload should be chcked against new MTU size as + * FIFO size is just 2K. + */ + JME_LOCK(sc); + if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { + ifp->if_capenable &= + ~(IFCAP_TXCSUM | IFCAP_TSO4); + ifp->if_hwassist &= + ~(JME_CSUM_FEATURES | CSUM_TSO); + VLAN_CAPABILITIES(ifp); + } + ifp->if_mtu = ifr->ifr_mtu; + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + jme_init_locked(sc); + JME_UNLOCK(sc); + } + break; + case SIOCSIFFLAGS: + JME_LOCK(sc); + if ((ifp->if_flags & IFF_UP) != 0) { + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + if (((ifp->if_flags ^ sc->jme_if_flags) + & (IFF_PROMISC | IFF_ALLMULTI)) != 0) + jme_set_filter(sc); + } else { + if ((sc->jme_flags & JME_FLAG_DETACH) == 0) + jme_init_locked(sc); + } + } else { + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + jme_stop(sc); + } + sc->jme_if_flags = ifp->if_flags; + JME_UNLOCK(sc); + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + JME_LOCK(sc); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + jme_set_filter(sc); + JME_UNLOCK(sc); + break; + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + mii = device_get_softc(sc->jme_miibus); + error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); + break; + case SIOCSIFCAP: + JME_LOCK(sc); + mask = ifr->ifr_reqcap ^ ifp->if_capenable; + if ((mask & IFCAP_TXCSUM) != 0 && + ifp->if_mtu < JME_TX_FIFO_SIZE) { + if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { + ifp->if_capenable ^= IFCAP_TXCSUM; + if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) + ifp->if_hwassist |= JME_CSUM_FEATURES; + else + ifp->if_hwassist &= ~JME_CSUM_FEATURES; + } + } + if ((mask & IFCAP_RXCSUM) != 0 && + (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { + ifp->if_capenable ^= IFCAP_RXCSUM; + reg = CSR_READ_4(sc, JME_RXMAC); + reg &= ~RXMAC_CSUM_ENB; + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) + reg |= RXMAC_CSUM_ENB; + CSR_WRITE_4(sc, JME_RXMAC, reg); + } + if ((mask & IFCAP_TSO4) != 0 && + ifp->if_mtu < JME_TX_FIFO_SIZE) { + if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) { + ifp->if_capenable ^= IFCAP_TSO4; + if ((IFCAP_TSO4 & ifp->if_capenable) != 0) + ifp->if_hwassist |= CSUM_TSO; + else + ifp->if_hwassist &= ~CSUM_TSO; + } + } + if ((mask & IFCAP_WOL_MAGIC) != 0 && + (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0) + ifp->if_capenable ^= IFCAP_WOL_MAGIC; + if ((mask & IFCAP_VLAN_HWCSUM) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) + ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; + if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && + (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { + ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; + jme_set_vlan(sc); + } + JME_UNLOCK(sc); + VLAN_CAPABILITIES(ifp); + break; + default: + error = ether_ioctl(ifp, cmd, data); + break; + } + + return (error); +} + +static void +jme_mac_config(struct jme_softc *sc) +{ + struct mii_data *mii; + uint32_t ghc, rxmac, txmac, txpause; + + JME_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->jme_miibus); + + CSR_WRITE_4(sc, JME_GHC, GHC_RESET); + DELAY(10); + CSR_WRITE_4(sc, JME_GHC, 0); + ghc = 0; + rxmac = CSR_READ_4(sc, JME_RXMAC); + rxmac &= ~RXMAC_FC_ENB; + txmac = CSR_READ_4(sc, JME_TXMAC); + txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); + txpause = CSR_READ_4(sc, JME_TXPFC); + txpause &= ~TXPFC_PAUSE_ENB; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { + ghc |= GHC_FULL_DUPLEX; + rxmac &= ~RXMAC_COLL_DET_ENB; + txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | + TXMAC_BACKOFF | TXMAC_CARRIER_EXT | + TXMAC_FRAME_BURST); +#ifdef notyet + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) + txpause |= TXPFC_PAUSE_ENB; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) + rxmac |= RXMAC_FC_ENB; +#endif + /* Disable retry transmit timer/retry limit. */ + CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & + ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); + } else { + rxmac |= RXMAC_COLL_DET_ENB; + txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; + /* Enable retry transmit timer/retry limit. */ + CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | + TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); + } + /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + ghc |= GHC_SPEED_10; + break; + case IFM_100_TX: + ghc |= GHC_SPEED_100; + break; + case IFM_1000_T: + if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) + break; + ghc |= GHC_SPEED_1000; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) + txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; + break; + default: + break; + } + CSR_WRITE_4(sc, JME_GHC, ghc); + CSR_WRITE_4(sc, JME_RXMAC, rxmac); + CSR_WRITE_4(sc, JME_TXMAC, txmac); + CSR_WRITE_4(sc, JME_TXPFC, txpause); +} + +static void +jme_link_task(void *arg, int pending) +{ + struct jme_softc *sc; + struct mii_data *mii; + struct ifnet *ifp; + struct jme_txdesc *txd; + bus_addr_t paddr; + int i; + + sc = (struct jme_softc *)arg; + + JME_LOCK(sc); + mii = device_get_softc(sc->jme_miibus); + ifp = sc->jme_ifp; + if (mii == NULL || ifp == NULL || + (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + JME_UNLOCK(sc); + return; + } + + sc->jme_flags &= ~JME_FLAG_LINK; + if ((mii->mii_media_status & IFM_AVALID) != 0) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + sc->jme_flags |= JME_FLAG_LINK; + break; + case IFM_1000_T: + if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) + break; + sc->jme_flags |= JME_FLAG_LINK; + break; + default: + break; + } + } + + /* + * Disabling Rx/Tx MACs have a side-effect of resetting + * JME_TXNDA/JME_RXNDA register to the first address of + * Tx/Rx descriptor address. So driver should reset its + * internal procucer/consumer pointer and reclaim any + * allocated resources. Note, just saving the value of + * JME_TXNDA and JME_RXNDA registers before stopping MAC + * and restoring JME_TXNDA/JME_RXNDA register is not + * sufficient to make sure correct MAC state because + * stopping MAC operation can take a while and hardware + * might have updated JME_TXNDA/JME_RXNDA registers + * during the stop operation. + */ +#ifdef notyet + /* Block execution of task. */ + taskqueue_block(sc->jme_tq); +#endif + /* Disable interrupts and stop driver. */ + CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + callout_stop(&sc->jme_tick_ch); + sc->jme_watchdog_timer = 0; + + /* Stop receiver/transmitter. */ + jme_stop_rx(sc); + jme_stop_tx(sc); + + /* XXX Drain all queued tasks. */ + JME_UNLOCK(sc); + taskqueue_drain(sc->jme_tq, &sc->jme_int_task); + taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); + JME_LOCK(sc); + + jme_rxintr(sc, JME_RX_RING_CNT); + if (sc->jme_cdata.jme_rxhead != NULL) + m_freem(sc->jme_cdata.jme_rxhead); + JME_RXCHAIN_RESET(sc); + jme_txeof(sc); + if (sc->jme_cdata.jme_tx_cnt != 0) { + /* Remove queued packets for transmit. */ + for (i = 0; i < JME_TX_RING_CNT; i++) { + txd = &sc->jme_cdata.jme_txdesc[i]; + if (txd->tx_m != NULL) { + bus_dmamap_sync( + sc->jme_cdata.jme_tx_tag, + txd->tx_dmamap, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload( + sc->jme_cdata.jme_tx_tag, + txd->tx_dmamap); + m_freem(txd->tx_m); + txd->tx_m = NULL; + txd->tx_ndesc = 0; + ifp->if_oerrors++; + } + } + } + + /* + * Reuse configured Rx descriptors and reset + * procuder/consumer index. + */ + sc->jme_cdata.jme_rx_cons = 0; + atomic_set_int(&sc->jme_morework, 0); + jme_init_tx_ring(sc); + /* Initialize shadow status block. */ + jme_init_ssb(sc); + + /* Program MAC with resolved speed/duplex/flow-control. */ + if ((sc->jme_flags & JME_FLAG_LINK) != 0) { + jme_mac_config(sc); + + CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); + CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); + + /* Set Tx ring address to the hardware. */ + paddr = JME_TX_RING_ADDR(sc, 0); + CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); + CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); + + /* Set Rx ring address to the hardware. */ + paddr = JME_RX_RING_ADDR(sc, 0); + CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); + CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); + + /* Restart receiver/transmitter. */ + CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | + RXCSR_RXQ_START); + CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); + } + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); +#ifdef notyet + /* Unblock execution of task. */ + taskqueue_unblock(sc->jme_tq); +#endif + /* Reenable interrupts. */ + CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); + + JME_UNLOCK(sc); +} + +#if __FreeBSD_version < 700000 +static void +#else +static int +#endif +jme_intr(void *arg) +{ + struct jme_softc *sc; + uint32_t status; + + sc = (struct jme_softc *)arg; + + status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); + if (status == 0 || status == 0xFFFFFFFF) + return FILTER_STRAY; + /* Disable interrupts. */ + CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); + taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); + + return FILTER_HANDLED; +} + +static void +jme_int_task(void *arg, int pending) +{ + struct jme_softc *sc; + struct ifnet *ifp; + uint32_t status; + int more; + + sc = (struct jme_softc *)arg; + ifp = sc->jme_ifp; + + status = CSR_READ_4(sc, JME_INTR_STATUS); + more = atomic_readandclear_int(&sc->jme_morework); + if (more != 0) { + status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; + more = 0; + } + if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) + goto done; + /* Reset PCC counter/timer and Ack interrupts. */ + status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); + if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) + status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; + if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) + status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; + CSR_WRITE_4(sc, JME_INTR_STATUS, status); + more = 0; + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { + more = jme_rxintr(sc, sc->jme_process_limit); + if (more != 0) + atomic_set_int(&sc->jme_morework, 1); + } + if ((status & INTR_RXQ_DESC_EMPTY) != 0) { + /* + * Notify hardware availability of new Rx + * buffers. + * Reading RXCSR takes very long time under + * heavy load so cache RXCSR value and writes + * the ORed value with the kick command to + * the RXCSR. This saves one register access + * cycle. + */ + CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | + RXCSR_RX_ENB | RXCSR_RXQ_START); + } + /* + * Reclaiming Tx buffers are deferred to make jme(4) run + * without locks held. + */ + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); + } + + if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { + taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); + return; + } +done: + /* Reenable interrupts. */ + CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); +} + +static void +jme_txeof(struct jme_softc *sc) +{ + struct ifnet *ifp; + struct jme_txdesc *txd; + uint32_t status; + int cons, nsegs; + + JME_LOCK_ASSERT(sc); + + ifp = sc->jme_ifp; + + cons = sc->jme_cdata.jme_tx_cons; + if (cons == sc->jme_cdata.jme_tx_prod) + return; + + bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, + sc->jme_cdata.jme_tx_ring_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + /* + * Go through our Tx list and free mbufs for those + * frames which have been transmitted. + */ + for (; cons != sc->jme_cdata.jme_tx_prod;) { + txd = &sc->jme_cdata.jme_txdesc[cons]; + status = le32toh(txd->tx_desc->flags); + if ((status & JME_TD_OWN) == JME_TD_OWN) + break; + + if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) + ifp->if_oerrors++; + else { + ifp->if_opackets++; + if ((status & JME_TD_COLLISION) != 0) + ifp->if_collisions += + le32toh(txd->tx_desc->buflen) & + JME_TD_BUF_LEN_MASK; + } + /* + * Only the first descriptor of multi-descriptor + * transmission is updated so driver have to skip entire + * chained buffers for the transmiited frame. In other + * words, JME_TD_OWN bit is valid only at the first + * descriptor of a multi-descriptor transmission. + */ + for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { + sc->jme_rdata.jme_tx_ring[cons].flags = 0; + JME_DESC_INC(cons, JME_TX_RING_CNT); + } + + /* Reclaim transferred mbufs. */ + bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); + + KASSERT(txd->tx_m != NULL, + ("%s: freeing NULL mbuf!\n", __func__)); + m_freem(txd->tx_m); + txd->tx_m = NULL; + sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; + KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, + ("%s: Active Tx desc counter was garbled\n", __func__)); + txd->tx_ndesc = 0; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + } + sc->jme_cdata.jme_tx_cons = cons; + /* Unarm watchog timer when there is no pending descriptors in queue. */ + if (sc->jme_cdata.jme_tx_cnt == 0) + sc->jme_watchdog_timer = 0; + + bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, + sc->jme_cdata.jme_tx_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + +static __inline void +jme_discard_rxbuf(struct jme_softc *sc, int cons) +{ + struct jme_desc *desc; + + desc = &sc->jme_rdata.jme_rx_ring[cons]; + desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); + desc->buflen = htole32(MCLBYTES); +} + +/* Receive a frame. */ +static void +jme_rxeof(struct jme_softc *sc) +{ + struct ifnet *ifp; + struct jme_desc *desc; + struct jme_rxdesc *rxd; + struct mbuf *mp, *m; + uint32_t flags, status; + int cons, count, nsegs; + + ifp = sc->jme_ifp; + + cons = sc->jme_cdata.jme_rx_cons; + desc = &sc->jme_rdata.jme_rx_ring[cons]; + flags = le32toh(desc->flags); + status = le32toh(desc->buflen); + nsegs = JME_RX_NSEGS(status); + sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; + if ((status & JME_RX_ERR_STAT) != 0) { + ifp->if_ierrors++; + jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); +#ifdef JME_SHOW_ERRORS + device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", + __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); +#endif + sc->jme_cdata.jme_rx_cons += nsegs; + sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; + return; + } + + for (count = 0; count < nsegs; count++, + JME_DESC_INC(cons, JME_RX_RING_CNT)) { + rxd = &sc->jme_cdata.jme_rxdesc[cons]; + mp = rxd->rx_m; + /* Add a new receive buffer to the ring. */ + if (jme_newbuf(sc, rxd) != 0) { + ifp->if_iqdrops++; + /* Reuse buffer. */ + for (; count < nsegs; count++) { + jme_discard_rxbuf(sc, cons); + JME_DESC_INC(cons, JME_RX_RING_CNT); + } + if (sc->jme_cdata.jme_rxhead != NULL) { + m_freem(sc->jme_cdata.jme_rxhead); + JME_RXCHAIN_RESET(sc); + } + break; + } + + /* + * Assume we've received a full sized frame. + * Actual size is fixed when we encounter the end of + * multi-segmented frame. + */ + mp->m_len = MCLBYTES; + + /* Chain received mbufs. */ + if (sc->jme_cdata.jme_rxhead == NULL) { + sc->jme_cdata.jme_rxhead = mp; + sc->jme_cdata.jme_rxtail = mp; + } else { + /* + * Receive processor can receive a maximum frame + * size of 65535 bytes. + */ + mp->m_flags &= ~M_PKTHDR; + sc->jme_cdata.jme_rxtail->m_next = mp; + sc->jme_cdata.jme_rxtail = mp; + } + + if (count == nsegs - 1) { + /* Last desc. for this frame. */ + m = sc->jme_cdata.jme_rxhead; + m->m_flags |= M_PKTHDR; + m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; + if (nsegs > 1) { + /* Set first mbuf size. */ + m->m_len = MCLBYTES - JME_RX_PAD_BYTES; + /* Set last mbuf size. */ + mp->m_len = sc->jme_cdata.jme_rxlen - + ((MCLBYTES - JME_RX_PAD_BYTES) + + (MCLBYTES * (nsegs - 2))); + } else + m->m_len = sc->jme_cdata.jme_rxlen; + m->m_pkthdr.rcvif = ifp; + + /* + * Account for 10bytes auto padding which is used + * to align IP header on 32bit boundary. Also note, + * CRC bytes is automatically removed by the + * hardware. + */ + m->m_data += JME_RX_PAD_BYTES; + + /* Set checksum information. */ + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && + (flags & JME_RD_IPV4) != 0) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + if ((flags & JME_RD_IPCSUM) != 0) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + if (((flags & JME_RD_MORE_FRAG) == 0) && + ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == + (JME_RD_TCP | JME_RD_TCPCSUM) || + (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == + (JME_RD_UDP | JME_RD_UDPCSUM))) { + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID | CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + + /* Check for VLAN tagged packets. */ + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && + (flags & JME_RD_VLAN_TAG) != 0) { +#if __FreeBSD_version < 700000 + VLAN_INPUT_TAG_NEW(ifp, m, + (flags & JME_RD_VLAN_MASK)); +#else + m->m_pkthdr.ether_vtag = + flags & JME_RD_VLAN_MASK; + m->m_flags |= M_VLANTAG; +#endif + } + + ifp->if_ipackets++; + /* Pass it on. */ + (*ifp->if_input)(ifp, m); + + /* Reset mbuf chains. */ + JME_RXCHAIN_RESET(sc); + } + } + + sc->jme_cdata.jme_rx_cons += nsegs; + sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; +} + +static int +jme_rxintr(struct jme_softc *sc, int count) +{ + struct jme_desc *desc; + int nsegs, prog, pktlen; + + bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, + sc->jme_cdata.jme_rx_ring_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + for (prog = 0; count > 0; prog++) { + desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; + if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) + break; + if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) + break; + nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); + /* + * Check number of segments against received bytes. + * Non-matching value would indicate that hardware + * is still trying to update Rx descriptors. I'm not + * sure whether this check is needed. + */ + pktlen = JME_RX_BYTES(le32toh(desc->buflen)); + if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES)) + break; + prog++; + /* Received a frame. */ + jme_rxeof(sc); + count -= nsegs; + } + + if (prog > 0) + bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, + sc->jme_cdata.jme_rx_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (count > 0 ? 0 : EAGAIN); +} + +static void +jme_tick(void *arg) +{ + struct jme_softc *sc; + struct mii_data *mii; + + sc = (struct jme_softc *)arg; + + JME_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->jme_miibus); + mii_tick(mii); + /* + * Reclaim Tx buffers that have been completed. It's not + * needed here but it would release allocated mbuf chains + * faster and limit the maximum delay to a hz. + */ + jme_txeof(sc); + jme_watchdog(sc); + callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); +} + +static void +jme_reset(struct jme_softc *sc) +{ + + /* Stop receiver, transmitter. */ + jme_stop_rx(sc); + jme_stop_tx(sc); + CSR_WRITE_4(sc, JME_GHC, GHC_RESET); + DELAY(10); + CSR_WRITE_4(sc, JME_GHC, 0); +} + +static void +jme_init(void *xsc) +{ + struct jme_softc *sc; + + sc = (struct jme_softc *)xsc; + JME_LOCK(sc); + jme_init_locked(sc); + JME_UNLOCK(sc); +} + +static void +jme_init_locked(struct jme_softc *sc) +{ + struct ifnet *ifp; + struct mii_data *mii; + uint8_t eaddr[ETHER_ADDR_LEN]; + bus_addr_t paddr; + uint32_t reg; + int error; + + JME_LOCK_ASSERT(sc); + + ifp = sc->jme_ifp; + mii = device_get_softc(sc->jme_miibus); + + /* + * Cancel any pending I/O. + */ + jme_stop(sc); + + /* + * Reset the chip to a known state. + */ + jme_reset(sc); + + /* Init descriptors. */ + error = jme_init_rx_ring(sc); + if (error != 0) { + device_printf(sc->jme_dev, + "%s: initialization failed: no memory for Rx buffers.\n", + __func__); + jme_stop(sc); + return; + } + jme_init_tx_ring(sc); + /* Initialize shadow status block. */ + jme_init_ssb(sc); + + /* Reprogram the station address. */ + bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_4(sc, JME_PAR0, + eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); + CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); + + /* + * Configure Tx queue. + * Tx priority queue weight value : 0 + * Tx FIFO threshold for processing next packet : 16QW + * Maximum Tx DMA length : 512 + * Allow Tx DMA burst. + */ + sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); + sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); + sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; + sc->jme_txcsr |= sc->jme_tx_dma_size; + sc->jme_txcsr |= TXCSR_DMA_BURST; + CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); + + /* Set Tx descriptor counter. */ + CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); + + /* Set Tx ring address to the hardware. */ + paddr = JME_TX_RING_ADDR(sc, 0); + CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); + CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); + + /* Configure TxMAC parameters. */ + reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; + reg |= TXMAC_THRESH_1_PKT; + reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; + CSR_WRITE_4(sc, JME_TXMAC, reg); + + /* + * Configure Rx queue. + * FIFO full threshold for transmitting Tx pause packet : 128T + * FIFO threshold for processing next packet : 128QW + * Rx queue 0 select + * Max Rx DMA length : 128 + * Rx descriptor retry : 32 + * Rx descriptor retry time gap : 256ns + * Don't receive runt/bad frame. + */ + sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; + /* + * Since Rx FIFO size is 4K bytes, receiving frames larger + * than 4K bytes will suffer from Rx FIFO overruns. So + * decrease FIFO threshold to reduce the FIFO overruns for + * frames larger than 4000 bytes. + * For best performance of standard MTU sized frames use + * maximum allowable FIFO threshold, 128QW. + */ + if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + + ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) + sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; + else + sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; + sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); + sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); + sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; + CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); + + /* Set Rx descriptor counter. */ + CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); + + /* Set Rx ring address to the hardware. */ + paddr = JME_RX_RING_ADDR(sc, 0); + CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); + CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); + + /* Clear receive filter. */ + CSR_WRITE_4(sc, JME_RXMAC, 0); + /* Set up the receive filter. */ + jme_set_filter(sc); + jme_set_vlan(sc); + + /* + * Disable all WOL bits as WOL can interfere normal Rx + * operation. Also clear WOL detection status bits. + */ + reg = CSR_READ_4(sc, JME_PMCS); + reg &= ~PMCS_WOL_ENB_MASK; + CSR_WRITE_4(sc, JME_PMCS, reg); + + reg = CSR_READ_4(sc, JME_RXMAC); + /* + * Pad 10bytes right before received frame. This will greatly + * help Rx performance on strict-alignment architectures as + * it does not need to copy the frame to align the payload. + */ + reg |= RXMAC_PAD_10BYTES; + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) + reg |= RXMAC_CSUM_ENB; + CSR_WRITE_4(sc, JME_RXMAC, reg); + + /* Configure general purpose reg0 */ + reg = CSR_READ_4(sc, JME_GPREG0); + reg &= ~GPREG0_PCC_UNIT_MASK; + /* Set PCC timer resolution to micro-seconds unit. */ + reg |= GPREG0_PCC_UNIT_US; + /* + * Disable all shadow register posting as we have to read + * JME_INTR_STATUS register in jme_int_task. Also it seems + * that it's hard to synchronize interrupt status between + * hardware and software with shadow posting due to + * requirements of bus_dmamap_sync(9). + */ + reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | + GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | + GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | + GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; + /* Disable posting of DW0. */ + reg &= ~GPREG0_POST_DW0_ENB; + /* Clear PME message. */ + reg &= ~GPREG0_PME_ENB; + /* Set PHY address. */ + reg &= ~GPREG0_PHY_ADDR_MASK; + reg |= sc->jme_phyaddr; + CSR_WRITE_4(sc, JME_GPREG0, reg); + + /* Configure Tx queue 0 packet completion coalescing. */ + reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & + PCCTX_COAL_TO_MASK; + reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & + PCCTX_COAL_PKT_MASK; + reg |= PCCTX_COAL_TXQ0; + CSR_WRITE_4(sc, JME_PCCTX, reg); + + /* Configure Rx queue 0 packet completion coalescing. */ + reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & + PCCRX_COAL_TO_MASK; + reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & + PCCRX_COAL_PKT_MASK; + CSR_WRITE_4(sc, JME_PCCRX0, reg); + + /* Configure shadow status block but don't enable posting. */ + paddr = sc->jme_rdata.jme_ssb_block_paddr; + CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); + CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); + + /* Disable Timer 1 and Timer 2. */ + CSR_WRITE_4(sc, JME_TIMER1, 0); + CSR_WRITE_4(sc, JME_TIMER2, 0); + + /* Configure retry transmit period, retry limit value. */ + CSR_WRITE_4(sc, JME_TXTRHD, + ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & + TXTRHD_RT_PERIOD_MASK) | + ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & + TXTRHD_RT_LIMIT_SHIFT)); + + /* Disable RSS. */ + CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); + + /* Initialize the interrupt mask. */ + CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); + CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); + + /* + * Enabling Tx/Rx DMA engines and Rx queue processing is + * done after detection of valid link in jme_link_task. + */ + + sc->jme_flags &= ~JME_FLAG_LINK; + /* Set the current media. */ + mii_mediachg(mii); + + callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; +} + +static void +jme_stop(struct jme_softc *sc) +{ + struct ifnet *ifp; + struct jme_txdesc *txd; + struct jme_rxdesc *rxd; + int i; + + JME_LOCK_ASSERT(sc); + /* + * Mark the interface down and cancel the watchdog timer. + */ + ifp = sc->jme_ifp; + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + sc->jme_flags &= ~JME_FLAG_LINK; + callout_stop(&sc->jme_tick_ch); + sc->jme_watchdog_timer = 0; + + /* + * Disable interrupts. + */ + CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); + CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); + + /* Disable updating shadow status block. */ + CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, + CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); + + /* Stop receiver, transmitter. */ + jme_stop_rx(sc); + jme_stop_tx(sc); + + /* Reclaim Rx/Tx buffers that have been completed. */ + jme_rxintr(sc, JME_RX_RING_CNT); + if (sc->jme_cdata.jme_rxhead != NULL) + m_freem(sc->jme_cdata.jme_rxhead); + JME_RXCHAIN_RESET(sc); + jme_txeof(sc); + /* + * Free RX and TX mbufs still in the queues. + */ + for (i = 0; i < JME_RX_RING_CNT; i++) { + rxd = &sc->jme_cdata.jme_rxdesc[i]; + if (rxd->rx_m != NULL) { + bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, + rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, + rxd->rx_dmamap); + m_freem(rxd->rx_m); + rxd->rx_m = NULL; + } + } + for (i = 0; i < JME_TX_RING_CNT; i++) { + txd = &sc->jme_cdata.jme_txdesc[i]; + if (txd->tx_m != NULL) { + bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, + txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, + txd->tx_dmamap); + m_freem(txd->tx_m); + txd->tx_m = NULL; + txd->tx_ndesc = 0; + } + } +} + +static void +jme_stop_tx(struct jme_softc *sc) +{ + uint32_t reg; + int i; + + reg = CSR_READ_4(sc, JME_TXCSR); + if ((reg & TXCSR_TX_ENB) == 0) + return; + reg &= ~TXCSR_TX_ENB; + CSR_WRITE_4(sc, JME_TXCSR, reg); + for (i = JME_TIMEOUT; i > 0; i--) { + DELAY(1); + if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) + break; + } + if (i == 0) + device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); +} + +static void +jme_stop_rx(struct jme_softc *sc) +{ + uint32_t reg; + int i; + + reg = CSR_READ_4(sc, JME_RXCSR); + if ((reg & RXCSR_RX_ENB) == 0) + return; + reg &= ~RXCSR_RX_ENB; + CSR_WRITE_4(sc, JME_RXCSR, reg); + for (i = JME_TIMEOUT; i > 0; i--) { + DELAY(1); + if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) + break; + } + if (i == 0) + device_printf(sc->jme_dev, "stopping recevier timeout!\n"); +} + +static void +jme_init_tx_ring(struct jme_softc *sc) +{ + struct jme_ring_data *rd; + struct jme_txdesc *txd; + int i; + + sc->jme_cdata.jme_tx_prod = 0; + sc->jme_cdata.jme_tx_cons = 0; + sc->jme_cdata.jme_tx_cnt = 0; + + rd = &sc->jme_rdata; + bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); + for (i = 0; i < JME_TX_RING_CNT; i++) { + txd = &sc->jme_cdata.jme_txdesc[i]; + txd->tx_m = NULL; + txd->tx_desc = &rd->jme_tx_ring[i]; + txd->tx_ndesc = 0; + } + + bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, + sc->jme_cdata.jme_tx_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + +static void +jme_init_ssb(struct jme_softc *sc) +{ + struct jme_ring_data *rd; + + rd = &sc->jme_rdata; + bzero(rd->jme_ssb_block, JME_SSB_SIZE); + bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + +static int +jme_init_rx_ring(struct jme_softc *sc) +{ + struct jme_ring_data *rd; + struct jme_rxdesc *rxd; + int i; + + sc->jme_cdata.jme_rx_cons = 0; + JME_RXCHAIN_RESET(sc); + atomic_set_int(&sc->jme_morework, 0); + + rd = &sc->jme_rdata; + bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); + for (i = 0; i < JME_RX_RING_CNT; i++) { + rxd = &sc->jme_cdata.jme_rxdesc[i]; + rxd->rx_m = NULL; + rxd->rx_desc = &rd->jme_rx_ring[i]; + if (jme_newbuf(sc, rxd) != 0) + return (ENOBUFS); + } + + bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, + sc->jme_cdata.jme_rx_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (0); +} + +static int +jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) +{ + struct jme_desc *desc; + struct mbuf *m; + bus_dma_segment_t segs[1]; + bus_dmamap_t map; + int nsegs; + + m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m == NULL) + return (ENOBUFS); + /* + * JMC250 has 64bit boundary alignment limitation so jme(4) + * takes advantage of 10 bytes padding feature of hardware + * in order not to copy entire frame to align IP header on + * 32bit boundary. + */ + m->m_len = m->m_pkthdr.len = MCLBYTES; + + if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, + sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { + m_freem(m); + return (ENOBUFS); + } + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); + + if (rxd->rx_m != NULL) { + bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); + } + map = rxd->rx_dmamap; + rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; + sc->jme_cdata.jme_rx_sparemap = map; + bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, + BUS_DMASYNC_PREREAD); + rxd->rx_m = m; + + desc = rxd->rx_desc; + desc->buflen = htole32(segs[0].ds_len); + desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); + desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); + desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); + + return (0); +} + +static void +jme_set_vlan(struct jme_softc *sc) +{ + struct ifnet *ifp; + uint32_t reg; + + JME_LOCK_ASSERT(sc); + + ifp = sc->jme_ifp; + reg = CSR_READ_4(sc, JME_RXMAC); + reg &= ~RXMAC_VLAN_ENB; + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) + reg |= RXMAC_VLAN_ENB; + CSR_WRITE_4(sc, JME_RXMAC, reg); +} + +static void +jme_set_filter(struct jme_softc *sc) +{ + struct ifnet *ifp; + struct ifmultiaddr *ifma; + uint32_t crc; + uint32_t mchash[2]; + uint32_t rxcfg; + + JME_LOCK_ASSERT(sc); + + ifp = sc->jme_ifp; + + rxcfg = CSR_READ_4(sc, JME_RXMAC); + rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | + RXMAC_ALLMULTI); + /* Always accept frames destined to our station address. */ + rxcfg |= RXMAC_UNICAST; + if ((ifp->if_flags & IFF_BROADCAST) != 0) + rxcfg |= RXMAC_BROADCAST; + if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { + if ((ifp->if_flags & IFF_PROMISC) != 0) + rxcfg |= RXMAC_PROMISC; + if ((ifp->if_flags & IFF_ALLMULTI) != 0) + rxcfg |= RXMAC_ALLMULTI; + CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); + CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); + CSR_WRITE_4(sc, JME_RXMAC, rxcfg); + return; + } + + /* + * Set up the multicast address filter by passing all multicast + * addresses through a CRC generator, and then using the low-order + * 6 bits as an index into the 64 bit multicast hash table. The + * high order bits select the register, while the rest of the bits + * select the bit within the register. + */ + rxcfg |= RXMAC_MULTICAST; + bzero(mchash, sizeof(mchash)); + + IF_ADDR_LOCK(ifp); + TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) + ifma->ifma_addr), ETHER_ADDR_LEN); + + /* Just want the 6 least significant bits. */ + crc &= 0x3f; + + /* Set the corresponding bit in the hash table. */ + mchash[crc >> 5] |= 1 << (crc & 0x1f); + } + IF_ADDR_UNLOCK(ifp); + + CSR_WRITE_4(sc, JME_MAR0, mchash[0]); + CSR_WRITE_4(sc, JME_MAR1, mchash[1]); + CSR_WRITE_4(sc, JME_RXMAC, rxcfg); +} + +static int +sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) +{ + int error, value; + + if (arg1 == NULL) + return (EINVAL); + value = *(int *)arg1; + error = sysctl_handle_int(oidp, &value, 0, req); + if (error || req->newptr == NULL) + return (error); + if (value < low || value > high) + return (EINVAL); + *(int *)arg1 = value; + + return (0); +} + +static int +sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) +{ + return (sysctl_int_range(oidp, arg1, arg2, req, + PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); +} + +static int +sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) +{ + return (sysctl_int_range(oidp, arg1, arg2, req, + PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); +} + +static int +sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) +{ + return (sysctl_int_range(oidp, arg1, arg2, req, + PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); +} + +static int +sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) +{ + return (sysctl_int_range(oidp, arg1, arg2, req, + PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); +} + +static int +sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) +{ + return (sysctl_int_range(oidp, arg1, arg2, req, + JME_PROC_MIN, JME_PROC_MAX)); +} --- /dev/null 2008-07-31 19:33:03.000000000 +0900 +++ sys/dev/jme/if_jmereg.h 2008-07-28 09:27:54.000000000 +0900 @@ -0,0 +1,1010 @@ +/*- + * Copyright (c) 2008, Pyun YongHyeon + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: stable/6/sys/dev/jme/if_jmereg.h 180856 2008-07-28 00:29:26Z yongari $ + */ + +#ifndef _IF_JMEREG_H +#define _IF_JMEREG_H + +/* + * JMicron Inc. PCI vendor ID + */ +#define VENDORID_JMICRON 0x197B + +/* + * JMC250 PCI device ID + */ +#define DEVICEID_JMC250 0x0250 +#define DEVICEREVID_JMC250 0x10 + +/* + * JMC260 PCI device ID + */ +#define DEVICEID_JMC260 0x0260 +#define DEVICEREVID_JMC260 0x20 + +/* JMC250 PCI configuration register. */ +#define JME_PCI_BAR0 0x10 /* 16KB memory window. */ + +#define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ + +#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ + +#define JME_PCI_BAR3 0x20 /* 64KB memory window. */ + +#define JME_PCI_EROM 0x30 + +#define JME_PCI_DBG 0x9C + +#define JME_PCI_SPI 0xB0 + +#define SPI_ENB 0x00000010 +#define SPI_SO_STATUS 0x00000008 +#define SPI_SI_CTRL 0x00000004 +#define SPI_SCK_CTRL 0x00000002 +#define SPI_CS_N_CTRL 0x00000001 + +#define JME_PCI_PHYCFG0 0xC0 + +#define JME_PCI_PHYCFG1 0xC4 + +#define JME_PCI_PHYCFG2 0xC8 + +#define JME_PCI_PHYCFG3 0xCC + +#define JME_PCI_PIPECTL1 0xD0 + +#define JME_PCI_PIPECTL2 0xD4 + +/* PCIe link error/status. */ +#define JME_PCI_LES 0xD8 + +/* propeietary register 0. */ +#define JME_PCI_PE0 0xE0 +#define PE0_SPI_EXIST 0x00200000 +#define PE0_PME_D0 0x00100000 +#define PE0_PME_D3H 0x00080000 +#define PE0_PME_SPI_PAD 0x00040000 +#define PE0_MASK_ASPM 0x00020000 +#define PE0_EEPROM_RW_DIS 0x00008000 +#define PE0_PCI_INTA 0x00001000 +#define PE0_PCI_INTB 0x00002000 +#define PE0_PCI_INTC 0x00003000 +#define PE0_PCI_INTD 0x00004000 +#define PE0_PCI_SVSSID_WR_ENB 0x00000800 +#define PE0_MSIX_SIZE_8 0x00000700 +#define PE0_MSIX_SIZE_7 0x00000600 +#define PE0_MSIX_SIZE_6 0x00000500 +#define PE0_MSIX_SIZE_5 0x00000400 +#define PE0_MSIX_SIZE_4 0x00000300 +#define PE0_MSIX_SIZE_3 0x00000200 +#define PE0_MSIX_SIZE_2 0x00000100 +#define PE0_MSIX_SIZE_1 0x00000000 +#define PE0_MSIX_SIZE_DEF 0x00000700 +#define PE0_MSIX_CAP_DIS 0x00000080 +#define PE0_MSI_PVMC_ENB 0x00000040 +#define PE0_LCAP_EXIT_LAT_MASK 0x00000038 +#define PE0_LCAP_EXIT_LAT_DEF 0x00000038 +#define PE0_PM_AUXC_MASK 0x00000007 +#define PE0_PM_AUXC_DEF 0x00000007 + +#define JME_PCI_PE1 0xE4 + +#define JME_PCI_PHYTEST 0xF8 + +#define JME_PCI_GPR 0xFC + +/* + * JMC Register Map. + * ----------------------------------------------------------------------- + * Register Size IO space Memory space + * ----------------------------------------------------------------------- + * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ + * BAR1 + 0x7F BAR0 + 0x7F + * ----------------------------------------------------------------------- + * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ + * BAR2 + 0x7F BAR0 + 0x47F + * ----------------------------------------------------------------------- + * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ + * BAR2 + 0x7F BAR0 + 0x87F + * ----------------------------------------------------------------------- + * To simplify register access fuctions and to get better performance + * this driver doesn't support IO space access. It could be implemented + * as a function which selects appropriate BARs to access requested + * register. + */ + +/* Tx control and status. */ +#define JME_TXCSR 0x0000 +#define TXCSR_QWEIGHT_MASK 0x0F000000 +#define TXCSR_QWEIGHT_SHIFT 24 +#define TXCSR_TXQ_SEL_MASK 0x00070000 +#define TXCSR_TXQ_SEL_SHIFT 16 +#define TXCSR_TXQ_START 0x00000001 +#define TXCSR_TXQ_START_SHIFT 8 +#define TXCSR_FIFO_THRESH_4QW 0x00000000 +#define TXCSR_FIFO_THRESH_8QW 0x00000040 +#define TXCSR_FIFO_THRESH_12QW 0x00000080 +#define TXCSR_FIFO_THRESH_16QW 0x000000C0 +#define TXCSR_DMA_SIZE_64 0x00000000 +#define TXCSR_DMA_SIZE_128 0x00000010 +#define TXCSR_DMA_SIZE_256 0x00000020 +#define TXCSR_DMA_SIZE_512 0x00000030 +#define TXCSR_DMA_BURST 0x00000004 +#define TXCSR_TX_SUSPEND 0x00000002 +#define TXCSR_TX_ENB 0x00000001 +#define TXCSR_TXQ0 0 +#define TXCSR_TXQ1 1 +#define TXCSR_TXQ2 2 +#define TXCSR_TXQ3 3 +#define TXCSR_TXQ4 4 +#define TXCSR_TXQ5 5 +#define TXCSR_TXQ6 6 +#define TXCSR_TXQ7 7 +#define TXCSR_TXQ_WEIGHT(x) \ + (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) +#define TXCSR_TXQ_WEIGHT_MIN 0 +#define TXCSR_TXQ_WEIGHT_MAX 15 +#define TXCSR_TXQ_N_SEL(x) \ + (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) +#define TXCSR_TXQ_N_START(x) \ + (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) + +/* Tx queue descriptor base address. 16bytes alignment required. */ +#define JME_TXDBA_LO 0x0004 +#define JME_TXDBA_HI 0x0008 + +/* Tx queue descriptor count. multiple of 16(max = 1024). */ +#define JME_TXQDC 0x000C +#define TXQDC_MASK 0x0000007F0 + +/* Tx queue next descriptor address. */ +#define JME_TXNDA 0x0010 +#define TXNDA_ADDR_MASK 0xFFFFFFF0 +#define TXNDA_DESC_EMPTY 0x00000008 +#define TXNDA_DESC_VALID 0x00000004 +#define TXNDA_DESC_WAIT 0x00000002 +#define TXNDA_DESC_FETCH 0x00000001 + +/* Tx MAC control ans status. */ +#define JME_TXMAC 0x0014 +#define TXMAC_IFG2_MASK 0xC0000000 +#define TXMAC_IFG2_DEFAULT 0x40000000 +#define TXMAC_IFG1_MASK 0x30000000 +#define TXMAC_IFG1_DEFAULT 0x20000000 +#define TXMAC_THRESH_1_PKT 0x00000300 +#define TXMAC_THRESH_1_2_PKT 0x00000200 +#define TXMAC_THRESH_1_4_PKT 0x00000100 +#define TXMAC_THRESH_1_8_PKT 0x00000000 +#define TXMAC_FRAME_BURST 0x00000080 +#define TXMAC_CARRIER_EXT 0x00000040 +#define TXMAC_IFG_ENB 0x00000020 +#define TXMAC_BACKOFF 0x00000010 +#define TXMAC_CARRIER_SENSE 0x00000008 +#define TXMAC_COLL_ENB 0x00000004 +#define TXMAC_CRC_ENB 0x00000002 +#define TXMAC_PAD_ENB 0x00000001 + +/* Tx pause frame control. */ +#define JME_TXPFC 0x0018 +#define TXPFC_VLAN_TAG_MASK 0xFFFF0000 +#define TXPFC_VLAN_TAG_SHIFT 16 +#define TXPFC_VLAN_ENB 0x00008000 +#define TXPFC_PAUSE_ENB 0x00000001 + +/* Tx timer/retry at half duplex. */ +#define JME_TXTRHD 0x001C +#define TXTRHD_RT_PERIOD_ENB 0x80000000 +#define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 +#define TXTRHD_RT_PERIOD_SHIFT 8 +#define TXTRHD_RT_LIMIT_ENB 0x00000080 +#define TXTRHD_RT_LIMIT_MASK 0x0000007F +#define TXTRHD_RT_LIMIT_SHIFT 0 +#define TXTRHD_RT_PERIOD_DEFAULT 8192 +#define TXTRHD_RT_LIMIT_DEFAULT 8 + +/* Rx control & status. */ +#define JME_RXCSR 0x0020 +#define RXCSR_FIFO_FTHRESH_16T 0x00000000 +#define RXCSR_FIFO_FTHRESH_32T 0x10000000 +#define RXCSR_FIFO_FTHRESH_64T 0x20000000 +#define RXCSR_FIFO_FTHRESH_128T 0x30000000 +#define RXCSR_FIFO_FTHRESH_MASK 0x30000000 +#define RXCSR_FIFO_THRESH_16QW 0x00000000 +#define RXCSR_FIFO_THRESH_32QW 0x04000000 +#define RXCSR_FIFO_THRESH_64QW 0x08000000 +#define RXCSR_FIFO_THRESH_128QW 0x0C000000 +#define RXCSR_FIFO_THRESH_MASK 0x0C000000 +#define RXCSR_DMA_SIZE_16 0x00000000 +#define RXCSR_DMA_SIZE_32 0x01000000 +#define RXCSR_DMA_SIZE_64 0x02000000 +#define RXCSR_DMA_SIZE_128 0x03000000 +#define RXCSR_RXQ_SEL_MASK 0x00030000 +#define RXCSR_RXQ_SEL_SHIFT 16 +#define RXCSR_DESC_RT_GAP_MASK 0x0000F000 +#define RXCSR_DESC_RT_GAP_SHIFT 12 +#define RXCSR_DESC_RT_GAP_256 0x00000000 +#define RXCSR_DESC_RT_GAP_512 0x00001000 +#define RXCSR_DESC_RT_GAP_1024 0x00002000 +#define RXCSR_DESC_RT_GAP_2048 0x00003000 +#define RXCSR_DESC_RT_GAP_4096 0x00004000 +#define RXCSR_DESC_RT_GAP_8192 0x00005000 +#define RXCSR_DESC_RT_GAP_16384 0x00006000 +#define RXCSR_DESC_RT_GAP_32768 0x00007000 +#define RXCSR_DESC_RT_CNT_MASK 0x00000F00 +#define RXCSR_DESC_RT_CNT_SHIFT 8 +#define RXCSR_PASS_WAKEUP_PKT 0x00000040 +#define RXCSR_PASS_MAGIC_PKT 0x00000020 +#define RXCSR_PASS_RUNT_PKT 0x00000010 +#define RXCSR_PASS_BAD_PKT 0x00000008 +#define RXCSR_RXQ_START 0x00000004 +#define RXCSR_RX_SUSPEND 0x00000002 +#define RXCSR_RX_ENB 0x00000001 + +#define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) +#define RXCSR_RXQ0 0 +#define RXCSR_RXQ1 1 +#define RXCSR_RXQ2 2 +#define RXCSR_RXQ3 3 +#define RXCSR_DESC_RT_CNT(x) \ + ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) +#define RXCSR_DESC_RT_CNT_DEFAULT 32 + +/* Rx queue descriptor base address. 16bytes alignment needed. */ +#define JME_RXDBA_LO 0x0024 +#define JME_RXDBA_HI 0x0028 + +/* Rx queue descriptor count. multiple of 16(max = 1024). */ +#define JME_RXQDC 0x002C +#define RXQDC_MASK 0x0000007F0 + +/* Rx queue next descriptor address. */ +#define JME_RXNDA 0x0030 +#define RXNDA_ADDR_MASK 0xFFFFFFF0 +#define RXNDA_DESC_EMPTY 0x00000008 +#define RXNDA_DESC_VALID 0x00000004 +#define RXNDA_DESC_WAIT 0x00000002 +#define RXNDA_DESC_FETCH 0x00000001 + +/* Rx MAC control and status. */ +#define JME_RXMAC 0x0034 +#define RXMAC_RSS_UNICAST 0x00000000 +#define RXMAC_RSS_UNI_MULTICAST 0x00010000 +#define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 +#define RXMAC_RSS_ALLFRAME 0x00030000 +#define RXMAC_PROMISC 0x00000800 +#define RXMAC_BROADCAST 0x00000400 +#define RXMAC_MULTICAST 0x00000200 +#define RXMAC_UNICAST 0x00000100 +#define RXMAC_ALLMULTI 0x00000080 +#define RXMAC_MULTICAST_FILTER 0x00000040 +#define RXMAC_COLL_DET_ENB 0x00000020 +#define RXMAC_FC_ENB 0x00000008 +#define RXMAC_VLAN_ENB 0x00000004 +#define RXMAC_PAD_10BYTES 0x00000002 +#define RXMAC_CSUM_ENB 0x00000001 + +/* Rx unicast MAC address. */ +#define JME_PAR0 0x0038 +#define JME_PAR1 0x003C + +/* Rx multicast address hash table. */ +#define JME_MAR0 0x0040 +#define JME_MAR1 0x0044 + +/* Wakeup frame output data port. */ +#define JME_WFODP 0x0048 + +/* Wakeup frame output interface. */ +#define JME_WFOI 0x004C +#define WFOI_MASK_0_31 0x00000000 +#define WFOI_MASK_31_63 0x00000010 +#define WFOI_MASK_64_95 0x00000020 +#define WFOI_MASK_96_127 0x00000030 +#define WFOI_MASK_SEL 0x00000008 +#define WFOI_CRC_SEL 0x00000000 +#define WFOI_WAKEUP_FRAME_MASK 0x00000007 +#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) + +/* Station management interface. */ +#define JME_SMI 0x0050 +#define SMI_DATA_MASK 0xFFFF0000 +#define SMI_DATA_SHIFT 16 +#define SMI_REG_ADDR_MASK 0x0000F800 +#define SMI_REG_ADDR_SHIFT 11 +#define SMI_PHY_ADDR_MASK 0x000007C0 +#define SMI_PHY_ADDR_SHIFT 6 +#define SMI_OP_WRITE 0x00000020 +#define SMI_OP_READ 0x00000000 +#define SMI_OP_EXECUTE 0x00000010 +#define SMI_MDIO 0x00000008 +#define SMI_MDOE 0x00000004 +#define SMI_MDC 0x00000002 +#define SMI_MDEN 0x00000001 +#define SMI_REG_ADDR(x) \ + (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) +#define SMI_PHY_ADDR(x) \ + (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) + +/* Global host control. */ +#define JME_GHC 0x0054 +#define GHC_LOOPBACK 0x80000000 +#define GHC_RESET 0x40000000 +#define GHC_FULL_DUPLEX 0x00000040 +#define GHC_SPEED_UNKNOWN 0x00000000 +#define GHC_SPEED_10 0x00000010 +#define GHC_SPEED_100 0x00000020 +#define GHC_SPEED_1000 0x00000030 +#define GHC_SPEED_MASK 0x00000030 +#define GHC_LINK_OFF 0x00000004 +#define GHC_LINK_ON 0x00000002 +#define GHC_LINK_STAT_POLLING 0x00000001 + +/* Power management control and status. */ +#define JME_PMCS 0x0060 +#define PMCS_WAKEUP_FRAME_7 0x80000000 +#define PMCS_WAKEUP_FRAME_6 0x40000000 +#define PMCS_WAKEUP_FRAME_5 0x20000000 +#define PMCS_WAKEUP_FRAME_4 0x10000000 +#define PMCS_WAKEUP_FRAME_3 0x08000000 +#define PMCS_WAKEUP_FRAME_2 0x04000000 +#define PMCS_WAKEUP_FRAME_1 0x02000000 +#define PMCS_WAKEUP_FRAME_0 0x01000000 +#define PMCS_LINK_FAIL 0x00040000 +#define PMCS_LINK_RISING 0x00020000 +#define PMCS_MAGIC_FRAME 0x00010000 +#define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 +#define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 +#define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 +#define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 +#define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 +#define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 +#define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 +#define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 +#define PMCS_LINK_FAIL_ENB 0x00000004 +#define PMCS_LINK_RISING_ENB 0x00000002 +#define PMCS_MAGIC_FRAME_ENB 0x00000001 +#define PMCS_WOL_ENB_MASK 0x0000FFFF + +/* Giga PHY & EEPROM registers. */ +#define JME_PHY_EEPROM_BASE_ADDR 0x0400 + +#define JME_GIGAR0LO 0x0400 +#define JME_GIGAR0HI 0x0404 +#define JME_GIGARALO 0x0408 +#define JME_GIGARAHI 0x040C +#define JME_GIGARBLO 0x0410 +#define JME_GIGARBHI 0x0414 +#define JME_GIGARCLO 0x0418 +#define JME_GIGARCHI 0x041C +#define JME_GIGARDLO 0x0420 +#define JME_GIGARDHI 0x0424 + +/* BIST status and control. */ +#define JME_GIGACSR 0x0428 +#define GIGACSR_STATUS 0x40000000 +#define GIGACSR_CTRL_MASK 0x30000000 +#define GIGACSR_CTRL_DEFAULT 0x30000000 +#define GIGACSR_TX_CLK_MASK 0x0F000000 +#define GIGACSR_RX_CLK_MASK 0x00F00000 +#define GIGACSR_TX_CLK_INV 0x00080000 +#define GIGACSR_RX_CLK_INV 0x00040000 +#define GIGACSR_PHY_RST 0x00010000 +#define GIGACSR_IRQ_N_O 0x00001000 +#define GIGACSR_BIST_OK 0x00000200 +#define GIGACSR_BIST_DONE 0x00000100 +#define GIGACSR_BIST_LED_ENB 0x00000010 +#define GIGACSR_BIST_MASK 0x00000003 + +/* PHY Link Status. */ +#define JME_LNKSTS 0x0430 +#define LINKSTS_SPEED_10 0x00000000 +#define LINKSTS_SPEED_100 0x00004000 +#define LINKSTS_SPEED_1000 0x00008000 +#define LINKSTS_FULL_DUPLEX 0x00002000 +#define LINKSTS_PAGE_RCVD 0x00001000 +#define LINKSTS_SPDDPX_RESOLVED 0x00000800 +#define LINKSTS_UP 0x00000400 +#define LINKSTS_ANEG_COMP 0x00000200 +#define LINKSTS_MDI_CROSSOVR 0x00000040 +#define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 +#define LINKSTS_LPAR_PAUSE 0x00000001 + +/* SMB control and status. */ +#define JME_SMBCSR 0x0440 +#define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 +#define SMBCSR_WR_DATA_NACK 0x00040000 +#define SMBCSR_CMD_NACK 0x00020000 +#define SMBCSR_RELOAD 0x00010000 +#define SMBCSR_CMD_ADDR_MASK 0x0000FF00 +#define SMBCSR_SCL_STAT 0x00000080 +#define SMBCSR_SDA_STAT 0x00000040 +#define SMBCSR_EEPROM_PRESENT 0x00000020 +#define SMBCSR_INIT_LD_DONE 0x00000010 +#define SMBCSR_HW_BUSY_MASK 0x0000000F +#define SMBCSR_HW_IDLE 0x00000000 + +/* SMB interface. */ +#define JME_SMBINTF 0x0444 +#define SMBINTF_RD_DATA_MASK 0xFF000000 +#define SMBINTF_RD_DATA_SHIFT 24 +#define SMBINTF_WR_DATA_MASK 0x00FF0000 +#define SMBINTF_WR_DATA_SHIFT 16 +#define SMBINTF_ADDR_MASK 0x0000FF00 +#define SMBINTF_ADDR_SHIFT 8 +#define SMBINTF_RD 0x00000020 +#define SMBINTF_WR 0x00000000 +#define SMBINTF_CMD_TRIGGER 0x00000010 +#define SMBINTF_BUSY 0x00000010 +#define SMBINTF_FAST_MODE 0x00000008 +#define SMBINTF_GPIO_SCL 0x00000004 +#define SMBINTF_GPIO_SDA 0x00000002 +#define SMBINTF_GPIO_ENB 0x00000001 + +#define JME_EEPROM_SIG0 0x55 +#define JME_EEPROM_SIG1 0xAA +#define JME_EEPROM_DESC_BYTES 3 +#define JME_EEPROM_DESC_END 0x80 +#define JME_EEPROM_FUNC_MASK 0x70 +#define JME_EEPROM_FUNC_SHIFT 4 +#define JME_EEPROM_PAGE_MASK 0x0F +#define JME_EEPROM_PAGE_SHIFT 0 + +#define JME_EEPROM_FUNC0 0 +/* PCI configuration space. */ +#define JME_EEPROM_PAGE_BAR0 0 +/* 128 bytes I/O window. */ +#define JME_EEPROM_PAGE_BAR1 1 +/* 256 bytes I/O window. */ +#define JME_EEPROM_PAGE_BAR2 2 + +#define JME_EEPROM_END 0xFF + +#define JME_EEPROM_MKDESC(f, p) \ + ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ + (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) + +/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ +#define JME_EEPINTF 0x0448 +#define EEPINTF_DATA_MASK 0xFFFF0000 +#define EEPINTF_DATA_SHIFT 16 +#define EEPINTF_ADDR_MASK 0x0000FC00 +#define EEPINTF_ADDR_SHIFT 10 +#define EEPRINTF_OP_MASK 0x00000300 +#define EEPINTF_OP_EXECUTE 0x00000080 +#define EEPINTF_DATA_OUT 0x00000008 +#define EEPINTF_DATA_IN 0x00000004 +#define EEPINTF_CLK 0x00000002 +#define EEPINTF_SEL 0x00000001 + +/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ +#define JME_EEPCSR 0x044C +#define EEPCSR_EEPROM_RELOAD 0x00000002 +#define EEPCSR_EEPROM_PRESENT 0x00000001 + +/* Misc registers. */ +#define JME_MISC_BASE_ADDR 0x800 + +/* Timer control and status. */ +#define JME_TMCSR 0x0800 +#define TMCSR_SW_INTR 0x80000000 +#define TMCSR_TIMER_INTR 0x10000000 +#define TMCSR_TIMER_ENB 0x01000000 +#define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF + +/* GPIO control and status. */ +#define JME_GPIO 0x0804 +#define GPIO_4_SPI_IN 0x80000000 +#define GPIO_3_SPI_IN 0x40000000 +#define GPIO_4_SPI_OUT 0x20000000 +#define GPIO_4_SPI_OUT_ENB 0x10000000 +#define GPIO_3_SPI_OUT 0x08000000 +#define GPIO_3_SPI_OUT_ENB 0x04000000 +#define GPIO_3_4_LED 0x00000000 +#define GPIO_3_4_GPIO 0x02000000 +#define GPIO_2_CLKREQN_IN 0x00100000 +#define GPIO_2_CLKREQN_OUT 0x00040000 +#define GPIO_2_CLKREQN_OUT_ENB 0x00020000 +#define GPIO_1_LED42_IN 0x00001000 +#define GPIO_1_LED42_OUT 0x00000400 +#define GPIO_1_LED42_OUT_ENB 0x00000200 +#define GPIO_1_LED42_ENB 0x00000100 +#define GPIO_0_SDA_IN 0x00000010 +#define GPIO_0_SDA_OUT 0x00000004 +#define GPIO_0_SDA_OUT_ENB 0x00000002 +#define GPIO_0_SDA_ENB 0x00000001 + +/* General purpose register 0. */ +#define JME_GPREG0 0x0808 +#define GPREG0_SH_POST_DW7_DIS 0x80000000 +#define GPREG0_SH_POST_DW6_DIS 0x40000000 +#define GPREG0_SH_POST_DW5_DIS 0x20000000 +#define GPREG0_SH_POST_DW4_DIS 0x10000000 +#define GPREG0_SH_POST_DW3_DIS 0x08000000 +#define GPREG0_SH_POST_DW2_DIS 0x04000000 +#define GPREG0_SH_POST_DW1_DIS 0x02000000 +#define GPREG0_SH_POST_DW0_DIS 0x01000000 +#define GPREG0_DMA_RD_REQ_8 0x00000000 +#define GPREG0_DMA_RD_REQ_6 0x00100000 +#define GPREG0_DMA_RD_REQ_5 0x00200000 +#define GPREG0_DMA_RD_REQ_4 0x00300000 +#define GPREG0_POST_DW0_ENB 0x00040000 +#define GPREG0_PCC_CLR_DIS 0x00020000 +#define GPREG0_FORCE_SCL_OUT 0x00010000 +#define GPREG0_DL_RSTB_DIS 0x00008000 +#define GPREG0_STICKY_RESET 0x00004000 +#define GPREG0_DL_RSTB_CFG_DIS 0x00002000 +#define GPREG0_LINK_CHG_POLL 0x00001000 +#define GPREG0_LINK_CHG_DIRECT 0x00000000 +#define GPREG0_MSI_GEN_SEL 0x00000800 +#define GPREG0_SMB_PAD_PU_DIS 0x00000400 +#define GPREG0_PCC_UNIT_16US 0x00000000 +#define GPREG0_PCC_UNIT_256US 0x00000100 +#define GPREG0_PCC_UNIT_US 0x00000200 +#define GPREG0_PCC_UNIT_MS 0x00000300 +#define GPREG0_PCC_UNIT_MASK 0x00000300 +#define GPREG0_INTR_EVENT_ENB 0x00000080 +#define GPREG0_PME_ENB 0x00000020 +#define GPREG0_PHY_ADDR_MASK 0x0000001F +#define GPREG0_PHY_ADDR_SHIFT 0 +#define GPREG0_PHY_ADDR 1 + +/* General purpose register 1. reserved for future use. */ +#define JME_GPREG1 0x080C + +/* MSIX entry number of interrupt source. */ +#define JME_MSINUM_BASE 0x0810 +#define JME_MSINUM_END 0x081F +#define MSINUM_MASK 0x7FFFFFFF +#define MSINUM_ENTRY_MASK 7 +#define MSINUM_REG_INDEX(x) ((x) / 8) +#define MSINUM_INTR_SOURCE(x, y) \ + (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) +#define MSINUM_NUM_INTR_SOURCE 32 + +/* Interrupt event status. */ +#define JME_INTR_STATUS 0x0820 +#define INTR_SW 0x80000000 +#define INTR_TIMER 0x40000000 +#define INTR_LINKCHG 0x20000000 +#define INTR_PAUSE 0x10000000 +#define INTR_MAGIC_PKT 0x08000000 +#define INTR_WAKEUP_PKT 0x04000000 +#define INTR_RXQ0_COAL_TO 0x02000000 +#define INTR_RXQ1_COAL_TO 0x01000000 +#define INTR_RXQ2_COAL_TO 0x00800000 +#define INTR_RXQ3_COAL_TO 0x00400000 +#define INTR_TXQ_COAL_TO 0x00200000 +#define INTR_RXQ0_COAL 0x00100000 +#define INTR_RXQ1_COAL 0x00080000 +#define INTR_RXQ2_COAL 0x00040000 +#define INTR_RXQ3_COAL 0x00020000 +#define INTR_TXQ_COAL 0x00010000 +#define INTR_RXQ3_DESC_EMPTY 0x00008000 +#define INTR_RXQ2_DESC_EMPTY 0x00004000 +#define INTR_RXQ1_DESC_EMPTY 0x00002000 +#define INTR_RXQ0_DESC_EMPTY 0x00001000 +#define INTR_RXQ3_COMP 0x00000800 +#define INTR_RXQ2_COMP 0x00000400 +#define INTR_RXQ1_COMP 0x00000200 +#define INTR_RXQ0_COMP 0x00000100 +#define INTR_TXQ7_COMP 0x00000080 +#define INTR_TXQ6_COMP 0x00000040 +#define INTR_TXQ5_COMP 0x00000020 +#define INTR_TXQ4_COMP 0x00000010 +#define INTR_TXQ3_COMP 0x00000008 +#define INTR_TXQ2_COMP 0x00000004 +#define INTR_TXQ1_COMP 0x00000002 +#define INTR_TXQ0_COMP 0x00000001 + +#define INTR_RXQ_COAL_TO \ + (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ + INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) + +#define INTR_RXQ_COAL \ + (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ + INTR_RXQ3_COAL) + +#define INTR_RXQ_COMP \ + (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ + INTR_RXQ3_COMP) + +#define INTR_RXQ_DESC_EMPTY \ + (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ + INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) + +#define INTR_RXQ_COMP \ + (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ + INTR_RXQ3_COMP) + +#define INTR_TXQ_COMP \ + (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ + INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ + INTR_TXQ6_COMP | INTR_TXQ7_COMP) + +#define JME_INTRS \ + (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ + INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) + +#define N_INTR_SW 31 +#define N_INTR_TIMER 30 +#define N_INTR_LINKCHG 29 +#define N_INTR_PAUSE 28 +#define N_INTR_MAGIC_PKT 27 +#define N_INTR_WAKEUP_PKT 26 +#define N_INTR_RXQ0_COAL_TO 25 +#define N_INTR_RXQ1_COAL_TO 24 +#define N_INTR_RXQ2_COAL_TO 23 +#define N_INTR_RXQ3_COAL_TO 22 +#define N_INTR_TXQ_COAL_TO 21 +#define N_INTR_RXQ0_COAL 20 +#define N_INTR_RXQ1_COAL 19 +#define N_INTR_RXQ2_COAL 18 +#define N_INTR_RXQ3_COAL 17 +#define N_INTR_TXQ_COAL 16 +#define N_INTR_RXQ3_DESC_EMPTY 15 +#define N_INTR_RXQ2_DESC_EMPTY 14 +#define N_INTR_RXQ1_DESC_EMPTY 13 +#define N_INTR_RXQ0_DESC_EMPTY 12 +#define N_INTR_RXQ3_COMP 11 +#define N_INTR_RXQ2_COMP 10 +#define N_INTR_RXQ1_COMP 9 +#define N_INTR_RXQ0_COMP 8 +#define N_INTR_TXQ7_COMP 7 +#define N_INTR_TXQ6_COMP 6 +#define N_INTR_TXQ5_COMP 5 +#define N_INTR_TXQ4_COMP 4 +#define N_INTR_TXQ3_COMP 3 +#define N_INTR_TXQ2_COMP 2 +#define N_INTR_TXQ1_COMP 1 +#define N_INTR_TXQ0_COMP 0 + +/* Interrupt request status. */ +#define JME_INTR_REQ_STATUS 0x0824 + +/* Interrupt enable - setting port. */ +#define JME_INTR_MASK_SET 0x0828 + +/* Interrupt enable - clearing port. */ +#define JME_INTR_MASK_CLR 0x082C + +/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ +#define JME_PCCRX0 0x0830 +#define JME_PCCRX1 0x0834 +#define JME_PCCRX2 0x0838 +#define JME_PCCRX3 0x083C +#define PCCRX_COAL_TO_MASK 0xFFFF0000 +#define PCCRX_COAL_TO_SHIFT 16 +#define PCCRX_COAL_PKT_MASK 0x0000FF00 +#define PCCRX_COAL_PKT_SHIFT 8 + +#define PCCRX_COAL_TO_MIN 1 +#define PCCRX_COAL_TO_DEFAULT 100 +#define PCCRX_COAL_TO_MAX 65535 + +#define PCCRX_COAL_PKT_MIN 1 +#define PCCRX_COAL_PKT_DEFAULT 2 +#define PCCRX_COAL_PKT_MAX 255 + +/* Packet completion coalescing control of Tx queue. */ +#define JME_PCCTX 0x0840 +#define PCCTX_COAL_TO_MASK 0xFFFF0000 +#define PCCTX_COAL_TO_SHIFT 16 +#define PCCTX_COAL_PKT_MASK 0x0000FF00 +#define PCCTX_COAL_PKT_SHIFT 8 +#define PCCTX_COAL_TXQ7 0x00000080 +#define PCCTX_COAL_TXQ6 0x00000040 +#define PCCTX_COAL_TXQ5 0x00000020 +#define PCCTX_COAL_TXQ4 0x00000010 +#define PCCTX_COAL_TXQ3 0x00000008 +#define PCCTX_COAL_TXQ2 0x00000004 +#define PCCTX_COAL_TXQ1 0x00000002 +#define PCCTX_COAL_TXQ0 0x00000001 + +#define PCCTX_COAL_TO_MIN 1 +#define PCCTX_COAL_TO_DEFAULT 100 +#define PCCTX_COAL_TO_MAX 65535 + +#define PCCTX_COAL_PKT_MIN 1 +#define PCCTX_COAL_PKT_DEFAULT 8 +#define PCCTX_COAL_PKT_MAX 255 + +/* Chip mode and FPGA version. */ +#define JME_CHIPMODE 0x0844 +#define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 +#define CHIPMODE_FPGA_REV_SHIFT 16 +#define CHIPMODE_NOT_FPGA 0 +#define CHIPMODE_REV_MASK 0x0000FF00 +#define CHIPMODE_REV_SHIFT 8 +#define CHIPMODE_MODE_48P 0x0000000C +#define CHIPMODE_MODE_64P 0x00000004 +#define CHIPMODE_MODE_128P_MAC 0x00000003 +#define CHIPMODE_MODE_128P_DBG 0x00000002 +#define CHIPMODE_MODE_128P_PHY 0x00000000 + +/* Shadow status base address high/low. */ +#define JME_SHBASE_ADDR_HI 0x0848 +#define JME_SHBASE_ADDR_LO 0x084C +#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 +#define SHBASE_POST_FORCE 0x00000002 +#define SHBASE_POST_ENB 0x00000001 + +/* Timer 1 and 2. */ +#define JME_TIMER1 0x0870 +#define JME_TIMER2 0x0874 +#define TIMER_ENB 0x01000000 +#define TIMER_CNT_MASK 0x00FFFFFF +#define TIMER_CNT_SHIFT 0 +#define TIMER_UNIT 1024 /* 1024us */ + +/* Aggresive power mode control. */ +#define JME_APMC 0x087C +#define APMC_PCIE_SDOWN_STAT 0x80000000 +#define APMC_PCIE_SDOWN_ENB 0x40000000 +#define APMC_PSEUDO_HOT_PLUG 0x20000000 +#define APMC_EXT_PLUGIN_ENB 0x04000000 +#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 +#define APMC_DIS_SRAM 0x00000004 +#define APMC_DIS_CLKPM 0x00000002 +#define APMC_DIS_CLKTX 0x00000001 + +/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ +#define JME_PCCSRX_BASE 0x0880 +#define JME_PCCSRX_END 0x088F +#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) +#define PCCSRX_TO_MASK 0xFFFF0000 +#define PCCSRX_TO_SHIFT 16 +#define PCCSRX_PKT_CNT_MASK 0x0000FF00 +#define PCCSRX_PKT_CNT_SHIFT 8 + +/* Packet completion coalesing status of Tx queue. */ +#define JME_PCCSTX 0x0890 +#define PCCSTX_TO_MASK 0xFFFF0000 +#define PCCSTX_TO_SHIFT 16 +#define PCCSTX_PKT_CNT_MASK 0x0000FF00 +#define PCCSTX_PKT_CNT_SHIFT 8 + +/* Tx queues empty indicator. */ +#define JME_TXQEMPTY 0x0894 +#define TXQEMPTY_TXQ7 0x00000080 +#define TXQEMPTY_TXQ6 0x00000040 +#define TXQEMPTY_TXQ5 0x00000020 +#define TXQEMPTY_TXQ4 0x00000010 +#define TXQEMPTY_TXQ3 0x00000008 +#define TXQEMPTY_TXQ2 0x00000004 +#define TXQEMPTY_TXQ1 0x00000002 +#define TXQEMPTY_TXQ0 0x00000001 +#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) + +/* RSS control registers. */ +#define JME_RSS_BASE 0x0C00 + +#define JME_RSSC 0x0C00 +#define RSSC_HASH_LEN_MASK 0x0000E000 +#define RSSC_HASH_64_ENTRY 0x0000A000 +#define RSSC_HASH_128_ENTRY 0x0000E000 +#define RSSC_HASH_NONE 0x00001000 +#define RSSC_HASH_IPV6 0x00000800 +#define RSSC_HASH_IPV4 0x00000400 +#define RSSC_HASH_IPV6_TCP 0x00000200 +#define RSSC_HASH_IPV4_TCP 0x00000100 +#define RSSC_NCPU_MASK 0x000000F8 +#define RSSC_NCPU_SHIFT 3 +#define RSSC_DIS_RSS 0x00000000 +#define RSSC_2RXQ_ENB 0x00000001 +#define RSSS_4RXQ_ENB 0x00000002 + +/* CPU vector. */ +#define JME_RSSCPU 0x0C04 +#define RSSCPU_N_SEL(x) ((1 << (x)) + +/* RSS Hash value. */ +#define JME_RSSHASH 0x0C10 + +#define JME_RSSHASH_STAT 0x0C14 + +#define JME_RSS_RDATA0 0x0C18 + +#define JME_RSS_RDATA1 0x0C1C + +/* RSS secret key. */ +#define JME_RSSKEY_BASE 0x0C40 +#define JME_RSSKEY_LAST 0x0C64 +#define JME_RSSKEY_END 0x0C67 +#define HASHKEY_NBYTES 40 +#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) +#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) + +/* RSS indirection table entries. */ +#define JME_RSSTBL_BASE 0x0C80 +#define JME_RSSTBL_END 0x0CFF +#define RSSTBL_NENTRY 128 +#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) +#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) + +/* MSI-X table. */ +#define JME_MSIX_BASE_ADDR 0x2000 + +#define JME_MSIX_BASE 0x2000 +#define JME_MSIX_END 0x207F +#define JME_MSIX_NENTRY 8 +#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) +#define MSIX_ADDR_HI_OFF 0x00 +#define MSIX_ADDR_LO_OFF 0x04 +#define MSIX_ADDR_LO_MASK 0xFFFFFFFC +#define MSIX_DATA_OFF 0x08 +#define MSIX_VECTOR_OFF 0x0C +#define MSIX_VECTOR_RSVD 0x80000000 +#define MSIX_VECTOR_DIS 0x00000001 + +/* MSI-X PBA. */ +#define JME_MSIX_PBA_BASE_ADDR 0x3000 + +#define JME_MSIX_PBA 0x3000 +#define MSIX_PBA_RSVD_MASK 0xFFFFFF00 +#define MSIX_PBA_RSVD_SHIFT 8 +#define MSIX_PBA_PEND_MASK 0x000000FF +#define MSIX_PBA_PEND_SHIFT 0 +#define MSIX_PBA_PEND_ENTRY7 0x00000080 +#define MSIX_PBA_PEND_ENTRY6 0x00000040 +#define MSIX_PBA_PEND_ENTRY5 0x00000020 +#define MSIX_PBA_PEND_ENTRY4 0x00000010 +#define MSIX_PBA_PEND_ENTRY3 0x00000008 +#define MSIX_PBA_PEND_ENTRY2 0x00000004 +#define MSIX_PBA_PEND_ENTRY1 0x00000002 +#define MSIX_PBA_PEND_ENTRY0 0x00000001 + +#define JME_PHY_OUI 0x001B8C +#define JME_PHY_MODEL 0x21 +#define JME_PHY_REV 0x01 +#define JME_PHY_ADDR 1 + +/* JMC250 shadow status block. */ +struct jme_ssb { + uint32_t dw0; + uint32_t dw1; + uint32_t dw2; + uint32_t dw3; + uint32_t dw4; + uint32_t dw5; + uint32_t dw6; + uint32_t dw7; +}; + +/* JMC250 descriptor structures. */ +struct jme_desc { + uint32_t flags; + uint32_t buflen; + uint32_t addr_hi; + uint32_t addr_lo; +}; + +#define JME_TD_OWN 0x80000000 +#define JME_TD_INTR 0x40000000 +#define JME_TD_64BIT 0x20000000 +#define JME_TD_TCPCSUM 0x10000000 +#define JME_TD_UDPCSUM 0x08000000 +#define JME_TD_IPCSUM 0x04000000 +#define JME_TD_TSO 0x02000000 +#define JME_TD_VLAN_TAG 0x01000000 +#define JME_TD_VLAN_MASK 0x0000FFFF + +#define JME_TD_MSS_MASK 0xFFFC0000 +#define JME_TD_MSS_SHIFT 18 +#define JME_TD_BUF_LEN_MASK 0x0000FFFF +#define JME_TD_BUF_LEN_SHIFT 0 + +#define JME_TD_FRAME_LEN_MASK 0x0000FFFF +#define JME_TD_FRAME_LEN_SHIFT 0 + +/* + * Only the first Tx descriptor of a packet is updated + * after packet transmission. + */ +#define JME_TD_TMOUT 0x20000000 +#define JME_TD_RETRY_EXP 0x10000000 +#define JME_TD_COLLISION 0x08000000 +#define JME_TD_UNDERRUN 0x04000000 +#define JME_TD_EHDR_SIZE_MASK 0x000000FF +#define JME_TD_EHDR_SIZE_SHIFT 0 + +#define JME_TD_SEG_CNT_MASK 0xFFFF0000 +#define JME_TD_SEG_CNT_SHIFT 16 +#define JME_TD_RETRY_CNT_MASK 0x0000FFFF +#define JME_TD_RETRY_CNT_SHIFT 0 + +#define JME_RD_OWN 0x80000000 +#define JME_RD_INTR 0x40000000 +#define JME_RD_64BIT 0x20000000 + +#define JME_RD_BUF_LEN_MASK 0x0000FFFF +#define JME_RD_BUF_LEN_SHIFT 0 + +/* + * Only the first Rx descriptor of a packet is updated + * after packet reception. + */ +#define JME_RD_MORE_FRAG 0x20000000 +#define JME_RD_TCP 0x10000000 +#define JME_RD_UDP 0x08000000 +#define JME_RD_IPCSUM 0x04000000 +#define JME_RD_TCPCSUM 0x02000000 +#define JME_RD_UDPCSUM 0x01000000 +#define JME_RD_VLAN_TAG 0x00800000 +#define JME_RD_IPV4 0x00400000 +#define JME_RD_IPV6 0x00200000 +#define JME_RD_PAUSE 0x00100000 +#define JME_RD_MAGIC 0x00080000 +#define JME_RD_WAKEUP 0x00040000 +#define JME_RD_BCAST 0x00030000 +#define JME_RD_MCAST 0x00020000 +#define JME_RD_UCAST 0x00010000 +#define JME_RD_VLAN_MASK 0x0000FFFF +#define JME_RD_VLAN_SHIFT 0 + +#define JME_RD_VALID 0x80000000 +#define JME_RD_CNT_MASK 0x7F000000 +#define JME_RD_CNT_SHIFT 24 +#define JME_RD_GIANT 0x00800000 +#define JME_RD_GMII_ERR 0x00400000 +#define JME_RD_NBL_RCVD 0x00200000 +#define JME_RD_COLL 0x00100000 +#define JME_RD_ABORT 0x00080000 +#define JME_RD_RUNT 0x00040000 +#define JME_RD_FIFO_OVRN 0x00020000 +#define JME_RD_CRC_ERR 0x00010000 +#define JME_RD_FRAME_LEN_MASK 0x0000FFFF + +#define JME_RX_ERR_STAT \ + (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ + JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ + JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) + +#define JME_RD_ERR_MASK 0x00FF0000 +#define JME_RD_ERR_SHIFT 16 +#define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) +#define JME_RX_ERR_BITS "\20" \ + "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ + "\5COLL\6NBLRCVD\7GMIIERR\10" + +#define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) +#define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) +#define JME_RX_PAD_BYTES 10 + +#define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF + +#define JME_RD_RSS_HASH_MASK 0x00003F00 +#define JME_RD_RSS_HASH_SHIFT 8 +#define JME_RD_RSS_HASH_NONE 0x00000000 +#define JME_RD_RSS_HASH_IPV4 0x00000100 +#define JME_RD_RSS_HASH_IPV4TCP 0x00000200 +#define JME_RD_RSS_HASH_IPV6 0x00000400 +#define JME_RD_RSS_HASH_IPV6TCP 0x00001000 +#define JME_RD_HASH_FN_NONE 0x00000000 +#define JME_RD_HASH_FN_TOEPLITZ 0x00000001 + +#endif --- sys/modules/Makefile.orig 2007-12-15 15:32:32.000000000 +0900 +++ sys/modules/Makefile 2008-07-31 19:02:33.000000000 +0900 @@ -134,6 +134,7 @@ ispfw \ ${_iwi} \ ${_ixgb} \ + jme \ joy \ kbdmux \ kue \ --- /dev/null 2008-07-31 19:33:03.000000000 +0900 +++ sys/modules/jme/Makefile 2008-07-31 19:13:04.000000000 +0900 @@ -0,0 +1,8 @@ +# $FreeBSD: stable/6/sys/modules/jme/Makefile 180858 2008-07-28 01:47:06Z yongari $ + +.PATH: ${.CURDIR}/../../dev/jme + +KMOD= if_jme +SRCS= if_jme.c device_if.h bus_if.h pci_if.h miibus_if.h + +.include --- sys/modules/mii/Makefile.orig 2006-08-08 17:54:00.000000000 +0900 +++ sys/modules/mii/Makefile 2008-07-31 19:06:30.000000000 +0900 @@ -7,7 +7,7 @@ SRCS+= miibus_if.h miidevs.h device_if.h miibus_if.c e1000phy.c exphy.c nsphy.c SRCS+= mlphy.c tlphy.c rlphy.c amphy.c dcphy.c pnphy.c inphy.c tdkphy.c SRCS+= bmtphy.c brgphy.c xmphy.c pnaphy.c lxtphy.c qsphy.c acphy.c nsgphy.c -SRCS+= rgephy.c ruephy.c gentbi.c ip1000phy.c +SRCS+= rgephy.c ruephy.c gentbi.c ip1000phy.c jmphy.c EXPORT_SYMS= mii_mediachg \ mii_tick \ --- sys/i386/conf/GENERIC.orig 2007-12-15 15:32:32.000000000 +0900 +++ sys/i386/conf/GENERIC 2008-07-31 19:07:49.000000000 +0900 @@ -197,6 +197,7 @@ device bge # Broadcom BCM570xx Gigabit Ethernet device dc # DEC/Intel 21143 and various workalikes device fxp # Intel EtherExpress PRO/100B (82557, 82558) +device jme # JMicron JMC250 Gigabit/JMC260 Fast Ethernet device lge # Level 1 LXT1001 gigabit Ethernet device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device nge # NatSemi DP83820 gigabit Ethernet --- sys/amd64/conf/GENERIC.orig 2007-12-15 15:32:33.000000000 +0900 +++ sys/amd64/conf/GENERIC 2008-07-31 19:08:35.000000000 +0900 @@ -188,6 +188,7 @@ device bge # Broadcom BCM570xx Gigabit Ethernet device dc # DEC/Intel 21143 and various workalikes device fxp # Intel EtherExpress PRO/100B (82557, 82558) +device jme # JMicron JMC250 Gigabit/JMC260 Fast Ethernet device lge # Level 1 LXT1001 gigabit Ethernet device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device nge # NatSemi DP83820 gigabit Ethernet