Index: sys/dev/alc/if_alc.c
===================================================================
--- sys/dev/alc/if_alc.c	(revision 295870)
+++ sys/dev/alc/if_alc.c	(working copy)
@@ -255,7 +255,7 @@ static struct resource_spec alc_irq_spec_msix[] =
 	{ -1,			0,		0 }
 };
 
-static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 };
+static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 };
 
 static int
 alc_miibus_readreg(device_t dev, int phy, int reg)
@@ -1469,10 +1469,12 @@ alc_attach(device_t dev)
 			device_printf(dev, "TLP payload size : %u bytes.\n",
 			    alc_dma_burst[sc->alc_dma_wr_burst]);
 		}
-		if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
-			sc->alc_dma_rd_burst = 3;
-		if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
-			sc->alc_dma_wr_burst = 3;
+		if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
+			if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
+				sc->alc_dma_rd_burst = 3;
+			if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
+				sc->alc_dma_wr_burst = 3;
+		}
 		alc_init_pcie(sc);
 	}
 
@@ -4184,16 +4186,22 @@ alc_init_locked(struct alc_softc *sc)
 	reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
 	    RXQ_CFG_RD_BURST_MASK;
 	reg |= RXQ_CFG_RSS_MODE_DIS;
-	if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
+	if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
 		reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<
 		    RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) &
 		    RXQ_CFG_816X_IDT_TBL_SIZE_MASK;
-	if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
-	    sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2)
-		reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M;
+		if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
+			reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+	} else {
+		if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
+		    sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2)
+			reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;
+	}
 	CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
 
 	/* Configure DMA parameters. */
+	reg = CSR_READ_4(sc, ALC_DMA_CFG);
+	device_printf(sc->alc_dev, "DMA CFG : 0x%08x\n", reg);
 	reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;
 	reg |= sc->alc_rcb;
 	if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
@@ -4200,8 +4208,10 @@ alc_init_locked(struct alc_softc *sc)
 		reg |= DMA_CFG_CMB_ENB;
 	if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
 		reg |= DMA_CFG_SMB_ENB;
-	else
-		reg |= DMA_CFG_SMB_DIS;
+	else {
+		if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
+			reg |= DMA_CFG_SMB_DIS;
+	}
 	reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
 	    DMA_CFG_RD_BURST_SHIFT;
 	reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
@@ -4293,16 +4303,17 @@ alc_stop(struct alc_softc *sc)
 	/* Disable interrupts. */
 	CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
 	CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
-	/* Disable DMA. */
-	reg = CSR_READ_4(sc, ALC_DMA_CFG);
-	reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
-	reg |= DMA_CFG_SMB_DIS;
-	CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
-	DELAY(1000);
+	if ((sc->alc_flags & (ALC_FLAG_CMB_BUG | ALC_FLAG_SMB_BUG)) == 0) {
+		/* Disable DMA. */
+		reg = CSR_READ_4(sc, ALC_DMA_CFG);
+		reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);
+		if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
+			reg |= DMA_CFG_SMB_DIS;
+		CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
+		DELAY(1000);
+	}
 	/* Stop Rx/Tx MACs. */
 	alc_stop_mac(sc);
-	/* Disable interrupts which might be touched in taskq handler. */
-	CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
 	/* Disable L0s/L1s */
 	alc_aspm(sc, 0, IFM_UNKNOWN);
 	/* Reclaim Rx buffers that have been processed. */