--- simulavr-1.0.0/examples/python/example_io.c.orig	2012-02-12 07:26:38.000000000 -0800
+++ simulavr-1.0.0/examples/python/example_io.c	2015-11-28 15:38:03.637962000 -0800
@@ -5,7 +5,7 @@
 volatile int port_val;
 volatile int port_cnt;
 
-ISR(SIG_OUTPUT_COMPARE2) {
+ISR(TIMER2_COMP_vect) {
    timer2_ticks++;
 }