*** if_bgereg.h.orig	Tue Nov 11 09:57:03 2003
--- if_bgereg.h	Tue Jun  8 19:33:24 2004
***************
*** 525,530 ****
--- 525,534 ----
  #define BGE_RX_BD_RULES_CTL15		0x04F8
  #define BGE_RX_BD_RULES_MASKVAL15	0x04FC
  #define BGE_RX_RULES_CFG		0x0500
+ #define BGE_SERDES_CFG			0x0590
+ #define BGE_SERDES_STS			0x0594
+ #define BGE_SGDIG_CFG			0x05B0
+ #define BGE_SGDIG_STS			0x05B4
  #define BGE_RX_STATS			0x0800
  #define BGE_TX_STATS			0x0880
  
***************
*** 654,659 ****
--- 658,697 ----
  /* Receive Rules Mask register */
  #define BGE_RXRULEMASK_VALUE		0x0000FFFF
  #define BGE_RXRULEMASK_MASKVAL		0xFFFF0000
+ 
+ /* SERDES configuration register */
+ #define BGE_SERDESCFG_RXR		0x00000007 /* phase interpolator */
+ #define BGE_SERDESCFG_RXG		0x00000018 /* rx gain setting */
+ #define BGE_SERDESCFG_RXEDGESEL		0x00000040 /* rising/falling egde */
+ #define BGE_SERDESCFG_TX_BIAS		0x00000380 /* TXDAC bias setting */
+ #define BGE_SERDESCFG_IBMAX		0x00000400 /* bias current +25% */
+ #define BGE_SERDESCFG_IBMIN		0x00000800 /* bias current -25% */
+ #define BGE_SERDESCFG_TXMODE		0x00001000
+ #define BGE_SERDESCFG_TXEDGESEL		0x00002000 /* rising/falling edge */
+ #define BGE_SERDESCFG_MODE		0x00004000 /* TXCP/TXCN disabled */
+ #define BGE_SERDESCFG_PLLTEST		0x00008000 /* PLL test mode */
+ #define BGE_SERDESCFG_CDET		0x00010000 /* comma detect enable */
+ #define BGE_SERDESCFG_TBILOOP		0x00020000 /* local loopback */
+ #define BGE_SERDESCFG_REMLOOP		0x00040000 /* remote loopback */
+ #define BGE_SERDESCFG_INVPHASE		0x00080000 /* Reverse 125Mhz clock */
+ #define BGE_SERDESCFG_12REGCTL		0x00300000 /* 1.2v regulator ctl */
+ #define BGE_SERDESCFG_REGCTL		0x00C00000 /* regulator ctl (2.5v) */
+ 
+ /* SERDES status register */
+ #define BGE_SERDESSTS_RXSTAT		0x0000000F /* receive status bits */
+ #define BGE_SERDESSTS_CDET		0x00000010 /* comma code detected */
+ 
+ /* SGDIG config (not documented) */
+ #define BGE_SGDIGCFG_PAUSE_CAP		0x00000800
+ #define BGE_SGDIGCFG_ASYM_PAUSE		0x00001000
+ #define BGE_SGDIGCFG_SEND		0x40000000
+ #define BGE_SGDIGCFG_AUTO		0x80000000
+ 
+ /* SGDIG status (not documented) */
+ #define BGE_SGDIGSTS_PAUSE_CAP		0x00080000
+ #define BGE_SGDIGSTS_ASYM_PAUSE		0x00100000
+ #define BGE_SGDIGSTS_DONE		0x00000002
+ 
  
  /* MI communication register */
  #define BGE_MICOMM_DATA			0x0000FFFF
*** if_bge.c.orig	Fri Nov 14 09:16:56 2003
--- if_bge.c	Tue Jun  8 19:33:23 2004
***************
*** 2405,2410 ****
--- 2405,2411 ----
  		    IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
  		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
  		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
+ 		sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
  	} else {
  		/*
  		 * Do transceiver setup.
***************
*** 2604,2609 ****
--- 2605,2617 ----
  
  	CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
  
+ 	if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
+ 		uint32_t serdescfg;
+ 		serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
+ 		serdescfg = (serdescfg & ~0xFFF) | 0x880;
+ 		CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
+ 	}
+ 
  	DELAY(10000);
  
  	return;
***************
*** 2939,2944 ****
--- 2947,2955 ----
  		if (CSR_READ_4(sc, BGE_MAC_STS) &
  		    BGE_MACSTAT_TBI_PCS_SYNCHED) {
  			sc->bge_link++;
+ 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
+ 				BGE_CLRBIT(sc, BGE_MAC_MODE,
+ 				    BGE_MACMODE_TBI_SEND_CFGS);
  			CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
  			printf("bge%d: gigabit link up\n", sc->bge_unit);
  			if (ifp->if_snd.ifq_head != NULL)
***************
*** 3335,3340 ****
--- 3346,3368 ----
  			return(EINVAL);
  		switch(IFM_SUBTYPE(ifm->ifm_media)) {
  		case IFM_AUTO:
+ 			/*
+ 			 * The BCM5704 ASIC appears to have a special
+ 			 * mechanism for programming the autoneg
+ 			 * advertisement registers in TBI mode.
+ 			 */
+ 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
+ 				uint32_t sgdig;
+ 				CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
+ 				sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
+ 				sgdig |= BGE_SGDIGCFG_AUTO|
+ 				    BGE_SGDIGCFG_PAUSE_CAP|
+ 				    BGE_SGDIGCFG_ASYM_PAUSE;
+ 				CSR_WRITE_4(sc, BGE_SGDIG_CFG,
+ 				    sgdig|BGE_SGDIGCFG_SEND);
+ 				DELAY(5);
+ 				CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
+ 			}
  			break;
  		case IFM_1000_SX:
  			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {