*** if_ste.c.orig	Mon Jul  9 10:58:37 2001
--- if_ste.c	Thu Aug 23 11:04:04 2001
***************
*** 583,590 ****
  	}
  
  	/* first, zot all the existing hash bits */
! 	CSR_WRITE_4(sc, STE_MAR0, 0);
! 	CSR_WRITE_4(sc, STE_MAR1, 0);
  
  	/* now program new ones */
  	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
--- 583,592 ----
  	}
  
  	/* first, zot all the existing hash bits */
! 	CSR_WRITE_2(sc, STE_MAR0, 0);
! 	CSR_WRITE_2(sc, STE_MAR1, 0);
! 	CSR_WRITE_2(sc, STE_MAR2, 0);
! 	CSR_WRITE_2(sc, STE_MAR3, 0);
  
  	/* now program new ones */
  	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
***************
*** 597,604 ****
  			hashes[1] |= (1 << (h - 32));
  	}
  
! 	CSR_WRITE_4(sc, STE_MAR0, hashes[0]);
! 	CSR_WRITE_4(sc, STE_MAR1, hashes[1]);
  	STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
  	STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
  
--- 599,608 ----
  			hashes[1] |= (1 << (h - 32));
  	}
  
! 	CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
! 	CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
! 	CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
! 	CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
  	STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
  	STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
  
*** if_stereg.h.orig	Thu Feb  8 22:11:20 2001
--- if_stereg.h	Thu Aug 23 11:02:01 2001
***************
*** 88,94 ****
  #define STE_TX_RECLAIM_THRESH	0x5D
  #define STE_PHYCTL		0x5E
  #define STE_MAR0		0x60
! #define STE_MAR1		0x64
  #define STE_STATS		0x68
  
  #define STE_DMACTL_RXDMA_STOPPED	0x00000001
--- 88,96 ----
  #define STE_TX_RECLAIM_THRESH	0x5D
  #define STE_PHYCTL		0x5E
  #define STE_MAR0		0x60
! #define STE_MAR1		0x62
! #define STE_MAR2		0x64
! #define STE_MAR3		0x66
  #define STE_STATS		0x68
  
  #define STE_DMACTL_RXDMA_STOPPED	0x00000001