amd64/amd64/bpf_jit_machdep.h:#define MOViq(i64, r64) do { \ amd64/include/vmm.h:#define VM_INTINFO_VECTOR(info) ((info) & 0xff) amd64/include/vmm.h:#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3) amd64/include/vmm.h:#define SEG_DESC_GRANULARITY(access) (((access) & 0x8000) ? 1 : 0) amd64/vmm/amd/vmcb.h:#define VMCB_ACCESS(o, w) (0x80000000 | (((w) & 0xF) << 16) | \ amd64/vmm/intel/ept.c:#define EPT_PDPTE_SUPERPAGE(cap) ((cap) & (1UL << 17)) /* 1GB pages */ amd64/vmm/io/vatpit.c:#define VATPIT_LOCKED(vatpit) mtx_owned(&((vatpit)->mtx)) arm/allwinner/a10/a10_intc.c:#define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4)) arm/allwinner/a10/a10_intc.c:#define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4)) arm/allwinner/a10_codec.c:#define AC_DAC_CNT(_sc) ((_sc)->cfg->DAC_CNT) arm/allwinner/a10_codec.c:#define AC_ADC_CNT(_sc) ((_sc)->cfg->ADC_CNT) arm/allwinner/a10_dmac.h:#define AWIN_DMA_IRQ_DDMA_HF(n) (1U << (16+2*(n))) arm/allwinner/a10_dmac.h:#define AWIN_DMA_IRQ_NDMA_HF(n) (1U << (0+2*(n))) arm/allwinner/a31_dmac.c:#define DMA_PAU_REG(n) (0x100 + (n) * 0x40 + 0x04) arm/allwinner/a31_dmac.c:#define DMA_CFG_REG(n) (0x100 + (n) * 0x40 + 0x0c) arm/allwinner/a31_dmac.c:#define DMA_CUR_SRC_REG(n) (0x100 + (n) * 0x40 + 0x10) arm/allwinner/a31_dmac.c:#define DMA_CUR_DEST_REG(n) (0x100 + (n) * 0x40 + 0x14) arm/allwinner/a31_dmac.c:#define DMA_BCNT_LEFT_REG(n) (0x100 + (n) * 0x40 + 0x18) arm/allwinner/a31_dmac.c:#define DMA_PARA_REG(n) (0x100 + (n) * 0x40 + 0x1c) arm/allwinner/aw_mp.c:#define CPU_CTL(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_CTL) arm/allwinner/aw_mp.c:#define CPU_STATUS(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_STATUS) arm/allwinner/aw_mp.c:#define CPUX_CL_CPU_STATUS(cl) (0x30 + (cluster) * 0x4) arm/allwinner/aw_rsb.c:#define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf) arm/allwinner/clk/aw_axiclk.c:#define AXICLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) arm/allwinner/clkng/aw_clk.h:#define NKMP_CLK_WITH_MUX(_clkname, \ arm/allwinner/if_awg.c:#define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) arm/amlogic/aml8726/aml8726_pic.c:#define AML_PIC_FIRQ_SEL(x) (AML_PIC_0_FIRQ_REG + AML_PIC_CTRL(x) * 16) arm/amlogic/aml8726/aml8726_rtc.c:#define AML_RTC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); arm/arm/debug_monitor.c:#define DBG_WB_CTRL_PLX_MASK(x) ((x) & (0x3 << 1)) arm/arm/disassem.c:#define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] arm/arm/gic_common.h:#define GICD_ISPENDR(n) (0x0200 + (((n) >> 5) * 4)) /* v1 ICDISPR */ arm/arm/gic_common.h:#define GICD_ICPENDR(n) (0x0280 + (((n) >> 5) * 4)) /* v1 ICDICPR */ arm/arm/gic_common.h:#define GICD_ICACTIVER(n) (0x0380 + (((n) >> 5) * 4)) /* v1 ICDABR */ arm/at91/at91_pitreg.h:#define PIT_CNT(x) ((x >>20) & 0xfff) /* periodic interval counter */ arm/at91/at91_pmcreg.h:#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */ arm/at91/at91_rtcreg.h:#define RTC_CALR_DOW(x) FROMBCD(((x) & RTC_CALR_DOW_M) >> RTC_CALR_DOW_S) arm/at91/at91_usartreg.h:#define USART_MR_MAXITERATION(x) ((x) << 24) arm/at91/if_ate.c:#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); arm/broadcom/bcm2835/bcm2835_dma.c:#define BCM_DMA_INFO(n) (0x100*(n) + 0x08) arm/broadcom/bcm2835/bcm2835_dma.c:#define BCM_DMA_SRC(n) (0x100*(n) + 0x0C) arm/broadcom/bcm2835/bcm2835_dma.c:#define BCM_DMA_DST(n) (0x100*(n) + 0x10) arm/broadcom/bcm2835/bcm2835_dma.c:#define BCM_DMA_LEN(n) (0x100*(n) + 0x14) arm/broadcom/bcm2835/bcm2835_dma.c:#define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18) arm/broadcom/bcm2835/bcm2835_gpio.c:#define BCM_GPIO_GPAREN(_bank) (0x7c + _bank * 4) /* Async Rising Edge */ arm/broadcom/bcm2835/bcm2835_gpio.c:#define BCM_GPIO_GPAFEN(_bank) (0x88 + _bank * 4) /* Async Falling Egde */ arm/broadcom/bcm2835/bcm2836.c:#define BCM_LINTC_GIRR_FIQ_CORE(n) ((n) << 2) arm/broadcom/bcm2835/bcm2836.c:#define BCM_LINTC_PIRR_FIQ_EN_CORE(n) (1 << ((n) + 4)) arm/broadcom/bcm2835/bcm2836.c:#define BCM_LINTC_TCR_FIQ_EN_TIMER(n) (1 << ((n) + 4)) arm/broadcom/bcm2835/bcm2836.c:#define BCM_LINTC_MCR_FIQ_EN_MBOX(n) (1 << ((n) + 4)) arm/broadcom/bcm2835/bcm2836.c:#define BCM_LINTC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->bls_mtx) arm/broadcom/bcm2835/bcm2836_mp.c:#define MBOXINTRCTRL_CORE(n) (0x00000050 + (0x04 * (n))) arm/cavium/cns11xx/if_ece.c:#define ECE_CLEANUPLOCK_DESTROY(_sc) \ arm/cavium/cns11xx/if_ece.c:#define ECE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); arm/cavium/cns11xx/if_ece.c:#define ECE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); arm/freescale/imx/imx51_dpllreg.h:#define DPLL_BASE(n) (0x83F80000 + (0x4000 * ((n)-1))) arm/freescale/imx/imx51_ipuv3.c:#define SUBMOD_DUMP_REG(_sc, _m, _l) \ arm/freescale/imx/imx51_ipuv3reg.h:#define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT) arm/freescale/imx/imx51_ipuv3reg.h:#define CM_GPR_IPU_GP(n) __BIT((n)) arm/freescale/imx/imx51_ipuv3reg.h:#define DI_GENERAL_POLARITY_CS(n) (1 << ((n) + 8)) arm/freescale/imx/imx51_ipuv3reg.h:#define DI_GENERAL_POLARITY(n) (1 << ((n) - 1)) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4) arm/freescale/imx/imx51_ipuv3reg.h:#define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \ arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4) arm/freescale/imx/imx51_ipuv3reg.h:#define DI_STP_REP_MASK(n) (0x00000fff << DI_STP_REP_SHIFT((n))) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_DC_RL(chan_base, evt) ((chan_base) + (evt / 2) *0x4) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_DC_MAP_CONF_PNTR(n) (0x00000108 + (n) * 4) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_DC_MAP_CONF_MASK(n) (0x00000144 + (n) * 4) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_DC_UGDE(m, n) (0x00000174 + (m) * 0x10 + (n) +4) arm/freescale/imx/imx51_ipuv3reg.h:#define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n)) arm/freescale/imx/imx51_ipuv3reg.h:#define DMFC_STAT_FIFO_FULL(n) __BIT((n)) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_IC_BASE(_base) ((_base) + 0x1e020000) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_IRT_BASE(_base) ((_base) + 0x1e028000) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_SMFC_BASE(_base) ((_base) + 0x1e050000) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_VDI_BASE(_base) ((_base) + 0x1e068000) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_LUT_BASE(_base) ((_base) + 0x1f020000) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_SRM_BASE(_base) ((_base) + 0x1f040000) arm/freescale/imx/imx51_ipuv3reg.h:#define IPU_TPM_BASE(_base) ((_base) + 0x1f060000) arm/freescale/imx/imx51_tzicreg.h:#define TZIC_SRCSET(n) (0x0200 + 0x04 * (n)) arm/freescale/imx/imx51_tzicreg.h:#define TZIC_SRCCLAR(n) (0x0280 + 0x04 * (n)) arm/freescale/imx/imx51_tzicreg.h:#define TZIC_HIPND(n) (0x0d80 + 0x04 * (n)) arm/freescale/imx/imx51_tzicreg.h:#define TZIC_WAKEUP(n) (0x0e00 + 0x04 * (n)) arm/freescale/imx/imx6_ipu.c:#define IPU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) arm/freescale/imx/imx6_ipu.c:#define IPU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) arm/freescale/imx/imx6_ipu.c:#define IPU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) arm/freescale/imx/imx6_ipu.c:#define IPU_READ_CH_PARAM(_sc, ch, param) bus_read_region_4( \ arm/freescale/vybrid/vf_anadig.c:#define USB_VBUS_DETECT(n) (0x1A0 + 0x60 * n) arm/freescale/vybrid/vf_anadig.c:#define USB_CHRG_DETECT(n) (0x1B0 + 0x60 * n) arm/freescale/vybrid/vf_anadig.c:#define USB_VBUS_DETECT_STATUS(n) (0x1C0 + 0x60 * n) arm/freescale/vybrid/vf_anadig.c:#define USB_CHRG_DETECT_STATUS(n) (0x1D0 + 0x60 * n) arm/freescale/vybrid/vf_anadig.c:#define USB_LOOPBACK(n) (0x1E0 + 0x60 * n) arm/freescale/vybrid/vf_ccm.c:#define CCM_CCPGR(n) (0x90 + (n * 0x04)) /* Platform Clock Gating */ arm/freescale/vybrid/vf_edma.h:#define DMA_TCDn_NBYTES_MLNO(n) (0x08 + 0x20 * n) /* Minor Byte Count */ arm/freescale/vybrid/vf_edma.h:#define DMA_TCDn_NBYTES_MLOFFNO(n) (0x08 + 0x20 * n) /* Signed Minor Loop Offset */ arm/freescale/vybrid/vf_edma.h:#define DMA_TCDn_CITER_ELINKYES(n) (0x16 + 0x20 * n) /* Current Minor Loop Link, Major Loop Count */ arm/freescale/vybrid/vf_edma.h:#define DMA_TCDn_BITER_ELINKYES(n) (0x1E + 0x20 * n) /* Beginning Minor Loop Link, Major Loop Count */ arm/include/armreg.h:#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) arm/include/asm.h:#define ASLENTRY(y) _LENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE arm/include/asm.h:#define ASEENTRY(y) _EENTRY(_ASM_LABEL(y)); arm/include/asm.h:#define ASLEENTRY(y) _LEENTRY(_ASM_LABEL(y)); arm/include/asm.h:#define ASLENTRY_NP(y) _LENTRY(_ASM_LABEL(y)) arm/include/asm.h:#define ASLEENTRY_NP(y) _LEENTRY(_ASM_LABEL(y)) arm/include/asm.h:#define ASEND(y) _END(_ASM_LABEL(y)) arm/include/asm.h:#define ASLEND(y) _LEND(_ASM_LABEL(y)) arm/include/asm.h:#define ASEEND(y) _EEND(_ASM_LABEL(y)) arm/include/asm.h:#define ASLEEND(y) _LEEND(_ASM_LABEL(y)) arm/include/bus_dma.h:#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) arm/include/cpufunc.h:#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() arm/include/pmap-v4.h:#define pmap_pde_section(pde) l1pte_section_p(*(pde)) arm/include/pmap-v4.h:#define pmap_pde_page(pde) l1pte_page_p(*(pde)) arm/include/pmap-v4.h:#define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) arm/include/pmap-v4.h:#define pmap_pte_pa(pte) l2pte_pa(*(pte)) arm/include/pmc_mdep.h:#define PMC_TRAPFRAME_TO_SVC_SP(TF) ((TF)->tf_svc_sp) arm/include/pmc_mdep.h:#define PMC_TRAPFRAME_TO_USR_SP(TF) ((TF)->tf_usr_sp) arm/include/pmc_mdep.h:#define PMC_TRAPFRAME_TO_SVC_LR(TF) ((TF)->tf_svc_lr) arm/include/pmc_mdep.h:#define PMC_TRAPFRAME_TO_USR_LR(TF) ((TF)->tf_usr_lr) arm/lpc/lpc_fb.c:#define lpc_fb_lock_assert(sc) mtx_assert(&(_sc)->lf_mtx, MA_OWNED) arm/lpc/lpcreg.h:#define LPC_CLKPWR_USB_CTRL_PREDIV(_x) ((_x & 0x3) << 9) arm/lpc/lpcreg.h:#define LPC_CLKPWR_LCDCLK_CTRL_CLKDIV(_n) ((_n) & 0x1f) arm/lpc/lpcreg.h:#define LPC_LCD_POL_ACB(_n) ((_n & 0x1f) << 6) arm/lpc/lpcreg.h:#define LPC_SPI_CON_MODE(_n) ((_n & 0x3) << 16) arm/lpc/lpcreg.h:#define LPC_SPI_CON_BITNUM(_n) ((_n & 0xf) << 9) arm/lpc/lpcreg.h:#define LPC_SPI_CON_RATE(_n) (_n & 0x7f) arm/lpc/lpcreg.h:#define LPC_DMAC_CH_CONTROL_XFERLEN(_n) (_n & 0xfff) arm/mv/mvreg.h:#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) arm/mv/mvreg.h:#define SATA_ICR_DMADONE(ch) (1 << (ch)) arm/mv/mvreg.h:#define SATA_ICR_DEV(ch) (1 << (8 + ch)) arm/mv/mvreg.h:#define SATA_MICR_ERR(ch) (1 << (2 * ch)) arm/mv/mvreg.h:#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) arm/mv/mvreg.h:#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) arm/mv/mvreg.h:#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) arm/mv/mvreg.h:#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) arm/mv/mvreg.h:#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) arm/mv/mvreg.h:#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) arm/mv/mvreg.h:#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) arm/mv/mvreg.h:#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) arm/mv/mvreg.h:#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) arm/mv/mvreg.h:#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) arm/mv/mvreg.h:#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) arm/mv/mvreg.h:#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) arm/mv/mvreg.h:#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) arm/mv/mvreg.h:#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) arm/mv/mvreg.h:#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) arm/mv/mvreg.h:#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) arm/mv/mvreg.h:#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) arm/mv/mvreg.h:#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) arm/mv/mvreg.h:#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) arm/mv/mvreg.h:#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) arm/mv/mvreg.h:#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) arm/mv/mvreg.h:#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) arm/mv/mvreg.h:#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) arm/mv/mvwin.h:#define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ arm/mv/mvwin.h:#define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) arm/mv/mvwin.h:#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) arm/mv/mvwin.h:#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) arm/mv/mvwin.h:#define WIN_REG_RD(pre,reg,off,base) \ arm/mv/mvwin.h:#define WIN_REG_WR(pre,reg,off,base) \ arm/nvidia/as3722_gpio.c:#define GPIO_ASSERT(_sc) sx_assert(&(_sc)->gpio_lock, SA_LOCKED) arm/nvidia/drm2/tegra_dc_reg.h:#define WIN_UPDATE(x) (1 << (9 + (x))) arm/nvidia/drm2/tegra_dc_reg.h:#define WIN_ACT_REQ(x) (1 << (1 + (x))) arm/nvidia/drm2/tegra_dc_reg.h:#define ORD_DITHER_ROTATION(x) (((x) & 0x3) << 12) arm/nvidia/drm2/tegra_hdmi.c:#define AC_FMT_CHAN_GET(x) (((x) >> 0) & 0xf) arm/nvidia/drm2/tegra_hdmi.c:#define AC_FMT_CHAN_BITS_GET(x) (((x) >> 4) & 0x7) arm/nvidia/drm2/tegra_hdmi.c:#define AC_FMT_DIV_GET(x) (((x) >> 8) & 0x7) arm/nvidia/drm2/tegra_hdmi.c:#define AC_FMT_MUL_GET(x) (((x) >> 11) & 0x7) arm/nvidia/drm2/tegra_hdmi_reg.h:#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) arm/nvidia/drm2/tegra_hdmi_reg.h:#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) arm/nvidia/drm2/tegra_hdmi_reg.h:#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) arm/nvidia/drm2/tegra_hdmi_reg.h:#define SOR_CSTM_ROTAT(x) (((x) & 0xf) << 28) arm/nvidia/drm2/tegra_hdmi_reg.h:#define SOR_SEQ_PC(x) (((x) & 0xf) << 16) arm/nvidia/tegra124/tegra124_pmc.c:#define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx); arm/nvidia/tegra124/tegra124_pmc.c:#define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED); arm/nvidia/tegra124/tegra124_pmc.c:#define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED); arm/nvidia/tegra_ahci.c:#define T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x) (((x) & 0xF) << 20) arm/nvidia/tegra_ahci.c:#define T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x) (((x) & 0x1F) << 8) arm/nvidia/tegra_ahci.c:#define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x) (((x) & 0xFF) << 24) arm/nvidia/tegra_ahci.c:#define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x) (((x) & 0x1F) << 16) arm/nvidia/tegra_ahci.c:#define T_AHCI_PORT_BKDR_PXDEVSLP_DM(x) (((x) & 0xF) << 10) arm/nvidia/tegra_mc.c:#define MC_ERR_ID(x) (((x) >> 0) & 07F) arm/nvidia/tegra_mc.c:#define MC_EMEM_NUMDEV(x) (((x) >> 0 ) & 0x1) arm/nvidia/tegra_mc.c:#define EMEM_DEV_DEVSIZE(x) (((x) >> 16) & 0xF) arm/nvidia/tegra_mc.c:#define EMEM_DEV_BANKWIDTH(x) (((x) >> 8) & 0x3) arm/nvidia/tegra_mc.c:#define EMEM_DEV_COLWIDTH(x) (((x) >> 8) & 0x3) arm/nvidia/tegra_soctherm.c:#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP(x) (((x) >> 0) & 0x3f) arm/nvidia/tegra_soctherm.c:#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT(x) (((x) >> 21) & 0x1f) arm/nvidia/tegra_usbphy.c:#define UTMIP_XCVR_FSSLEW(x) (((x) & 0x3) << 6) arm/nvidia/tegra_usbphy.c:#define UTMIP_ACTIVE_TERM_OFFSET(x) (((x) & 0x7) << 15) arm/nvidia/tegra_usbphy.c:#define UTMIP_ACTIVE_PULLUP_OFFSET(x) (((x) & 0x7) << 12) arm/nvidia/tegra_usbphy.c:#define UTMIP_VBUS_LEVEL_LEVEL(x) (((x) & 0x3) << 8) arm/nvidia/tegra_usbphy.c:#define UTMIP_SESS_LEVEL_LEVEL(x) (((x) & 0x3) << 6) arm/nvidia/tegra_usbphy.c:#define UTMIP_HSCHIRP_LEVEL(x) (((x) & 0x3) << 4) arm/nvidia/tegra_usbphy.c:#define UTMIP_KEEP_PATT_ON_ACTIVE(x) (((x) & 0x3) << 30) arm/nvidia/tegra_usbphy.c:#define UTMIP_PCOUNT_UPDN_DIV(x) (((x) & 0xf) << 24) arm/nvidia/tegra_usbphy.c:#define UTMIP_SQUELCH_EOP_DLY(x) (((x) & 0x7) << 21) arm/nvidia/tegra_usbphy.c:#define UTMIP_PCOUNT_INERTIA(x) (((x) & 0x3) << 4) arm/nvidia/tegra_usbphy.c:#define UTMIP_PHASE_ADJUST(x) (((x) & 0x3) << 2) arm/nvidia/tegra_usbphy.c:#define UTMIP_HS_TX_IPG_DLY(x) (((x) & 0x1f) << 10) arm/nvidia/tegra_usbphy.c:#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) arm/nvidia/tegra_usbphy.c:#define UTMIP_INJECT_ERROR_TYPE(x) (((x) & 0x3) << 19) arm/nvidia/tegra_usbphy.c:#define UTMIP_STABLE_COUNT(x) (((x) & 0x7) << 5) arm/nvidia/tegra_usbphy.c:#define UTMIP_BIAS_DEBOUNCE_B(x) (((x) & 0xffff) << 16) arm/nvidia/tegra_usbphy.c:#define UTMIP_CHRG_DEBOUNCE_TIMESCALE(x) (((x) & 0x1f) << 8) arm/nvidia/tegra_usbphy.c:#define UTMIP_XCVR_RPU_RANGE_ADJ(x) (((x) & 0x3) << 26) arm/nvidia/tegra_usbphy.c:#define UTMIP_XCVR_HS_IREF_CAP(x) (((x) & 0x3) << 24) arm/nvidia/tegra_usbphy.c:#define UTMIP_XCVR_SPARE(x) (((x) & 0x3) << 22) arm/nvidia/tegra_usbphy.c:#define UTMIP_RCTRL_SW_VAL(x) (((x) & 0x1f) << 12) arm/nvidia/tegra_usbphy.c:#define UTMIP_TCTRL_SW_VAL(x) (((x) & 0x1f) << 6) arm/nvidia/tegra_usbphy.c:#define UTMIP_BIAS_DEBOUNCE_TIMESCALE(x) (((x) & 0x3f) << 8) arm/ralink/if_fvreg.h:#define FV_PKTSIZE(len) ((len & 0xffff0000) >> 16) arm/samsung/exynos/exynos5_combiner.c:#define IECR(n) (0x10 * n + 0x4) /* Interrupt enable clear */ arm/samsung/exynos/exynos5_combiner.c:#define IMSR(n) (0x10 * n + 0xC) /* Interrupt masked status */ arm/samsung/exynos/exynos5_usb_phy.c:#define PHYCLKRST_SSC_RANGE(x) ((x) << 21) arm/samsung/exynos/exynos5_xhci.c:#define GCTL_PWRDNSCALE(n) ((n) << 19) arm/samsung/exynos/exynos5_xhci.c:#define GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) arm/ti/aintc.c:#define INTC_ISR_SET(x) (0x90 + ((x) * 0x20)) arm/ti/aintc.c:#define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20)) arm/ti/am335x/am335x_ehrpwm.c:#define TBCTL_HSPCLKDIV(x) ((x) << 7) arm/ti/am335x/am335x_lcd.c:#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); arm/ti/am335x/tda19988.c:#define EDID_TIMING_X(v) (((v) + 31) * 8) arm/ti/am335x/tda19988.c:#define EDID_FREQ(v) (((v) & 0x3f) + 60) arm/ti/am335x/tda19988.c:#define EDID_RATIO(v) (((v) >> 6) & 0x3) arm/ti/cpsw/if_cpsw.c:#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED) arm/ti/cpsw/if_cpsw.c:#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED) arm/ti/cpsw/if_cpsw.c:#define cpsw_cpdma_write_bd_flags(sc, slot, val) \ arm/ti/cpsw/if_cpsw.c:#define CPSW_DUMP_SLOT(cs, slot) do { \ arm/ti/cpsw/if_cpsw.c:#define CPSW_DUMP_QUEUE(sc, q) do { \ arm/ti/cpsw/if_cpswreg.h:#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100)) arm/ti/cpsw/if_cpswreg.h:#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100)) arm/ti/cpsw/if_cpswreg.h:#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08) arm/ti/cpsw/if_cpswreg.h:#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18) arm/ti/cpsw/if_cpswreg.h:#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C) arm/ti/cpsw/if_cpswreg.h:#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) arm/ti/cpsw/if_cpswreg.h:#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) arm/ti/cpsw/if_cpswreg.h:#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) arm/ti/ti_cpuid.h:#define OMAP_REV_MINOR_MINOR(x) (((x) >> 0) & 0xf) arm/ti/ti_gpio.c:#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) arm/ti/ti_gpio.c:#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) arm/ti/ti_mbox.h:#define TI_MBOX_MSGSTATUS(n) (0xc0 + (n) * 0x4) arm/ti/ti_mbox.h:#define TI_MBOX_IRQSTATUS_RAW(n) (0x100 + (n) * 0x10) arm/ti/ti_mbox.h:#define TI_MBOX_IRQSTATUS_CLR(n) (0x104 + (n) * 0x10) arm/ti/ti_mbox.h:#define TI_MBOX_IRQENABLE_CLR(n) (0x10c + (n) * 0x10) arm/ti/ti_sdma.c:#define TI_SDMA_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); arm/ti/ti_sdma.c:#define TI_SDMA_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); arm/ti/ti_sdma.c:#define TI_SDMA_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); arm/ti/ti_spireg.h:#define MCSPI_XFERLEVEL_AFL(_a) (((_a) >> 8) & 0xff) arm/ti/ti_spireg.h:#define MCSPI_XFERLEVEL_AEL(_a) (((_a) >> 0) & 0xff) arm/ti/twl/twl.c:#define TWL_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); arm/ti/twl/twl.c:#define TWL_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); arm/ti/usb/omap_ehci.c:#define OMAP_USBHOST_PORTSC(i) (0x0054 + (0x04 * (i))) arm/ti/usb/omap_ehci.c:#define ULPI_CLR(a) (a + 2) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_SAR_CNTX(i) (0x0400 + (0x04 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_VENDOR_ID_LO(i) (0x0800 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_VENDOR_ID_HI(i) (0x0801 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_PRODUCT_ID_LO(i) (0x0802 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_PRODUCT_ID_HI(i) (0x0803 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_FUNCTION_CTRL(i) (0x0804 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_FUNCTION_CTRL_SET(i) (0x0805 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_FUNCTION_CTRL_CLR(i) (0x0806 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_INTERFACE_CTRL(i) (0x0807 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_INTERFACE_CTRL_SET(i) (0x0808 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_INTERFACE_CTRL_CLR(i) (0x0809 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_OTG_CTRL(i) (0x080A + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_OTG_CTRL_SET(i) (0x080B + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_OTG_CTRL_CLR(i) (0x080C + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_EN_RISE(i) (0x080D + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_EN_RISE_SET(i) (0x080E + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_EN_RISE_CLR(i) (0x080F + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_EN_FALL(i) (0x0810 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_EN_FALL_SET(i) (0x0811 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_EN_FALL_CLR(i) (0x0812 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_STATUS(i) (0x0813 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_LATCH(i) (0x0814 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_DEBUG(i) (0x0815 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_SCRATCH_REGISTER(i) (0x0816 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_SCRATCH_REGISTER_SET(i) (0x0817 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_SCRATCH_REGISTER_CLR(i) (0x0818 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_EXTENDED_SET_ACCESS(i) (0x082F + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_EN(i) (0x0830 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_EN_SET(i) (0x0831 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_EN_CLR(i) (0x0832 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_STATUS(i) (0x0833 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VCONTROL_LATCH(i) (0x0834 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VSTATUS(i) (0x0835 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VSTATUS_SET(i) (0x0836 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_UTMI_VSTATUS_CLR(i) (0x0837 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_USB_INT_LATCH_NOCLR(i) (0x0838 + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_VENDOR_INT_EN(i) (0x083B + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_VENDOR_INT_EN_SET(i) (0x083C + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_VENDOR_INT_EN_CLR(i) (0x083D + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_VENDOR_INT_STATUS(i) (0x083E + (0x100 * (i))) arm/ti/usb/omap_tll.c:#define OMAP_USBTLL_ULPI_VENDOR_INT_LATCH(i) (0x083F + (0x100 * (i))) arm/xscale/i8134x/i80321reg.h:#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) arm/xscale/i8134x/i80321reg.h:#define PCIXSR_FUNCNO(x) ((x) & 0x7) arm/xscale/i8134x/i80321reg.h:#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) arm/xscale/i8134x/i80321reg.h:#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) arm/xscale/i8134x/i80321reg.h:#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) arm/xscale/i8134x/i80321reg.h:#define PBIU_PBLRx_SIZE(x) (~((x) - 1)) arm/xscale/ixp425/cambria_exp_space.c:#define EXP_LOCK_DESTROY(exp) \ arm/xscale/ixp425/if_npe.c:#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); arm/xscale/ixp425/if_npereg.h:#define NPE_QM_Q_PRIO(e) (((e)>>0)&0x3) /* 802.1d priority */ arm/xscale/ixp425/if_npereg.h:#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2)) arm/xscale/ixp425/ixp425_npereg.h:#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \ arm/xscale/ixp425/ixp425_npereg.h:#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \ arm/xscale/ixp425/ixp425_npereg.h:#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \ arm/xscale/ixp425/ixp425_npevar.h:#define NPEIMAGE_MAKEID(dev, npe, func, maj, min) \ arm/xscale/ixp425/ixp425_pci.c:#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I) arm/xscale/ixp425/ixp425_pci.c:#define PCI_CONF_UNLOCK(s) restore_interrupts((s)) arm/xscale/ixp425/ixp425reg.h:#define MCU_DDR_SDPR(n) (0x50+(n)*4) /* SDRAM Page Register 0-7 */ arm/xscale/pxa/pxareg.h:#define DMAC_DCSR(n) ((n)*4) arm/xscale/pxa/pxareg.h:#define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */ arm/xscale/pxa/pxareg.h:#define DMAC_DDADR(n) (0x0200+(n)*16) arm/xscale/pxa/pxareg.h:#define DMAC_DSADR(n) (0x0204+(n)*16) arm/xscale/pxa/pxareg.h:#define DMAC_DTADR(n) (0x0208+(n)*16) arm/xscale/pxa/pxareg.h:#define DMAC_DCMD(n) (0x020c+(n)*16) arm/xscale/pxa/pxareg.h:#define GPIO_BANK(pin) ((pin) / 32) arm/xscale/pxa/pxareg.h:#define GPIO_IS_GPIO(n) (GPIO_FN(n) == 0) arm/xscale/pxa/pxareg.h:#define GPIO_IS_GPIO_IN(n) (((n) & (GPIO_FN_MASK|GPIO_OUT)) == GPIO_IN) arm/xscale/pxa/pxareg.h:#define MEMCTL_MCMEM(n) (0x28+4*(n)) arm/xscale/pxa/pxareg.h:#define MEMCTL_MCATT(n) (0x30+4*(n)) arm/xscale/pxa/pxareg.h:#define MEMCTL_MCIO(n) (0x38+4*(n)) arm/xscale/pxa/pxareg.h:#define MC_TIMING_VAL(hold,asst,set) (((hold)<ddadr = dadr; } while (0) arm/xscale/pxa/pxavar.h:#define DMACD_SET_SOURCE(d, sadr) do { d->dsadr = sadr; } while (0) arm/xscale/pxa/pxavar.h:#define DMACD_SET_TARGET(d, tadr) do { d->dtadr = tadr; } while (0) arm/xscale/pxa/pxavar.h:#define DMACD_SET_COMMAND(d, cmd) do { d->dcmd = cmd; } while (0) arm64/arm64/debug_monitor.c:#define DBG_WB_CTRL_ELX_MASK(x) ((x) & (0x3 << 1)) arm64/cavium/thunder_pcie_pem.c:#define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) arm64/include/armreg.h:#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) arm64/include/cpu.h:#define CPU_MATCH_RAW(mask, devid) \ boot/arm/at91/libat91/lib.h:#define ToASCII(x) ((x > 9) ? (x + 'A' - 0xa) : (x + '0')) boot/efi/include/efidevp.h:#define DP_IS_END_TYPE(a) boot/efi/include/efidevp.h:#define DP_IS_END_SUBTYPE(a) ( ((a)->SubType == END_ENTIRE_DEVICE_PATH_SUBTYPE ) boot/efi/include/efidevp.h:#define IsDevicePathUnpacked(a) ( (a)->Type & EFI_DP_TYPE_UNPACKED ) boot/efi/include/efifs.h:#define EFI_FILE_LBAL(a) ((EFI_LBAL *) (((CHAR8 *) (a)) + (a)->LBALOffset)) boot/efi/include/efifs.h:#define EFI_LBAL_ARRAY_SIZE(lbal,offs,blks) \ boot/efi/include/efifs.h:#define EFI_LBAL_RL(a) ((EFI_RL*) (((CHAR8 *) (a)) + (a)->Hdr.HeaderSize)) boot/efi/include/efiprot.h:#define EFI_PCI_ADDRESS(bus,dev,func,reg) \ boot/ficl/ficl.h:#define GETTOP() stackGetTop(pVM->pStack) boot/ficl/ficl.h:#define SETTOP(c) stackSetTop(pVM->pStack,LVALUEtoCELL(c)) boot/ficl/ficl.h:#define DEPTH() stackDepth(pVM->pStack) boot/ficl/ficl.h:#define vmGetRunningWord(pVM) ((pVM)->runningWord) boot/ficl/ficl.h:#define vmGetTibIndex(pVM) (pVM)->tib.index boot/libsa/cd9660.c:#define PTSIZE(pp) roundup(PTFIXSZ + isonum_711((pp)->namlen), 2) boot/libsa/stand.h:#define PCHK(fmt, args...) {printf("%s(%d): " fmt "\n", __func__, __LINE__ , ##args); getchar();} boot/libsa/ufsread.c:#define FS_TO_VBA(fs, fsb, off) (fsbtodb(fs, fsb) + \ boot/libsa/ufsread.c:#define FS_TO_VBO(fs, fsb, off) ((off) & VBLKMASK) bsm/audit_kevents.h:#define AUE_IS_A_KEVENT(e) (((e) > 0 && (e) < 2048) || \ cam/cam_ccb.h:#define CCB_CLEAR_ALL_EXCEPT_HDR(ccbp) \ cam/cam_queue.h:#define CAMQ_GET_HEAD(camq) ((camq)->queue_array[CAMQ_HEAD]) cam/cam_sim.h:#define CAM_SIM_LOCK(sim) mtx_lock((sim)->mtx) cam/cam_sim.h:#define CAM_SIM_UNLOCK(sim) mtx_unlock((sim)->mtx) cam/scsi/scsi_enc_internal.h:#define MEMCPY(dest, src, amt) bcopy(src, dest, amt) cam/scsi/scsi_enc_safte.c:#define SAFT_ALARM_OFFSET(cc) (cc)->slotoff - 1 cam/scsi/scsi_iu.h:#define SIU_PKTFAIL_OFFSET(siu) 12 cam/scsi/scsi_low.h:#define SCSI_LOW_PERIOD(n) DVF_SCSI_PERIOD(n) cam/scsi/scsi_low.h:#define SCSI_LOW_OFFSET(n) DVF_SCSI_OFFSET(n) cam/scsi/scsi_sa.c:#define SASBADDINT(sb, indent, data, fmt, name) \ cam/scsi/scsi_sa.c:#define SASBADDFIXEDSTR(sb, indent, data, fmt, name) \ cam/scsi/scsi_sa.c:#define SASBADDFIXEDSTRDESC(sb, indent, data, fmt, name, desc) \ cam/scsi/scsi_sa.c:#define SA_PROT_ENABLED(softc) ((softc->flags & SA_FLAG_PROTECT_SUPP) \ cam/scsi/scsi_sa.c:#define SA_PROT_LEN(softc) softc->prot_info.cur_prot_state.pi_length cddl/boot/zfs/zfsimpl.h:#define BP_IS_OLDER(bp, txg) (!BP_IS_HOLE(bp) && (bp)->blk_birth < (txg)) cddl/boot/zfs/zfsimpl.h:#define DN_SLOTS_TO_BONUSLEN(slots) DN_BONUS_SIZE((slots) << DNODE_SHIFT) cddl/boot/zfs/zfsimpl.h:#define ZFS_DIRENT_MAKE(type, obj) (((uint64_t)type << 60) | obj) cddl/compat/opensolaris/sys/atomic.h:#define casptr(_a, _b, _c) \ cddl/compat/opensolaris/sys/dnlc.h:#define dnlc_lookup(dvp, name) (NULL) cddl/compat/opensolaris/sys/dnlc.h:#define dnlc_update(dvp, name, vp) do { } while (0) cddl/compat/opensolaris/sys/dnlc.h:#define dnlc_remove(dvp, name) do { } while (0) cddl/compat/opensolaris/sys/elf.h:#define EC_ADDR(a) ((Elf64_Addr)(a)) /* "ull" */ cddl/compat/opensolaris/sys/elf.h:#define EC_OFF(a) ((Elf64_Off)(a)) /* "ull" */ cddl/compat/opensolaris/sys/elf.h:#define EC_HALF(a) ((Elf64_Half)(a)) /* "d" */ cddl/compat/opensolaris/sys/elf.h:#define EC_WORD(a) ((Elf64_Word)(a)) /* "u" */ cddl/compat/opensolaris/sys/elf.h:#define EC_SWORD(a) ((Elf64_Sword)(a)) /* "d" */ cddl/compat/opensolaris/sys/elf.h:#define EC_XWORD(a) ((Elf64_Xword)(a)) /* "ull" */ cddl/compat/opensolaris/sys/elf.h:#define EC_SXWORD(a) ((Elf64_Sxword)(a)) /* "ll" */ cddl/compat/opensolaris/sys/elf.h:#define EC_LWORD(a) ((Elf64_Lword)(a)) /* "ull" */ cddl/compat/opensolaris/sys/kidmap.h:#define kidmap_get_create() (NULL) cddl/compat/opensolaris/sys/kidmap.h:#define kidmap_get_destroy(hdl) do { } while (0) cddl/compat/opensolaris/sys/kidmap.h:#define kidmap_get_mappings(hdl) (NULL) cddl/compat/opensolaris/sys/random.h:#define random_get_bytes(p, s) read_random((p), (int)(s)) cddl/compat/opensolaris/sys/rwlock.h:#define RW_ISWRITER(x) (rw_iswriter(x)) cddl/compat/opensolaris/sys/time.h:#define SEC_TO_TICK(sec) ((sec) * hz) cddl/compat/opensolaris/sys/time.h:#define NSEC_TO_TICK(nsec) ((nsec) / (NANOSEC / hz)) cddl/compat/opensolaris/sys/vnode.h:#define IS_XATTRDIR(dvp) (0) cddl/compat/opensolaris/sys/vnode.h:#define vn_vfsunlock(vp) do { } while (0) cddl/compat/opensolaris/sys/vnode.h:#define vn_ismntpt(vp) ((vp)->v_type == VDIR && (vp)->v_mountedhere != NULL) cddl/compat/opensolaris/sys/vnode.h:#define vn_mountedvfs(vp) ((vp)->v_mountedhere) cddl/compat/opensolaris/sys/vnode.h:#define vn_invalid(vp) do { } while (0) cddl/compat/opensolaris/sys/vnode.h:#define vn_free(vp) do { } while (0) cddl/compat/opensolaris/sys/vnode.h:#define vnevent_create(vp, ct) do { } while (0) cddl/compat/opensolaris/sys/vnode.h:#define specvp(vp, rdev, type, cr) (VN_HOLD(vp), (vp)) cddl/contrib/opensolaris/uts/common/fs/zfs/abd.c:#define ABDSTAT(stat) (abd_stats.stat.value.ui64) cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c:#define HDR_ISTYPE_DATA(hdr) (!HDR_ISTYPE_METADATA(hdr)) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lauxlib.h:#define luaL_checklong(L,n) ((long)luaL_checkinteger(L, (n))) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lauxlib.h:#define luaL_optlong(L,n,d) ((long)luaL_optinteger(L, (n), (d))) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lauxlib.h:#define luaL_dofile(L, fn) \ cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lauxlib.h:#define luaL_dostring(L, s) \ cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lauxlib.h:#define luaL_prepbuffer(B) luaL_prepbuffsize(B, LUAL_BUFFERSIZE) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lobject.h:#define ttislngstring(o) checktag((o), ctb(LUA_TLNGSTR)) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lopcodes.h:#define SETARG_Ax(i,v) setarg(i, v, POS_Ax, SIZE_Ax) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lua.h:#define lua_register(L,n,f) (lua_pushcfunction(L, (f)), lua_setglobal(L, (n))) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lua.h:#define lua_isfunction(L,n) (lua_type(L, (n)) == LUA_TFUNCTION) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lua.h:#define lua_islightuserdata(L,n) (lua_type(L, (n)) == LUA_TLIGHTUSERDATA) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lua.h:#define lua_isboolean(L,n) (lua_type(L, (n)) == LUA_TBOOLEAN) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lua.h:#define lua_isthread(L,n) (lua_type(L, (n)) == LUA_TTHREAD) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lua.h:#define lua_isnone(L,n) (lua_type(L, (n)) == LUA_TNONE) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/luaconf.h:#define lua_strlen(L,i) lua_rawlen(L, (i)) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/luaconf.h:#define lua_objlen(L,i) lua_rawlen(L, (i)) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/luaconf.h:#define lua_equal(L,idx1,idx2) lua_compare(L,(idx1),(idx2),LUA_OPEQ) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/luaconf.h:#define lua_lessthan(L,idx1,idx2) lua_compare(L,(idx1),(idx2),LUA_OPLT) cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lvm.c:#define KBx(i) \ cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dbuf.h:#define DB_DNODE_HELD(_db) (!zrl_is_zero(&DB_DNODE_LOCK(_db))) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/metaslab_impl.h:#define WEIGHT_GET_COUNT(weight) BF64_GET((weight), 0, 55) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/rrwlock.h:#define RRW_READ_HELD(x) rrw_held(x, RW_READER) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/space_map.h:#define SM_DEBUG_ACTION_DECODE(x) BF64_DECODE(x, 60, 3) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/space_map.h:#define SM_DEBUG_SYNCPASS_DECODE(x) BF64_DECODE(x, 50, 10) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/space_map.h:#define SM_DEBUG_TXG_DECODE(x) BF64_DECODE(x, 0, 50) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ioctl.h:#define DMU_STREAM_SUPPORTED(x) (!((x) & ~DMU_BACKUP_FEATURE_MASK)) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ioctl.h:#define DRR_IS_DEDUP_CAPABLE(flags) ((flags) & DRR_CHECKSUM_DEDUP) cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zio.h:#define ZB_IS_ROOT(zb) \ cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c:#define ZFSCTL_INO_SNAP(id) (id) cddl/contrib/opensolaris/uts/common/sys/bitmap.h:#define BITX(u, h, l) (((u) >> (l)) & ((1LU << ((h) - (l) + 1LU)) - 1LU)) cddl/contrib/opensolaris/uts/common/sys/callb.h:#define CALLB_CPR_INIT_SAFE(t, name) { \ cddl/contrib/opensolaris/uts/common/sys/ccompile.h:#define __PRINTFLIKE(__n) __sun_attr__((__PRINTFLIKE__(__n))) cddl/contrib/opensolaris/uts/common/sys/ccompile.h:#define __VPRINTFLIKE(__n) __sun_attr__((__VPRINTFLIKE__(__n))) cddl/contrib/opensolaris/uts/common/sys/cpupart.h:#define DISP_MUST_SURRENDER(t) \ cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define INTR_ACTIVE(cpup, level) \ cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define CPU_CPR_IS_OFFLINE(cpu) (((cpu)->cpu_cpr_flags & CPU_CPR_ONLINE) == 0) cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define CPU_CPR_IS_ONLINE(cpu) ((cpu)->cpu_cpr_flags & CPU_CPR_ONLINE) cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define CPU_SET_CPR_FLAGS(cpu, flag) ((cpu)->cpu_cpr_flags |= flag) cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define CPU_STATS_ENTER_K() kpreempt_disable() cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define CPU_STATS_EXIT_K() kpreempt_enable() cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define CPU_STATS_ADD_K(class, stat, amount) \ cddl/contrib/opensolaris/uts/common/sys/cpuvar.h:#define CPU_STATS(cp, stat) \ cddl/contrib/opensolaris/uts/common/sys/cred.h:#define VALID_UID(id, zn) \ cddl/contrib/opensolaris/uts/common/sys/cred.h:#define VALID_GID(id, zn) \ cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_INFO_ISROOT(info) (((info) & 0x0400) >> 10) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_TYPE_ISPARENT(id) ((id) < 0x8000) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_TYPE_TO_INDEX(id) ((id) & 0x7fff) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_INDEX_TO_TYPE(id, child) ((child) ? ((id) | 0x8000) : (id)) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_SIZE_TO_LSIZE_HI(size) ((uint32_t)((uint64_t)(size) >> 32)) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_SIZE_TO_LSIZE_LO(size) ((uint32_t)(size)) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_INT_ENCODING(data) (((data) & 0xff000000) >> 24) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_INT_OFFSET(data) (((data) & 0x00ff0000) >> 16) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_INT_BITS(data) (((data) & 0x0000ffff)) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_FP_ENCODING(data) (((data) & 0xff000000) >> 24) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_FP_OFFSET(data) (((data) & 0x00ff0000) >> 16) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_FP_BITS(data) (((data) & 0x0000ffff)) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_LMEM_OFFSET(ctlmp) \ cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_OFFSET_TO_LMEMHI(offset) ((uint32_t)((uint64_t)(offset) >> 32)) cddl/contrib/opensolaris/uts/common/sys/ctf.h:#define CTF_OFFSET_TO_LMEMLO(offset) ((uint32_t)(offset)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_XLREF(i) (((i) >> 8) & 0xffff) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_NOT(r1, d) (DIF_INSTR_FMT(DIF_OP_NOT, r1, 0, d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_MOV(r1, d) (DIF_INSTR_FMT(DIF_OP_MOV, r1, 0, d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_CMP(op, r1, r2) (DIF_INSTR_FMT(op, r1, r2, 0)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_TST(r1) (DIF_INSTR_FMT(DIF_OP_TST, r1, 0, 0)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_BRANCH(op, label) (((op) << 24) | (label)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_STORE(op, r1, d) (DIF_INSTR_FMT(op, r1, 0, d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_SETX(i, d) ((DIF_OP_SETX << 24) | ((i) << 8) | (d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_SETS(s, d) ((DIF_OP_SETS << 24) | ((s) << 8) | (d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_RET(d) (DIF_INSTR_FMT(DIF_OP_RET, 0, 0, d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_LDA(op, v, r, d) (DIF_INSTR_FMT(op, v, r, d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_LDV(op, v, d) (((op) << 24) | ((v) << 8) | (d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_STV(op, v, rs) (((op) << 24) | ((v) << 8) | (rs)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_CALL(s, d) ((DIF_OP_CALL << 24) | ((s) << 8) | (d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_PUSHTS(op, t, r2, rs) (DIF_INSTR_FMT(op, t, r2, rs)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_ALLOCS(r1, d) (DIF_INSTR_FMT(DIF_OP_ALLOCS, r1, 0, d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_COPYS(r1, r2, d) (DIF_INSTR_FMT(DIF_OP_COPYS, r1, r2, d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DIF_INSTR_XLATE(op, r, d) (((op) << 24) | ((r) << 8) | (d)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DTRACEACT_ISSPECULATIVE(x) \ cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DOF_ATTR(n, d, c) (((n) << 24) | ((d) << 16) | ((c) << 8)) cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DTRACE_SIZEOF_EPROBEDESC(desc) \ cddl/contrib/opensolaris/uts/common/sys/dtrace.h:#define DTRACE_SIZEOF_AGGDESC(desc) \ cddl/contrib/opensolaris/uts/common/sys/extdirent.h:#define ED_CASE_CONFLICTS(x) ((x)->ed_eflags & ED_CASE_CONFLICT) cddl/contrib/opensolaris/uts/common/sys/fs/zfs.h:#define VDEV_STAT_VALID(field, uint64_t_field_count) \ cddl/contrib/opensolaris/uts/common/sys/idmap.h:#define IDMAP_ID_IS_EPHEMERAL(pid) \ cddl/contrib/opensolaris/uts/common/sys/nvpair.h:#define NVP_SIZE(nvp) ((nvp)->nvp_size) cddl/contrib/opensolaris/uts/common/sys/nvpair.h:#define NVL_VERSION(nvl) ((nvl)->nvl_version) cddl/contrib/opensolaris/uts/common/sys/nvpair.h:#define NVL_SIZE(nvl) ((nvl)->nvl_size) cddl/contrib/opensolaris/uts/common/sys/nvpair.h:#define NVL_FLAG(nvl) ((nvl)->nvl_flag) cddl/contrib/opensolaris/uts/common/sys/procset.h:#define setprocset(psp, op, ltype, lid, rtype, rid) \ cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define dtob(DD) ((DD) << DEV_BSHIFT) cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define btod(BB) (((BB) + DEV_BSIZE - 1) >> DEV_BSHIFT) cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define btodt(BB) ((BB) >> DEV_BSHIFT) cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define lbtod(BB) (((offset_t)(BB) + DEV_BSIZE - 1) >> DEV_BSHIFT) cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define BYTE_TO_BCD(x) byte_to_bcd[(x) & 0xff] cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define BCD_TO_BYTE(x) bcd_to_byte[(x) & 0xff] cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define geteminor(x) (minor_t)((x) & L_MAXMIN) cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define cmpdev(x) \ cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define expdev(x) \ cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define INCR_COUNT(var, mutex) mutex_enter(mutex), (*(var))++, mutex_exit(mutex) cddl/contrib/opensolaris/uts/common/sys/sysmacros.h:#define DECR_COUNT(var, mutex) mutex_enter(mutex), (*(var))--, mutex_exit(mutex) cddl/contrib/opensolaris/uts/intel/dtrace/fasttrap_isa.c:#define FASTTRAP_REX_W(rex) (((rex) >> 3) & 1) cddl/contrib/opensolaris/uts/intel/dtrace/fasttrap_isa.c:#define FASTTRAP_REX_R(rex) (((rex) >> 2) & 1) cddl/dev/fbt/fbt.c:#define ctf_list_prev(elem) ((void *)(((ctf_list_t *)(elem))->l_prev)) compat/linux/linux_dtrace.h:#define LIN_SDT_PROBE_DECLARE(a, b, c) _LIN_SDT_PROBE_DECLARE( \ compat/linux/linux_socket.h:#define LINUX_CMSG_SPACE(len) (LINUX_CMSG_ALIGN(sizeof(struct l_cmsghdr)) + \ compat/linuxkpi/common/include/asm/atomic-long.h:#define ATOMIC_LONG_INIT(x) { .counter = (x) } compat/linuxkpi/common/include/asm/atomic-long.h:#define atomic_long_inc_return(v) atomic_long_add_return(1, (v)) compat/linuxkpi/common/include/asm/atomic-long.h:#define atomic_long_inc_not_zero(v) atomic_long_add_unless((v), 1, 0) compat/linuxkpi/common/include/asm/atomic.h:#define cmpxchg_relaxed(...) cmpxchg(__VA_ARGS__) compat/linuxkpi/common/include/asm/msr.h:#define rdmsrl(msr, val) ((val) = rdmsr(msr)) compat/linuxkpi/common/include/asm/smp.h:#define wbinvd_on_all_cpus() linux_wbinvd_on_all_cpus() compat/linuxkpi/common/include/asm/smp.h:#define get_cpu() ({ \ compat/linuxkpi/common/include/asm/smp.h:#define put_cpu() \ compat/linuxkpi/common/include/asm/uaccess.h:#define __copy_in_user(...) copy_from_user(__VA_ARGS__) compat/linuxkpi/common/include/linux/clocksource.h:#define CLOCKSOURCE_MASK(x) ((u64)(-1ULL >> ((-(x)) & 63))) compat/linuxkpi/common/include/linux/compiler.h:#define __chk_user_ptr(x) ((void)0) compat/linuxkpi/common/include/linux/compiler.h:#define __chk_io_ptr(x) ((void)0) compat/linuxkpi/common/include/linux/compiler.h:#define __builtin_warning(x, y...) (1) compat/linuxkpi/common/include/linux/compiler.h:#define __cond_lock(x,c) (c) compat/linuxkpi/common/include/linux/compiler.h:#define __PASTE(a,b) ___PASTE(a,b) compat/linuxkpi/common/include/linux/compiler.h:#define lockless_dereference(p) READ_ONCE(p) compat/linuxkpi/common/include/linux/completion.h:#define wait_for_completion_interuptible(c) \ compat/linuxkpi/common/include/linux/completion.h:#define completion_done(c) \ compat/linuxkpi/common/include/linux/device.h:#define DEVICE_ATTR_RO(_name) \ compat/linuxkpi/common/include/linux/device.h:#define DEVICE_ATTR_WO(_name) \ compat/linuxkpi/common/include/linux/device.h:#define DEVICE_ATTR_RW(_name) \ compat/linuxkpi/common/include/linux/device.h:#define CLASS_ATTR_STRING(_name, _mode, _str) \ compat/linuxkpi/common/include/linux/device.h:#define dev_notice(dev, fmt, ...) device_printf((dev)->bsddev, fmt, ##__VA_ARGS__) compat/linuxkpi/common/include/linux/device.h:#define dev_err_ratelimited(dev, ...) do { \ compat/linuxkpi/common/include/linux/device.h:#define dev_warn_ratelimited(dev, ...) do { \ compat/linuxkpi/common/include/linux/fs.h:#define replace_fops(f, fops) ((f)->f_op = (fops)) compat/linuxkpi/common/include/linux/fs.h:#define iminor(...) linux_iminor(__VA_ARGS__) compat/linuxkpi/common/include/linux/fs.h:#define invalidate_mapping_pages(...) \ compat/linuxkpi/common/include/linux/fs.h:#define shmem_read_mapping_page(...) \ compat/linuxkpi/common/include/linux/fs.h:#define shmem_read_mapping_page_gfp(...) \ compat/linuxkpi/common/include/linux/fs.h:#define shmem_file_setup(...) \ compat/linuxkpi/common/include/linux/fs.h:#define shmem_truncate_range(...) \ compat/linuxkpi/common/include/linux/gfp.h:#define SetPageReserved(page) do { } while (0) /* NOP */ compat/linuxkpi/common/include/linux/gfp.h:#define ClearPageReserved(page) do { } while (0) /* NOP */ compat/linuxkpi/common/include/linux/hrtimer.h:#define hrtimer_active(hrtimer) linux_hrtimer_active(hrtimer) compat/linuxkpi/common/include/linux/hrtimer.h:#define hrtimer_cancel(hrtimer) linux_hrtimer_cancel(hrtimer) compat/linuxkpi/common/include/linux/hrtimer.h:#define hrtimer_init(hrtimer, clock, mode) do { \ compat/linuxkpi/common/include/linux/hrtimer.h:#define hrtimer_set_expires(hrtimer, time) \ compat/linuxkpi/common/include/linux/hrtimer.h:#define hrtimer_start(hrtimer, time, mode) do { \ compat/linuxkpi/common/include/linux/hrtimer.h:#define hrtimer_start_range_ns(hrtimer, time, prec, mode) do { \ compat/linuxkpi/common/include/linux/idr.h:#define DEFINE_IDA(name) \ compat/linuxkpi/common/include/linux/idr.h:#define idr_for_each_entry(idp, entry, id) \ compat/linuxkpi/common/include/linux/interrupt.h:#define DECLARE_TASKLET(name, func, data) \ compat/linuxkpi/common/include/linux/jiffies.h:#define time_in_range(a,b,c) \ compat/linuxkpi/common/include/linux/jiffies.h:#define time_is_after_eq_jiffies(a) time_after_eq(a, jiffies) compat/linuxkpi/common/include/linux/kernel.h:#define BUILD_BUG_ON_MSG(x, msg) BUILD_BUG_ON(x) compat/linuxkpi/common/include/linux/kernel.h:#define DIV_ROUND_UP_ULL(x, n) DIV_ROUND_UP((unsigned long long)(x), (n)) compat/linuxkpi/common/include/linux/kernel.h:#define pr_emerg(fmt, ...) \ compat/linuxkpi/common/include/linux/kernel.h:#define pr_alert(fmt, ...) \ compat/linuxkpi/common/include/linux/kernel.h:#define pr_crit(fmt, ...) \ compat/linuxkpi/common/include/linux/kernel.h:#define pr_notice(fmt, ...) \ compat/linuxkpi/common/include/linux/kernel.h:#define pr_warn_ratelimited(...) do { \ compat/linuxkpi/common/include/linux/kernel.h:#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi) compat/linuxkpi/common/include/linux/kernel.h:#define num_possible_cpus() mp_ncpus compat/linuxkpi/common/include/linux/kernel.h:#define DIV_ROUND_CLOSEST_ULL(x, divisor) ({ \ compat/linuxkpi/common/include/linux/kthread.h:#define kthread_should_stop_task(task) linux_kthread_should_stop_task(task) compat/linuxkpi/common/include/linux/kthread.h:#define kthread_park(task) linux_kthread_park(task) compat/linuxkpi/common/include/linux/kthread.h:#define kthread_parkme() linux_kthread_parkme() compat/linuxkpi/common/include/linux/kthread.h:#define kthread_should_park() linux_kthread_should_park() compat/linuxkpi/common/include/linux/kthread.h:#define in_atomic() linux_in_atomic() compat/linuxkpi/common/include/linux/ktime.h:#define ktime_to_timespec(kt) ns_to_timespec((kt).tv64) compat/linuxkpi/common/include/linux/ktime.h:#define ktime_get_raw_ns() ktime_get_ns() compat/linuxkpi/common/include/linux/list.h:#define LINUX_LIST_HEAD(name) \ compat/linuxkpi/common/include/linux/list.h:#define list_first_entry_or_null(ptr, type, member) \ compat/linuxkpi/common/include/linux/list.h:#define list_for_each_entry_from(p, h, field) \ compat/linuxkpi/common/include/linux/lockdep.h:#define lockdep_set_class(lock, key) compat/linuxkpi/common/include/linux/lockdep.h:#define lockdep_assert_held(m) \ compat/linuxkpi/common/include/linux/lockdep.h:#define lockdep_assert_held_once(m) \ compat/linuxkpi/common/include/linux/lockdep.h:#define lockdep_is_held(m) (sx_xholder(&(m)->sx) == curthread) compat/linuxkpi/common/include/linux/lockdep.h:#define might_lock(m) do { } while (0) compat/linuxkpi/common/include/linux/mm.h:#define copy_highpage(to, from) pmap_copy_page(from, to) compat/linuxkpi/common/include/linux/mm_types.h:#define get_task_mm(task) linux_get_task_mm(task) compat/linuxkpi/common/include/linux/module.h:#define MODULE_INFO(tag, info) compat/linuxkpi/common/include/linux/module.h:#define module_get(module) compat/linuxkpi/common/include/linux/module.h:#define postcore_initcall(fn) module_init(fn) compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_bool(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_byte(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_short(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_ushort(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_int(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_uint(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_long(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define LINUXKPI_PARAM_ulong(name, var, perm) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define module_param_named_unsafe(name, var, type, mode) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define module_param_unsafe(var, type, mode) \ compat/linuxkpi/common/include/linux/moduleparam.h:#define module_param_array(var, type, addr_argc, mode) compat/linuxkpi/common/include/linux/mutex.h:#define mutex_lock_nest_lock(_m, _s) mutex_lock(_m) compat/linuxkpi/common/include/linux/mutex.h:#define mutex_init_witness(_m) \ compat/linuxkpi/common/include/linux/netdevice.h:#define net_eq(a,b) ((a) == (b)) compat/linuxkpi/common/include/linux/netdevice.h:#define netif_oper_up(dev) !!((dev)->if_flags & IFF_UP) compat/linuxkpi/common/include/linux/pci.h:#define pci_map_single(_hwdev, _ptr, _size, _dir) \ compat/linuxkpi/common/include/linux/pci.h:#define pci_unmap_single(_hwdev, _addr, _size, _dir) \ compat/linuxkpi/common/include/linux/pci.h:#define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); compat/linuxkpi/common/include/linux/pfn.h:#define PFN_ALIGN(x) (((unsigned long)(x) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1)) compat/linuxkpi/common/include/linux/pfn.h:#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) compat/linuxkpi/common/include/linux/pfn.h:#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) compat/linuxkpi/common/include/linux/pfn.h:#define PFN_PHYS(x) ((phys_addr_t)(x) << PAGE_SHIFT) compat/linuxkpi/common/include/linux/pfn.h:#define PHYS_PFN(x) ((unsigned long)((x) >> PAGE_SHIFT)) compat/linuxkpi/common/include/linux/pid.h:#define pid_nr(n) (n) compat/linuxkpi/common/include/linux/pid.h:#define pid_vnr(n) (n) compat/linuxkpi/common/include/linux/pid.h:#define from_kuid_munged(a, uid) (uid) compat/linuxkpi/common/include/linux/pid.h:#define pid_task(pid, type) ({ \ compat/linuxkpi/common/include/linux/pid.h:#define get_pid_task(pid, type) ({ \ compat/linuxkpi/common/include/linux/printk.h:#define printk_ratelimited(...) do { \ compat/linuxkpi/common/include/linux/radix-tree.h:#define RADIX_TREE(name, mask) \ compat/linuxkpi/common/include/linux/rbtree.h:#define rb_is_red(r) (rb_color(r) == RB_RED) compat/linuxkpi/common/include/linux/rbtree.h:#define rb_is_black(r) (rb_color(r) == RB_BLACK) compat/linuxkpi/common/include/linux/rbtree.h:#define RB_EMPTY_ROOT(root) RB_EMPTY((struct linux_root *)root) compat/linuxkpi/common/include/linux/rbtree.h:#define RB_EMPTY_NODE(node) (rb_parent(node) == node) compat/linuxkpi/common/include/linux/rbtree.h:#define RB_CLEAR_NODE(node) (rb_set_parent(node, node)) compat/linuxkpi/common/include/linux/rbtree.h:#define rb_prev(node) RB_PREV(linux_root, NULL, (node)) compat/linuxkpi/common/include/linux/rbtree.h:#define rb_last(root) RB_MAX(linux_root, (struct linux_root *)(root)) compat/linuxkpi/common/include/linux/rculist.h:#define hlist_pprev_rcu(node) (*((struct hlist_node **)((node)->pprev))) compat/linuxkpi/common/include/linux/rculist.h:#define hlist_for_each_entry_rcu(pos, head, member) \ compat/linuxkpi/common/include/linux/rcupdate.h:#define RCU_INITIALIZER(v) \ compat/linuxkpi/common/include/linux/rcupdate.h:#define RCU_INIT_POINTER(p, v) do { \ compat/linuxkpi/common/include/linux/rcupdate.h:#define rcu_read_lock(void) do { \ compat/linuxkpi/common/include/linux/rcupdate.h:#define rcu_read_unlock(void) do { \ compat/linuxkpi/common/include/linux/rcupdate.h:#define synchronize_rcu_expedited(void) do { \ compat/linuxkpi/common/include/linux/rcupdate.h:#define rcu_access_pointer(p) \ compat/linuxkpi/common/include/linux/rcupdate.h:#define rcu_dereference(p) \ compat/linuxkpi/common/include/linux/rcupdate.h:#define rcu_pointer_handoff(p) (p) compat/linuxkpi/common/include/linux/rwlock.h:#define read_lock_irq(lock) read_lock((lock)) compat/linuxkpi/common/include/linux/rwlock.h:#define read_unlock_irq(lock) read_unlock((lock)) compat/linuxkpi/common/include/linux/rwsem.h:#define down_read_trylock(_rw) !!sx_try_slock(&(_rw)->sx) compat/linuxkpi/common/include/linux/rwsem.h:#define down_write_trylock(_rw) !!sx_try_xlock(&(_rw)->sx) compat/linuxkpi/common/include/linux/rwsem.h:#define downgrade_write(_rw) sx_downgrade(&(_rw)->sx) compat/linuxkpi/common/include/linux/rwsem.h:#define DECLARE_RWSEM(name) \ compat/linuxkpi/common/include/linux/scatterlist.h:#define for_each_sg_page(sgl, iter, nents, pgoffset) \ compat/linuxkpi/common/include/linux/sched.h:#define task_pid_group_leader(task) (task)->task_thread->td_proc->p_pid compat/linuxkpi/common/include/linux/sched.h:#define task_pid(task) ((task)->pid) compat/linuxkpi/common/include/linux/sched.h:#define task_pid_nr(task) ((task)->pid) compat/linuxkpi/common/include/linux/sched.h:#define get_pid(x) (x) compat/linuxkpi/common/include/linux/sched.h:#define put_pid(x) do { } while (0) compat/linuxkpi/common/include/linux/sched.h:#define current_euid() (curthread->td_ucred->cr_uid) compat/linuxkpi/common/include/linux/sched.h:#define signal_pending_state(state, task) \ compat/linuxkpi/common/include/linux/sched.h:#define schedule_timeout_killable(timeout) \ compat/linuxkpi/common/include/linux/sched.h:#define schedule_timeout_interruptible(timeout) ({ \ compat/linuxkpi/common/include/linux/sched.h:#define io_schedule() schedule() compat/linuxkpi/common/include/linux/sched.h:#define io_schedule_timeout(timeout) schedule_timeout(timeout) compat/linuxkpi/common/include/linux/slab.h:#define kvmalloc(size) kmalloc(size, 0) compat/linuxkpi/common/include/linux/slab.h:#define kfree_const(ptr) kfree(ptr) compat/linuxkpi/common/include/linux/slab.h:#define vmalloc_user(size) __vmalloc(size, GFP_KERNEL | __GFP_ZERO, 0) compat/linuxkpi/common/include/linux/slab.h:#define __kmalloc(...) kmalloc(__VA_ARGS__) compat/linuxkpi/common/include/linux/spinlock.h:#define spin_lock_irqsave_nested(_l, flags, _n) do { \ compat/linuxkpi/common/include/linux/spinlock.h:#define assert_spin_locked(_l) do { \ compat/linuxkpi/common/include/linux/srcu.h:#define srcu_dereference(ptr,srcu) ((__typeof(*(ptr)) *)(ptr)) compat/linuxkpi/common/include/linux/sysfs.h:#define ATTRIBUTE_GROUPS(_name) \ compat/linuxkpi/common/include/linux/timer.h:#define __setup_timer(timer, func, dat, flags) do { \ compat/linuxkpi/common/include/linux/uaccess.h:#define clear_user(...) linux_clear_user(__VA_ARGS__) compat/linuxkpi/common/include/linux/usb.h:#define USB_DEVICE(vend,prod) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_sndctrlpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_rcvctrlpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_sndisocpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_rcvisocpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_sndbulkpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_rcvbulkpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_sndintpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define usb_rcvintpipe(dev,endpoint) \ compat/linuxkpi/common/include/linux/usb.h:#define interface_to_usbdev(intf) (intf)->linux_udev compat/linuxkpi/common/include/linux/usb.h:#define interface_to_bsddev(intf) (intf)->linux_udev compat/linuxkpi/common/include/linux/wait.h:#define SKIP_SLEEP() (SCHEDULER_STOPPED() || kdb_active) compat/linuxkpi/common/include/linux/wait.h:#define DECLARE_WAITQUEUE(name, task) \ compat/linuxkpi/common/include/linux/wait.h:#define DECLARE_WAIT_QUEUE_HEAD(name) \ compat/linuxkpi/common/include/linux/wait.h:#define wake_up_locked(wqh) \ compat/linuxkpi/common/include/linux/wait.h:#define wake_up_all_locked(wqh) \ compat/linuxkpi/common/include/linux/wait.h:#define wait_event_interruptible_locked(wqh, cond) ({ \ compat/linuxkpi/common/include/linux/wait.h:#define wait_event_interruptible_lock_irq(wqh, cond, lock) ({ \ compat/linuxkpi/common/include/linux/wait.h:#define waitqueue_active(wqh) linux_waitqueue_active(wqh) compat/linuxkpi/common/include/linux/wait.h:#define wake_up_bit(word, bit) linux_wake_up_bit(word, bit) compat/linuxkpi/common/include/linux/wait.h:#define wait_on_bit_timeout(word, bit, state, timeout) \ compat/linuxkpi/common/include/linux/wait.h:#define wake_up_atomic_t(a) linux_wake_up_atomic_t(a) compat/linuxkpi/common/include/linux/wait.h:#define wait_on_atomic_t(a, state) linux_wait_on_atomic_t(a, state) compat/linuxkpi/common/include/linux/workqueue.h:#define DECLARE_DELAYED_WORK(name, fn) \ compat/linuxkpi/common/include/linux/workqueue.h:#define INIT_WORK_ONSTACK(work, fn) \ compat/linuxkpi/common/include/linux/workqueue.h:#define schedule_delayed_work_on(cpu, dwork, delay) \ compat/linuxkpi/common/include/linux/workqueue.h:#define queue_work_on(cpu, wq, work) \ compat/linuxkpi/common/include/linux/workqueue.h:#define queue_delayed_work_on(cpu, wq, dwork, delay) \ compat/linuxkpi/common/include/linux/workqueue.h:#define alloc_ordered_workqueue(name, flags) \ compat/linuxkpi/common/include/linux/workqueue.h:#define delayed_work_pending(dwork) \ compat/linuxkpi/common/include/linux/workqueue.h:#define flush_work(work) \ compat/linuxkpi/common/include/linux/workqueue.h:#define flush_delayed_work(dwork) \ compat/linuxkpi/common/include/linux/workqueue.h:#define work_busy(work) \ compat/linuxkpi/common/include/linux/workqueue.h:#define destroy_work_on_stack(work) \ compat/linuxkpi/common/include/linux/workqueue.h:#define destroy_delayed_work_on_stack(dwork) \ compat/linuxkpi/common/include/linux/ww_mutex.h:#define DEFINE_WW_CLASS(name) \ compat/linuxkpi/common/include/linux/ww_mutex.h:#define DEFINE_WW_MUTEX(name, ww_class) \ compat/linuxkpi/common/include/linux/ww_mutex.h:#define ww_mutex_is_locked(_m) \ compat/linuxkpi/common/include/linux/ww_mutex.h:#define ww_mutex_lock_slow(_m, _x) \ compat/linuxkpi/common/include/linux/ww_mutex.h:#define ww_mutex_lock_slow_interruptible(_m, _x) \ compat/ndis/ndis_var.h:#define NdisInitializeWorkItem(w, f, c) \ compat/ndis/ndis_var.h:#define NdisQueryPacket(p, pbufcnt, bufcnt, firstbuf, plen) \ compat/ndis/ntoskrnl_var.h:#define MmGetMdlStartVa(mdl) ((mdl)->mdl_startva) compat/ndis/ntoskrnl_var.h:#define AT_PASSIVE_LEVEL(td) \ compat/ndis/ntoskrnl_var.h:#define AT_DISPATCH_LEVEL(td) \ compat/ndis/ntoskrnl_var.h:#define AT_DIRQL_LEVEL(td) \ compat/ndis/ntoskrnl_var.h:#define AT_HIGH_LEVEL(td) \ compat/ndis/ntoskrnl_var.h:#define IO_FUNC(x) (((x) & 0x7FFC) >> 2) compat/ndis/ntoskrnl_var.h:#define IOCTL_CODE(dev, func, iomethod, acc) \ compat/ndis/ntoskrnl_var.h:#define IoSetCompletionRoutine(irp, func, ctx, ok, err, cancel) \ compat/ndis/ntoskrnl_var.h:#define IoUnmarkIrpPending(irp) \ compat/ndis/ntoskrnl_var.h:#define IoCopyCurrentIrpStackLocationToNext(irp) \ compat/ndis/pe_var.h:#define IMAGE_SIZEOF_NT_HEADER(nthdr) \ compat/netbsd/dvcfg.h:#define DVCFG_MINOR(dvcfg) (((u_int)(dvcfg)) & 0xffff) compat/netbsd/dvcfg.h:#define DVCFG_MKCFG(major, minor) ((((u_int)(major)) << 16) | ((minor) & 0xffff)) compat/netbsd/dvcfg.h:#define DVCFG_HWSEL_SZ(array) (sizeof(array) / sizeof(dvcfg_hw_t)) compat/netbsd/dvcfg.h:#define DVCFG_HW(SELP, NUM) dvcfg_hw((SELP), (NUM)) contrib/alpine-hal/al_hal_common.h:#define al_max_t(type, x, y) ({ \ contrib/alpine-hal/al_hal_nb_regs.h:#define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE(i) \ contrib/alpine-hal/al_hal_plat_services.h:#define al_print(type, fmt, ...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_NONE) { AL_DBG_LOCK(); printf(fmt, ##__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0) contrib/alpine-hal/al_hal_plat_services.h:#define al_strcmp(s1, s2) strcmp(s1, s2) contrib/alpine-hal/al_hal_plat_services.h:#define al_get_cpu_id() 0 contrib/alpine-hal/al_hal_plat_types.h:#define PLAT_ARCH_IS_LITTLE() AL_TRUE contrib/alpine-hal/al_hal_reg_utils.h:#define AL_REG_BITS_FIELD(shift, val) \ contrib/alpine-hal/al_hal_reg_utils.h:#define AL_REG_CLEAR_AND_SET(reg, clear_mask, set_mask) \ contrib/alpine-hal/al_hal_reg_utils.h:#define AL_ALIGN_UP(val, size) \ contrib/alpine-hal/al_hal_udma.h:#define cdesc_is_first(flags) ((flags) & AL_UDMA_CDESC_FIRST) contrib/alpine-hal/eth/al_hal_eth.h:#define AL_ETH_FSM_ENTRY_INNER(idx) (((idx) >> 3) & 7) contrib/alpine-hal/eth/al_hal_eth.h:#define AL_ETH_FSM_ENTRY_TUNNELED(idx) (((idx) >> 6) & 1) contrib/ck/include/ck_array.h:#define CK_ARRAY_FOREACH(a, i, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_INSTANCE(n_entries) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_ITERATOR_INIT(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_INIT(a, b, c) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_NEXT(a, b, c) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_SET(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_BTS(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_RESET(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_TEST(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_UNION(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_INTERSECTION(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_INTERSECTION_NEGATE(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_CLEAR(a) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_EMPTY(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_FULL(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_COUNT(a, b) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_COUNT_INTERSECT(a, b, c) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_BITS(a) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP_BUFFER(a) \ contrib/ck/include/ck_bitmap.h:#define CK_BITMAP(a) \ contrib/ck/include/ck_cc.h:#define CK_CC_PAD(x) union { char pad[x]; } contrib/ck/include/ck_cohort.h:#define CK_COHORT_INIT(N, C, GL, LL, P) ck_cohort_##N##_init(C, GL, LL, P) contrib/ck/include/ck_cohort.h:#define CK_COHORT_TRYLOCK(N, C, GLC, LLC, LUC) ck_cohort_##N##_trylock(C, GLC, LLC, LUC) contrib/ck/include/ck_cohort.h:#define CK_COHORT_TRYLOCK_PROTOTYPE(N, GL, GU, GI, GTL, LL, LU, LI, LTL) \ contrib/ck/include/ck_elide.h:#define CK_ELIDE_LOCK(NAME, LOCK) ck_elide_##NAME##_lock(LOCK) contrib/ck/include/ck_elide.h:#define CK_ELIDE_UNLOCK(NAME, LOCK) ck_elide_##NAME##_unlock(LOCK) contrib/ck/include/ck_elide.h:#define CK_ELIDE_TRYLOCK(NAME, LOCK) ck_elide_##NAME##_trylock(LOCK) contrib/ck/include/ck_elide.h:#define CK_ELIDE_LOCK_ADAPTIVE(NAME, STAT, CONFIG, LOCK) \ contrib/ck/include/ck_elide.h:#define CK_ELIDE_UNLOCK_ADAPTIVE(NAME, STAT, LOCK) \ contrib/ck/include/ck_epoch.h:#define CK_EPOCH_CONTAINER(T, M, N) \ contrib/ck/include/ck_fifo.h:#define CK_FIFO_SPSC_ISEMPTY(f) ((f)->head->next == NULL) contrib/ck/include/ck_fifo.h:#define CK_FIFO_SPSC_SPARE(f) ((f)->head) contrib/ck/include/ck_fifo.h:#define CK_FIFO_SPSC_FOREACH(fifo, entry) \ contrib/ck/include/ck_fifo.h:#define CK_FIFO_SPSC_FOREACH_SAFE(fifo, entry, T) \ contrib/ck/include/ck_fifo.h:#define CK_FIFO_MPMC_ISEMPTY(f) ((f)->head.pointer->next.pointer == NULL) contrib/ck/include/ck_fifo.h:#define CK_FIFO_MPMC_FOREACH(fifo, entry) \ contrib/ck/include/ck_fifo.h:#define CK_FIFO_MPMC_FOREACH_SAFE(fifo, entry, T) \ contrib/ck/include/ck_hp_fifo.h:#define CK_HP_FIFO_ISEMPTY(f) ((f)->head->next == NULL) contrib/ck/include/ck_hp_fifo.h:#define CK_HP_FIFO_FOREACH(fifo, entry) \ contrib/ck/include/ck_hp_fifo.h:#define CK_HP_FIFO_FOREACH_SAFE(fifo, entry, T) \ contrib/ck/include/ck_hs.h:#define CK_HS_HASH(T, F, K) F((K), (T)->seed) contrib/ck/include/ck_pr.h:#define ck_pr_store_char(DST, VAL) CK_PR_STORE_SAFE((DST), (VAL), char) contrib/ck/include/ck_pr.h:#define ck_pr_store_double(DST, VAL) CK_PR_STORE_SAFE((DST), (VAL), double) contrib/ck/include/ck_pr.h:#define ck_pr_load_char(SRC) CK_PR_LOAD_SAFE((SRC), char) contrib/ck/include/ck_pr.h:#define ck_pr_load_double(SRC) CK_PR_LOAD_SAFE((SRC), double) contrib/ck/include/ck_queue.h:#define CK_SLIST_HEAD(name, type) \ contrib/ck/include/ck_queue.h:#define CK_SLIST_HEAD_INITIALIZER(head) \ contrib/ck/include/ck_queue.h:#define CK_SLIST_ENTRY(type) \ contrib/ck/include/ck_queue.h:#define CK_SLIST_EMPTY(head) \ contrib/ck/include/ck_queue.h:#define CK_SLIST_FOREACH(var, head, field) \ contrib/ck/include/ck_queue.h:#define CK_SLIST_FOREACH_SAFE(var, head, field, tvar) \ contrib/ck/include/ck_queue.h:#define CK_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ contrib/ck/include/ck_queue.h:#define CK_SLIST_INIT(head) do { \ contrib/ck/include/ck_queue.h:#define CK_SLIST_INSERT_AFTER(a, b, field) do { \ contrib/ck/include/ck_queue.h:#define CK_SLIST_INSERT_HEAD(head, elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_SLIST_REMOVE(head, elm, type, field) do { \ contrib/ck/include/ck_queue.h:#define CK_SLIST_MOVE(head1, head2, field) do { \ contrib/ck/include/ck_queue.h:#define CK_SLIST_SWAP(a, b, type) do { \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_HEAD(name, type) \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_HEAD_INITIALIZER(head) \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_ENTRY(type) \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_CONCAT(head1, head2) do { \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_FOREACH(var, head, field) \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_FOREACH_SAFE(var, head, field, tvar) \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_INSERT_HEAD(head, elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_INSERT_TAIL(head, elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_REMOVE(head, elm, type, field) do { \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_MOVE(head1, head2, field) do { \ contrib/ck/include/ck_queue.h:#define CK_STAILQ_SWAP(head1, head2, type) do { \ contrib/ck/include/ck_queue.h:#define CK_LIST_HEAD(name, type) \ contrib/ck/include/ck_queue.h:#define CK_LIST_HEAD_INITIALIZER(head) \ contrib/ck/include/ck_queue.h:#define CK_LIST_ENTRY(type) \ contrib/ck/include/ck_queue.h:#define CK_LIST_EMPTY(head) (CK_LIST_FIRST(head) == NULL) contrib/ck/include/ck_queue.h:#define CK_LIST_FOREACH(var, head, field) \ contrib/ck/include/ck_queue.h:#define CK_LIST_FOREACH_SAFE(var, head, field, tvar) \ contrib/ck/include/ck_queue.h:#define CK_LIST_INIT(head) do { \ contrib/ck/include/ck_queue.h:#define CK_LIST_INSERT_AFTER(listelm, elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_LIST_INSERT_BEFORE(listelm, elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_LIST_INSERT_HEAD(head, elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_LIST_REMOVE(elm, field) do { \ contrib/ck/include/ck_queue.h:#define CK_LIST_MOVE(head1, head2, field) do { \ contrib/ck/include/ck_queue.h:#define CK_LIST_SWAP(head1, head2, type, field) do { \ contrib/ck/include/ck_rhs.h:#define CK_RHS_HASH(T, F, K) F((K), (T)->seed) contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_SPSC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_SPSC_SIZE(name, a, b, c, d) \ contrib/ck/include/ck_ring.h:#define CK_RING_DEQUEUE_SPSC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_SPMC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_SPMC_SIZE(name, a, b, c, d) \ contrib/ck/include/ck_ring.h:#define CK_RING_TRYDEQUEUE_SPMC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_DEQUEUE_SPMC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_MPSC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_MPSC_SIZE(name, a, b, c, d) \ contrib/ck/include/ck_ring.h:#define CK_RING_DEQUEUE_MPSC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_MPMC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_ENQUEUE_MPMC_SIZE(name, a, b, c, d) \ contrib/ck/include/ck_ring.h:#define CK_RING_TRYDEQUEUE_MPMC(name, a, b, c) \ contrib/ck/include/ck_ring.h:#define CK_RING_DEQUEUE_MPMC(name, a, b, c) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_WP_INIT(N, RW, WL) ck_rwcohort_wp_##N##_init(RW, WL) contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_WP_READ_LOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_WP_READ_UNLOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_WP_WRITE_LOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_WP_WRITE_UNLOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_WP_PROTOTYPE(N) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_RP_INIT(N, RW, WL) ck_rwcohort_rp_##N##_init(RW, WL) contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_RP_READ_LOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_RP_READ_UNLOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_RP_WRITE_LOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_RP_WRITE_UNLOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_RP_PROTOTYPE(N) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_NEUTRAL_INIT(N, RW) ck_rwcohort_neutral_##N##_init(RW) contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_NEUTRAL_READ_LOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_NEUTRAL_READ_UNLOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_NEUTRAL_WRITE_LOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_NEUTRAL_WRITE_UNLOCK(N, RW, C, GC, LC) \ contrib/ck/include/ck_rwcohort.h:#define CK_RWCOHORT_NEUTRAL_PROTOTYPE(N) \ contrib/ck/include/ck_sequence.h:#define CK_SEQUENCE_READ(seqlock, version) \ contrib/ck/include/ck_spinlock.h:#define ck_spinlock_lock_eb(x) ck_spinlock_fas_lock_eb(x) contrib/ck/include/ck_stack.h:#define CK_STACK_ISEMPTY(m) ((m)->head == NULL) contrib/dev/acpica/common/dmtbinfo.c:#define ACPI_SDEI_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_TABLE_SDEI,f) contrib/dev/acpica/common/dmtbinfo.c:#define ACPI_SDEV_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_TABLE_SDEV,f) contrib/dev/acpica/common/dmtbinfo.c:#define ACPI_SLIC_OFFSET(f) (UINT16) ACPI_OFFSET (ACPI_TABLE_SLIC,f) contrib/dev/acpica/compiler/asldefine.h:#define ASL_PTR_DIFF(a,b) ((UINT8 *)(b) - (UINT8 *)(a)) contrib/dev/acpica/compiler/asldefine.h:#define ASL_PTR_ADD(a,b) ((UINT8 *)(a) = ((UINT8 *)(a) + (b))) contrib/dev/acpica/include/acapps.h:#define ACPI_USAGE_TEXT(Description) \ contrib/dev/acpica/include/acapps.h:#define ACPI_CHECK_OK(Name, Status) ACPI_CHECK_STATUS (Name, Status, AE_OK); contrib/dev/acpica/include/acdebug.h:#define PARAM_LIST(pl) pl contrib/dev/acpica/include/acmacros.h:#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a) ACPI_ROUND_DOWN(a, sizeof(ACPI_SIZE)) contrib/dev/acpica/include/acmacros.h:#define ACPI_INIT_UUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ contrib/dev/acpica/include/actypes.h:#define ACPI_LOBYTE(Integer) ((UINT8) (UINT16)(Integer)) contrib/dev/acpica/include/actypes.h:#define ACPI_HIBYTE(Integer) ((UINT8) (((UINT16)(Integer)) >> 8)) contrib/dev/acpica/include/actypes.h:#define ACPI_MAX(a,b) (((a)>(b))?(a):(b)) contrib/dev/acpica/include/actypes.h:#define ACPI_MAKE_RSDP_SIG(dest) (memcpy (ACPI_CAST_PTR (char, (dest)), ACPI_SIG_RSDP, 8)) contrib/dev/acpica/include/acutils.h:#define AcpiUtAllocateObjectDesc() AcpiUtAllocateObjectDescDbg (_AcpiModuleName,__LINE__,_COMPONENT) contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c:#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c:#define MAC_DMA_CFG_HALT_REQ_GET(x) (((x) & MAC_DMA_CFG_HALT_REQ_MASK) >> MAC_DMA_CFG_HALT_REQ_LSB) contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c:#define MAC_DMA_CFG_HALT_ACK_SET(x) (((x) << MAC_DMA_CFG_HALT_ACK_LSB) & MAC_DMA_CFG_HALT_ACK_MASK) contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c:#define DDR_REG_WRITE(_ah, _reg, _val) \ contrib/dev/ath/ath_hal/ar9300/ar9300desc.h:#define is_valid_tx_rate(_r) ((1<<(_r)) & VALID_TX_RATES) contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_BBB_RX_CTRL(_i) AR_BBB_OFFSET(BB_bbb_rx_ctrl_##_i) contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_RF_CTL(_i) AR_SM_OFFSET(BB_tx_timing_##_i) contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_TX_FIR(_i) AR_SM_OFFSET(BB_bbb_txfir_##_i) contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_TPC(_i) AR_SM_OFFSET(BB_tpc_##_i) /* values 1-3, 7-10 and 12-15 */ contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_TXGAIN_TAB_PAL(_i) AR_SM_OFFSET(BB_tx_gain_tab_pal_##_i) /* values 1-22 */ contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) contrib/dev/ath/ath_hal/ar9300/ar9300phy.h:#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i))) contrib/dev/ath/ath_hal/ar9300/ar9300reg.h:#define AR_AN_OFFSET(_x) offsetof(struct analog_intf_reg_csr, _x) contrib/dev/ath/ath_hal/ar9300/ar9300reg.h:#define AR_WOW_PAT_END_OF_PKT(x) ((x & 0xf) << 0) contrib/dev/ath/ath_hal/ar9300/ar9300reg.h:#define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8) contrib/dev/ath/ath_hal/ar9300/ar9300reg.h:#define AR_CVCACHE(_idx) (AR_CVCACHE_0+(_idx)) contrib/dev/ath/ath_hal/ar9300/ar9300reg.h:#define AR_BTCOEX_MAX_RFGAIN(_x) AR_WLAN_COEX_OFFSET(BTCOEX_MAX_RFGAIN[_x]) contrib/dev/ath/ath_hal/ar9300/ar9300reg.h:#define AR_GLB_SCRATCH(_ah) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__AHB_RESET__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__AHB_RESET__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__AHB_RESET__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__AHB_RESET__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__AHB_RESET__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__AHB_RESET__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__APB_RESET__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__APB_RESET__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__APB_RESET__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__APB_RESET__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__APB_RESET__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__APB_RESET__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RESET_CONTROL__LOCAL_RESET__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__GDATA_WA_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_CURNT_STATE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_DSTATE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_PM_STATUS__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__PCIE_XMLH_LTSSM_STATE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CXPL_DEBUG_INFOL__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CXPL_DEBUG_INFOH__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__FORCE_RESET__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_CTRL__PROTECT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_SREV__MAC_ID__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_CAUSE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_CAUSE__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_CAUSE__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_CAUSE__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_ENABLE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_ENABLE__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_ENABLE__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_ENABLE__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_MASK__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_MASK__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_MASK__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_MASK__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_MASK__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_MASK__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_MASK__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_SYNC_MASK__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_CAUSE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_ASYNC_ENABLE__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_RW__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_RW__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_RW__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_RW__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LOAD__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LOAD__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LOAD__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LOAD__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OUT__OUT__READ(src) (u_int32_t)(src) & 0x0001ffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OUT__OUT__WRITE(src) ((u_int32_t)(src) & 0x0001ffffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OUT__OUT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OUT__OUT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_IN__IN__READ(src) (u_int32_t)(src) & 0x0001ffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OE__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_OE__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INTR_POLAR__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INTR_POLAR__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INTR_POLAR__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INTR_POLAR__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__FORCE__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__FORCE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__FORCE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__FORCE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__FORCE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__FORCE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__CNT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__CNT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__CNT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_CLKRUN__CNT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__RD_DATA__READ(src) (u_int32_t)(src) & 0x0000ffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__BUSY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__BUSY__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__BUSY__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__BUSY_ACCESS__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__MASK_ACCESS__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__MASK_ACCESS__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_EEPROM_STS__MASK_ACCESS__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_SEL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_SEL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_SEL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__ANT_SEL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__ANT_SEL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__ANT_SEL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__ANT_SEL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_MODE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_MODE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_MODE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OBS_CTRL__OBS_MODE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__FORCE__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__FORCE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__FORCE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__FORCE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__FORCE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__FORCE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__INVERT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__INVERT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__INVERT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__INVERT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__INVERT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__INVERT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_RFSILENT__RTC_RESET_INVERT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_PDPU__INT__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_PDPU__INT__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_PDPU__INT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_PDPU__INT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_DS__INT__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_DS__INT__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_DS__INT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_GPIO_DS__INT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__AT_SPEED_EN__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__AT_SPEED_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__AT_SPEED_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__AT_SPEED_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__AT_SPEED_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__AT_SPEED_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_EN__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__MULTI_MSI__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__MULTI_MSI__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__MULTI_MSI__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__MULTI_MSI__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_MSI__IRQ_PENDING__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXAPSYNC__ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXAPSYNC__ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXAPSYNC__ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXAPSYNC__ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXAPSYNC__ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXAPSYNC__ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define HOST_INTF_OTP__BOND_OPTION__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FPGA_PHY_LAYER_REVID__FPGA_RADIO_FEATURE_INDEX__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FPGA_PHY_LAYER_REVID__FPGA_BASEBAND_FEATURE_INDEX__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FPGA_LINK_LAYER_REVID__FPGA_MAC_FEATURE_INDEX__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FPGA_LINK_LAYER_REVID__FPGA_SOC_FEATURE_INDEX__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLL_CONTROL__DIV__READ(src) (u_int32_t)(src) & 0x000003ffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLL_CONTROL__DIV__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLL_CONTROL__DIV__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLL_CONTROL__DIV__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define RTC_SYNC_DERIVED__FORCE_LPO_PWD__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_BT_COEX__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_BT_COEX__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_BT_COEX__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_BT_COEX__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_BT_COEX__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_BT_COEX__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__WLAN_BT_PRIORITY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__WLAN_BT_PRIORITY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__WLAN_BT_PRIORITY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__WLAN_BT_PRIORITY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__WLAN_BT_PRIORITY__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__WLAN_BT_PRIORITY__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__RFSAT_RESTART_THRESH__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__RFSAT_RESTART_THRESH__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__RFSAT_RESTART_THRESH__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__RFSAT_RESTART_THRESH__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_RFSAT_RESTART__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_RFSAT_RESTART__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_RFSAT_RESTART__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_RFSAT_RESTART__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define BT_COEX__ENABLE_RFSAT_RESTART__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__BYPASS_DAC_FIFO_N__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__ML_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__ML_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__ML_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__ML_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__ML_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__ML_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TXIQCAL_START__DO_TX_IQCAL__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TXIQCAL_START__DO_TX_IQCAL__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TXIQCAL_START__DO_TX_IQCAL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TXIQCAL_START__DO_TX_IQCAL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TXIQCAL_START__DO_TX_IQCAL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TXIQCAL_START__DO_TX_IQCAL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_MEM__OTP_MEM__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_MEM__OTP_MEM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_MEM__OTP_MEM__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_MEM__OTP_MEM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_CONTROL__ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_CONTROL__ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_CONTROL__ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_CONTROL__ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_POWER_GOOD__DELAY__READ(src) (u_int32_t)(src) & 0x00000fffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_POWER_GOOD__DELAY__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_POWER_GOOD__DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_POWER_GOOD__DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_STATUS__POWER_ON__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_STATUS__POWER_ON__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_LDO_STATUS__POWER_ON__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_VDDQ_HOLD_TIME__DELAY__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_VDDQ_HOLD_TIME__DELAY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_VDDQ_HOLD_TIME__DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_VDDQ_HOLD_TIME__DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_PGENB_SETUP_HOLD_TIME__DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_STROBE_PULSE_INTERVAL__DELAY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_STROBE_PULSE_INTERVAL__DELAY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_STROBE_PULSE_INTERVAL__DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_STROBE_PULSE_INTERVAL__DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWD_PLLSDM__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWD_PLLSDM__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWD_PLLSDM__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWD_PLLSDM__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWD_PLLSDM__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWD_PLLSDM__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWDPLL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWDPLL__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWDPLL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWDPLL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWDPLL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PWDPLL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PLLFRAC__READ(src) (((u_int32_t)(src) & 0x0001fffcU) >> 2) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PLLFRAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0001fffcU) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PLLFRAC__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__PLLFRAC__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__REFDIV__READ(src) (((u_int32_t)(src) & 0x001e0000U) >> 17) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__REFDIV__WRITE(src) (((u_int32_t)(src) << 17) & 0x001e0000U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__REFDIV__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__REFDIV__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__DIV__READ(src) (((u_int32_t)(src) & 0x7fe00000U) >> 21) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__DIV__WRITE(src) (((u_int32_t)(src) << 21) & 0x7fe00000U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__DIV__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__DIV__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__LOCAL_PLL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__LOCAL_PLL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__LOCAL_PLL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__LOCAL_PLL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__LOCAL_PLL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define PLLCLKMODA__LOCAL_PLL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_RSEL__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_RSEL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_RSEL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_RSEL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_RSEL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TEST_PAD_EN__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TEST_PAD_EN__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TEST_PAD_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TEST_PAD_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TEST_PAD_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TEST_PAD_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__PWDBG__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__PWDBG__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__PWDBG__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__PWDBG__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00000080U))) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__PWDBG__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__PWDBG__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_OFF__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_OFF__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_OFF__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_OFF__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_OFF__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_OFF__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_BUFEN__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_BUFEN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_BUFEN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_BUFEN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define TOP__TESTIQ_BUFEN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define THERM__XPABIASLVL_MSB__READ(src) (u_int32_t)(src) & 0x00000003U contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define THERM__XPABIASLVL_MSB__WRITE(src) ((u_int32_t)(src) & 0x00000003U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define THERM__XPABIASLVL_MSB__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define THERM__XPABIASLVL_MSB__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define XTAL__XTAL_SELVREG__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define XTAL__XTAL_SELVREG__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define XTAL__XTAL_SELVREG__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define XTAL__XTAL_SELVREG__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define XTAL__XTAL_SELVREG__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/osprey_reg_map_macro.h:#define XTAL__XTAL_SELVREG__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__READ(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__FORCE_SEL_ON__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SELECT_SLV_PCIE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/poseidon_reg_map_macro.h:#define AXI_INTERCONNECT_CTRL__SW_WOW_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CR__SPARE__READ(src) (((u_int32_t)(src) & 0x00000780U) >> 7) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CR__SPARE__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000780U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CR__SPARE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CR__SPARE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_QCU_TXD__SPARE__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_QCU_TXD__SPARE__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_QCU_TXD__SPARE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_QCU_TXD__SPARE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_PAUSE__SPARE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_PAUSE__SPARE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_PAUSE__SPARE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_DCU_PAUSE__SPARE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_SLEEP_STATUS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_SLEEP_STATUS__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_SLEEP_STATUS__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_SLEEP_STATUS__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_LED_CONFIG__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_LED_CONFIG__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_LED_CONFIG__DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_LED_CONFIG__DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_INT__READ(src) (u_int32_t)(src) & 0x0000003fU contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_INT__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_INT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_INT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_FRAC__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_FRAC__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_FRAC__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define PLL_CONTROL__DIV_FRAC__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_BCN_RSSI_AVE__SPARE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_BCN_RSSI_AVE__SPARE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_BCN_RSSI_AVE__SPARE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_BCN_RSSI_AVE__SPARE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__FROM_TO_DS__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__FROM_TO_DS__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__FROM_TO_DS__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__FROM_TO_DS__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__FROM_TO_DS__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_RX_FILTER__FROM_TO_DS__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__PM_CHANGE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__PM_CHANGE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__PM_CHANGE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__PM_CHANGE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__PM_CHANGE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__PM_CHANGE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__RESET__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__RESET__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__RESET__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__RESET__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__RESET__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_FILTER_RSSI_AVE__RESET__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__BK_VALID_DELAY__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__BK_VALID_DELAY__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__BK_VALID_DELAY__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__BK_VALID_DELAY__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RX_OCGAIN__GAIN_ENTRY__READ(src) (u_int32_t)(src) & 0xffffffffU contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_OB__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_OB__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_OB__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_OB__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_DB__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_DB__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_DB__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TX_FORCED_GAIN__FORCED_DB__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__ENA_RADIO_RETENTION__READ(src) (u_int32_t)(src) & 0x00000001U contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__ENA_RADIO_RETENTION__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__ENA_RADIO_RETENTION__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__ENA_RADIO_RETENTION__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__ENA_RADIO_RETENTION__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__ENA_RADIO_RETENTION__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__RESTORE_MASK__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__RESTORE_MASK__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__RESTORE_MASK__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__RESTORE_MASK__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__FORCE_RADIO_RESTORE__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__FORCE_RADIO_RESTORE__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__FORCE_RADIO_RESTORE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__FORCE_RADIO_RESTORE__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__FORCE_RADIO_RESTORE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define RTT_CTRL__FORCE_RADIO_RESTORE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NFRAC__READ(src) (u_int32_t)(src) & 0x0003ffffU contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NFRAC__WRITE(src) ((u_int32_t)(src) & 0x0003ffffU) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NFRAC__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NFRAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x0003ffffU))) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NINT__READ(src) (((u_int32_t)(src) & 0x07fc0000U) >> 18) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NINT__WRITE(src) (((u_int32_t)(src) << 18) & 0x07fc0000U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NINT__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__NINT__VERIFY(src) (!((((u_int32_t)(src) << 18) & ~0x07fc0000U))) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__REFDIV__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__REFDIV__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__REFDIV__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define DPLL__REFDIV__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__SPARE__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__SPARE__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__LOCAL_XPAON__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__LOCAL_XPAON__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__LOCAL_XPAON__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__LOCAL_XPAON__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__LOCAL_XPAON__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define TOP__LOCAL_XPAON__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__SPARE__READ(src) (u_int32_t)(src) & 0x0000003fU contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__SPARE__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000003fU))) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__RST_WARM_L_THERM__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__RST_WARM_L_THERM__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__RST_WARM_L_THERM__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__RST_WARM_L_THERM__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__RST_WARM_L_THERM__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define THERM__RST_WARM_L_THERM__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__SWREGCLK_EDGE_SEL__READ(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__SWREGCLK_EDGE_SEL__WRITE(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__SWREGCLK_EDGE_SEL__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__SWREGCLK_EDGE_SEL__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__SWREGCLK_EDGE_SEL__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__SWREGCLK_EDGE_SEL__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__PWD_SWREGCLK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__PWD_SWREGCLK__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__PWD_SWREGCLK__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__PWD_SWREGCLK__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__PWD_SWREGCLK__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__PWD_SWREGCLK__CLR(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__XTAL_ATBVREG__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__XTAL_ATBVREG__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__XTAL_ATBVREG__MODIFY(dst, src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__XTAL_ATBVREG__VERIFY(src) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__XTAL_ATBVREG__SET(dst) \ contrib/dev/ath/ath_hal/ar9300/scorpion_reg_map_macro.h:#define XTAL__XTAL_ATBVREG__CLR(dst) \ contrib/edk2/Include/Base.h:#define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE))) contrib/edk2/Include/Base.h:#define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment)))) contrib/edk2/Include/Library/BaseLib.h:#define INITIALIZE_LIST_HEAD_VARIABLE(ListHead) {&(ListHead), &(ListHead)} contrib/edk2/Include/Library/PcdLib.h:#define FeaturePcdGet(TokenName) _PCD_GET_MODE_BOOL_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define FixedPcdGetBool(TokenName) _PCD_VALUE_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define FixedPcdGetPtr(TokenName) ((VOID *)_PCD_VALUE_##TokenName) contrib/edk2/Include/Library/PcdLib.h:#define PatchPcdGetBool(TokenName) _gPcd_BinaryPatch_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define PatchPcdGetPtr(TokenName) ((VOID *)_gPcd_BinaryPatch_##TokenName) contrib/edk2/Include/Library/PcdLib.h:#define PatchPcdSetBool(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value)) contrib/edk2/Include/Library/PcdLib.h:#define PatchPcdSetPtr(TokenName, Size, Buffer) \ contrib/edk2/Include/Library/PcdLib.h:#define PcdGetPtr(TokenName) _PCD_GET_MODE_PTR_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define FixedPcdGetSize(TokenName) _PCD_SIZE_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define PatchPcdGetSize(TokenName) _gPcd_BinaryPatch_Size_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define PcdGetSize(TokenName) _PCD_GET_MODE_SIZE_##TokenName contrib/edk2/Include/Library/PcdLib.h:#define PcdGetExSize(Guid, TokenName) LibPcdGetExSize ((Guid), PcdTokenEx(Guid,TokenName)) contrib/edk2/Include/Library/PcdLib.h:#define PcdSetPtr(TokenName, SizeOfBuffer, Buffer) \ contrib/edk2/Include/Library/PcdLib.h:#define PcdSetBool(TokenName, Value) _PCD_SET_MODE_BOOL_##TokenName ((Value)) contrib/edk2/Include/Library/PcdLib.h:#define PcdSetPtrS(TokenName, SizeOfBuffer, Buffer) \ contrib/edk2/Include/Library/PcdLib.h:#define PcdSetBoolS(TokenName, Value) _PCD_SET_MODE_BOOL_S_##TokenName ((Value)) contrib/edk2/Include/Library/PcdLib.h:#define PcdGetExPtr(Guid, TokenName) LibPcdGetExPtr ((Guid), PcdTokenEx(Guid,TokenName)) contrib/edk2/Include/Library/PcdLib.h:#define PcdGetExBool(Guid, TokenName) LibPcdGetExBool ((Guid), PcdTokenEx(Guid,TokenName)) contrib/edk2/Include/Library/PcdLib.h:#define PcdSetExPtr(Guid, TokenName, SizeOfBuffer, Buffer) \ contrib/edk2/Include/Library/PcdLib.h:#define PcdSetExBool(Guid, TokenName, Value) \ contrib/edk2/Include/Library/PcdLib.h:#define PcdSetExPtrS(Guid, TokenName, SizeOfBuffer, Buffer) \ contrib/edk2/Include/Library/PcdLib.h:#define PcdSetExBoolS(Guid, TokenName, Value) \ contrib/edk2/Include/Protocol/DevicePath.h:#define ACPI_DISPLAY_ADR(_DeviceIdScheme, _HeadId, _NonVgaOutput, _BiosCanDetect, _VendorInfo, _Type, _Port, _Index) \ contrib/edk2/Include/Uefi/UefiBaseType.h:#define EFI_PAGES_TO_SIZE(Pages) ((Pages) << EFI_PAGE_SHIFT) contrib/ena-com/ena_plat.h:#define ENA_ABORT() BUG() contrib/ipfilter/netinet/ip_compat.h:#define NETBSD_GT_REV(x) (defined(__NetBSD_Version__) && \ contrib/ipfilter/netinet/ip_compat.h:#define FREEBSD_GT_REV(x) (defined(__FreeBSD_version) && \ contrib/ipfilter/netinet/ip_compat.h:#define BSDOS_GT_REV(x) (defined(_BSDI_VERSION) && \ contrib/ipfilter/netinet/ip_compat.h:#define BSDOS_LT_REV(x) (defined(_BSDI_VERSION) && \ contrib/ipfilter/netinet/ip_compat.h:#define OPENBSD_GT_REV(x) (defined(OpenBSD) && (OpenBSD > (x))) contrib/ipfilter/netinet/ip_compat.h:#define BSD_LT_YEAR(x) (defined(BSD) && (BSD < (x))) contrib/ipfilter/netinet/ip_compat.h:#define ISALNUM(x) isalnum((u_char)(x)) contrib/ipfilter/netinet/ip_compat.h:#define ISUPPER(x) isupper((u_char)(x)) contrib/ipfilter/netinet/ip_compat.h:#define ISXDIGIT(x) isxdigit((u_char)(x)) contrib/ipfilter/netinet/ip_compat.h:#define ISLOWER(x) islower((u_char)(x)) contrib/ipfilter/netinet/ip_compat.h:#define TOLOWER(x) tolower((u_char)(x)) contrib/ipfilter/netinet/ip_compat.h:#define IPMINLEN(i, h) ((i)->ip_len >= (IP_HL(i) * 4 + sizeof(struct h))) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_QR(x) ((ntohs(x) & 0x8000) >> 15) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_OPCODE(x) ((ntohs(x) & 0x7800) >> 11) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_AA(x) ((ntohs(x) & 0x0400) >> 10) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_TC(x) ((ntohs(x) & 0x0200) >> 9) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_RD(x) ((ntohs(x) & 0x0100) >> 8) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_RA(x) ((ntohs(x) & 0x0080) >> 7) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_Z(x) ((ntohs(x) & 0x0070) >> 4) contrib/ipfilter/netinet/ip_dns_pxy.c:#define DNS_RCODE(x) ((ntohs(x) & 0x000f) >> 0) contrib/ipfilter/netinet/ip_fil.h:#define FR_ISNOMATCH(x) ((x) & FR_NOMATCH) contrib/ipfilter/netinet/ip_fil.h:#define FG_NAME(g) (*(g)->fg_name == '\0' ? "" : (g)->fg_name) contrib/ipfilter/netinet/ip_fil.h:#define IPFHASH(x,y) typedef struct { \ contrib/ipfilter/netinet/ip_nat.c:#define NBUMP(x) softn->(x)++ contrib/ipfilter/netinet/ip_nat.c:#define NBUMPSIDEDF(y,x)do { softn->ipf_nat_stats.ns_side[y].x++; \ contrib/ipfilter/netinet/ip_state.h:#define IPPAIR(s1,d1,s2,d2) PAIRS((s1).s_addr, (d1).s_addr, \ contrib/ipfilter/netinet/ipf_rb.h:#define RBI_ISEMPTY(_h) ((_h)->count == 0) contrib/libfdt/libfdt.h:#define fdt_property_string(fdt, name, str) \ contrib/ncsw/Peripherals/BM/bman_low.c:#define bm_cl(n) (void *)((n) << 6) contrib/ncsw/Peripherals/BM/fsl_bman.h:#define bm_isr_enable_read(bm) __bm_isr_read(bm, bm_isr_enable) contrib/ncsw/Peripherals/BM/fsl_bman.h:#define bm_isr_disable_read(bm) __bm_isr_read(bm, bm_isr_disable) contrib/ncsw/Peripherals/BM/fsl_bman.h:#define BM_MCR_QUERY_AVAILABILITY(r,p) bman_depletion_get(&r->query.as.state,p) contrib/ncsw/Peripherals/BM/fsl_bman.h:#define BM_MCR_QUERY_DEPLETION(r,p) bman_depletion_get(&r->query.ds.state,p) contrib/ncsw/Peripherals/FM/Pcd/fm_pcd.h:#define PLCR_PORT_WINDOW_SIZE(hardwarePortId) contrib/ncsw/Peripherals/FM/inc/fm_common.h:#define CC_NEXT_NODE_F_OBJECT(ptr) LIST_OBJECT(ptr, t_CcNodeInfo, node) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QM_VDQCR_NUMFRAMES_GET(n) (((n) >> 24) & 0x3f) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QM_PDQCR_CHANNELS_POOL(n) (0x00008000 >> (n)) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QM_PDQCR_SPECIFICWQ_POOL(n) ((n) << 4) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QM_PDQCR_SPECIFICWQ_WQ(n) (n) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */ contrib/ncsw/Peripherals/QM/fsl_qman.h:#define qm_isr_disable_read(qm) __qm_isr_read(qm, qm_isr_disable) contrib/ncsw/Peripherals/QM/fsl_qman.h:#define QMAN_ENQUEUE_FLAG_DCA_PTR(p) /* If DCA, p is DQRR entry */ \ contrib/ncsw/Peripherals/QM/qm.h:#define PORTALS_OFFSET_CE(portal) (0x4000 * portal) contrib/ncsw/Peripherals/QM/qm.h:#define PORTALS_OFFSET_CI(portal) (0x1000 * portal) contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_FD_GET_DD(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_DD_MASK) >> (31-1)) /**< Macro to get FD DD field */ contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_FD_GET_PID(fd) (((((t_DpaaFD *)fd)->id & DPAA_FD_PID_MASK) >> (31-7)) | \ contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_FD_GET_BPID(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_BPID_MASK) >> (31-15)) /**< Macro to get FD BPID field */ contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_SGTE_GET_EXTENSION(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_E_MASK) >> (31-0)) /**< Macro to get SGTE EXTENSION field */ contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_SGTE_GET_FINAL(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_F_MASK) >> (31-1)) /**< Macro to get SGTE FINAL field */ contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_SGTE_GET_LENGTH(sgte) (((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_LENGTH_MASK) /**< Macro to get SGTE LENGTH field */ contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_SGTE_GET_BPID(sgte) ((((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_BPID_MASK) >> (31-15)) /**< Macro to get SGTE BPID field */ contrib/ncsw/inc/Peripherals/dpaa_ext.h:#define DPAA_SGTE_GET_OFFSET(sgte) (((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_OFFSET_MASK) /**< Macro to get SGTE OFFSET field */ contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_GET_OVERRIDE(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_OVERRIDE_MASK) >> (31-0)) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_GET_ICMD(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_ICMD_MASK) >> (31-1)) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_GET_MACCMD(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_MASK) >> (31-15)) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_GET_MACCMD_VALID(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_VALID_MASK) >> (31-8)) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_GET_MACCMD_SECURED(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_SECURED_MASK) >> (31-11)) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_GET_MACCMD_SECURE_CHANNEL(contextA) ((((t_FmContextA *)contextA)->command & FM_CONTEXTA_MACCMD_SC_MASK) >> (31-15)) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_SET_OVERRIDE(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_OVERRIDE_MASK) | (((uint32_t)(val) << (31-0)) & FM_CONTEXTA_OVERRIDE_MASK) )) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_SET_ICMD(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_ICMD_MASK) | (((val) << (31-1)) & FM_CONTEXTA_ICMD_MASK) )) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_SET_MACCMD(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_MASK) | (((val) << (31-15)) & FM_CONTEXTA_MACCMD_MASK) )) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_SET_MACCMD_VALID(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_VALID_MASK) | (((val) << (31-8)) & FM_CONTEXTA_MACCMD_VALID_MASK) )) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_SET_MACCMD_SECURED(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_SECURED_MASK) | (((val) << (31-11)) & FM_CONTEXTA_MACCMD_SECURED_MASK) )) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTA_SET_MACCMD_SECURE_CHANNEL(contextA,val) (((t_FmContextA *)contextA)->command = (uint32_t)((((t_FmContextA *)contextA)->command & ~FM_CONTEXTA_MACCMD_SC_MASK) | (((val) << (31-15)) & FM_CONTEXTA_MACCMD_SC_MASK) )) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTB_GET_FQID(contextB) (*((t_FmContextB *)contextB) & FM_CONTEXTB_FQID_MASK) contrib/ncsw/inc/Peripherals/fm_ext.h:#define FM_CONTEXTB_SET_FQID(contextB,val) (*((t_FmContextB *)contextB) = ((*((t_FmContextB *)contextB) & ~FM_CONTEXTB_FQID_MASK) | ((val) & FM_CONTEXTB_FQID_MASK))) contrib/ncsw/inc/ctype_ext.h:#define toascii(c) (((unsigned char)(c))&0x7f) contrib/ncsw/inc/enet_ext.h:#define IS_ENET_MODE_VALID(mode) \ contrib/ncsw/inc/etc/mem_ext.h:#define MEM_GetBase(h_Mem) ((t_MemorySegment *)(h_Mem))->p_Bases[0] contrib/ncsw/inc/etc/mem_ext.h:#define MEM_GetSize(h_Mem) ((t_MemorySegment *)(h_Mem))->dataSize contrib/ncsw/inc/etc/mem_ext.h:#define MEM_GetPrefixSize(h_Mem) ((t_MemorySegment *)(h_Mem))->prefixSize contrib/ncsw/inc/etc/mem_ext.h:#define MEM_GetPostfixSize(h_Mem) ((t_MemorySegment *)(h_Mem))->postfixSize contrib/ncsw/inc/etc/mem_ext.h:#define MEM_GetAlignment(h_Mem) ((t_MemorySegment *)(h_Mem))->alignment contrib/ncsw/inc/etc/mem_ext.h:#define MEM_GetNumOfBlocks(h_Mem) ((t_MemorySegment *)(h_Mem))->num contrib/ncsw/inc/integrations/dpaa_integration_ext.h:#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE contrib/ncsw/inc/math_ext.h:#define ULOW(x) ( sizeof(x)==8 ? *(1+(uint32_t*)&x) : (*(uint32_t*)&x)) contrib/ncsw/inc/math_ext.h:#define UHIGH(x) (*(uint32_t*)&x) contrib/ncsw/inc/ncsw_ext.h:#define CYCLES_TO_USEC(cycles,clk) ((cycles) / (clk)) contrib/ncsw/inc/ncsw_ext.h:#define NSEC_TO_CLK(nsec,clk) DIV_CEIL(((nsec) * (clk)), 1000) contrib/ncsw/inc/ncsw_ext.h:#define CYCLES_TO_NSEC(cycles,clk) (((cycles) * 1000) / (clk)) contrib/ncsw/inc/ncsw_ext.h:#define PSEC_TO_CLK(psec,clk) DIV_CEIL(((psec) * (clk)), 1000000) contrib/ncsw/inc/ncsw_ext.h:#define CYCLES_TO_PSEC(cycles,clk) (((cycles) * 1000000) / (clk)) contrib/ncsw/inc/ncsw_ext.h:#define BUF_POSITION(first, last) state[(!!(last))<<1 | !!(first)] contrib/ngatm/netnatm/msg/uni_hdr.h:#define IE_ADDPRESENT(IE) \ contrib/ngatm/netnatm/sig/unimkmsg.h:#define COPY_FROM_RELEASE_COMPL(U,DEST) \ contrib/ngatm/netnatm/unimsg.h:#define uni_msg_size(M) ((size_t)((M)->b_lim - (M)->b_buf)); contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SYNCI(address, offset) asm volatile ("synci " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_DONT_WRITE_BACK(address, offset) CVMX_PREFETCH_PREFX(29, address, offset) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_BADDU(result, input1, input2) asm ("baddu %[rd],%[rs],%[rt]" : [rd] "=d" (result) : [rs] "d" (input1) , [rt] "d" (input2)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_ROTRV(result, input1, input2) asm ("rotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_DROTR(result, input1, shiftconst) asm ("drotr %[rd],%[rs]," CVMX_TMP_STR(shiftconst) : [rd] "=d" (result) : [rs] "d" (input1)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_DROTRV(result, input1, input2) asm ("drotrv %[rd],%[rt],%[rs]" : [rd] "=d" (result) : [rt] "d" (input1) , [rs] "d" (input2)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SEB(result, input1) asm ("seb %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SEH(result, input1) asm ("seh %[rd],%[rt]" : [rd] "=d" (result) : [rt] "d" (input1)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_EXTSP(result,input,pos,len) CVMX_EXTS(result,input,pos,(len)-1) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_CINSP(result,input,pos,len) CVMX_CINS(result,input,pos,(len)-1) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_CLO(result, input) asm ("clo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_DCLO(result, input) asm ("dclo %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_DI(result) asm volatile ("di %[rt]" : [rt] "=d" (result)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_EI(result) asm volatile ("ei %[rt]" : [rt] "=d" (result)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_VMULU(dest,mpcand,accum) asm volatile ("vmulu %[rd],%[rs],%[rt]" : [rd] "=d" (dest) : [rs] "d" (mpcand), [rt] "d" (accum)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_ASM_LABEL(label) label \ contrib/octeon-sdk/cvmx-asm.h:#define CVMX_LL(dest, address, offset) asm volatile ("ll %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_LLD(dest, address, offset) asm volatile ("lld %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (dest) : [rbase] "d" (address) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SC(srcdest, address, offset) asm volatile ("sc %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SCD(srcdest, address, offset) asm volatile ("scd %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_LWR(srcdest, address, offset) asm volatile ("lwr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_LWL(srcdest, address, offset) asm volatile ("lwl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_LDR(srcdest, address, offset) asm volatile ("ldr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_LDL(srcdest, address, offset) asm volatile ("ldl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : [rt] "=d" (srcdest) : [rbase] "d" (address), "[rt]" (srcdest) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SWR(src, address, offset) asm volatile ("swr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SWL(src, address, offset) asm volatile ("swl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SDR(src, address, offset) asm volatile ("sdr %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_SDL(src, address, offset) asm volatile ("sdl %[rt], " CVMX_TMP_STR(offset) "(%[rbase])" : : [rbase] "d" (address), [rt] "d" (src) ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_POLYNOMIAL(val) asm volatile ("dmtc2 %[rt],0x4200" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_IV(val) asm volatile ("dmtc2 %[rt],0x0201" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_LEN(val) asm volatile ("dmtc2 %[rt],0x1202" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_BYTE(val) asm volatile ("dmtc2 %[rt],0x0204" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_HALF(val) asm volatile ("dmtc2 %[rt],0x0205" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_WORD(val) asm volatile ("dmtc2 %[rt],0x0206" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_DWORD(val) asm volatile ("dmtc2 %[rt],0x1207" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_VAR(val) asm volatile ("dmtc2 %[rt],0x1208" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_POLYNOMIAL_REFLECT(val) asm volatile ("dmtc2 %[rt],0x4210" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_IV_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0211" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_BYTE_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0214" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_HALF_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0215" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_WORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x0216" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_DWORD_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1217" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CRC_VAR_REFLECT(val) asm volatile ("dmtc2 %[rt],0x1218" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_CRC_POLYNOMIAL(val) asm volatile ("dmfc2 %[rt],0x0200" : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_CRC_IV(val) asm volatile ("dmfc2 %[rt],0x0201" : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_CRC_IV_REFLECT(val) asm volatile ("dmfc2 %[rt],0x0203" : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_CRC_LEN(val) asm volatile ("dmfc2 %[rt],0x0202" : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_HSH_DATW(val,pos) asm volatile ("dmtc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_HSH_DATWZ(pos) asm volatile ("dmtc2 $0,0x0240+" CVMX_TMP_STR(pos) : : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_HSH_IVW(val,pos) asm volatile ("dmtc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_HSH_DAT(val,pos) asm volatile ("dmfc2 %[rt],0x0040+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_HSH_DATW(val,pos) asm volatile ("dmfc2 %[rt],0x0240+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_HSH_IVW(val,pos) asm volatile ("dmfc2 %[rt],0x0250+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_KAS_KEY(val,pos) CVMX_MT_3DES_KEY(val,pos) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_KAS_ENC_CBC(val) asm volatile ("dmtc2 %[rt],0x4089" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_KAS_ENC(val) asm volatile ("dmtc2 %[rt],0x408b" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_KAS_RESULT(val) CVMX_MT_3DES_RESULT(val) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_KAS_KEY(val,pos) CVMX_MF_3DES_KEY(val,pos) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_KAS_RESULT(val) CVMX_MF_3DES_RESULT(val) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_AES_RESULT(val,pos) asm volatile ("dmtc2 %[rt],0x0100+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_AES_IV(val,pos) asm volatile ("dmfc2 %[rt],0x0102+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_AES_KEY(val,pos) asm volatile ("dmfc2 %[rt],0x0104+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_AES_KEYLENGTH(val) asm volatile ("dmfc2 %[rt],0x0110" : [rt] "=d" (val) : ) // read the keylen contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_GFM_MUL(val,pos) asm volatile ("dmfc2 %[rt],0x0258+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_GFM_POLY(val) asm volatile ("dmfc2 %[rt],0x025e" : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_GFM_RESINP(val,pos) asm volatile ("dmfc2 %[rt],0x025a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_GFM_RESINP_REFLECT(val,pos) asm volatile ("dmfc2 %[rt],0x005a+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_GFM_MUL(val,pos) asm volatile ("dmtc2 %[rt],0x0258+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_GFM_POLY(val) asm volatile ("dmtc2 %[rt],0x025e" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_GFM_RESINP(val,pos) asm volatile ("dmtc2 %[rt],0x025a+" CVMX_TMP_STR(pos) : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_GFM_MUL_REFLECT(val,pos) asm volatile ("dmtc2 %[rt],0x0058+" CVMX_TMP_STR(pos) : [rt] "=d" (val) : ) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CYCLE(src) asm volatile ("dmtc0 %[rt],$9,6" :: [rt] "d" (src)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_DCACHE_ERR(val) CVMX_MF_COP0(val, COP0_CACHEERRD) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_CVM_CTL(val) CVMX_MF_COP0(val, COP0_CVMCTL) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_CVM_CTL(val) CVMX_MT_COP0(val, COP0_CVMCTL) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_PAGEGRAIN(val) asm volatile ("mtc0 %[rt],$5,1" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_TLB_CONTEXT(val) asm volatile ("dmtc0 %[rt],$4,0" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MT_TLB_RANDOM(val) asm volatile ("mtc0 %[rt],$1,0" : : [rt] "d" (val)) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_PAGEGRAIN(val) asm volatile ("mfc0 %[rt],$5,1" : [rt] "=d" (val):) contrib/octeon-sdk/cvmx-asm.h:#define CVMX_MF_TLB_RANDOM(val) asm volatile ("mfc0 %[rt],$1,0" : [rt] "=d" (val):) contrib/octeon-sdk/cvmx-debug-handler.S:#define SAVE_REGISTER(reg) \ contrib/octeon-sdk/cvmx-debug-handler.S:#define RESTORE_REGISTER(reg) \ contrib/octeon-sdk/cvmx-debug-handler.S:#define SAVE_ADDRESS(addr) \ contrib/octeon-sdk/cvmx-debug-handler.S:#define RESTORE_ADDRESS(addr) \ contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_INSTRUCTION_BREAKPOINT_ADDRESS(num) (0xFFFFFFFFFF301100 + 0x100 * (num)) contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_INSTRUCTION_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF301108 + 0x100 * (num)) contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_INSTRUCTION_BREAKPOINT_ASID(num) (0xFFFFFFFFFF301110 + 0x100 * (num)) contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_INSTRUCTION_BREAKPOINT_CONTROL(num) (0xFFFFFFFFFF301118 + 0x100 * (num)) contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_DATA_BREAKPOINT_ADDRESS(num) (0xFFFFFFFFFF302100 + 0x100 * (num)) contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_DATA_BREAKPOINT_ADDRESS_MASK(num) (0xFFFFFFFFFF302108 + 0x100 * (num)) contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_DATA_BREAKPOINT_ASID(num) (0xFFFFFFFFFF302110 + 0x100 * (num)) contrib/octeon-sdk/cvmx-debug-handler.S:#define HW_DATA_BREAKPOINT_CONTROL(num) (0xFFFFFFFFFF302118 + 0x100 * (num)) contrib/octeon-sdk/cvmx-interrupt.h:#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__) contrib/octeon-sdk/cvmx-malloc/malloc.c:#define set_inuse(p)\ contrib/octeon-sdk/cvmx-malloc/malloc.c:#define clear_inuse(p)\ contrib/octeon-sdk/cvmx-malloc/malloc.c:#define unmark_bin(m,i) ((m)->binmap[idx2block(i)] &= ~(idx2bit(i))) contrib/octeon-sdk/cvmx-malloc/malloc.c:#define set_contiguous(M) ((M)->max_fast &= ~NONCONTIGUOUS_BIT) contrib/octeon-sdk/cvmx-malloc/thread-m.h:#define tsd_key_create(key, destr) do {} while(0) contrib/octeon-sdk/cvmx-malloc/thread-m.h:#define thread_atfork(prepare, parent, child) do {} while(0) contrib/vchiq/interface/compat/vchi_bsd.h:#define DEFINE_RWLOCK(name) \ contrib/vchiq/interface/vchi/message_drivers/message.h:#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) contrib/vchiq/interface/vchi/message_drivers/message.h:#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) contrib/vchiq/interface/vchi/vchi.h:#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1)) contrib/vchiq/interface/vchi/vchi.h:#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1)) contrib/vchiq/interface/vchi/vchi.h:#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1)))) contrib/vchiq/interface/vchi/vchi.h:#define VCHI_VERSION(v_) { v_, v_ } contrib/vchiq/interface/vchi/vchi.h:#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF contrib/vchiq/interface/vchiq_arm/vchiq_core.h:#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE) contrib/vchiq/interface/vchiq_arm/vchiq_core.h:#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID) contrib/vchiq/interface/vchiq_arm/vchiq_core.h:#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b)) contrib/vchiq/interface/vchiq_arm/vchiq_if.h:#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service) contrib/x86emu/x86emu_regs.h:#define CLEARALL_FLAG(m) (emu->x86.R_FLG = 0) crypto/sha1.c:#define PUTBYTE(x) { \ crypto/skein/skein.h:#define Skein_Set_Type(ctxPtr,BLK_TYPE) \ crypto/skein/skein.h:#define Skein_Clear_First_Flag(hdr) { (hdr).T[1] &= ~SKEIN_T1_FLAG_FIRST; } crypto/skein/skein.h:#define Skein_Set_Bit_Pad_Flag(hdr) { (hdr).T[1] |= SKEIN_T1_FLAG_BIT_PAD; } crypto/skein/skein.h:#define Skein_Set_Tree_Level(hdr,height) { (hdr).T[1] |= SKEIN_T1_TREE_LEVEL(height);} ddb/db_sym.h:#define db_find_sym_and_offset(val,namep,offp) \ ddb/ddb.h:#define DB_ALIAS(alias_name, func_name) \ ddb/ddb.h:#define DB_SHOW_ALL_ALIAS(alias_name, func_name) \ dev/aac/aac_tables.h:#define AAC_COMMAND_STATUS(x) aac_describe_code(aac_command_status_table, x) dev/acpica/acpi_cpu.c:#define CPU_SET_REG(reg, width, val) \ dev/acpica/acpi_smbus.h:#define SMBATT_BS_GET_ERROR(x) ((x) & 0xf) dev/acpica/acpi_smbus.h:#define SMBATT_SI_GET_REVISION(x) (((x) >> 0) & 0xf) dev/acpica/acpi_smbus.h:#define SMBATT_SI_GET_VERSION(x) (((x) >> 4) & 0xf) dev/acpica/acpi_smbus.h:#define SMBATT_SI_GET_VSCALE(x) (((x) >> 8) & 0xf) dev/acpica/acpi_smbus.h:#define SMBATT_SI_GET_IPSCALE(x) (((x) >> 12) & 0xf) dev/acpica/acpi_smbus.h:#define SMBATT_MD_GET_DAY(x) (((x) >> 0) & 0x1f) dev/acpica/acpi_smbus.h:#define SMBATT_MD_GET_MONTH(x) (((x) >> 5) & 0xf) dev/acpica/acpi_smbus.h:#define SMBATT_MD_GET_YEAR(x) ((((x) >> 9) & 0x7f) + 1980) dev/acpica/acpi_throttle.c:#define CPU_SPEED_PRINTABLE(x) (CPU_SPEED_PERCENT(x) / 10), \ dev/advansys/advlib.h:#define ADV_TIX_TO_TARGET_MASK(tix) (0x01 << ((tix) & ADV_MAX_TID)) dev/advansys/advlib.h:#define ADV_TID_TO_TIX(tid) ((tid) & ADV_MAX_TID) dev/advansys/advlib.h:#define EEPROM_SET_DMA_SPEED(ep, speed) \ dev/advansys/advlib.h:#define ADV_INSB(adv, offset, valp, count) \ dev/advansys/adwlib.h:#define adw_inl(adw, port) \ dev/advansys/adwlib.h:#define adw_outl(adw, port, value) \ dev/age/if_agereg.h:#define AGE_RX_CSUM(x) \ dev/aic/aic6360reg.h:#define PORTB_EXTTRAN(b)((b) & 1) dev/aic/aic6360reg.h:#define PORTB_SYNC(b) ((b) & 8) dev/aic/aic6360reg.h:#define PORTB_BOOT(b) ((b) & 0x40) dev/aic7xxx/aic79xx.h:#define AHD_COPY_SCB_COL_IDX(dst, src) \ dev/aic7xxx/aic79xx_inline.h:#define AHD_COPY_COL_IDX(dst, src) \ dev/aic7xxx/aic_osm_lib.h:#define aic_dmamap_destroy(aic, tag, map) \ dev/alc/if_alcreg.h:#define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) dev/alc/if_alcreg.h:#define RRD_CSUM(x) \ dev/alc/if_alcreg.h:#define RRD_HEAD_LEN(x) \ dev/alc/if_alcreg.h:#define RRD_CPU(x) \ dev/ale/if_alereg.h:#define ALE_RX_CSUM(x) \ dev/ale/if_alereg.h:#define ALE_RX_CPU(x) \ dev/alpm/alpm.c:#define ALPM_LOCK_ASSERT(alpm) mtx_assert(&(alpm)->lock, MA_OWNED) dev/altera/pio/pio.h:#define PIO_OUT(n) (1 << n) dev/altera/pio/pio.h:#define PIO_UNMASK(n) (1 << n) dev/amr/amrreg.h:#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) dev/amr/amrreg.h:#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) dev/amr/amrreg.h:#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) dev/amr/amrreg.h:#define AMR_SDISABLE_INTR(sc) \ dev/amr/amrreg.h:#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) dev/amr/amrreg.h:#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) dev/amr/amrreg.h:#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) dev/arcmsr/arcmsr.h:#define get_max(x,y) ((x) < (y) ? (y) : (x)) dev/ata/ata-all.h:#define ATA_IDX_INSW(ch, idx, addr, count) \ dev/ata/ata-all.h:#define ATA_IDX_INSL(ch, idx, addr, count) \ dev/ata/ata-all.h:#define ATA_IDX_OUTSW(ch, idx, addr, count) \ dev/ata/ata-all.h:#define ATA_IDX_OUTSL(ch, idx, addr, count) \ dev/ata/chipsets/ata-marvell.c:#define ATA_MV_HOST_BASE(ch) \ dev/ata/chipsets/ata-marvell.c:#define ATA_MV_EDMA_BASE(ch) \ dev/ath/ath_hal/ah_btcoex.h:#define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \ dev/ath/ath_hal/ah_eeprom.h:#define is_reg_dmn_etsi(reg_dmn) \ dev/ath/ath_hal/ah_eeprom.h:#define is_reg_dmn_mkk(reg_dmn) \ dev/ath/ath_hal/ah_internal.h:#define ath_hal_gpioSet(_ah, _gpio, _val) \ dev/ath/ath_hal/ah_internal.h:#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) dev/ath/ath_hal/ar5210/ar5210reg.h:#define AR_GPIOCR_OUT(n) (3<<((n)*2)) /* always output */ dev/ath/ath_hal/ar5416/ar5416_xmit.c:#define isValidKeyType(_t) ((1 << (_t)) & VALID_KEY_TYPES) dev/ath/ath_hal/ar5416/ar5416desc.h:#define RXSTATUS_DUPLICATE(ah, ads) \ dev/ath/if_ath_tx_ht.c:#define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us dev/ath/if_ath_tx_ht.c:#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us dev/ath/if_athvar.h:#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) dev/ath/if_athvar.h:#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ dev/ath/if_athvar.h:#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) dev/ath/if_athvar.h:#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ dev/ath/if_athvar.h:#define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ dev/ath/if_athvar.h:#define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ dev/ath/if_athvar.h:#define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ dev/ath/if_athvar.h:#define ath_hal_intrget(_ah) \ dev/ath/if_athvar.h:#define ath_hal_getrxfilter(_ah) \ dev/ath/if_athvar.h:#define ath_hal_waitforbeacon(_ah, _bf) \ dev/ath/if_athvar.h:#define ath_hal_resettsf(_ah) \ dev/ath/if_athvar.h:#define ath_hal_setchannel(_ah, _chan) \ dev/ath/if_athvar.h:#define ath_hal_calibrate(_ah, _chan, _iqcal) \ dev/ath/if_athvar.h:#define ath_hal_beaconreset(_ah) \ dev/ath/if_athvar.h:#define ath_hal_setregdomain(_ah, _rd) \ dev/ath/if_athvar.h:#define ath_hal_gettkipmic(_ah) \ dev/ath/if_athvar.h:#define ath_hal_gettkipsplit(_ah) \ dev/ath/if_athvar.h:#define ath_hal_getnumtxqueues(_ah, _pv) \ dev/ath/if_athvar.h:#define ath_hal_gettxpowlimit(_ah, _ppow) \ dev/ath/if_athvar.h:#define ath_hal_getmaxtxpow(_ah, _ppow) \ dev/ath/if_athvar.h:#define ath_hal_gettsfadjust(_ah) \ dev/ath/if_athvar.h:#define ath_hal_getenforcetxop(_ah) \ dev/ath/if_athvar.h:#define ath_hal_hasldpc(_ah) \ dev/ath/if_athvar.h:#define ath_hal_hasldpcwar(_ah) \ dev/ath/if_athvar.h:#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ dev/ath/if_athvar.h:#define ath_hal_gettxdesclink(_ah, _ds, _link) \ dev/ath/if_athvar.h:#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ dev/ath/if_athvar.h:#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ dev/ath/if_athvar.h:#define ath_hal_gpioget(_ah, _gpio) \ dev/ath/if_athvar.h:#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ dev/ath/if_athvar.h:#define ath_hal_disablepcie(_ah) \ dev/ath/if_athvar.h:#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ dev/ath/if_athvar.h:#define ath_hal_is_fast_clock_enabled(_ah) \ dev/ath/if_athvar.h:#define ath_hal_radar_wait(_ah, _chan) \ dev/ath/if_athvar.h:#define ath_hal_get_chan_ext_busy(_ah) \ dev/ath/if_athvar.h:#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ dev/ath/if_athvar.h:#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ dev/ath/if_athvar.h:#define ath_hal_btcoex_disable(_ah) \ dev/axgbe/xgbe-common.h:#define XSIR_SET_BITS(_var, _prefix, _field, _val) \ dev/axgbe/xgbe-common.h:#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ dev/axgbe/xgbe-common.h:#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ dev/axgbe/xgbe-common.h:#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ dev/bce/if_bcereg.h:#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) dev/bce/if_bcereg.h:#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) dev/bce/if_bcereg.h:#define BCE_ASICREV(x) ((x) >> 28) dev/bce/if_bcereg.h:#define BCE_CHIPREV(x) ((x) >> 24) dev/bce/if_bcereg.h:#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) \ dev/bce/if_bcereg.h:#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo dev/bce/if_bcereg.h:#define BCM_PAGES(x) ((((x) + BCM_PAGE_SIZE - 1) & \ dev/bce/if_bcereg.h:#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) dev/bce/if_bcereg.h:#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) dev/bce/if_bcereg.h:#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) dev/beri/virtio/network/if_vtbe.c:#define VTBE_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); dev/bge/if_bgereg.h:#define BGE_MEMWIN_READ(sc, x, val) \ dev/bge/if_bgereg.h:#define APE_SETBIT(sc, reg, x) \ dev/bge/if_bgereg.h:#define APE_CLRBIT(sc, reg, x) \ dev/bhnd/bcma/bcma_dmp.h:#define BCMA_DMP_GET_BITS(_value, _field) \ dev/bhnd/bcma/bcma_dmp.h:#define BHND_DMP_SET_BITS(_value, _field) \ dev/bhnd/bcma/bcma_dmp.h:#define BCMA_DMP_OOBSELIN(_bank, _sel) \ dev/bhnd/bcma/bcma_dmp.h:#define BCMA_DMP_OOBSYNC(_bank) (BCMA_DMP_OOBSYNCA + (_bank * 8)) dev/bhnd/bcma/bcma_dmp.h:#define BCMA_DMP_OOBSELOUT_EN(_bank) (BCMA_DMP_OOBSELOUTAEN + (_bank * 8)) dev/bhnd/bcma/bcma_dmp.h:#define BCMA_DMP_OOB_EXTWIDTH(_bank) (BCMA_DMP_OOBAEXTWIDTH + (_bank * 12)) dev/bhnd/bcma/bcma_dmp.h:#define BCMA_DMP_OOB_INWIDTH(_bank) (BCMA_DMP_OOBAINWIDTH + (_bank * 12)) dev/bhnd/bhnd.h:#define BHND_DIRECT_RESOURCE(_r) ((struct bhnd_resource) { \ dev/bhnd/bhnd_debug.h:#define BHND_ERROR(fmt, ...) \ dev/bhnd/bhnd_match.h:#define BHND_HWREV_IS_ANY(_m) \ dev/bhnd/bhnd_match.h:#define BHND_HWREV_EQ(_hwrev) BHND_HWREV_RANGE(_hwrev, _hwrev) dev/bhnd/bhnd_match.h:#define BHND_HWREV_GTE(_start) BHND_HWREV_RANGE(_start, BHND_HWREV_INVALID) dev/bhnd/bhnd_match.h:#define BHND_HWREV_LTE(_end) BHND_HWREV_RANGE(0, _end) dev/bhnd/bhnd_match.h:#define BHND_CHIP_IPR(_cid, _pkg, _rev) \ dev/bhnd/cores/chipc/chipc.c:#define CHIPC_ASSERT_CAP(_sc, name) \ dev/bhnd/cores/chipc/chipcreg.h:#define CHIPC_HAS_EROMPTR(_chipid) \ dev/bhnd/cores/chipc/chipcreg.h:#define CHIPC_OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctlvar.h:#define PWRCTL_ASSERT_QUIRK(_sc, name) \ dev/bhnd/cores/pci/bhnd_pci_hostb.c:#define BPCI_REG_GET(_regv, _attr) \ dev/bhnd/cores/pci/bhnd_pci_hostb.c:#define BPCI_CMN_REG_SET(_regv, _attr, _val) \ dev/bhnd/cores/pci/bhnd_pci_hostb.c:#define BPCI_CMN_REG_GET(_regv, _attr) \ dev/bhnd/cores/pci/bhnd_pcireg.h:#define BHND_PCIE_CFG_OFFSET(f, r) \ dev/bhnd/cores/pmu/bhnd_pmu_private.h:#define BHND_PMU_REGCTRL_READ(_sc, _reg) \ dev/bhnd/cores/pmu/bhnd_pmuvar.h:#define BPMU_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) dev/bhnd/nvram/bhnd_nvram_storevar.h:#define BHND_NVSTORE_GET_BITS(_value, _field) \ dev/bhnd/nvram/bhnd_nvram_value.c:#define BHND_NVRAM_VAL_EXTREF_BORROWED_DATA(_flags) \ dev/bnxt/bnxt.h:#define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ dev/bnxt/bnxt.h:#define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) dev/bnxt/hsi_struct_def.h:#define GET_EVENT_ID(x) \ dev/bwn/if_bwnvar.h:#define BWN_VAP_CONST(vap) ((const struct mwl_vap *)(vap)) dev/bxe/bxe.h:#define GET_FLAG(value, mask) \ dev/bxe/bxe.h:#define RX_SGE_ONES_MASK(idx) \ dev/bxe/bxe.h:#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) dev/bxe/bxe.h:#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) dev/bxe/bxe.h:#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) dev/bxe/bxe.h:#define MIN_RX_SIZE_TPA(sc) \ dev/bxe/bxe.h:#define MIN_RX_SIZE_NONTPA(sc) \ dev/bxe/bxe.h:#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) dev/bxe/bxe.h:#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) dev/bxe/bxe.h:#define SGE_MASK_SET_BIT(fp, idx) \ dev/bxe/bxe.h:#define SGE_MASK_CLEAR_BIT(fp, idx) \ dev/bxe/bxe.h:#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) dev/bxe/bxe.h:#define FP_IDX(fp) (fp->index) dev/bxe/bxe.h:#define FP_CL_ID(fp) (fp->cl_id) dev/bxe/bxe.h:#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) dev/bxe/bxe.h:#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ dev/bxe/bxe.h:#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ dev/bxe/bxe.h:#define FOR_EACH_CNIC_QUEUE(sc, var) \ dev/bxe/bxe.h:#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) dev/bxe/bxe.h:#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) dev/bxe/bxe.h:#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) dev/bxe/bxe.h:#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) dev/bxe/bxe.h:#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) dev/bxe/bxe.h:#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) dev/bxe/bxe.h:#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) dev/bxe/bxe.h:#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) dev/bxe/bxe.h:#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) dev/bxe/bxe.h:#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) dev/bxe/bxe.h:#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) dev/bxe/bxe.h:#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) dev/bxe/bxe.h:#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) dev/bxe/bxe.h:#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) dev/bxe/bxe.h:#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) dev/bxe/bxe.h:#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) dev/bxe/bxe.h:#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) dev/bxe/bxe.h:#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) dev/bxe/bxe.h:#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) dev/bxe/bxe.h:#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) dev/bxe/bxe.h:#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) dev/bxe/bxe.h:#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) dev/bxe/bxe.h:#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) dev/bxe/bxe.h:#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) dev/bxe/bxe.h:#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) dev/bxe/bxe.h:#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) dev/bxe/bxe.h:#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) dev/bxe/bxe.h:#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) dev/bxe/bxe.h:#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) dev/bxe/bxe.h:#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ dev/bxe/bxe.h:#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) dev/bxe/bxe_dcb.h:#define BXE_DCBX_STRICT_COS_NEXT_LOWER_PRI(sp) ((sp) + 1) dev/bxe/bxe_dcb.h:#define GET_FLAGS(flags, bits) ((flags) & (bits)) dev/bxe/bxe_dcb.h:#define PFC_QUANTA_IN_NANOSEC_FROM_SPEED_MEGA(mega_speed) \ dev/bxe/bxe_dcb.h:#define DCBX_IS_PFC_PRI_SOME_PAUSE(sc, pg_pri) \ dev/bxe/bxe_dcb.h:#define IS_DCBX_PFC_PRI_MIX_PAUSE(sc, pg_pri) \ dev/bxe/bxe_elink.h:#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \ dev/bxe/bxe_elink.h:#define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2) dev/bxe/bxe_elink.h:#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ dev/bxe/bxe_elink.h:#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ dev/bxe/bxe_elink.h:#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ dev/bxe/ecore_hsi.h:#define DCBX_PRI_PG_GET(a, i) \ dev/bxe/ecore_hsi.h:#define DCBX_PRI_PG_SET(a, i, val) \ dev/bxe/ecore_hsi.h:#define DCBX_PG_BW_GET(a, i) \ dev/bxe/ecore_hsi.h:#define DCBX_PG_BW_SET(a, i, val) \ dev/bxe/ecore_reg.h:#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) dev/bxe/ecore_reg.h:#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \ dev/bxe/ecore_reg.h:#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) dev/bxe/ecore_sp.h:#define ECORE_SMP_RMB() rmb() dev/bxe/ecore_sp.h:#define ECORE_SMP_WMB() wmb() dev/ce/ceddk.c:#define CE_DUMP_QUEUE(list) \ dev/ce/if_ce.c:#define CE_LOCK_ASSERT(_bd) mtx_assert (&(_bd)->ce_mtx, MA_OWNED) dev/ciss/cissreg.h:#define CISS_BIG_MAP_ID(sc, bus, target) \ dev/cm/smc90cx6reg.h:#define CM_RX(x) (0x04 | ((x)<<3)) dev/cm/smc90cx6reg.h:#define CM_LDTST(x) (0x07 | (x)) dev/cmx/cmxvar.h:#define cmx_write_BSR(sc, val) \ dev/cmx/cmxvar.h:#define CMX_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, (what)) dev/cp/cpddk.h:#define DESC_LEN(v) ((v) >> 16 & 0x1fff) dev/cp/if_cp.c:#define CP_LOCK_ASSERT(_bd) mtx_assert (&(_bd)->cp_mtx, MA_OWNED) dev/ctau/ctddk.h:#define ct_get_phony(c) ((c)->gopt.phony) dev/ctau/ds2153.h:#define SSR_CSC(v) (((v) >> 2) & 0x3c | ((v) >> 3) & 1) dev/ctau/ds2153.h:#define FASCRH(h) ((h) << 4) /* 12-bit FAS error count */ dev/ctau/ds2153.h:#define FASCRL(l) ((l) >> 2) /* 12-bit FAS error count */ dev/ctau/if_ct.c:#define CT_LOCK_ASSERT(_bd) mtx_assert (&(_bd)->ct_mtx, MA_OWNED) dev/cx/cxreg.h:#define LICR(b) R(b,0x25) /* local interrupting channel register */ dev/cx/cxreg.h:#define RISRL(b) R(b,0x8a) /* receive interrupt status register low */ dev/cx/cxreg.h:#define RISRH(b) R(b,0x8b) /* receive interrupt status register high */ dev/cx/cxreg.h:#define RFOC(b) R(b,0x33) /* receive FIFO output count */ dev/cx/cxreg.h:#define TFTC(b) R(b,0x83) /* transmit FIFO transfer count */ dev/cx/cxreg.h:#define TCBADRL(b) R(b,0x38) /* transmit current buffer address lower */ dev/cx/cxreg.h:#define TCBADRU(b) R(b,0x3a) /* transmit current buffer address upper */ dev/cx/cxreg.h:#define RTPRL(b) R(b,0x26) /* receive timeout period register low */ dev/cx/cxreg.h:#define RTPTH(b) R(b,0x27) /* receive timeout period register high */ dev/cx/cxreg.h:#define BSR_NODSR(n) (0x100 << (n)) /* DSR from channels 0-3, inverted */ dev/cx/cxreg.h:#define BSR_NOCD(n) (0x1000 << (n)) /* CD from channels 0-3, inverted */ dev/cx/if_cx.c:#define CX_LOCK_ASSERT(_bd) mtx_assert (&(_bd)->cx_mtx, MA_OWNED) dev/cxgb/common/cxgb_common.h:#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) dev/cxgb/common/cxgb_common.h:#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) dev/cxgb/common/cxgb_common.h:#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) dev/cxgb/common/cxgb_common.h:#define G_TP_VERSION_MICRO(x) \ dev/cxgb/common/cxgb_firmware_exports.h:#define V_FW_VERSION_TYPE(x) ((x) << S_FW_VERSION_TYPE) dev/cxgb/common/cxgb_firmware_exports.h:#define V_FW_VERSION_MAJOR(x) ((x) << S_FW_VERSION_MAJOR) dev/cxgb/common/cxgb_firmware_exports.h:#define V_FW_VERSION_MINOR(x) ((x) << S_FW_VERSION_MINOR) dev/cxgb/common/cxgb_firmware_exports.h:#define V_FW_VERSION_MICRO(x) ((x) << S_FW_VERSION_MICRO) dev/cxgb/common/cxgb_mv88e1xxx.c:#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) dev/cxgb/common/cxgb_mv88e1xxx.c:#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN) dev/cxgb/common/cxgb_mv88e1xxx.c:#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED) dev/cxgb/common/cxgb_regs.h:#define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE) dev/cxgb/common/cxgb_regs.h:#define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE) dev/cxgb/common/cxgb_regs.h:#define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX) dev/cxgb/common/cxgb_regs.h:#define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ) dev/cxgb/common/cxgb_regs.h:#define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER) dev/cxgb/common/cxgb_regs.h:#define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX) dev/cxgb/common/cxgb_regs.h:#define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE) dev/cxgb/common/cxgb_regs.h:#define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT) dev/cxgb/common/cxgb_regs.h:#define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT) dev/cxgb/common/cxgb_regs.h:#define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT) dev/cxgb/common/cxgb_regs.h:#define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS) dev/cxgb/common/cxgb_regs.h:#define V_DATAINTR(x) ((x) << S_DATAINTR) dev/cxgb/common/cxgb_regs.h:#define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR) dev/cxgb/common/cxgb_regs.h:#define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH) dev/cxgb/common/cxgb_regs.h:#define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH) dev/cxgb/common/cxgb_regs.h:#define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH) dev/cxgb/common/cxgb_regs.h:#define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH) dev/cxgb/common/cxgb_regs.h:#define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH) dev/cxgb/common/cxgb_regs.h:#define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH) dev/cxgb/common/cxgb_regs.h:#define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH) dev/cxgb/common/cxgb_regs.h:#define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH) dev/cxgb/common/cxgb_regs.h:#define V_RSPQXSTARVED(x) ((x) << S_RSPQXSTARVED) dev/cxgb/common/cxgb_regs.h:#define G_RSPQXSTARVED(x) (((x) >> S_RSPQXSTARVED) & M_RSPQXSTARVED) dev/cxgb/common/cxgb_regs.h:#define V_FLXEMPTY(x) ((x) << S_FLXEMPTY) dev/cxgb/common/cxgb_regs.h:#define G_FLXEMPTY(x) (((x) >> S_FLXEMPTY) & M_FLXEMPTY) dev/cxgb/common/cxgb_regs.h:#define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE) dev/cxgb/common/cxgb_regs.h:#define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE) dev/cxgb/common/cxgb_regs.h:#define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE) dev/cxgb/common/cxgb_regs.h:#define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE) dev/cxgb/common/cxgb_regs.h:#define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE) dev/cxgb/common/cxgb_regs.h:#define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE) dev/cxgb/common/cxgb_regs.h:#define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) dev/cxgb/common/cxgb_regs.h:#define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) dev/cxgb/common/cxgb_regs.h:#define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH) dev/cxgb/common/cxgb_regs.h:#define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH) dev/cxgb/common/cxgb_regs.h:#define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR) dev/cxgb/common/cxgb_regs.h:#define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR) dev/cxgb/common/cxgb_regs.h:#define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR) dev/cxgb/common/cxgb_regs.h:#define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR) dev/cxgb/common/cxgb_regs.h:#define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT) dev/cxgb/common/cxgb_regs.h:#define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD) dev/cxgb/common/cxgb_regs.h:#define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH) dev/cxgb/common/cxgb_regs.h:#define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH) dev/cxgb/common/cxgb_regs.h:#define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR) dev/cxgb/common/cxgb_regs.h:#define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR) dev/cxgb/common/cxgb_regs.h:#define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR) dev/cxgb/common/cxgb_regs.h:#define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR) dev/cxgb/common/cxgb_regs.h:#define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC) dev/cxgb/common/cxgb_regs.h:#define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC) dev/cxgb/common/cxgb_regs.h:#define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC) dev/cxgb/common/cxgb_regs.h:#define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC) dev/cxgb/common/cxgb_regs.h:#define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR) dev/cxgb/common/cxgb_regs.h:#define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR) dev/cxgb/common/cxgb_regs.h:#define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT) dev/cxgb/common/cxgb_regs.h:#define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT) dev/cxgb/common/cxgb_regs.h:#define V_PCLKRANGE(x) ((x) << S_PCLKRANGE) dev/cxgb/common/cxgb_regs.h:#define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT) dev/cxgb/common/cxgb_regs.h:#define V_PERCALDIV(x) ((x) << S_PERCALDIV) dev/cxgb/common/cxgb_regs.h:#define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV) dev/cxgb/common/cxgb_regs.h:#define V_ZPDMAN(x) ((x) << S_ZPDMAN) dev/cxgb/common/cxgb_regs.h:#define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN) dev/cxgb/common/cxgb_regs.h:#define V_ZPUMAN(x) ((x) << S_ZPUMAN) dev/cxgb/common/cxgb_regs.h:#define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN) dev/cxgb/common/cxgb_regs.h:#define V_ZPDOUT(x) ((x) << S_ZPDOUT) dev/cxgb/common/cxgb_regs.h:#define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT) dev/cxgb/common/cxgb_regs.h:#define V_ZPUOUT(x) ((x) << S_ZPUOUT) dev/cxgb/common/cxgb_regs.h:#define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT) dev/cxgb/common/cxgb_regs.h:#define V_ZPDIN(x) ((x) << S_ZPDIN) dev/cxgb/common/cxgb_regs.h:#define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN) dev/cxgb/common/cxgb_regs.h:#define V_ZPUIN(x) ((x) << S_ZPUIN) dev/cxgb/common/cxgb_regs.h:#define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN) dev/cxgb/common/cxgb_regs.h:#define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL) dev/cxgb/common/cxgb_regs.h:#define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL) dev/cxgb/common/cxgb_regs.h:#define V_RFINIST(x) ((x) << S_RFINIST) dev/cxgb/common/cxgb_regs.h:#define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST) dev/cxgb/common/cxgb_regs.h:#define V_RFRESPRDST(x) ((x) << S_RFRESPRDST) dev/cxgb/common/cxgb_regs.h:#define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST) dev/cxgb/common/cxgb_regs.h:#define V_TARCST(x) ((x) << S_TARCST) dev/cxgb/common/cxgb_regs.h:#define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST) dev/cxgb/common/cxgb_regs.h:#define V_TARXST(x) ((x) << S_TARXST) dev/cxgb/common/cxgb_regs.h:#define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST) dev/cxgb/common/cxgb_regs.h:#define V_WFREQWRST(x) ((x) << S_WFREQWRST) dev/cxgb/common/cxgb_regs.h:#define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST) dev/cxgb/common/cxgb_regs.h:#define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL) dev/cxgb/common/cxgb_regs.h:#define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL) dev/cxgb/common/cxgb_regs.h:#define V_WFINIST(x) ((x) << S_WFINIST) dev/cxgb/common/cxgb_regs.h:#define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST) dev/cxgb/common/cxgb_regs.h:#define V_ARBST(x) ((x) << S_ARBST) dev/cxgb/common/cxgb_regs.h:#define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST) dev/cxgb/common/cxgb_regs.h:#define V_PMIST(x) ((x) << S_PMIST) dev/cxgb/common/cxgb_regs.h:#define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST) dev/cxgb/common/cxgb_regs.h:#define V_CALST(x) ((x) << S_CALST) dev/cxgb/common/cxgb_regs.h:#define G_CALST(x) (((x) >> S_CALST) & M_CALST) dev/cxgb/common/cxgb_regs.h:#define V_CFREQRDST(x) ((x) << S_CFREQRDST) dev/cxgb/common/cxgb_regs.h:#define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST) dev/cxgb/common/cxgb_regs.h:#define V_CFINIST(x) ((x) << S_CFINIST) dev/cxgb/common/cxgb_regs.h:#define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST) dev/cxgb/common/cxgb_regs.h:#define V_CFRESPRDST(x) ((x) << S_CFRESPRDST) dev/cxgb/common/cxgb_regs.h:#define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST) dev/cxgb/common/cxgb_regs.h:#define V_INICST(x) ((x) << S_INICST) dev/cxgb/common/cxgb_regs.h:#define G_INICST(x) (((x) >> S_INICST) & M_INICST) dev/cxgb/common/cxgb_regs.h:#define V_INIXST(x) ((x) << S_INIXST) dev/cxgb/common/cxgb_regs.h:#define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST) dev/cxgb/common/cxgb_regs.h:#define V_INTST(x) ((x) << S_INTST) dev/cxgb/common/cxgb_regs.h:#define G_INTST(x) (((x) >> S_INTST) & M_INTST) dev/cxgb/common/cxgb_regs.h:#define V_PIOST(x) ((x) << S_PIOST) dev/cxgb/common/cxgb_regs.h:#define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST) dev/cxgb/common/cxgb_regs.h:#define V_RFREQRDST(x) ((x) << S_RFREQRDST) dev/cxgb/common/cxgb_regs.h:#define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST) dev/cxgb/common/cxgb_regs.h:#define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR) dev/cxgb/common/cxgb_regs.h:#define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC) dev/cxgb/common/cxgb_regs.h:#define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR) dev/cxgb/common/cxgb_regs.h:#define V_TAR_STATE(x) ((x) << S_TAR_STATE) dev/cxgb/common/cxgb_regs.h:#define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE) dev/cxgb/common/cxgb_regs.h:#define V_RF_STATEINI(x) ((x) << S_RF_STATEINI) dev/cxgb/common/cxgb_regs.h:#define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI) dev/cxgb/common/cxgb_regs.h:#define V_CF_STATEINI(x) ((x) << S_CF_STATEINI) dev/cxgb/common/cxgb_regs.h:#define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI) dev/cxgb/common/cxgb_regs.h:#define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL) dev/cxgb/common/cxgb_regs.h:#define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL) dev/cxgb/common/cxgb_regs.h:#define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC) dev/cxgb/common/cxgb_regs.h:#define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC) dev/cxgb/common/cxgb_regs.h:#define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) dev/cxgb/common/cxgb_regs.h:#define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE) dev/cxgb/common/cxgb_regs.h:#define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE) dev/cxgb/common/cxgb_regs.h:#define V_INI_STATE(x) ((x) << S_INI_STATE) dev/cxgb/common/cxgb_regs.h:#define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE) dev/cxgb/common/cxgb_regs.h:#define V_WF_STATEINI(x) ((x) << S_WF_STATEINI) dev/cxgb/common/cxgb_regs.h:#define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI) dev/cxgb/common/cxgb_regs.h:#define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT) dev/cxgb/common/cxgb_regs.h:#define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT) dev/cxgb/common/cxgb_regs.h:#define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT) dev/cxgb/common/cxgb_regs.h:#define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT) dev/cxgb/common/cxgb_regs.h:#define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT) dev/cxgb/common/cxgb_regs.h:#define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT) dev/cxgb/common/cxgb_regs.h:#define V_ZMAN(x) ((x) << S_ZMAN) dev/cxgb/common/cxgb_regs.h:#define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN) dev/cxgb/common/cxgb_regs.h:#define V_ZOUT(x) ((x) << S_ZOUT) dev/cxgb/common/cxgb_regs.h:#define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT) dev/cxgb/common/cxgb_regs.h:#define V_ZIN(x) ((x) << S_ZIN) dev/cxgb/common/cxgb_regs.h:#define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN) dev/cxgb/common/cxgb_regs.h:#define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE) dev/cxgb/common/cxgb_regs.h:#define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE) dev/cxgb/common/cxgb_regs.h:#define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE) dev/cxgb/common/cxgb_regs.h:#define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE) dev/cxgb/common/cxgb_regs.h:#define V_PME_STATE(x) ((x) << S_PME_STATE) dev/cxgb/common/cxgb_regs.h:#define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE) dev/cxgb/common/cxgb_regs.h:#define V_INT_STATE(x) ((x) << S_INT_STATE) dev/cxgb/common/cxgb_regs.h:#define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE) dev/cxgb/common/cxgb_regs.h:#define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) dev/cxgb/common/cxgb_regs.h:#define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT) dev/cxgb/common/cxgb_regs.h:#define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT) dev/cxgb/common/cxgb_regs.h:#define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT) dev/cxgb/common/cxgb_regs.h:#define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT) dev/cxgb/common/cxgb_regs.h:#define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID) dev/cxgb/common/cxgb_regs.h:#define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID) dev/cxgb/common/cxgb_regs.h:#define V_LANE(x) ((x) << S_LANE) dev/cxgb/common/cxgb_regs.h:#define G_LANE(x) (((x) >> S_LANE) & M_LANE) dev/cxgb/common/cxgb_regs.h:#define V_RECDETUSEC(x) ((x) << S_RECDETUSEC) dev/cxgb/common/cxgb_regs.h:#define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC) dev/cxgb/common/cxgb_regs.h:#define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC) dev/cxgb/common/cxgb_regs.h:#define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC) dev/cxgb/common/cxgb_regs.h:#define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC) dev/cxgb/common/cxgb_regs.h:#define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC) dev/cxgb/common/cxgb_regs.h:#define V_TESTSIG(x) ((x) << S_TESTSIG) dev/cxgb/common/cxgb_regs.h:#define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG) dev/cxgb/common/cxgb_regs.h:#define V_MANLPBKEN(x) ((x) << S_MANLPBKEN) dev/cxgb/common/cxgb_regs.h:#define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN) dev/cxgb/common/cxgb_regs.h:#define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE) dev/cxgb/common/cxgb_regs.h:#define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN) dev/cxgb/common/cxgb_regs.h:#define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP) dev/cxgb/common/cxgb_regs.h:#define V_PREEMPH(x) ((x) << S_PREEMPH) dev/cxgb/common/cxgb_regs.h:#define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH) dev/cxgb/common/cxgb_regs.h:#define V_RXEQCTL(x) ((x) << S_RXEQCTL) dev/cxgb/common/cxgb_regs.h:#define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL) dev/cxgb/common/cxgb_regs.h:#define V_RXTERMADJ(x) ((x) << S_RXTERMADJ) dev/cxgb/common/cxgb_regs.h:#define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ) dev/cxgb/common/cxgb_regs.h:#define V_TXTERMADJ(x) ((x) << S_TXTERMADJ) dev/cxgb/common/cxgb_regs.h:#define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ) dev/cxgb/common/cxgb_regs.h:#define V_DEQ(x) ((x) << S_DEQ) dev/cxgb/common/cxgb_regs.h:#define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ) dev/cxgb/common/cxgb_regs.h:#define V_DTX(x) ((x) << S_DTX) dev/cxgb/common/cxgb_regs.h:#define G_DTX(x) (((x) >> S_DTX) & M_DTX) dev/cxgb/common/cxgb_regs.h:#define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT) dev/cxgb/common/cxgb_regs.h:#define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT) dev/cxgb/common/cxgb_regs.h:#define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET) dev/cxgb/common/cxgb_regs.h:#define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET) dev/cxgb/common/cxgb_regs.h:#define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT) dev/cxgb/common/cxgb_regs.h:#define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT) dev/cxgb/common/cxgb_regs.h:#define V_P_WMARK(x) ((x) << S_P_WMARK) dev/cxgb/common/cxgb_regs.h:#define G_P_WMARK(x) (((x) >> S_P_WMARK) & M_P_WMARK) dev/cxgb/common/cxgb_regs.h:#define V_NP_WMARK(x) ((x) << S_NP_WMARK) dev/cxgb/common/cxgb_regs.h:#define G_NP_WMARK(x) (((x) >> S_NP_WMARK) & M_NP_WMARK) dev/cxgb/common/cxgb_regs.h:#define V_CPL_WMARK(x) ((x) << S_CPL_WMARK) dev/cxgb/common/cxgb_regs.h:#define G_CPL_WMARK(x) (((x) >> S_CPL_WMARK) & M_CPL_WMARK) dev/cxgb/common/cxgb_regs.h:#define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE) dev/cxgb/common/cxgb_regs.h:#define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH) dev/cxgb/common/cxgb_regs.h:#define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH) dev/cxgb/common/cxgb_regs.h:#define V_BISTMODE(x) ((x) << S_BISTMODE) dev/cxgb/common/cxgb_regs.h:#define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE) dev/cxgb/common/cxgb_regs.h:#define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL) dev/cxgb/common/cxgb_regs.h:#define G_X_RBC_LANE_SEL(x) (((x) >> S_X_RBC_LANE_SEL) & M_X_RBC_LANE_SEL) dev/cxgb/common/cxgb_regs.h:#define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL) dev/cxgb/common/cxgb_regs.h:#define G_PE_RBC_LANE_SEL(x) (((x) >> S_PE_RBC_LANE_SEL) & M_PE_RBC_LANE_SEL) dev/cxgb/common/cxgb_regs.h:#define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO) dev/cxgb/common/cxgb_regs.h:#define G_PMON_FDEL_AUTO(x) (((x) >> S_PMON_FDEL_AUTO) & M_PMON_FDEL_AUTO) dev/cxgb/common/cxgb_regs.h:#define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO) dev/cxgb/common/cxgb_regs.h:#define G_PMON_CDEL_AUTO(x) (((x) >> S_PMON_CDEL_AUTO) & M_PMON_CDEL_AUTO) dev/cxgb/common/cxgb_regs.h:#define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL) dev/cxgb/common/cxgb_regs.h:#define G_PMON_FDEL_MANUAL(x) (((x) >> S_PMON_FDEL_MANUAL) & M_PMON_FDEL_MANUAL) dev/cxgb/common/cxgb_regs.h:#define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL) dev/cxgb/common/cxgb_regs.h:#define G_PMON_CDEL_MANUAL(x) (((x) >> S_PMON_CDEL_MANUAL) & M_PMON_CDEL_MANUAL) dev/cxgb/common/cxgb_regs.h:#define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ) dev/cxgb/common/cxgb_regs.h:#define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ) dev/cxgb/common/cxgb_regs.h:#define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ) dev/cxgb/common/cxgb_regs.h:#define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ) dev/cxgb/common/cxgb_regs.h:#define V_DEN(x) ((x) << S_DEN) dev/cxgb/common/cxgb_regs.h:#define G_MODE(x) (((x) >> S_MODE) & M_MODE) dev/cxgb/common/cxgb_regs.h:#define V_OCDCODE(x) ((x) << S_OCDCODE) dev/cxgb/common/cxgb_regs.h:#define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE) dev/cxgb/common/cxgb_regs.h:#define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV) dev/cxgb/common/cxgb_regs.h:#define V_DLLDELTA(x) ((x) << S_DLLDELTA) dev/cxgb/common/cxgb_regs.h:#define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA) dev/cxgb/common/cxgb_regs.h:#define V_MANDELTA(x) ((x) << S_MANDELTA) dev/cxgb/common/cxgb_regs.h:#define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA) dev/cxgb/common/cxgb_regs.h:#define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY) dev/cxgb/common/cxgb_regs.h:#define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY) dev/cxgb/common/cxgb_regs.h:#define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC) dev/cxgb/common/cxgb_regs.h:#define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC) dev/cxgb/common/cxgb_regs.h:#define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC) dev/cxgb/common/cxgb_regs.h:#define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY) dev/cxgb/common/cxgb_regs.h:#define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY) dev/cxgb/common/cxgb_regs.h:#define V_MEM_HWM(x) ((x) << S_MEM_HWM) dev/cxgb/common/cxgb_regs.h:#define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM) dev/cxgb/common/cxgb_regs.h:#define V_ULP_HWM(x) ((x) << S_ULP_HWM) dev/cxgb/common/cxgb_regs.h:#define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM) dev/cxgb/common/cxgb_regs.h:#define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT) dev/cxgb/common/cxgb_regs.h:#define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT) dev/cxgb/common/cxgb_regs.h:#define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT) dev/cxgb/common/cxgb_regs.h:#define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT) dev/cxgb/common/cxgb_regs.h:#define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT) dev/cxgb/common/cxgb_regs.h:#define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT) dev/cxgb/common/cxgb_regs.h:#define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV) dev/cxgb/common/cxgb_regs.h:#define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV) dev/cxgb/common/cxgb_regs.h:#define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD) dev/cxgb/common/cxgb_regs.h:#define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD) dev/cxgb/common/cxgb_regs.h:#define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU) dev/cxgb/common/cxgb_regs.h:#define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU) dev/cxgb/common/cxgb_regs.h:#define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD) dev/cxgb/common/cxgb_regs.h:#define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD) dev/cxgb/common/cxgb_regs.h:#define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU) dev/cxgb/common/cxgb_regs.h:#define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU) dev/cxgb/common/cxgb_regs.h:#define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD) dev/cxgb/common/cxgb_regs.h:#define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD) dev/cxgb/common/cxgb_regs.h:#define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU) dev/cxgb/common/cxgb_regs.h:#define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU) dev/cxgb/common/cxgb_regs.h:#define V_ERRADDRESS(x) ((x) << S_ERRADDRESS) dev/cxgb/common/cxgb_regs.h:#define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS) dev/cxgb/common/cxgb_regs.h:#define V_ERRAGENT(x) ((x) << S_ERRAGENT) dev/cxgb/common/cxgb_regs.h:#define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT) dev/cxgb/common/cxgb_regs.h:#define V_UECNT(x) ((x) << S_UECNT) dev/cxgb/common/cxgb_regs.h:#define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT) dev/cxgb/common/cxgb_regs.h:#define V_CECNT(x) ((x) << S_CECNT) dev/cxgb/common/cxgb_regs.h:#define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT) dev/cxgb/common/cxgb_regs.h:#define V_ADDRBEG(x) ((x) << S_ADDRBEG) dev/cxgb/common/cxgb_regs.h:#define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG) dev/cxgb/common/cxgb_regs.h:#define V_ADDREND(x) ((x) << S_ADDREND) dev/cxgb/common/cxgb_regs.h:#define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND) dev/cxgb/common/cxgb_regs.h:#define V_DATAPAT(x) ((x) << S_DATAPAT) dev/cxgb/common/cxgb_regs.h:#define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT) dev/cxgb/common/cxgb_regs.h:#define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID) dev/cxgb/common/cxgb_regs.h:#define V_OBQDBGQID(x) ((x) << S_OBQDBGQID) dev/cxgb/common/cxgb_regs.h:#define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID) dev/cxgb/common/cxgb_regs.h:#define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI) dev/cxgb/common/cxgb_regs.h:#define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI) dev/cxgb/common/cxgb_regs.h:#define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO) dev/cxgb/common/cxgb_regs.h:#define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO) dev/cxgb/common/cxgb_regs.h:#define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE) dev/cxgb/common/cxgb_regs.h:#define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE) dev/cxgb/common/cxgb_regs.h:#define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE) dev/cxgb/common/cxgb_regs.h:#define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE) dev/cxgb/common/cxgb_regs.h:#define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE) dev/cxgb/common/cxgb_regs.h:#define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE) dev/cxgb/common/cxgb_regs.h:#define V_PMSIZE(x) ((x) << S_PMSIZE) dev/cxgb/common/cxgb_regs.h:#define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE) dev/cxgb/common/cxgb_regs.h:#define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) dev/cxgb/common/cxgb_regs.h:#define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX) dev/cxgb/common/cxgb_regs.h:#define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE) dev/cxgb/common/cxgb_regs.h:#define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE) dev/cxgb/common/cxgb_regs.h:#define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE) dev/cxgb/common/cxgb_regs.h:#define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU) dev/cxgb/common/cxgb_regs.h:#define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU) dev/cxgb/common/cxgb_regs.h:#define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE) dev/cxgb/common/cxgb_regs.h:#define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE) dev/cxgb/common/cxgb_regs.h:#define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE) dev/cxgb/common/cxgb_regs.h:#define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE) dev/cxgb/common/cxgb_regs.h:#define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE) dev/cxgb/common/cxgb_regs.h:#define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE) dev/cxgb/common/cxgb_regs.h:#define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE) dev/cxgb/common/cxgb_regs.h:#define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE) dev/cxgb/common/cxgb_regs.h:#define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS) dev/cxgb/common/cxgb_regs.h:#define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS) dev/cxgb/common/cxgb_regs.h:#define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS) dev/cxgb/common/cxgb_regs.h:#define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS) dev/cxgb/common/cxgb_regs.h:#define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD) dev/cxgb/common/cxgb_regs.h:#define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD) dev/cxgb/common/cxgb_regs.h:#define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD) dev/cxgb/common/cxgb_regs.h:#define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD) dev/cxgb/common/cxgb_regs.h:#define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD) dev/cxgb/common/cxgb_regs.h:#define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD) dev/cxgb/common/cxgb_regs.h:#define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN) dev/cxgb/common/cxgb_regs.h:#define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE) dev/cxgb/common/cxgb_regs.h:#define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG) dev/cxgb/common/cxgb_regs.h:#define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG) dev/cxgb/common/cxgb_regs.h:#define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG) dev/cxgb/common/cxgb_regs.h:#define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG) dev/cxgb/common/cxgb_regs.h:#define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR) dev/cxgb/common/cxgb_regs.h:#define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR) dev/cxgb/common/cxgb_regs.h:#define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR) dev/cxgb/common/cxgb_regs.h:#define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR) dev/cxgb/common/cxgb_regs.h:#define V_SGETPQID(x) ((x) << S_SGETPQID) dev/cxgb/common/cxgb_regs.h:#define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID) dev/cxgb/common/cxgb_regs.h:#define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL) dev/cxgb/common/cxgb_regs.h:#define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL) dev/cxgb/common/cxgb_regs.h:#define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT) dev/cxgb/common/cxgb_regs.h:#define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT) dev/cxgb/common/cxgb_regs.h:#define V_MCADEPTH(x) ((x) << S_MCADEPTH) dev/cxgb/common/cxgb_regs.h:#define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH) dev/cxgb/common/cxgb_regs.h:#define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT) dev/cxgb/common/cxgb_regs.h:#define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT) dev/cxgb/common/cxgb_regs.h:#define V_RXTPCNT(x) ((x) << S_RXTPCNT) dev/cxgb/common/cxgb_regs.h:#define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT) dev/cxgb/common/cxgb_regs.h:#define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB) dev/cxgb/common/cxgb_regs.h:#define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB) dev/cxgb/common/cxgb_regs.h:#define V_MCAPARERR(x) ((x) << S_MCAPARERR) dev/cxgb/common/cxgb_regs.h:#define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR) dev/cxgb/common/cxgb_regs.h:#define V_RXTPPARERR(x) ((x) << S_RXTPPARERR) dev/cxgb/common/cxgb_regs.h:#define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR) dev/cxgb/common/cxgb_regs.h:#define V_ZERO_CMD(x) ((x) << S_ZERO_CMD) dev/cxgb/common/cxgb_regs.h:#define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD) dev/cxgb/common/cxgb_regs.h:#define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX) dev/cxgb/common/cxgb_regs.h:#define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX) dev/cxgb/common/cxgb_regs.h:#define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA) dev/cxgb/common/cxgb_regs.h:#define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA) dev/cxgb/common/cxgb_regs.h:#define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR) dev/cxgb/common/cxgb_regs.h:#define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR) dev/cxgb/common/cxgb_regs.h:#define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR) dev/cxgb/common/cxgb_regs.h:#define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR) dev/cxgb/common/cxgb_regs.h:#define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR) dev/cxgb/common/cxgb_regs.h:#define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR) dev/cxgb/common/cxgb_regs.h:#define V_MDI_DATA(x) ((x) << S_MDI_DATA) dev/cxgb/common/cxgb_regs.h:#define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA) dev/cxgb/common/cxgb_regs.h:#define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP) dev/cxgb/common/cxgb_regs.h:#define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV) dev/cxgb/common/cxgb_regs.h:#define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV) dev/cxgb/common/cxgb_regs.h:#define V_LCK(x) ((x) << S_LCK) dev/cxgb/common/cxgb_regs.h:#define G_LCK(x) (((x) >> S_LCK) & M_LCK) dev/cxgb/common/cxgb_regs.h:#define V_MAN_PU(x) ((x) << S_MAN_PU) dev/cxgb/common/cxgb_regs.h:#define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU) dev/cxgb/common/cxgb_regs.h:#define V_MAN_PD(x) ((x) << S_MAN_PD) dev/cxgb/common/cxgb_regs.h:#define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD) dev/cxgb/common/cxgb_regs.h:#define V_CAL_PU(x) ((x) << S_CAL_PU) dev/cxgb/common/cxgb_regs.h:#define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU) dev/cxgb/common/cxgb_regs.h:#define V_CAL_PD(x) ((x) << S_CAL_PD) dev/cxgb/common/cxgb_regs.h:#define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD) dev/cxgb/common/cxgb_regs.h:#define V_SET_PU(x) ((x) << S_SET_PU) dev/cxgb/common/cxgb_regs.h:#define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU) dev/cxgb/common/cxgb_regs.h:#define V_SET_PD(x) ((x) << S_SET_PD) dev/cxgb/common/cxgb_regs.h:#define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD) dev/cxgb/common/cxgb_regs.h:#define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE) dev/cxgb/common/cxgb_regs.h:#define V_TMTYPE(x) ((x) << S_TMTYPE) dev/cxgb/common/cxgb_regs.h:#define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT) dev/cxgb/common/cxgb_regs.h:#define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT) dev/cxgb/common/cxgb_regs.h:#define V_NLIP(x) ((x) << S_NLIP) dev/cxgb/common/cxgb_regs.h:#define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP) dev/cxgb/common/cxgb_regs.h:#define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE) dev/cxgb/common/cxgb_regs.h:#define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE) dev/cxgb/common/cxgb_regs.h:#define V_RAMADDR(x) ((x) << S_RAMADDR) dev/cxgb/common/cxgb_regs.h:#define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR) dev/cxgb/common/cxgb_regs.h:#define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT) dev/cxgb/common/cxgb_regs.h:#define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT) dev/cxgb/common/cxgb_regs.h:#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT) dev/cxgb/common/cxgb_regs.h:#define V_PARLAT(x) ((x) << S_PARLAT) dev/cxgb/common/cxgb_regs.h:#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT) dev/cxgb/common/cxgb_regs.h:#define V_IDINDEX(x) ((x) << S_IDINDEX) dev/cxgb/common/cxgb_regs.h:#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX) dev/cxgb/common/cxgb_regs.h:#define V_RSTMAX(x) ((x) << S_RSTMAX) dev/cxgb/common/cxgb_regs.h:#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX) dev/cxgb/common/cxgb_regs.h:#define V_ACTCNT(x) ((x) << S_ACTCNT) dev/cxgb/common/cxgb_regs.h:#define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT) dev/cxgb/common/cxgb_regs.h:#define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL) dev/cxgb/common/cxgb_regs.h:#define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL) dev/cxgb/common/cxgb_regs.h:#define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR) dev/cxgb/common/cxgb_regs.h:#define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR) dev/cxgb/common/cxgb_regs.h:#define V_WRREQSIZE(x) ((x) << S_WRREQSIZE) dev/cxgb/common/cxgb_regs.h:#define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE) dev/cxgb/common/cxgb_regs.h:#define V_CMDMODE(x) ((x) << S_CMDMODE) dev/cxgb/common/cxgb_regs.h:#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE) dev/cxgb/common/cxgb_regs.h:#define V_MBUSCMD(x) ((x) << S_MBUSCMD) dev/cxgb/common/cxgb_regs.h:#define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD) dev/cxgb/common/cxgb_regs.h:#define V_IDTCMDHI(x) ((x) << S_IDTCMDHI) dev/cxgb/common/cxgb_regs.h:#define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI) dev/cxgb/common/cxgb_regs.h:#define V_IDTCMDLO(x) ((x) << S_IDTCMDLO) dev/cxgb/common/cxgb_regs.h:#define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO) dev/cxgb/common/cxgb_regs.h:#define V_IDTCMD(x) ((x) << S_IDTCMD) dev/cxgb/common/cxgb_regs.h:#define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD) dev/cxgb/common/cxgb_regs.h:#define V_LCMDB(x) ((x) << S_LCMDB) dev/cxgb/common/cxgb_regs.h:#define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB) dev/cxgb/common/cxgb_regs.h:#define V_LCMDA(x) ((x) << S_LCMDA) dev/cxgb/common/cxgb_regs.h:#define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA) dev/cxgb/common/cxgb_regs.h:#define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI) dev/cxgb/common/cxgb_regs.h:#define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI) dev/cxgb/common/cxgb_regs.h:#define V_PO_DWR(x) ((x) << S_PO_DWR) dev/cxgb/common/cxgb_regs.h:#define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR) dev/cxgb/common/cxgb_regs.h:#define V_PO_MWR(x) ((x) << S_PO_MWR) dev/cxgb/common/cxgb_regs.h:#define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR) dev/cxgb/common/cxgb_regs.h:#define V_AO_SRCH(x) ((x) << S_AO_SRCH) dev/cxgb/common/cxgb_regs.h:#define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH) dev/cxgb/common/cxgb_regs.h:#define V_AO_LRN(x) ((x) << S_AO_LRN) dev/cxgb/common/cxgb_regs.h:#define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN) dev/cxgb/common/cxgb_regs.h:#define V_SYN_SRCH(x) ((x) << S_SYN_SRCH) dev/cxgb/common/cxgb_regs.h:#define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH) dev/cxgb/common/cxgb_regs.h:#define V_SYN_LRN(x) ((x) << S_SYN_LRN) dev/cxgb/common/cxgb_regs.h:#define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN) dev/cxgb/common/cxgb_regs.h:#define V_ACK_SRCH(x) ((x) << S_ACK_SRCH) dev/cxgb/common/cxgb_regs.h:#define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH) dev/cxgb/common/cxgb_regs.h:#define V_ACK_LRN(x) ((x) << S_ACK_LRN) dev/cxgb/common/cxgb_regs.h:#define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN) dev/cxgb/common/cxgb_regs.h:#define V_I_SRCH(x) ((x) << S_I_SRCH) dev/cxgb/common/cxgb_regs.h:#define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH) dev/cxgb/common/cxgb_regs.h:#define V_E_SRCH(x) ((x) << S_E_SRCH) dev/cxgb/common/cxgb_regs.h:#define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH) dev/cxgb/common/cxgb_regs.h:#define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE) dev/cxgb/common/cxgb_regs.h:#define V_READCMD(x) ((x) << S_READCMD) dev/cxgb/common/cxgb_regs.h:#define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD) dev/cxgb/common/cxgb_regs.h:#define V_MASKWR(x) ((x) << S_MASKWR) dev/cxgb/common/cxgb_regs.h:#define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR) dev/cxgb/common/cxgb_regs.h:#define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM) dev/cxgb/common/cxgb_regs.h:#define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) dev/cxgb/common/cxgb_regs.h:#define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH) dev/cxgb/common/cxgb_regs.h:#define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER) dev/cxgb/common/cxgb_regs.h:#define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER) dev/cxgb/common/cxgb_regs.h:#define V_PAUSETIMER(x) ((x) << S_PAUSETIMER) dev/cxgb/common/cxgb_regs.h:#define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER) dev/cxgb/common/cxgb_regs.h:#define V_CMURANGE(x) ((x) << S_CMURANGE) dev/cxgb/common/cxgb_regs.h:#define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE) dev/cxgb/common/cxgb_regs.h:#define V_GAIN(x) ((x) << S_GAIN) dev/cxgb/common/cxgb_regs.h:#define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN) dev/cxgb/common/cxgb_regs.h:#define V_BANDGAP(x) ((x) << S_BANDGAP) dev/cxgb/common/cxgb_regs.h:#define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP) dev/cxgb/common/cxgb_regs.h:#define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN) dev/cxgb/common/cxgb_regs.h:#define V_TESTPATTERN(x) ((x) << S_TESTPATTERN) dev/cxgb/common/cxgb_regs.h:#define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN) dev/cxgb/common/cxgb_regs.h:#define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH) dev/cxgb/common/cxgb_regs.h:#define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH) dev/cxgb/common/cxgb_regs.h:#define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD) dev/cxgb/common/cxgb_regs.h:#define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU) dev/cxgb/common/cxgb_regs.h:#define V_CALIMP(x) ((x) << S_CALIMP) dev/cxgb/common/cxgb_regs.h:#define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP) dev/cxgb/common/cxgb_regs.h:#define V_BISTDONE(x) ((x) << S_BISTDONE) dev/cxgb/common/cxgb_regs.h:#define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE) dev/cxgb/common/cxgb_regs.h:#define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH) dev/cxgb/common/cxgb_regs.h:#define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH) dev/cxgb/common/cxgb_regs.h:#define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE) dev/cxgb/common/cxgb_regs.h:#define V_TXPOLARITY(x) ((x) << S_TXPOLARITY) dev/cxgb/common/cxgb_regs.h:#define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY) dev/cxgb/common/cxgb_regs.h:#define V_RXPOLARITY(x) ((x) << S_RXPOLARITY) dev/cxgb/common/cxgb_regs.h:#define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY) dev/cxgb/common/cxgb_regs.h:#define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS) dev/cxgb/common/cxgb_regs.h:#define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS) dev/cxgb/common/cxgb_regs.h:#define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR) dev/cxgb/common/cxgb_regs.h:#define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR) dev/cxgb/common/cxgb_regs.h:#define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR) dev/cxgb/common/cxgb_regs.h:#define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR) dev/cxgb/common/cxgb_regs.h:#define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE) dev/cxgb/common/cxgb_regs.h:#define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE) dev/cxgb/common/cxgb_regs.h:#define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR) dev/cxgb/common/cxgb_regs.h:#define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR) dev/cxgb/common/cxgb_regs.h:#define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS) dev/cxgb/common/cxgb_regs.h:#define V_XGM_DEQ(x) ((x) << S_XGM_DEQ) dev/cxgb/common/cxgb_regs.h:#define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ) dev/cxgb/common/cxgb_regs.h:#define V_XGM_DTX(x) ((x) << S_XGM_DTX) dev/cxgb/common/cxgb_regs.h:#define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX) dev/cxgb/common/cxgb_regs.h:#define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS) dev/cxgb/common/cxgb_regs.h:#define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS) dev/cxgb/common/cxgb_regs.h:#define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR) dev/cxgb/common/cxgb_regs.h:#define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR) dev/cxgb/common/cxgb_regs.h:#define V_GMIISPEED(x) ((x) << S_GMIISPEED) dev/cxgb/common/cxgb_regs.h:#define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_BASE_HI(x) (((x) >> S_EC_BASE_HI) & M_EC_BASE_HI) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_RESPQ(x) (((x) >> S_EC_RESPQ) & M_EC_RESPQ) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_TYPE(x) (((x) >> S_EC_TYPE) & M_EC_TYPE) dev/cxgb/common/cxgb_sge_defs.h:#define G_EC_UP_TOKEN(x) (((x) >> S_EC_UP_TOKEN) & M_EC_UP_TOKEN) dev/cxgb/common/cxgb_sge_defs.h:#define G_RQ_MSI_VEC(x) (((x) >> S_RQ_MSI_VEC) & M_RQ_MSI_VEC) dev/cxgb/common/cxgb_sge_defs.h:#define G_CQ_SIZE(x) (((x) >> S_CQ_SIZE) & M_CQ_SIZE) dev/cxgb/common/cxgb_sge_defs.h:#define G_CQ_BASE_HI(x) (((x) >> S_CQ_BASE_HI) & M_CQ_BASE_HI) dev/cxgb/common/cxgb_sge_defs.h:#define G_CQ_RSPQ(x) (((x) >> S_CQ_RSPQ) & M_CQ_RSPQ) dev/cxgb/common/cxgb_sge_defs.h:#define G_CQ_CREDITS(x) (((x) >> S_CQ_CREDITS) & M_CQ_CREDITS) dev/cxgb/common/cxgb_sge_defs.h:#define G_CQ_CREDIT_THRES(x) (((x) >> S_CQ_CREDIT_THRES) & M_CQ_CREDIT_THRES) dev/cxgb/common/cxgb_sge_defs.h:#define G_FL_BASE_HI(x) (((x) >> S_FL_BASE_HI) & M_FL_BASE_HI) dev/cxgb/common/cxgb_sge_defs.h:#define G_FL_INDEX_LO(x) (((x) >> S_FL_INDEX_LO) & M_FL_INDEX_LO) dev/cxgb/common/cxgb_sge_defs.h:#define G_FL_INDEX_HI(x) (((x) >> S_FL_INDEX_HI) & M_FL_INDEX_HI) dev/cxgb/common/cxgb_sge_defs.h:#define G_FL_SIZE(x) (((x) >> S_FL_SIZE) & M_FL_SIZE) dev/cxgb/common/cxgb_sge_defs.h:#define G_FL_ENTRY_SIZE_LO(x) (((x) >> S_FL_ENTRY_SIZE_LO) & M_FL_ENTRY_SIZE_LO) dev/cxgb/common/cxgb_sge_defs.h:#define G_FL_ENTRY_SIZE_HI(x) (((x) >> S_FL_ENTRY_SIZE_HI) & M_FL_ENTRY_SIZE_HI) dev/cxgb/common/cxgb_sge_defs.h:#define G_FL_CONG_THRES(x) (((x) >> S_FL_CONG_THRES) & M_FL_CONG_THRES) dev/cxgb/common/cxgb_sge_defs.h:#define V_RSPD_INR_VEC(x) ((x) << S_RSPD_INR_VEC) dev/cxgb/common/cxgb_sge_defs.h:#define G_RSPD_INR_VEC(x) (((x) >> S_RSPD_INR_VEC) & M_RSPD_INR_VEC) dev/cxgb/common/cxgb_t3_cpl.h:#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) dev/cxgb/common/cxgb_t3_cpl.h:#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) dev/cxgb/common/cxgb_t3_cpl.h:#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) dev/cxgb/common/cxgb_t3_cpl.h:#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) dev/cxgb/common/cxgb_t3_cpl.h:#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_TOS(x) (((x) >> S_TOS) & M_TOS) dev/cxgb/common/cxgb_t3_cpl.h:#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) dev/cxgb/common/cxgb_t3_cpl.h:#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) dev/cxgb/common/cxgb_t3_cpl.h:#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) dev/cxgb/common/cxgb_t3_cpl.h:#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) dev/cxgb/common/cxgb_t3_cpl.h:#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) dev/cxgb/common/cxgb_t3_cpl.h:#define V_CPU_IDX(x) ((x) << S_CPU_IDX) dev/cxgb/common/cxgb_t3_cpl.h:#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) dev/cxgb/common/cxgb_t3_cpl.h:#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) dev/cxgb/common/cxgb_t3_cpl.h:#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) dev/cxgb/common/cxgb_t3_cpl.h:#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) dev/cxgb/common/cxgb_t3_cpl.h:#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) dev/cxgb/common/cxgb_t3_cpl.h:#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) dev/cxgb/common/cxgb_t3_cpl.h:#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) dev/cxgb/common/cxgb_t3_cpl.h:#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) dev/cxgb/common/cxgb_t3_cpl.h:#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) dev/cxgb/common/cxgb_t3_cpl.h:#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) dev/cxgb/common/cxgb_t3_cpl.h:#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) dev/cxgb/common/cxgb_t3_cpl.h:#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) dev/cxgb/common/cxgb_t3_cpl.h:#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) dev/cxgb/common/cxgb_t3_cpl.h:#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) dev/cxgb/common/cxgb_t3_cpl.h:#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) dev/cxgb/common/cxgb_t3_cpl.h:#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) dev/cxgb/common/cxgb_t3_cpl.h:#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) dev/cxgb/common/cxgb_t3_cpl.h:#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) dev/cxgb/common/cxgb_t3_cpl.h:#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) dev/cxgb/common/cxgb_t3_cpl.h:#define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) dev/cxgb/common/cxgb_t3_cpl.h:#define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) dev/cxgb/common/cxgb_t3_cpl.h:#define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) dev/cxgb/common/cxgb_t3_cpl.h:#define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) dev/cxgb/common/cxgb_t3_cpl.h:#define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) dev/cxgb/common/cxgb_t3_cpl.h:#define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) dev/cxgb/common/cxgb_t3_cpl.h:#define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) dev/cxgb/common/cxgb_t3_cpl.h:#define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) dev/cxgb/common/cxgb_t3_cpl.h:#define V_TERM_TID(x) ((x) << S_TERM_TID) dev/cxgb/common/cxgb_t3_cpl.h:#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_DIP(x) ((x) << S_TCB_DIP) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_SIP(x) ((x) << S_TCB_SIP) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_DP(x) ((x) << S_TCB_DP) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_SP(x) ((x) << S_TCB_SP) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM) dev/cxgb/common/cxgb_tcb.h:#define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM) dev/cxgb/common/cxgb_tcb.h:#define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS) dev/cxgb/common/cxgb_tcb.h:#define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD) dev/cxgb/common/cxgb_tcb.h:#define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY) dev/cxgb/common/cxgb_tcb.h:#define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD) dev/cxgb/common/cxgb_tcb.h:#define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL) dev/cxgb/common/cxgb_vsc8211.c:#define V_ACSR_ACTIPHY_TMR(x) ((x) << S_ACSR_ACTIPHY_TMR) dev/cxgb/cxgb_offload.h:#define M_GETHDR_OFLD(qset, ctrl, cpl) \ dev/cxgb/cxgb_offload.h:#define CXGB_UNIMPLEMENTED() \ dev/cxgbe/adapter.h:#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) dev/cxgbe/adapter.h:#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) dev/cxgbe/adapter.h:#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) dev/cxgbe/adapter.h:#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) dev/cxgbe/adapter.h:#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) dev/cxgbe/adapter.h:#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) dev/cxgbe/common/t4_hw.h:#define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX) dev/cxgbe/common/t4_hw.h:#define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX) dev/cxgbe/common/t4_hw.h:#define V_RSPD_QID(x) V_RSPD_LEN(x) dev/cxgbe/common/t4_hw.h:#define G_RSPD_QID(x) G_RSPD_LEN(x) dev/cxgbe/common/t4_hw.h:#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) dev/cxgbe/common/t4_hw.h:#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) dev/cxgbe/common/t4_hw.h:#define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR) dev/cxgbe/common/t4_hw.h:#define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) dev/cxgbe/common/t4_hw.h:#define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP) dev/cxgbe/common/t4_hw.h:#define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP) dev/cxgbe/common/t4_msg.h:#define V_TID_TID(x) ((x) << S_TID_TID) dev/cxgbe/common/t4_msg.h:#define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) dev/cxgbe/common/t4_msg.h:#define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) dev/cxgbe/common/t4_msg.h:#define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) dev/cxgbe/common/t4_msg.h:#define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) dev/cxgbe/common/t4_msg.h:#define V_DSCP(x) ((x) << S_DSCP) dev/cxgbe/common/t4_msg.h:#define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) dev/cxgbe/common/t4_msg.h:#define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) dev/cxgbe/common/t4_msg.h:#define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) dev/cxgbe/common/t4_msg.h:#define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) dev/cxgbe/common/t4_msg.h:#define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) dev/cxgbe/common/t4_msg.h:#define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) dev/cxgbe/common/t4_msg.h:#define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) dev/cxgbe/common/t4_msg.h:#define V_FILT_INFO(x) ((x) << S_FILT_INFO) dev/cxgbe/common/t4_msg.h:#define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) dev/cxgbe/common/t4_msg.h:#define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) dev/cxgbe/common/t4_msg.h:#define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) dev/cxgbe/common/t4_msg.h:#define V_PACE(x) ((x) << S_PACE) dev/cxgbe/common/t4_msg.h:#define G_PACE(x) (((x) >> S_PACE) & M_PACE) dev/cxgbe/common/t4_msg.h:#define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) dev/cxgbe/common/t4_msg.h:#define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) dev/cxgbe/common/t4_msg.h:#define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) dev/cxgbe/common/t4_msg.h:#define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) dev/cxgbe/common/t4_msg.h:#define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) dev/cxgbe/common/t4_msg.h:#define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) dev/cxgbe/common/t4_msg.h:#define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) dev/cxgbe/common/t4_msg.h:#define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) dev/cxgbe/common/t4_msg.h:#define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) dev/cxgbe/common/t4_msg.h:#define V_SYN_INTF(x) ((x) << S_SYN_INTF) dev/cxgbe/common/t4_msg.h:#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) dev/cxgbe/common/t4_msg.h:#define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) dev/cxgbe/common/t4_msg.h:#define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) dev/cxgbe/common/t4_msg.h:#define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) dev/cxgbe/common/t4_msg.h:#define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) dev/cxgbe/common/t4_msg.h:#define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) dev/cxgbe/common/t4_msg.h:#define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) dev/cxgbe/common/t4_msg.h:#define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) dev/cxgbe/common/t4_msg.h:#define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) dev/cxgbe/common/t4_msg.h:#define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) dev/cxgbe/common/t4_msg.h:#define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) dev/cxgbe/common/t4_msg.h:#define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) dev/cxgbe/common/t4_msg.h:#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) dev/cxgbe/common/t4_msg.h:#define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_OP(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_FIRST(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_LAST(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_HDRCRC(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_PLDCRC(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_SCSI(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ dev/cxgbe/common/t4_msg.h:#define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) dev/cxgbe/common/t4_msg.h:#define G_FCOE_FCHDR_RCTL(x) \ dev/cxgbe/common/t4_msg.h:#define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) dev/cxgbe/common/t4_msg.h:#define G_FCOE_FCHDR_FCTL(x) \ dev/cxgbe/common/t4_msg.h:#define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) dev/cxgbe/common/t4_msg.h:#define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) dev/cxgbe/common/t4_msg.h:#define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) dev/cxgbe/common/t4_msg.h:#define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) dev/cxgbe/common/t4_msg.h:#define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) dev/cxgbe/common/t4_msg.h:#define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) dev/cxgbe/common/t4_msg.h:#define V_RX_CHAN(x) ((x) << S_RX_CHAN) dev/cxgbe/common/t4_msg.h:#define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) dev/cxgbe/common/t4_msg.h:#define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) dev/cxgbe/common/t4_msg.h:#define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) dev/cxgbe/common/t4_msg.h:#define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) dev/cxgbe/common/t4_msg.h:#define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) dev/cxgbe/common/t4_msg.h:#define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) dev/cxgbe/common/t4_msg.h:#define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) dev/cxgbe/common/t4_msg.h:#define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) dev/cxgbe/common/t4_msg.h:#define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) dev/cxgbe/common/t4_msg.h:#define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) dev/cxgbe/common/t4_msg.h:#define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) dev/cxgbe/common/t4_msg.h:#define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) dev/cxgbe/common/t4_msg.h:#define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) dev/cxgbe/common/t4_msg.h:#define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) dev/cxgbe/common/t4_msg.h:#define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) dev/cxgbe/common/t4_msg.h:#define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) dev/cxgbe/common/t4_msg.h:#define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) dev/cxgbe/common/t4_msg.h:#define V_SMTW_VF(x) ((x) << S_SMTW_VF) dev/cxgbe/common/t4_msg.h:#define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) dev/cxgbe/common/t4_msg.h:#define V_SMTW_PF(x) ((x) << S_SMTW_PF) dev/cxgbe/common/t4_msg.h:#define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) dev/cxgbe/common/t4_msg.h:#define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) dev/cxgbe/common/t4_msg.h:#define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) dev/cxgbe/common/t4_msg.h:#define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) dev/cxgbe/common/t4_msg.h:#define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) dev/cxgbe/common/t4_msg.h:#define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) dev/cxgbe/common/t4_msg.h:#define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) dev/cxgbe/common/t4_msg.h:#define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) dev/cxgbe/common/t4_msg.h:#define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) dev/cxgbe/common/t4_msg.h:#define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) dev/cxgbe/common/t4_msg.h:#define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) dev/cxgbe/common/t4_msg.h:#define V_LE_CHAN(x) ((x) << S_LE_CHAN) dev/cxgbe/common/t4_msg.h:#define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) dev/cxgbe/common/t4_msg.h:#define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) dev/cxgbe/common/t4_msg.h:#define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) dev/cxgbe/common/t4_msg.h:#define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) dev/cxgbe/common/t4_msg.h:#define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) dev/cxgbe/common/t4_msg.h:#define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) dev/cxgbe/common/t4_msg.h:#define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) dev/cxgbe/common/t4_msg.h:#define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) dev/cxgbe/common/t4_msg.h:#define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) dev/cxgbe/common/t4_msg.h:#define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) dev/cxgbe/common/t4_msg.h:#define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) dev/cxgbe/common/t4_msg.h:#define V_AUTOEQU(x) ((x) << S_AUTOEQU) dev/cxgbe/common/t4_msg.h:#define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) dev/cxgbe/common/t4_msg.h:#define V_EGR_QID(x) ((x) << S_EGR_QID) dev/cxgbe/common/t4_msg.h:#define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) dev/cxgbe/common/t4_msg.h:#define G_ULP_TXPKT_DATAMODIFY(x) \ dev/cxgbe/common/t4_msg.h:#define G_ULP_TXPKT_CHANNELID(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_OPCODE(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_FIRST(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_LAST(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_FLOW(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_MSS(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TNL_LSO_SIZE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_MPS_PKT_OP(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_MPS_PKT_TYPE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_SFO_OPCODE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) dev/cxgbe/common/t4_msg.h:#define G_CPL_TLS_DATA_OPCODE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) dev/cxgbe/common/t4_msg.h:#define G_CPL_TLS_DATA_TID(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) dev/cxgbe/common/t4_msg.h:#define G_CPL_TLS_DATA_LENGTH(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_TLS_CMP_OPCODE(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_TLS_CMP_TID(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_TLS_CMP_LENGTH(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_SEQ_NO_CTRL(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_STATUS_PRESENT(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_PROTO_VERSION(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_ENC_DEC_CTRL(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_CIPH_MODE(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_AUTH_MODE(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_HMAC_CTRL(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_IV_SIZE(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_NUM_IVS(x) \ dev/cxgbe/common/t4_msg.h:#define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) dev/cxgbe/common/t4_msg.h:#define G_SCMD_ENB_DBGID(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_IV_GEN_CTRL(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) dev/cxgbe/common/t4_msg.h:#define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) dev/cxgbe/common/t4_msg.h:#define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) dev/cxgbe/common/t4_msg.h:#define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) dev/cxgbe/common/t4_msg.h:#define G_SCMD_KEY_CTX_INLINE(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_TLS_FRAG_ENABLE(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_MAC_ONLY(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_AADIVDROP(x) \ dev/cxgbe/common/t4_msg.h:#define G_SCMD_HDR_LEN(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_OPCODE(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_RXCHID(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_CPLLEN(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_AADSTART(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_AADSTOP(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_DCAID(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_OPCODE(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_RXCHID(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_FWMSG(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ dev/cxgbe/common/t4_msg.h:#define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_CPLLEN(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_LCB(x) \ dev/cxgbe/common/t4_msg.h:#define G_CPL_TX_TLS_ACK_PHASH(x) \ dev/cxgbe/common/t4_regs.h:#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr)) dev/cxgbe/common/t4_regs.h:#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) dev/cxgbe/common/t4_regs.h:#define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16) dev/cxgbe/common/t4_regs.h:#define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) dev/cxgbe/common/t4_regs.h:#define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16) dev/cxgbe/common/t4_regs.h:#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288) dev/cxgbe/common/t4_regs.h:#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) dev/cxgbe/common/t4_regs.h:#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) dev/cxgbe/common/t4_regs.h:#define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) dev/cxgbe/common/t4_regs.h:#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_REQUEST_TRACE_MAC_DA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_L + (idx) * 32) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_REQUEST_TRACE_MAC_DA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_DA_H + (idx) * 32) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_REQUEST_TRACE_MAC_SA_L(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_L + (idx) * 32) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_REQUEST_TRACE_MAC_SA_H(idx) (A_MPS_CLS_REQUEST_TRACE_MAC_SA_H + (idx) * 32) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_REQUEST_TRACE_PORT_VLAN(idx) (A_MPS_CLS_REQUEST_TRACE_PORT_VLAN + (idx) * 32) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_REQUEST_TRACE_ENCAP(idx) (A_MPS_CLS_REQUEST_TRACE_ENCAP + (idx) * 32) dev/cxgbe/common/t4_regs.h:#define MPS_CLS_RESULT_TRACE(idx) (A_MPS_CLS_RESULT_TRACE + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define MPS_RX_HASH_LKP_TABLE(idx) (A_MPS_RX_HASH_LKP_TABLE + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define LE_DB_DBG_MATCH_DATA_MASK(idx) (A_LE_DB_DBG_MATCH_DATA_MASK + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define LE_DB_DBG_MATCH_DATA(idx) (A_LE_DB_DBG_MATCH_DATA + (idx) * 4) dev/cxgbe/common/t4_regs.h:#define G_QID(x) (((x) >> S_QID) & M_QID) dev/cxgbe/common/t4_regs.h:#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX) dev/cxgbe/common/t4_regs.h:#define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID) dev/cxgbe/common/t4_regs.h:#define V_TIMERREG(x) ((x) << S_TIMERREG) dev/cxgbe/common/t4_regs.h:#define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG) dev/cxgbe/common/t4_regs.h:#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC) dev/cxgbe/common/t4_regs.h:#define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL) dev/cxgbe/common/t4_regs.h:#define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL) dev/cxgbe/common/t4_regs.h:#define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN) dev/cxgbe/common/t4_regs.h:#define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN) dev/cxgbe/common/t4_regs.h:#define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE) dev/cxgbe/common/t4_regs.h:#define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE) dev/cxgbe/common/t4_regs.h:#define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY) dev/cxgbe/common/t4_regs.h:#define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY) dev/cxgbe/common/t4_regs.h:#define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY) dev/cxgbe/common/t4_regs.h:#define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY) dev/cxgbe/common/t4_regs.h:#define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN) dev/cxgbe/common/t4_regs.h:#define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN) dev/cxgbe/common/t4_regs.h:#define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX) dev/cxgbe/common/t4_regs.h:#define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX) dev/cxgbe/common/t4_regs.h:#define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN) dev/cxgbe/common/t4_regs.h:#define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN) dev/cxgbe/common/t4_regs.h:#define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX) dev/cxgbe/common/t4_regs.h:#define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX) dev/cxgbe/common/t4_regs.h:#define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE) dev/cxgbe/common/t4_regs.h:#define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_MEMSEL(x) ((x) << S_MEMSEL) dev/cxgbe/common/t4_regs.h:#define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL) dev/cxgbe/common/t4_regs.h:#define V_SIZE(x) ((x) << S_SIZE) dev/cxgbe/common/t4_regs.h:#define G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE) dev/cxgbe/common/t4_regs.h:#define V_OPMODE(x) ((x) << S_OPMODE) dev/cxgbe/common/t4_regs.h:#define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE) dev/cxgbe/common/t4_regs.h:#define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT) dev/cxgbe/common/t4_regs.h:#define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT) dev/cxgbe/common/t4_regs.h:#define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT) dev/cxgbe/common/t4_regs.h:#define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ) dev/cxgbe/common/t4_regs.h:#define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ) dev/cxgbe/common/t4_regs.h:#define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH) dev/cxgbe/common/t4_regs.h:#define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH) dev/cxgbe/common/t4_regs.h:#define V_CREDITCNT(x) ((x) << S_CREDITCNT) dev/cxgbe/common/t4_regs.h:#define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT) dev/cxgbe/common/t4_regs.h:#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING) dev/cxgbe/common/t4_regs.h:#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING) dev/cxgbe/common/t4_regs.h:#define V_NULLPTR(x) ((x) << S_NULLPTR) dev/cxgbe/common/t4_regs.h:#define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR) dev/cxgbe/common/t4_regs.h:#define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD) dev/cxgbe/common/t4_regs.h:#define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD) dev/cxgbe/common/t4_regs.h:#define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD) dev/cxgbe/common/t4_regs.h:#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING) dev/cxgbe/common/t4_regs.h:#define V_TSOP(x) ((x) << S_TSOP) dev/cxgbe/common/t4_regs.h:#define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP) dev/cxgbe/common/t4_regs.h:#define V_TSVAL(x) ((x) << S_TSVAL) dev/cxgbe/common/t4_regs.h:#define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL) dev/cxgbe/common/t4_regs.h:#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) dev/cxgbe/common/t4_regs.h:#define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH) dev/cxgbe/common/t4_regs.h:#define V_HP_COUNT(x) ((x) << S_HP_COUNT) dev/cxgbe/common/t4_regs.h:#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) dev/cxgbe/common/t4_regs.h:#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) dev/cxgbe/common/t4_regs.h:#define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH) dev/cxgbe/common/t4_regs.h:#define V_LP_COUNT(x) ((x) << S_LP_COUNT) dev/cxgbe/common/t4_regs.h:#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) dev/cxgbe/common/t4_regs.h:#define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT) dev/cxgbe/common/t4_regs.h:#define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT) dev/cxgbe/common/t4_regs.h:#define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL) dev/cxgbe/common/t4_regs.h:#define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL) dev/cxgbe/common/t4_regs.h:#define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT) dev/cxgbe/common/t4_regs.h:#define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT) dev/cxgbe/common/t4_regs.h:#define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG) dev/cxgbe/common/t4_regs.h:#define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG) dev/cxgbe/common/t4_regs.h:#define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT) dev/cxgbe/common/t4_regs.h:#define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT) dev/cxgbe/common/t4_regs.h:#define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME) dev/cxgbe/common/t4_regs.h:#define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME) dev/cxgbe/common/t4_regs.h:#define V_LL_EMPTY(x) ((x) << S_LL_EMPTY) dev/cxgbe/common/t4_regs.h:#define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY) dev/cxgbe/common/t4_regs.h:#define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH) dev/cxgbe/common/t4_regs.h:#define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH) dev/cxgbe/common/t4_regs.h:#define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH) dev/cxgbe/common/t4_regs.h:#define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH) dev/cxgbe/common/t4_regs.h:#define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK) dev/cxgbe/common/t4_regs.h:#define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK) dev/cxgbe/common/t4_regs.h:#define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH) dev/cxgbe/common/t4_regs.h:#define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH) dev/cxgbe/common/t4_regs.h:#define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH) dev/cxgbe/common/t4_regs.h:#define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH) dev/cxgbe/common/t4_regs.h:#define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE) dev/cxgbe/common/t4_regs.h:#define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE) dev/cxgbe/common/t4_regs.h:#define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE) dev/cxgbe/common/t4_regs.h:#define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE) dev/cxgbe/common/t4_regs.h:#define V_STATSOURCE(x) ((x) << S_STATSOURCE) dev/cxgbe/common/t4_regs.h:#define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE) dev/cxgbe/common/t4_regs.h:#define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR) dev/cxgbe/common/t4_regs.h:#define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR) dev/cxgbe/common/t4_regs.h:#define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR) dev/cxgbe/common/t4_regs.h:#define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR) dev/cxgbe/common/t4_regs.h:#define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP) dev/cxgbe/common/t4_regs.h:#define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP) dev/cxgbe/common/t4_regs.h:#define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT) dev/cxgbe/common/t4_regs.h:#define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT) dev/cxgbe/common/t4_regs.h:#define V_ERROR_QID(x) ((x) << S_ERROR_QID) dev/cxgbe/common/t4_regs.h:#define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER) dev/cxgbe/common/t4_regs.h:#define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER) dev/cxgbe/common/t4_regs.h:#define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT) dev/cxgbe/common/t4_regs.h:#define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT) dev/cxgbe/common/t4_regs.h:#define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL) dev/cxgbe/common/t4_regs.h:#define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL) dev/cxgbe/common/t4_regs.h:#define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH) dev/cxgbe/common/t4_regs.h:#define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH) dev/cxgbe/common/t4_regs.h:#define V_FL_COUNT(x) ((x) << S_FL_COUNT) dev/cxgbe/common/t4_regs.h:#define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT) dev/cxgbe/common/t4_regs.h:#define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL) dev/cxgbe/common/t4_regs.h:#define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL) dev/cxgbe/common/t4_regs.h:#define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY) dev/cxgbe/common/t4_regs.h:#define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY) dev/cxgbe/common/t4_regs.h:#define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY) dev/cxgbe/common/t4_regs.h:#define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY) dev/cxgbe/common/t4_regs.h:#define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL) dev/cxgbe/common/t4_regs.h:#define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL) dev/cxgbe/common/t4_regs.h:#define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP) dev/cxgbe/common/t4_regs.h:#define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP) dev/cxgbe/common/t4_regs.h:#define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP) dev/cxgbe/common/t4_regs.h:#define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP) dev/cxgbe/common/t4_regs.h:#define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL) dev/cxgbe/common/t4_regs.h:#define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL) dev/cxgbe/common/t4_regs.h:#define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP) dev/cxgbe/common/t4_regs.h:#define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP) dev/cxgbe/common/t4_regs.h:#define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP) dev/cxgbe/common/t4_regs.h:#define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP) dev/cxgbe/common/t4_regs.h:#define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE) dev/cxgbe/common/t4_regs.h:#define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW) dev/cxgbe/common/t4_regs.h:#define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW) dev/cxgbe/common/t4_regs.h:#define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW) dev/cxgbe/common/t4_regs.h:#define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW) dev/cxgbe/common/t4_regs.h:#define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW) dev/cxgbe/common/t4_regs.h:#define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW) dev/cxgbe/common/t4_regs.h:#define V_CTXTOP(x) ((x) << S_CTXTOP) dev/cxgbe/common/t4_regs.h:#define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP) dev/cxgbe/common/t4_regs.h:#define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE) dev/cxgbe/common/t4_regs.h:#define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID) dev/cxgbe/common/t4_regs.h:#define V_QIDX(x) ((x) << S_QIDX) dev/cxgbe/common/t4_regs.h:#define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX) dev/cxgbe/common/t4_regs.h:#define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK) dev/cxgbe/common/t4_regs.h:#define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK) dev/cxgbe/common/t4_regs.h:#define V_FLMTHRESH(x) ((x) << S_FLMTHRESH) dev/cxgbe/common/t4_regs.h:#define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH) dev/cxgbe/common/t4_regs.h:#define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG) dev/cxgbe/common/t4_regs.h:#define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG) dev/cxgbe/common/t4_regs.h:#define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG) dev/cxgbe/common/t4_regs.h:#define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG) dev/cxgbe/common/t4_regs.h:#define V_ST_CONG(x) ((x) << S_ST_CONG) dev/cxgbe/common/t4_regs.h:#define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG) dev/cxgbe/common/t4_regs.h:#define V_LAST_QID(x) ((x) << S_LAST_QID) dev/cxgbe/common/t4_regs.h:#define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID) dev/cxgbe/common/t4_regs.h:#define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID) dev/cxgbe/common/t4_regs.h:#define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID) dev/cxgbe/common/t4_regs.h:#define V_CIM_WM(x) ((x) << S_CIM_WM) dev/cxgbe/common/t4_regs.h:#define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT) dev/cxgbe/common/t4_regs.h:#define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT) dev/cxgbe/common/t4_regs.h:#define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT) dev/cxgbe/common/t4_regs.h:#define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT) dev/cxgbe/common/t4_regs.h:#define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT) dev/cxgbe/common/t4_regs.h:#define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT) dev/cxgbe/common/t4_regs.h:#define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT) dev/cxgbe/common/t4_regs.h:#define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID) dev/cxgbe/common/t4_regs.h:#define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN) dev/cxgbe/common/t4_regs.h:#define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN) dev/cxgbe/common/t4_regs.h:#define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL) dev/cxgbe/common/t4_regs.h:#define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL) dev/cxgbe/common/t4_regs.h:#define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP) dev/cxgbe/common/t4_regs.h:#define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP) dev/cxgbe/common/t4_regs.h:#define V_THREAD_QID(x) ((x) << S_THREAD_QID) dev/cxgbe/common/t4_regs.h:#define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID) dev/cxgbe/common/t4_regs.h:#define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE) dev/cxgbe/common/t4_regs.h:#define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE) dev/cxgbe/common/t4_regs.h:#define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE) dev/cxgbe/common/t4_regs.h:#define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE) dev/cxgbe/common/t4_regs.h:#define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE) dev/cxgbe/common/t4_regs.h:#define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE) dev/cxgbe/common/t4_regs.h:#define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET) dev/cxgbe/common/t4_regs.h:#define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET) dev/cxgbe/common/t4_regs.h:#define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE) dev/cxgbe/common/t4_regs.h:#define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE) dev/cxgbe/common/t4_regs.h:#define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE) dev/cxgbe/common/t4_regs.h:#define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET) dev/cxgbe/common/t4_regs.h:#define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET) dev/cxgbe/common/t4_regs.h:#define V_AIVEC(x) ((x) << S_AIVEC) dev/cxgbe/common/t4_regs.h:#define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC) dev/cxgbe/common/t4_regs.h:#define V_INTXTYPE(x) ((x) << S_INTXTYPE) dev/cxgbe/common/t4_regs.h:#define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE) dev/cxgbe/common/t4_regs.h:#define V_MSGTYPE(x) ((x) << S_MSGTYPE) dev/cxgbe/common/t4_regs.h:#define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE) dev/cxgbe/common/t4_regs.h:#define V_MEMSEL_PCIE(x) ((x) << S_MEMSEL_PCIE) dev/cxgbe/common/t4_regs.h:#define G_MEMSEL_PCIE(x) (((x) >> S_MEMSEL_PCIE) & M_MEMSEL_PCIE) dev/cxgbe/common/t4_regs.h:#define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX) dev/cxgbe/common/t4_regs.h:#define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX) dev/cxgbe/common/t4_regs.h:#define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX) dev/cxgbe/common/t4_regs.h:#define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX) dev/cxgbe/common/t4_regs.h:#define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ) dev/cxgbe/common/t4_regs.h:#define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ) dev/cxgbe/common/t4_regs.h:#define V_AI_TCVAL(x) ((x) << S_AI_TCVAL) dev/cxgbe/common/t4_regs.h:#define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL) dev/cxgbe/common/t4_regs.h:#define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS) dev/cxgbe/common/t4_regs.h:#define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS) dev/cxgbe/common/t4_regs.h:#define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ) dev/cxgbe/common/t4_regs.h:#define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ) dev/cxgbe/common/t4_regs.h:#define V_VPDTIMER(x) ((x) << S_VPDTIMER) dev/cxgbe/common/t4_regs.h:#define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER) dev/cxgbe/common/t4_regs.h:#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG) dev/cxgbe/common/t4_regs.h:#define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG) dev/cxgbe/common/t4_regs.h:#define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE) dev/cxgbe/common/t4_regs.h:#define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE) dev/cxgbe/common/t4_regs.h:#define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE) dev/cxgbe/common/t4_regs.h:#define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE) dev/cxgbe/common/t4_regs.h:#define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define V_MAXTAG(x) ((x) << S_MAXTAG) dev/cxgbe/common/t4_regs.h:#define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG) dev/cxgbe/common/t4_regs.h:#define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE) dev/cxgbe/common/t4_regs.h:#define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE) dev/cxgbe/common/t4_regs.h:#define V_STATEREQ(x) ((x) << S_STATEREQ) dev/cxgbe/common/t4_regs.h:#define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ) dev/cxgbe/common/t4_regs.h:#define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT) dev/cxgbe/common/t4_regs.h:#define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT) dev/cxgbe/common/t4_regs.h:#define V_STATEAREQ(x) ((x) << S_STATEAREQ) dev/cxgbe/common/t4_regs.h:#define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ) dev/cxgbe/common/t4_regs.h:#define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT) dev/cxgbe/common/t4_regs.h:#define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT) dev/cxgbe/common/t4_regs.h:#define V_GENPME(x) ((x) << S_GENPME) dev/cxgbe/common/t4_regs.h:#define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME) dev/cxgbe/common/t4_regs.h:#define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT) dev/cxgbe/common/t4_regs.h:#define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT) dev/cxgbe/common/t4_regs.h:#define V_PERSTTIMER(x) ((x) << S_PERSTTIMER) dev/cxgbe/common/t4_regs.h:#define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER) dev/cxgbe/common/t4_regs.h:#define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define V_MAXREQCNT(x) ((x) << S_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define V_RSPCNT(x) ((x) << S_RSPCNT) dev/cxgbe/common/t4_regs.h:#define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT) dev/cxgbe/common/t4_regs.h:#define V_REQCNT(x) ((x) << S_REQCNT) dev/cxgbe/common/t4_regs.h:#define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT) dev/cxgbe/common/t4_regs.h:#define V_IPLTSSM(x) ((x) << S_IPLTSSM) dev/cxgbe/common/t4_regs.h:#define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM) dev/cxgbe/common/t4_regs.h:#define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN) dev/cxgbe/common/t4_regs.h:#define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN) dev/cxgbe/common/t4_regs.h:#define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT) dev/cxgbe/common/t4_regs.h:#define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT) dev/cxgbe/common/t4_regs.h:#define V_CPLCONFIG(x) ((x) << S_CPLCONFIG) dev/cxgbe/common/t4_regs.h:#define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG) dev/cxgbe/common/t4_regs.h:#define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT) dev/cxgbe/common/t4_regs.h:#define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT) dev/cxgbe/common/t4_regs.h:#define V_BUS(x) ((x) << S_BUS) dev/cxgbe/common/t4_regs.h:#define G_BUS(x) (((x) >> S_BUS) & M_BUS) dev/cxgbe/common/t4_regs.h:#define V_DEVICE(x) ((x) << S_DEVICE) dev/cxgbe/common/t4_regs.h:#define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE) dev/cxgbe/common/t4_regs.h:#define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION) dev/cxgbe/common/t4_regs.h:#define V_EXTREGISTER(x) ((x) << S_EXTREGISTER) dev/cxgbe/common/t4_regs.h:#define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER) dev/cxgbe/common/t4_regs.h:#define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER) dev/cxgbe/common/t4_regs.h:#define V_WRBE(x) ((x) << S_WRBE) dev/cxgbe/common/t4_regs.h:#define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE) dev/cxgbe/common/t4_regs.h:#define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF) dev/cxgbe/common/t4_regs.h:#define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF) dev/cxgbe/common/t4_regs.h:#define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF) dev/cxgbe/common/t4_regs.h:#define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF) dev/cxgbe/common/t4_regs.h:#define V_PCIEOFST(x) ((x) << S_PCIEOFST) dev/cxgbe/common/t4_regs.h:#define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) dev/cxgbe/common/t4_regs.h:#define G_BIR(x) (((x) >> S_BIR) & M_BIR) dev/cxgbe/common/t4_regs.h:#define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW) dev/cxgbe/common/t4_regs.h:#define V_MEMOFST(x) ((x) << S_MEMOFST) dev/cxgbe/common/t4_regs.h:#define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST) dev/cxgbe/common/t4_regs.h:#define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST) dev/cxgbe/common/t4_regs.h:#define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST) dev/cxgbe/common/t4_regs.h:#define V_MBOXBIR(x) ((x) << S_MBOXBIR) dev/cxgbe/common/t4_regs.h:#define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR) dev/cxgbe/common/t4_regs.h:#define V_MBOXWIN(x) ((x) << S_MBOXWIN) dev/cxgbe/common/t4_regs.h:#define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN) dev/cxgbe/common/t4_regs.h:#define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT) dev/cxgbe/common/t4_regs.h:#define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE) dev/cxgbe/common/t4_regs.h:#define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE) dev/cxgbe/common/t4_regs.h:#define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE) dev/cxgbe/common/t4_regs.h:#define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE) dev/cxgbe/common/t4_regs.h:#define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG) dev/cxgbe/common/t4_regs.h:#define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG) dev/cxgbe/common/t4_regs.h:#define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE) dev/cxgbe/common/t4_regs.h:#define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE) dev/cxgbe/common/t4_regs.h:#define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME) dev/cxgbe/common/t4_regs.h:#define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME) dev/cxgbe/common/t4_regs.h:#define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE) dev/cxgbe/common/t4_regs.h:#define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE) dev/cxgbe/common/t4_regs.h:#define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE) dev/cxgbe/common/t4_regs.h:#define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE) dev/cxgbe/common/t4_regs.h:#define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT) dev/cxgbe/common/t4_regs.h:#define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT) dev/cxgbe/common/t4_regs.h:#define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT) dev/cxgbe/common/t4_regs.h:#define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT) dev/cxgbe/common/t4_regs.h:#define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT) dev/cxgbe/common/t4_regs.h:#define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT) dev/cxgbe/common/t4_regs.h:#define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT) dev/cxgbe/common/t4_regs.h:#define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT) dev/cxgbe/common/t4_regs.h:#define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE) dev/cxgbe/common/t4_regs.h:#define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE) dev/cxgbe/common/t4_regs.h:#define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE) dev/cxgbe/common/t4_regs.h:#define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE) dev/cxgbe/common/t4_regs.h:#define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE) dev/cxgbe/common/t4_regs.h:#define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE) dev/cxgbe/common/t4_regs.h:#define V_PL_CONTROL(x) ((x) << S_PL_CONTROL) dev/cxgbe/common/t4_regs.h:#define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL) dev/cxgbe/common/t4_regs.h:#define V_POINTER(x) ((x) << S_POINTER) dev/cxgbe/common/t4_regs.h:#define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER) dev/cxgbe/common/t4_regs.h:#define V_SELECT(x) ((x) << S_SELECT) dev/cxgbe/common/t4_regs.h:#define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT) dev/cxgbe/common/t4_regs.h:#define V_PBAOFST(x) ((x) << S_PBAOFST) dev/cxgbe/common/t4_regs.h:#define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST) dev/cxgbe/common/t4_regs.h:#define V_TABOFST(x) ((x) << S_TABOFST) dev/cxgbe/common/t4_regs.h:#define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST) dev/cxgbe/common/t4_regs.h:#define V_VECNUM(x) ((x) << S_VECNUM) dev/cxgbe/common/t4_regs.h:#define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM) dev/cxgbe/common/t4_regs.h:#define V_VECBASE(x) ((x) << S_VECBASE) dev/cxgbe/common/t4_regs.h:#define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE) dev/cxgbe/common/t4_regs.h:#define V_PNDTXNS(x) ((x) << S_PNDTXNS) dev/cxgbe/common/t4_regs.h:#define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS) dev/cxgbe/common/t4_regs.h:#define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM) dev/cxgbe/common/t4_regs.h:#define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT) dev/cxgbe/common/t4_regs.h:#define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT) dev/cxgbe/common/t4_regs.h:#define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT) dev/cxgbe/common/t4_regs.h:#define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT) dev/cxgbe/common/t4_regs.h:#define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID) dev/cxgbe/common/t4_regs.h:#define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID) dev/cxgbe/common/t4_regs.h:#define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC) dev/cxgbe/common/t4_regs.h:#define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC) dev/cxgbe/common/t4_regs.h:#define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF) dev/cxgbe/common/t4_regs.h:#define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF) dev/cxgbe/common/t4_regs.h:#define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF) dev/cxgbe/common/t4_regs.h:#define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF) dev/cxgbe/common/t4_regs.h:#define V_TC(x) ((x) << S_TC) dev/cxgbe/common/t4_regs.h:#define G_TC(x) (((x) >> S_TC) & M_TC) dev/cxgbe/common/t4_regs.h:#define V_FUNC(x) ((x) << S_FUNC) dev/cxgbe/common/t4_regs.h:#define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC) dev/cxgbe/common/t4_regs.h:#define V_COOKIEB(x) ((x) << S_COOKIEB) dev/cxgbe/common/t4_regs.h:#define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB) dev/cxgbe/common/t4_regs.h:#define V_COOKIEA(x) ((x) << S_COOKIEA) dev/cxgbe/common/t4_regs.h:#define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA) dev/cxgbe/common/t4_regs.h:#define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE) dev/cxgbe/common/t4_regs.h:#define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE) dev/cxgbe/common/t4_regs.h:#define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE) dev/cxgbe/common/t4_regs.h:#define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE) dev/cxgbe/common/t4_regs.h:#define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE) dev/cxgbe/common/t4_regs.h:#define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE) dev/cxgbe/common/t4_regs.h:#define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE) dev/cxgbe/common/t4_regs.h:#define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE) dev/cxgbe/common/t4_regs.h:#define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE) dev/cxgbe/common/t4_regs.h:#define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE) dev/cxgbe/common/t4_regs.h:#define V_RCVDVDMRXCOOKIE(x) ((x) << S_RCVDVDMRXCOOKIE) dev/cxgbe/common/t4_regs.h:#define G_RCVDVDMRXCOOKIE(x) (((x) >> S_RCVDVDMRXCOOKIE) & M_RCVDVDMRXCOOKIE) dev/cxgbe/common/t4_regs.h:#define V_RCVDVDMTXCOOKIE(x) ((x) << S_RCVDVDMTXCOOKIE) dev/cxgbe/common/t4_regs.h:#define G_RCVDVDMTXCOOKIE(x) (((x) >> S_RCVDVDMTXCOOKIE) & M_RCVDVDMTXCOOKIE) dev/cxgbe/common/t4_regs.h:#define V_PM_STATUS(x) ((x) << S_PM_STATUS) dev/cxgbe/common/t4_regs.h:#define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS) dev/cxgbe/common/t4_regs.h:#define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE) dev/cxgbe/common/t4_regs.h:#define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE) dev/cxgbe/common/t4_regs.h:#define V_STATECFGINITF(x) ((x) << S_STATECFGINITF) dev/cxgbe/common/t4_regs.h:#define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF) dev/cxgbe/common/t4_regs.h:#define V_STATECFGINIT(x) ((x) << S_STATECFGINIT) dev/cxgbe/common/t4_regs.h:#define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT) dev/cxgbe/common/t4_regs.h:#define V_STATECFGINITF_PCIE(x) ((x) << S_STATECFGINITF_PCIE) dev/cxgbe/common/t4_regs.h:#define G_STATECFGINITF_PCIE(x) (((x) >> S_STATECFGINITF_PCIE) & M_STATECFGINITF_PCIE) dev/cxgbe/common/t4_regs.h:#define V_STATECFGINIT_PCIE(x) ((x) << S_STATECFGINIT_PCIE) dev/cxgbe/common/t4_regs.h:#define G_STATECFGINIT_PCIE(x) (((x) >> S_STATECFGINIT_PCIE) & M_STATECFGINIT_PCIE) dev/cxgbe/common/t4_regs.h:#define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT) dev/cxgbe/common/t4_regs.h:#define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT) dev/cxgbe/common/t4_regs.h:#define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT) dev/cxgbe/common/t4_regs.h:#define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT) dev/cxgbe/common/t4_regs.h:#define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT) dev/cxgbe/common/t4_regs.h:#define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT) dev/cxgbe/common/t4_regs.h:#define V_LINK_STATE(x) ((x) << S_LINK_STATE) dev/cxgbe/common/t4_regs.h:#define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE) dev/cxgbe/common/t4_regs.h:#define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER) dev/cxgbe/common/t4_regs.h:#define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER) dev/cxgbe/common/t4_regs.h:#define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS) dev/cxgbe/common/t4_regs.h:#define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS) dev/cxgbe/common/t4_regs.h:#define V_N_FTS(x) ((x) << S_N_FTS) dev/cxgbe/common/t4_regs.h:#define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS) dev/cxgbe/common/t4_regs.h:#define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY) dev/cxgbe/common/t4_regs.h:#define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY) dev/cxgbe/common/t4_regs.h:#define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE) dev/cxgbe/common/t4_regs.h:#define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE) dev/cxgbe/common/t4_regs.h:#define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW) dev/cxgbe/common/t4_regs.h:#define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW) dev/cxgbe/common/t4_regs.h:#define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER) dev/cxgbe/common/t4_regs.h:#define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER) dev/cxgbe/common/t4_regs.h:#define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER) dev/cxgbe/common/t4_regs.h:#define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER) dev/cxgbe/common/t4_regs.h:#define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER) dev/cxgbe/common/t4_regs.h:#define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER) dev/cxgbe/common/t4_regs.h:#define V_MAXFUNC(x) ((x) << S_MAXFUNC) dev/cxgbe/common/t4_regs.h:#define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC) dev/cxgbe/common/t4_regs.h:#define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER) dev/cxgbe/common/t4_regs.h:#define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER) dev/cxgbe/common/t4_regs.h:#define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL) dev/cxgbe/common/t4_regs.h:#define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL) dev/cxgbe/common/t4_regs.h:#define V_TXPH_FC(x) ((x) << S_TXPH_FC) dev/cxgbe/common/t4_regs.h:#define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC) dev/cxgbe/common/t4_regs.h:#define V_TXPD_FC(x) ((x) << S_TXPD_FC) dev/cxgbe/common/t4_regs.h:#define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC) dev/cxgbe/common/t4_regs.h:#define V_TXNPH_FC(x) ((x) << S_TXNPH_FC) dev/cxgbe/common/t4_regs.h:#define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC) dev/cxgbe/common/t4_regs.h:#define V_TXNPD_FC(x) ((x) << S_TXNPD_FC) dev/cxgbe/common/t4_regs.h:#define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC) dev/cxgbe/common/t4_regs.h:#define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC) dev/cxgbe/common/t4_regs.h:#define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC) dev/cxgbe/common/t4_regs.h:#define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC) dev/cxgbe/common/t4_regs.h:#define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC) dev/cxgbe/common/t4_regs.h:#define V_NUM_LANES(x) ((x) << S_NUM_LANES) dev/cxgbe/common/t4_regs.h:#define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES) dev/cxgbe/common/t4_regs.h:#define V_FULL_SWING(x) ((x) << S_FULL_SWING) dev/cxgbe/common/t4_regs.h:#define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING) dev/cxgbe/common/t4_regs.h:#define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY) dev/cxgbe/common/t4_regs.h:#define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY) dev/cxgbe/common/t4_regs.h:#define V_POSTCURSOR(x) ((x) << S_POSTCURSOR) dev/cxgbe/common/t4_regs.h:#define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR) dev/cxgbe/common/t4_regs.h:#define V_CURSOR(x) ((x) << S_CURSOR) dev/cxgbe/common/t4_regs.h:#define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR) dev/cxgbe/common/t4_regs.h:#define V_PRECURSOR(x) ((x) << S_PRECURSOR) dev/cxgbe/common/t4_regs.h:#define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR) dev/cxgbe/common/t4_regs.h:#define V_INDEX(x) ((x) << S_INDEX) dev/cxgbe/common/t4_regs.h:#define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX) dev/cxgbe/common/t4_regs.h:#define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR) dev/cxgbe/common/t4_regs.h:#define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR) dev/cxgbe/common/t4_regs.h:#define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE) dev/cxgbe/common/t4_regs.h:#define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE) dev/cxgbe/common/t4_regs.h:#define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH) dev/cxgbe/common/t4_regs.h:#define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH) dev/cxgbe/common/t4_regs.h:#define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME) dev/cxgbe/common/t4_regs.h:#define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME) dev/cxgbe/common/t4_regs.h:#define V_CRMC(x) ((x) << S_CRMC) dev/cxgbe/common/t4_regs.h:#define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC) dev/cxgbe/common/t4_regs.h:#define V_SBRS(x) ((x) << S_SBRS) dev/cxgbe/common/t4_regs.h:#define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS) dev/cxgbe/common/t4_regs.h:#define V_OTWS(x) ((x) << S_OTWS) dev/cxgbe/common/t4_regs.h:#define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS) dev/cxgbe/common/t4_regs.h:#define V_RVID(x) ((x) << S_RVID) dev/cxgbe/common/t4_regs.h:#define G_RVID(x) (((x) >> S_RVID) & M_RVID) dev/cxgbe/common/t4_regs.h:#define V_BRVN(x) ((x) << S_BRVN) dev/cxgbe/common/t4_regs.h:#define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN) dev/cxgbe/common/t4_regs.h:#define V_MINTAG(x) ((x) << S_MINTAG) dev/cxgbe/common/t4_regs.h:#define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG) dev/cxgbe/common/t4_regs.h:#define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT) dev/cxgbe/common/t4_regs.h:#define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT) dev/cxgbe/common/t4_regs.h:#define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT) dev/cxgbe/common/t4_regs.h:#define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT) dev/cxgbe/common/t4_regs.h:#define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT) dev/cxgbe/common/t4_regs.h:#define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT) dev/cxgbe/common/t4_regs.h:#define V_COOKIECNT(x) ((x) << S_COOKIECNT) dev/cxgbe/common/t4_regs.h:#define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT) dev/cxgbe/common/t4_regs.h:#define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT) dev/cxgbe/common/t4_regs.h:#define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT) dev/cxgbe/common/t4_regs.h:#define V_SIREQCNT(x) ((x) << S_SIREQCNT) dev/cxgbe/common/t4_regs.h:#define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT) dev/cxgbe/common/t4_regs.h:#define V_WRSOPCNT(x) ((x) << S_WRSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_RDSOPCNT(x) ((x) << S_RDSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_RSPERRCNT(x) ((x) << S_RSPERRCNT) dev/cxgbe/common/t4_regs.h:#define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT) dev/cxgbe/common/t4_regs.h:#define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_RDREQCNT(x) ((x) << S_RDREQCNT) dev/cxgbe/common/t4_regs.h:#define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT) dev/cxgbe/common/t4_regs.h:#define V_RTOS(x) ((x) << S_RTOS) dev/cxgbe/common/t4_regs.h:#define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS) dev/cxgbe/common/t4_regs.h:#define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT) dev/cxgbe/common/t4_regs.h:#define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT) dev/cxgbe/common/t4_regs.h:#define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT) dev/cxgbe/common/t4_regs.h:#define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT) dev/cxgbe/common/t4_regs.h:#define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT) dev/cxgbe/common/t4_regs.h:#define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT) dev/cxgbe/common/t4_regs.h:#define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT) dev/cxgbe/common/t4_regs.h:#define V_TIMERVALUE(x) ((x) << S_TIMERVALUE) dev/cxgbe/common/t4_regs.h:#define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE) dev/cxgbe/common/t4_regs.h:#define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED) dev/cxgbe/common/t4_regs.h:#define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED) dev/cxgbe/common/t4_regs.h:#define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED) dev/cxgbe/common/t4_regs.h:#define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED) dev/cxgbe/common/t4_regs.h:#define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT) dev/cxgbe/common/t4_regs.h:#define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT) dev/cxgbe/common/t4_regs.h:#define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY) dev/cxgbe/common/t4_regs.h:#define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY) dev/cxgbe/common/t4_regs.h:#define V_REQTAG(x) ((x) << S_REQTAG) dev/cxgbe/common/t4_regs.h:#define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG) dev/cxgbe/common/t4_regs.h:#define V_CID(x) ((x) << S_CID) dev/cxgbe/common/t4_regs.h:#define G_CID(x) (((x) >> S_CID) & M_CID) dev/cxgbe/common/t4_regs.h:#define V_CHNUM(x) ((x) << S_CHNUM) dev/cxgbe/common/t4_regs.h:#define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM) dev/cxgbe/common/t4_regs.h:#define V_BYTELEN(x) ((x) << S_BYTELEN) dev/cxgbe/common/t4_regs.h:#define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN) dev/cxgbe/common/t4_regs.h:#define V_REASON(x) ((x) << S_REASON) dev/cxgbe/common/t4_regs.h:#define G_REASON(x) (((x) >> S_REASON) & M_REASON) dev/cxgbe/common/t4_regs.h:#define V_CPLSTATUS(x) ((x) << S_CPLSTATUS) dev/cxgbe/common/t4_regs.h:#define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS) dev/cxgbe/common/t4_regs.h:#define V_REQVFID(x) ((x) << S_REQVFID) dev/cxgbe/common/t4_regs.h:#define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID) dev/cxgbe/common/t4_regs.h:#define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH) dev/cxgbe/common/t4_regs.h:#define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH) dev/cxgbe/common/t4_regs.h:#define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL) dev/cxgbe/common/t4_regs.h:#define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL) dev/cxgbe/common/t4_regs.h:#define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH) dev/cxgbe/common/t4_regs.h:#define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH) dev/cxgbe/common/t4_regs.h:#define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL) dev/cxgbe/common/t4_regs.h:#define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL) dev/cxgbe/common/t4_regs.h:#define V_DBI_TIMER(x) ((x) << S_DBI_TIMER) dev/cxgbe/common/t4_regs.h:#define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER) dev/cxgbe/common/t4_regs.h:#define V_SOURCE(x) ((x) << S_SOURCE) dev/cxgbe/common/t4_regs.h:#define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE) dev/cxgbe/common/t4_regs.h:#define V_DBI_WRITE(x) ((x) << S_DBI_WRITE) dev/cxgbe/common/t4_regs.h:#define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE) dev/cxgbe/common/t4_regs.h:#define V_DBI_PF(x) ((x) << S_DBI_PF) dev/cxgbe/common/t4_regs.h:#define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF) dev/cxgbe/common/t4_regs.h:#define V_PL_TOVF(x) ((x) << S_PL_TOVF) dev/cxgbe/common/t4_regs.h:#define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF) dev/cxgbe/common/t4_regs.h:#define V_BUFRDCNT(x) ((x) << S_BUFRDCNT) dev/cxgbe/common/t4_regs.h:#define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT) dev/cxgbe/common/t4_regs.h:#define V_BUFWRCNT(x) ((x) << S_BUFWRCNT) dev/cxgbe/common/t4_regs.h:#define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT) dev/cxgbe/common/t4_regs.h:#define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ) dev/cxgbe/common/t4_regs.h:#define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ) dev/cxgbe/common/t4_regs.h:#define V_PB_SEL(x) ((x) << S_PB_SEL) dev/cxgbe/common/t4_regs.h:#define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL) dev/cxgbe/common/t4_regs.h:#define V_PB_SELREG(x) ((x) << S_PB_SELREG) dev/cxgbe/common/t4_regs.h:#define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG) dev/cxgbe/common/t4_regs.h:#define V_PB_FUNC(x) ((x) << S_PB_FUNC) dev/cxgbe/common/t4_regs.h:#define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC) dev/cxgbe/common/t4_regs.h:#define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH) dev/cxgbe/common/t4_regs.h:#define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH) dev/cxgbe/common/t4_regs.h:#define V_ACTIVELANES(x) ((x) << S_ACTIVELANES) dev/cxgbe/common/t4_regs.h:#define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES) dev/cxgbe/common/t4_regs.h:#define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNH_RXPWRSTATE(x) ((x) << S_REQ_LNH_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNH_RXPWRSTATE(x) (((x) >> S_REQ_LNH_RXPWRSTATE) & M_REQ_LNH_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNG_RXPWRSTATE(x) ((x) << S_REQ_LNG_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNG_RXPWRSTATE(x) (((x) >> S_REQ_LNG_RXPWRSTATE) & M_REQ_LNG_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNF_RXPWRSTATE(x) ((x) << S_REQ_LNF_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNF_RXPWRSTATE(x) (((x) >> S_REQ_LNF_RXPWRSTATE) & M_REQ_LNF_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNE_RXPWRSTATE(x) ((x) << S_REQ_LNE_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNE_RXPWRSTATE(x) (((x) >> S_REQ_LNE_RXPWRSTATE) & M_REQ_LNE_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LND_RXPWRSTATE(x) ((x) << S_REQ_LND_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LND_RXPWRSTATE(x) (((x) >> S_REQ_LND_RXPWRSTATE) & M_REQ_LND_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNC_RXPWRSTATE(x) ((x) << S_REQ_LNC_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNC_RXPWRSTATE(x) (((x) >> S_REQ_LNC_RXPWRSTATE) & M_REQ_LNC_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNB_RXPWRSTATE(x) ((x) << S_REQ_LNB_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNB_RXPWRSTATE(x) (((x) >> S_REQ_LNB_RXPWRSTATE) & M_REQ_LNB_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNA_RXPWRSTATE(x) ((x) << S_REQ_LNA_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNA_RXPWRSTATE(x) (((x) >> S_REQ_LNA_RXPWRSTATE) & M_REQ_LNA_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNH_RXPWRSTATE(x) ((x) << S_CUR_LNH_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNH_RXPWRSTATE(x) (((x) >> S_CUR_LNH_RXPWRSTATE) & M_CUR_LNH_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNG_RXPWRSTATE(x) ((x) << S_CUR_LNG_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNG_RXPWRSTATE(x) (((x) >> S_CUR_LNG_RXPWRSTATE) & M_CUR_LNG_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNF_RXPWRSTATE(x) ((x) << S_CUR_LNF_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNF_RXPWRSTATE(x) (((x) >> S_CUR_LNF_RXPWRSTATE) & M_CUR_LNF_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNE_RXPWRSTATE(x) ((x) << S_CUR_LNE_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNE_RXPWRSTATE(x) (((x) >> S_CUR_LNE_RXPWRSTATE) & M_CUR_LNE_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LND_RXPWRSTATE(x) ((x) << S_CUR_LND_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LND_RXPWRSTATE(x) (((x) >> S_CUR_LND_RXPWRSTATE) & M_CUR_LND_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNC_RXPWRSTATE(x) ((x) << S_CUR_LNC_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNC_RXPWRSTATE(x) (((x) >> S_CUR_LNC_RXPWRSTATE) & M_CUR_LNC_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNB_RXPWRSTATE(x) ((x) << S_CUR_LNB_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNB_RXPWRSTATE(x) (((x) >> S_CUR_LNB_RXPWRSTATE) & M_CUR_LNB_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNA_RXPWRSTATE(x) ((x) << S_CUR_LNA_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNA_RXPWRSTATE(x) (((x) >> S_CUR_LNA_RXPWRSTATE) & M_CUR_LNA_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LND_STAT(x) ((x) << S_LND_STAT) dev/cxgbe/common/t4_regs.h:#define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT) dev/cxgbe/common/t4_regs.h:#define V_LND_CMD(x) ((x) << S_LND_CMD) dev/cxgbe/common/t4_regs.h:#define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNC_STAT(x) ((x) << S_LNC_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNC_CMD(x) ((x) << S_LNC_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNB_STAT(x) ((x) << S_LNB_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNB_CMD(x) ((x) << S_LNB_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNA_STAT(x) ((x) << S_LNA_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNA_CMD(x) ((x) << S_LNA_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNH_STAT(x) ((x) << S_LNH_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNH_CMD(x) ((x) << S_LNH_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNG_STAT(x) ((x) << S_LNG_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNG_CMD(x) ((x) << S_LNG_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNF_STAT(x) ((x) << S_LNF_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNF_CMD(x) ((x) << S_LNF_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNE_STAT(x) ((x) << S_LNE_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNE_CMD(x) ((x) << S_LNE_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD) dev/cxgbe/common/t4_regs.h:#define V_COEFFLANE(x) ((x) << S_COEFFLANE) dev/cxgbe/common/t4_regs.h:#define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE) dev/cxgbe/common/t4_regs.h:#define V_COEFF(x) ((x) << S_COEFF) dev/cxgbe/common/t4_regs.h:#define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF) dev/cxgbe/common/t4_regs.h:#define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR) dev/cxgbe/common/t4_regs.h:#define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR) dev/cxgbe/common/t4_regs.h:#define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN) dev/cxgbe/common/t4_regs.h:#define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN) dev/cxgbe/common/t4_regs.h:#define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR) dev/cxgbe/common/t4_regs.h:#define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR) dev/cxgbe/common/t4_regs.h:#define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN) dev/cxgbe/common/t4_regs.h:#define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN) dev/cxgbe/common/t4_regs.h:#define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR) dev/cxgbe/common/t4_regs.h:#define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR) dev/cxgbe/common/t4_regs.h:#define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST) dev/cxgbe/common/t4_regs.h:#define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNP_RXPWRSTATE(x) ((x) << S_REQ_LNP_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNP_RXPWRSTATE(x) (((x) >> S_REQ_LNP_RXPWRSTATE) & M_REQ_LNP_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNO_RXPWRSTATE(x) ((x) << S_REQ_LNO_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNO_RXPWRSTATE(x) (((x) >> S_REQ_LNO_RXPWRSTATE) & M_REQ_LNO_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNN_RXPWRSTATE(x) ((x) << S_REQ_LNN_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNN_RXPWRSTATE(x) (((x) >> S_REQ_LNN_RXPWRSTATE) & M_REQ_LNN_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNM_RXPWRSTATE(x) ((x) << S_REQ_LNM_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNM_RXPWRSTATE(x) (((x) >> S_REQ_LNM_RXPWRSTATE) & M_REQ_LNM_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNL_RXPWRSTATE(x) ((x) << S_REQ_LNL_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNL_RXPWRSTATE(x) (((x) >> S_REQ_LNL_RXPWRSTATE) & M_REQ_LNL_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNK_RXPWRSTATE(x) ((x) << S_REQ_LNK_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNK_RXPWRSTATE(x) (((x) >> S_REQ_LNK_RXPWRSTATE) & M_REQ_LNK_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNJ_RXPWRSTATE(x) ((x) << S_REQ_LNJ_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNJ_RXPWRSTATE(x) (((x) >> S_REQ_LNJ_RXPWRSTATE) & M_REQ_LNJ_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_REQ_LNI_RXPWRSTATE(x) ((x) << S_REQ_LNI_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_REQ_LNI_RXPWRSTATE(x) (((x) >> S_REQ_LNI_RXPWRSTATE) & M_REQ_LNI_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNP_RXPWRSTATE(x) ((x) << S_CUR_LNP_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNP_RXPWRSTATE(x) (((x) >> S_CUR_LNP_RXPWRSTATE) & M_CUR_LNP_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNO_RXPWRSTATE(x) ((x) << S_CUR_LNO_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNO_RXPWRSTATE(x) (((x) >> S_CUR_LNO_RXPWRSTATE) & M_CUR_LNO_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNN_RXPWRSTATE(x) ((x) << S_CUR_LNN_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNN_RXPWRSTATE(x) (((x) >> S_CUR_LNN_RXPWRSTATE) & M_CUR_LNN_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNM_RXPWRSTATE(x) ((x) << S_CUR_LNM_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNM_RXPWRSTATE(x) (((x) >> S_CUR_LNM_RXPWRSTATE) & M_CUR_LNM_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNL_RXPWRSTATE(x) ((x) << S_CUR_LNL_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNL_RXPWRSTATE(x) (((x) >> S_CUR_LNL_RXPWRSTATE) & M_CUR_LNL_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNK_RXPWRSTATE(x) ((x) << S_CUR_LNK_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNK_RXPWRSTATE(x) (((x) >> S_CUR_LNK_RXPWRSTATE) & M_CUR_LNK_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNJ_RXPWRSTATE(x) ((x) << S_CUR_LNJ_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNJ_RXPWRSTATE(x) (((x) >> S_CUR_LNJ_RXPWRSTATE) & M_CUR_LNJ_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_CUR_LNI_RXPWRSTATE(x) ((x) << S_CUR_LNI_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define G_CUR_LNI_RXPWRSTATE(x) (((x) >> S_CUR_LNI_RXPWRSTATE) & M_CUR_LNI_RXPWRSTATE) dev/cxgbe/common/t4_regs.h:#define V_LNL_STAT(x) ((x) << S_LNL_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNL_STAT(x) (((x) >> S_LNL_STAT) & M_LNL_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNL_CMD(x) ((x) << S_LNL_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNL_CMD(x) (((x) >> S_LNL_CMD) & M_LNL_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNK_STAT(x) ((x) << S_LNK_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNK_STAT(x) (((x) >> S_LNK_STAT) & M_LNK_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNK_CMD(x) ((x) << S_LNK_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNK_CMD(x) (((x) >> S_LNK_CMD) & M_LNK_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNJ_STAT(x) ((x) << S_LNJ_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNJ_STAT(x) (((x) >> S_LNJ_STAT) & M_LNJ_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNJ_CMD(x) ((x) << S_LNJ_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNJ_CMD(x) (((x) >> S_LNJ_CMD) & M_LNJ_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNI_STAT(x) ((x) << S_LNI_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNI_STAT(x) (((x) >> S_LNI_STAT) & M_LNI_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNI_CMD(x) ((x) << S_LNI_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNI_CMD(x) (((x) >> S_LNI_CMD) & M_LNI_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNP_STAT(x) ((x) << S_LNP_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNP_STAT(x) (((x) >> S_LNP_STAT) & M_LNP_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNP_CMD(x) ((x) << S_LNP_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNP_CMD(x) (((x) >> S_LNP_CMD) & M_LNP_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNO_STAT(x) ((x) << S_LNO_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNO_STAT(x) (((x) >> S_LNO_STAT) & M_LNO_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNO_CMD(x) ((x) << S_LNO_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNO_CMD(x) (((x) >> S_LNO_CMD) & M_LNO_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNN_STAT(x) ((x) << S_LNN_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNN_STAT(x) (((x) >> S_LNN_STAT) & M_LNN_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNN_CMD(x) ((x) << S_LNN_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNN_CMD(x) (((x) >> S_LNN_CMD) & M_LNN_CMD) dev/cxgbe/common/t4_regs.h:#define V_LNM_STAT(x) ((x) << S_LNM_STAT) dev/cxgbe/common/t4_regs.h:#define G_LNM_STAT(x) (((x) >> S_LNM_STAT) & M_LNM_STAT) dev/cxgbe/common/t4_regs.h:#define V_LNM_CMD(x) ((x) << S_LNM_CMD) dev/cxgbe/common/t4_regs.h:#define G_LNM_CMD(x) (((x) >> S_LNM_CMD) & M_LNM_CMD) dev/cxgbe/common/t4_regs.h:#define V_PHY_REG_SELECT(x) ((x) << S_PHY_REG_SELECT) dev/cxgbe/common/t4_regs.h:#define G_PHY_REG_SELECT(x) (((x) >> S_PHY_REG_SELECT) & M_PHY_REG_SELECT) dev/cxgbe/common/t4_regs.h:#define V_PHY_REG_REGADDR(x) ((x) << S_PHY_REG_REGADDR) dev/cxgbe/common/t4_regs.h:#define G_PHY_REG_REGADDR(x) (((x) >> S_PHY_REG_REGADDR) & M_PHY_REG_REGADDR) dev/cxgbe/common/t4_regs.h:#define V_PHY_REG_DATA(x) ((x) << S_PHY_REG_DATA) dev/cxgbe/common/t4_regs.h:#define G_PHY_REG_DATA(x) (((x) >> S_PHY_REG_DATA) & M_PHY_REG_DATA) dev/cxgbe/common/t4_regs.h:#define V_VFID_PCIE(x) ((x) << S_VFID_PCIE) dev/cxgbe/common/t4_regs.h:#define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE) dev/cxgbe/common/t4_regs.h:#define V_HDRFREECNT(x) ((x) << S_HDRFREECNT) dev/cxgbe/common/t4_regs.h:#define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT) dev/cxgbe/common/t4_regs.h:#define V_DATAFREECNT(x) ((x) << S_DATAFREECNT) dev/cxgbe/common/t4_regs.h:#define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT) dev/cxgbe/common/t4_regs.h:#define V_LASTRESETSTATE(x) ((x) << S_LASTRESETSTATE) dev/cxgbe/common/t4_regs.h:#define G_LASTRESETSTATE(x) (((x) >> S_LASTRESETSTATE) & M_LASTRESETSTATE) dev/cxgbe/common/t4_regs.h:#define V_PHY_MAC_PHYSTATUS(x) ((x) << S_PHY_MAC_PHYSTATUS) dev/cxgbe/common/t4_regs.h:#define G_PHY_MAC_PHYSTATUS(x) (((x) >> S_PHY_MAC_PHYSTATUS) & M_PHY_MAC_PHYSTATUS) dev/cxgbe/common/t4_regs.h:#define V_SI_REQVFID(x) ((x) << S_SI_REQVFID) dev/cxgbe/common/t4_regs.h:#define G_SI_REQVFID(x) (((x) >> S_SI_REQVFID) & M_SI_REQVFID) dev/cxgbe/common/t4_regs.h:#define V_SI_REQVEC(x) ((x) << S_SI_REQVEC) dev/cxgbe/common/t4_regs.h:#define G_SI_REQVEC(x) (((x) >> S_SI_REQVEC) & M_SI_REQVEC) dev/cxgbe/common/t4_regs.h:#define V_SI_REQTCVAL(x) ((x) << S_SI_REQTCVAL) dev/cxgbe/common/t4_regs.h:#define G_SI_REQTCVAL(x) (((x) >> S_SI_REQTCVAL) & M_SI_REQTCVAL) dev/cxgbe/common/t4_regs.h:#define V_SMARB(x) ((x) << S_SMARB) dev/cxgbe/common/t4_regs.h:#define G_SMARB(x) (((x) >> S_SMARB) & M_SMARB) dev/cxgbe/common/t4_regs.h:#define V_SMDEFR(x) ((x) << S_SMDEFR) dev/cxgbe/common/t4_regs.h:#define G_SMDEFR(x) (((x) >> S_SMDEFR) & M_SMDEFR) dev/cxgbe/common/t4_regs.h:#define V_SYS_INT(x) ((x) << S_SYS_INT) dev/cxgbe/common/t4_regs.h:#define G_SYS_INT(x) (((x) >> S_SYS_INT) & M_SYS_INT) dev/cxgbe/common/t4_regs.h:#define V_CFG_INTXCLR(x) ((x) << S_CFG_INTXCLR) dev/cxgbe/common/t4_regs.h:#define G_CFG_INTXCLR(x) (((x) >> S_CFG_INTXCLR) & M_CFG_INTXCLR) dev/cxgbe/common/t4_regs.h:#define V_PIO_INTXCLR(x) ((x) << S_PIO_INTXCLR) dev/cxgbe/common/t4_regs.h:#define G_PIO_INTXCLR(x) (((x) >> S_PIO_INTXCLR) & M_PIO_INTXCLR) dev/cxgbe/common/t4_regs.h:#define V_PLI_REQADDR(x) ((x) << S_PLI_REQADDR) dev/cxgbe/common/t4_regs.h:#define G_PLI_REQADDR(x) (((x) >> S_PLI_REQADDR) & M_PLI_REQADDR) dev/cxgbe/common/t4_regs.h:#define V_PLI_REQVFID(x) ((x) << S_PLI_REQVFID) dev/cxgbe/common/t4_regs.h:#define G_PLI_REQVFID(x) (((x) >> S_PLI_REQVFID) & M_PLI_REQVFID) dev/cxgbe/common/t4_regs.h:#define V_PLI_REQPBASTART(x) ((x) << S_PLI_REQPBASTART) dev/cxgbe/common/t4_regs.h:#define G_PLI_REQPBASTART(x) (((x) >> S_PLI_REQPBASTART) & M_PLI_REQPBASTART) dev/cxgbe/common/t4_regs.h:#define V_PLI_REQPBAEND(x) ((x) << S_PLI_REQPBAEND) dev/cxgbe/common/t4_regs.h:#define G_PLI_REQPBAEND(x) (((x) >> S_PLI_REQPBAEND) & M_PLI_REQPBAEND) dev/cxgbe/common/t4_regs.h:#define V_DI_REQWREN(x) ((x) << S_DI_REQWREN) dev/cxgbe/common/t4_regs.h:#define G_DI_REQWREN(x) (((x) >> S_DI_REQWREN) & M_DI_REQWREN) dev/cxgbe/common/t4_regs.h:#define V_AI_REQVLD(x) ((x) << S_AI_REQVLD) dev/cxgbe/common/t4_regs.h:#define G_AI_REQVLD(x) (((x) >> S_AI_REQVLD) & M_AI_REQVLD) dev/cxgbe/common/t4_regs.h:#define V_STATEMPIO(x) ((x) << S_STATEMPIO) dev/cxgbe/common/t4_regs.h:#define G_STATEMPIO(x) (((x) >> S_STATEMPIO) & M_STATEMPIO) dev/cxgbe/common/t4_regs.h:#define V_STATECPL(x) ((x) << S_STATECPL) dev/cxgbe/common/t4_regs.h:#define G_STATECPL(x) (((x) >> S_STATECPL) & M_STATECPL) dev/cxgbe/common/t4_regs.h:#define V_STATEALIN(x) ((x) << S_STATEALIN) dev/cxgbe/common/t4_regs.h:#define G_STATEALIN(x) (((x) >> S_STATEALIN) & M_STATEALIN) dev/cxgbe/common/t4_regs.h:#define V_STATEPL(x) ((x) << S_STATEPL) dev/cxgbe/common/t4_regs.h:#define G_STATEPL(x) (((x) >> S_STATEPL) & M_STATEPL) dev/cxgbe/common/t4_regs.h:#define V_MA_TAGSINUSE(x) ((x) << S_MA_TAGSINUSE) dev/cxgbe/common/t4_regs.h:#define G_MA_TAGSINUSE(x) (((x) >> S_MA_TAGSINUSE) & M_MA_TAGSINUSE) dev/cxgbe/common/t4_regs.h:#define V_PIO_WRCNT(x) ((x) << S_PIO_WRCNT) dev/cxgbe/common/t4_regs.h:#define G_PIO_WRCNT(x) (((x) >> S_PIO_WRCNT) & M_PIO_WRCNT) dev/cxgbe/common/t4_regs.h:#define V_ALIND_REQWRCNT(x) ((x) << S_ALIND_REQWRCNT) dev/cxgbe/common/t4_regs.h:#define G_ALIND_REQWRCNT(x) (((x) >> S_ALIND_REQWRCNT) & M_ALIND_REQWRCNT) dev/cxgbe/common/t4_regs.h:#define V_FID_LKUPWRCNT(x) ((x) << S_FID_LKUPWRCNT) dev/cxgbe/common/t4_regs.h:#define G_FID_LKUPWRCNT(x) (((x) >> S_FID_LKUPWRCNT) & M_FID_LKUPWRCNT) dev/cxgbe/common/t4_regs.h:#define V_TGT_TAGQ_RDVLD(x) ((x) << S_TGT_TAGQ_RDVLD) dev/cxgbe/common/t4_regs.h:#define G_TGT_TAGQ_RDVLD(x) (((x) >> S_TGT_TAGQ_RDVLD) & M_TGT_TAGQ_RDVLD) dev/cxgbe/common/t4_regs.h:#define V_CPLTXNDISABLE(x) ((x) << S_CPLTXNDISABLE) dev/cxgbe/common/t4_regs.h:#define G_CPLTXNDISABLE(x) (((x) >> S_CPLTXNDISABLE) & M_CPLTXNDISABLE) dev/cxgbe/common/t4_regs.h:#define V_D_RSPVLD(x) ((x) << S_D_RSPVLD) dev/cxgbe/common/t4_regs.h:#define G_D_RSPVLD(x) (((x) >> S_D_RSPVLD) & M_D_RSPVLD) dev/cxgbe/common/t4_regs.h:#define V_D_RSPAFULL(x) ((x) << S_D_RSPAFULL) dev/cxgbe/common/t4_regs.h:#define G_D_RSPAFULL(x) (((x) >> S_D_RSPAFULL) & M_D_RSPAFULL) dev/cxgbe/common/t4_regs.h:#define V_D_RDREQVLD(x) ((x) << S_D_RDREQVLD) dev/cxgbe/common/t4_regs.h:#define G_D_RDREQVLD(x) (((x) >> S_D_RDREQVLD) & M_D_RDREQVLD) dev/cxgbe/common/t4_regs.h:#define V_D_RDREQAFULL(x) ((x) << S_D_RDREQAFULL) dev/cxgbe/common/t4_regs.h:#define G_D_RDREQAFULL(x) (((x) >> S_D_RDREQAFULL) & M_D_RDREQAFULL) dev/cxgbe/common/t4_regs.h:#define V_D_WRREQVLD(x) ((x) << S_D_WRREQVLD) dev/cxgbe/common/t4_regs.h:#define G_D_WRREQVLD(x) (((x) >> S_D_WRREQVLD) & M_D_WRREQVLD) dev/cxgbe/common/t4_regs.h:#define V_D_WRREQAFULL(x) ((x) << S_D_WRREQAFULL) dev/cxgbe/common/t4_regs.h:#define G_D_WRREQAFULL(x) (((x) >> S_D_WRREQAFULL) & M_D_WRREQAFULL) dev/cxgbe/common/t4_regs.h:#define V_C_REQVLD(x) ((x) << S_C_REQVLD) dev/cxgbe/common/t4_regs.h:#define G_C_REQVLD(x) (((x) >> S_C_REQVLD) & M_C_REQVLD) dev/cxgbe/common/t4_regs.h:#define V_C_RSPAFULL(x) ((x) << S_C_RSPAFULL) dev/cxgbe/common/t4_regs.h:#define G_C_RSPAFULL(x) (((x) >> S_C_RSPAFULL) & M_C_RSPAFULL) dev/cxgbe/common/t4_regs.h:#define V_C_REQAFULL(x) ((x) << S_C_REQAFULL) dev/cxgbe/common/t4_regs.h:#define G_C_REQAFULL(x) (((x) >> S_C_REQAFULL) & M_C_REQAFULL) dev/cxgbe/common/t4_regs.h:#define V_H_REQVLD(x) ((x) << S_H_REQVLD) dev/cxgbe/common/t4_regs.h:#define G_H_REQVLD(x) (((x) >> S_H_REQVLD) & M_H_REQVLD) dev/cxgbe/common/t4_regs.h:#define V_ER_RSPVLD(x) ((x) << S_ER_RSPVLD) dev/cxgbe/common/t4_regs.h:#define G_ER_RSPVLD(x) (((x) >> S_ER_RSPVLD) & M_ER_RSPVLD) dev/cxgbe/common/t4_regs.h:#define V_VPD_RSPVLD(x) ((x) << S_VPD_RSPVLD) dev/cxgbe/common/t4_regs.h:#define G_VPD_RSPVLD(x) (((x) >> S_VPD_RSPVLD) & M_VPD_RSPVLD) dev/cxgbe/common/t4_regs.h:#define V_MA_REQDATAVLD(x) ((x) << S_MA_REQDATAVLD) dev/cxgbe/common/t4_regs.h:#define G_MA_REQDATAVLD(x) (((x) >> S_MA_REQDATAVLD) & M_MA_REQDATAVLD) dev/cxgbe/common/t4_regs.h:#define V_PLM_REQVLD(x) ((x) << S_PLM_REQVLD) dev/cxgbe/common/t4_regs.h:#define G_PLM_REQVLD(x) (((x) >> S_PLM_REQVLD) & M_PLM_REQVLD) dev/cxgbe/common/t4_regs.h:#define V_PLM_REQVLDA(x) ((x) << S_PLM_REQVLDA) dev/cxgbe/common/t4_regs.h:#define G_PLM_REQVLDA(x) (((x) >> S_PLM_REQVLDA) & M_PLM_REQVLDA) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P) dev/cxgbe/common/t4_regs.h:#define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL) dev/cxgbe/common/t4_regs.h:#define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL) dev/cxgbe/common/t4_regs.h:#define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL) dev/cxgbe/common/t4_regs.h:#define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL) dev/cxgbe/common/t4_regs.h:#define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL) dev/cxgbe/common/t4_regs.h:#define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V) dev/cxgbe/common/t4_regs.h:#define V_PSRO_SEL(x) ((x) << S_PSRO_SEL) dev/cxgbe/common/t4_regs.h:#define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL) dev/cxgbe/common/t4_regs.h:#define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD) dev/cxgbe/common/t4_regs.h:#define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD) dev/cxgbe/common/t4_regs.h:#define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR) dev/cxgbe/common/t4_regs.h:#define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR) dev/cxgbe/common/t4_regs.h:#define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT) dev/cxgbe/common/t4_regs.h:#define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT) dev/cxgbe/common/t4_regs.h:#define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO) dev/cxgbe/common/t4_regs.h:#define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO) dev/cxgbe/common/t4_regs.h:#define V_DBG_FEF(x) ((x) << S_DBG_FEF) dev/cxgbe/common/t4_regs.h:#define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF) dev/cxgbe/common/t4_regs.h:#define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL) dev/cxgbe/common/t4_regs.h:#define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL) dev/cxgbe/common/t4_regs.h:#define V_DBG_FETIME(x) ((x) << S_DBG_FETIME) dev/cxgbe/common/t4_regs.h:#define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_MULTFRAC(x) ((x) << S_STATIC_M_PLL_MULTFRAC) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_STATIC_M_PLL_MULTFRAC) & M_STATIC_M_PLL_MULTFRAC) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_SDORDER(x) ((x) << S_STATIC_M_PLL_SDORDER) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_SDORDER(x) (((x) >> S_STATIC_M_PLL_SDORDER) & M_STATIC_M_PLL_SDORDER) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_MULTPRE(x) ((x) << S_STATIC_M_PLL_MULTPRE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_MULTPRE(x) (((x) >> S_STATIC_M_PLL_MULTPRE) & M_STATIC_M_PLL_MULTPRE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_FFTUNE(x) ((x) << S_STATIC_M_PLL_FFTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_FFTUNE(x) (((x) >> S_STATIC_M_PLL_FFTUNE) & M_STATIC_M_PLL_FFTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_RANGEPRE(x) ((x) << S_STATIC_M_PLL_RANGEPRE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_STATIC_M_PLL_RANGEPRE) & M_STATIC_M_PLL_RANGEPRE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_VCVTUNE(x) ((x) << S_STATIC_M_PLL_VCVTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_STATIC_M_PLL_VCVTUNE) & M_STATIC_M_PLL_VCVTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_STARTUP(x) ((x) << S_STATIC_M_PLL_STARTUP) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_STARTUP(x) (((x) >> S_STATIC_M_PLL_STARTUP) & M_STATIC_M_PLL_STARTUP) dev/cxgbe/common/t4_regs.h:#define V_STATIC_M_PLL_VREGTUNE(x) ((x) << S_STATIC_M_PLL_VREGTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_M_PLL_VREGTUNE(x) (((x) >> S_STATIC_M_PLL_VREGTUNE) & M_STATIC_M_PLL_VREGTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_MULTFRAC(x) ((x) << S_STATIC_C_PLL_MULTFRAC) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_STATIC_C_PLL_MULTFRAC) & M_STATIC_C_PLL_MULTFRAC) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_STARTUP(x) ((x) << S_STATIC_C_PLL_STARTUP) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_STARTUP(x) (((x) >> S_STATIC_C_PLL_STARTUP) & M_STATIC_C_PLL_STARTUP) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_SDORDER(x) ((x) << S_STATIC_C_PLL_SDORDER) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_SDORDER(x) (((x) >> S_STATIC_C_PLL_SDORDER) & M_STATIC_C_PLL_SDORDER) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_MULTPRE(x) ((x) << S_STATIC_C_PLL_MULTPRE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_MULTPRE(x) (((x) >> S_STATIC_C_PLL_MULTPRE) & M_STATIC_C_PLL_MULTPRE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_RANGEPRE(x) ((x) << S_STATIC_C_PLL_RANGEPRE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_STATIC_C_PLL_RANGEPRE) & M_STATIC_C_PLL_RANGEPRE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_MULTFRAC(x) ((x) << S_STATIC_U_PLL_MULTFRAC) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_STATIC_U_PLL_MULTFRAC) & M_STATIC_U_PLL_MULTFRAC) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_STARTUP(x) ((x) << S_STATIC_U_PLL_STARTUP) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_STARTUP(x) (((x) >> S_STATIC_U_PLL_STARTUP) & M_STATIC_U_PLL_STARTUP) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_SDORDER(x) ((x) << S_STATIC_U_PLL_SDORDER) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_SDORDER(x) (((x) >> S_STATIC_U_PLL_SDORDER) & M_STATIC_U_PLL_SDORDER) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_MULTPRE(x) ((x) << S_STATIC_U_PLL_MULTPRE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_MULTPRE(x) (((x) >> S_STATIC_U_PLL_MULTPRE) & M_STATIC_U_PLL_MULTPRE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_FFTUNE(x) ((x) << S_STATIC_U_PLL_FFTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_FFTUNE(x) (((x) >> S_STATIC_U_PLL_FFTUNE) & M_STATIC_U_PLL_FFTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_RANGEPRE(x) ((x) << S_STATIC_U_PLL_RANGEPRE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_STATIC_U_PLL_RANGEPRE) & M_STATIC_U_PLL_RANGEPRE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_VCVTUNE(x) ((x) << S_STATIC_U_PLL_VCVTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_STATIC_U_PLL_VCVTUNE) & M_STATIC_U_PLL_VCVTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_CPISEL(x) ((x) << S_STATIC_KR_PLL_CPISEL) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_CPISEL(x) (((x) >> S_STATIC_KR_PLL_CPISEL) & M_STATIC_KR_PLL_CPISEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KR_PLL_CCALBANDSEL) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KR_PLL_CCALBANDSEL) & M_STATIC_KR_PLL_CCALBANDSEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KR_PLL_ANALOGTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KR_PLL_ANALOGTUNE) & M_STATIC_KR_PLL_ANALOGTUNE) dev/cxgbe/common/t4_regs.h:#define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT) dev/cxgbe/common/t4_regs.h:#define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT) dev/cxgbe/common/t4_regs.h:#define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B) dev/cxgbe/common/t4_regs.h:#define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B) dev/cxgbe/common/t4_regs.h:#define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A) dev/cxgbe/common/t4_regs.h:#define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_CPISEL(x) ((x) << S_STATIC_KX_PLL_CPISEL) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_CPISEL(x) (((x) >> S_STATIC_KX_PLL_CPISEL) & M_STATIC_KX_PLL_CPISEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KX_PLL_CCALBANDSEL) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KX_PLL_CCALBANDSEL) & M_STATIC_KX_PLL_CCALBANDSEL) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A) dev/cxgbe/common/t4_regs.h:#define V_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KX_PLL_ANALOGTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KX_PLL_ANALOGTUNE) & M_STATIC_KX_PLL_ANALOGTUNE) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B) dev/cxgbe/common/t4_regs.h:#define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A) dev/cxgbe/common/t4_regs.h:#define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B) dev/cxgbe/common/t4_regs.h:#define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A) dev/cxgbe/common/t4_regs.h:#define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B) dev/cxgbe/common/t4_regs.h:#define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A) dev/cxgbe/common/t4_regs.h:#define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A) dev/cxgbe/common/t4_regs.h:#define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY) dev/cxgbe/common/t4_regs.h:#define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS) dev/cxgbe/common/t4_regs.h:#define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS) dev/cxgbe/common/t4_regs.h:#define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE) dev/cxgbe/common/t4_regs.h:#define V_STATIC_C_PLL_VREGTUNE(x) ((x) << S_STATIC_C_PLL_VREGTUNE) dev/cxgbe/common/t4_regs.h:#define G_STATIC_C_PLL_VREGTUNE(x) (((x) >> S_STATIC_C_PLL_VREGTUNE) & M_STATIC_C_PLL_VREGTUNE) dev/cxgbe/common/t4_regs.h:#define V_EFUSE_PROG_PERIOD(x) ((x) << S_EFUSE_PROG_PERIOD) dev/cxgbe/common/t4_regs.h:#define G_EFUSE_PROG_PERIOD(x) (((x) >> S_EFUSE_PROG_PERIOD) & M_EFUSE_PROG_PERIOD) dev/cxgbe/common/t4_regs.h:#define V_EFUSE_OPER_TYP(x) ((x) << S_EFUSE_OPER_TYP) dev/cxgbe/common/t4_regs.h:#define G_EFUSE_OPER_TYP(x) (((x) >> S_EFUSE_OPER_TYP) & M_EFUSE_OPER_TYP) dev/cxgbe/common/t4_regs.h:#define V_EFUSE_ADDR(x) ((x) << S_EFUSE_ADDR) dev/cxgbe/common/t4_regs.h:#define G_EFUSE_ADDR(x) (((x) >> S_EFUSE_ADDR) & M_EFUSE_ADDR) dev/cxgbe/common/t4_regs.h:#define V_EFUSE_DIN(x) ((x) << S_EFUSE_DIN) dev/cxgbe/common/t4_regs.h:#define G_EFUSE_DIN(x) (((x) >> S_EFUSE_DIN) & M_EFUSE_DIN) dev/cxgbe/common/t4_regs.h:#define V_EFUSE_DOUT(x) ((x) << S_EFUSE_DOUT) dev/cxgbe/common/t4_regs.h:#define G_EFUSE_DOUT(x) (((x) >> S_EFUSE_DOUT) & M_EFUSE_DOUT) dev/cxgbe/common/t4_regs.h:#define V_STATE_CMD(x) ((x) << S_STATE_CMD) dev/cxgbe/common/t4_regs.h:#define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD) dev/cxgbe/common/t4_regs.h:#define V_CTL_STAT(x) ((x) << S_CTL_STAT) dev/cxgbe/common/t4_regs.h:#define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT) dev/cxgbe/common/t4_regs.h:#define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL) dev/cxgbe/common/t4_regs.h:#define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL) dev/cxgbe/common/t4_regs.h:#define V_RANK_SEL(x) ((x) << S_RANK_SEL) dev/cxgbe/common/t4_regs.h:#define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL) dev/cxgbe/common/t4_regs.h:#define V_BANK_ADDR(x) ((x) << S_BANK_ADDR) dev/cxgbe/common/t4_regs.h:#define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR) dev/cxgbe/common/t4_regs.h:#define V_CMD_ADDR(x) ((x) << S_CMD_ADDR) dev/cxgbe/common/t4_regs.h:#define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR) dev/cxgbe/common/t4_regs.h:#define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE) dev/cxgbe/common/t4_regs.h:#define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_TFAW_CFG(x) ((x) << S_TFAW_CFG) dev/cxgbe/common/t4_regs.h:#define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG) dev/cxgbe/common/t4_regs.h:#define V_PD_IDLE(x) ((x) << S_PD_IDLE) dev/cxgbe/common/t4_regs.h:#define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE) dev/cxgbe/common/t4_regs.h:#define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY) dev/cxgbe/common/t4_regs.h:#define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY) dev/cxgbe/common/t4_regs.h:#define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS) dev/cxgbe/common/t4_regs.h:#define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS) dev/cxgbe/common/t4_regs.h:#define V_DV_ALAT(x) ((x) << S_DV_ALAT) dev/cxgbe/common/t4_regs.h:#define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT) dev/cxgbe/common/t4_regs.h:#define V_DV_ALEN(x) ((x) << S_DV_ALEN) dev/cxgbe/common/t4_regs.h:#define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN) dev/cxgbe/common/t4_regs.h:#define V_DSE_ALAT(x) ((x) << S_DSE_ALAT) dev/cxgbe/common/t4_regs.h:#define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT) dev/cxgbe/common/t4_regs.h:#define V_DSE_ALEN(x) ((x) << S_DSE_ALEN) dev/cxgbe/common/t4_regs.h:#define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN) dev/cxgbe/common/t4_regs.h:#define V_QSE_ALAT(x) ((x) << S_QSE_ALAT) dev/cxgbe/common/t4_regs.h:#define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT) dev/cxgbe/common/t4_regs.h:#define V_QSE_ALEN(x) ((x) << S_QSE_ALEN) dev/cxgbe/common/t4_regs.h:#define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN) dev/cxgbe/common/t4_regs.h:#define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL) dev/cxgbe/common/t4_regs.h:#define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL) dev/cxgbe/common/t4_regs.h:#define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS) dev/cxgbe/common/t4_regs.h:#define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS) dev/cxgbe/common/t4_regs.h:#define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH) dev/cxgbe/common/t4_regs.h:#define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH) dev/cxgbe/common/t4_regs.h:#define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH) dev/cxgbe/common/t4_regs.h:#define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH) dev/cxgbe/common/t4_regs.h:#define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH) dev/cxgbe/common/t4_regs.h:#define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH) dev/cxgbe/common/t4_regs.h:#define V_T_INIT(x) ((x) << S_T_INIT) dev/cxgbe/common/t4_regs.h:#define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT) dev/cxgbe/common/t4_regs.h:#define V_T_RSTH(x) ((x) << S_T_RSTH) dev/cxgbe/common/t4_regs.h:#define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH) dev/cxgbe/common/t4_regs.h:#define V_T_REFI(x) ((x) << S_T_REFI) dev/cxgbe/common/t4_regs.h:#define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI) dev/cxgbe/common/t4_regs.h:#define V_T_MRD(x) ((x) << S_T_MRD) dev/cxgbe/common/t4_regs.h:#define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD) dev/cxgbe/common/t4_regs.h:#define V_T_RFC(x) ((x) << S_T_RFC) dev/cxgbe/common/t4_regs.h:#define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC) dev/cxgbe/common/t4_regs.h:#define V_T_RP(x) ((x) << S_T_RP) dev/cxgbe/common/t4_regs.h:#define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP) dev/cxgbe/common/t4_regs.h:#define V_T_RTW(x) ((x) << S_T_RTW) dev/cxgbe/common/t4_regs.h:#define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW) dev/cxgbe/common/t4_regs.h:#define V_T_AL(x) ((x) << S_T_AL) dev/cxgbe/common/t4_regs.h:#define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL) dev/cxgbe/common/t4_regs.h:#define V_T_CL(x) ((x) << S_T_CL) dev/cxgbe/common/t4_regs.h:#define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL) dev/cxgbe/common/t4_regs.h:#define V_T_CWL(x) ((x) << S_T_CWL) dev/cxgbe/common/t4_regs.h:#define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL) dev/cxgbe/common/t4_regs.h:#define V_T_RAS(x) ((x) << S_T_RAS) dev/cxgbe/common/t4_regs.h:#define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS) dev/cxgbe/common/t4_regs.h:#define V_T_RC(x) ((x) << S_T_RC) dev/cxgbe/common/t4_regs.h:#define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC) dev/cxgbe/common/t4_regs.h:#define V_T_RCD(x) ((x) << S_T_RCD) dev/cxgbe/common/t4_regs.h:#define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD) dev/cxgbe/common/t4_regs.h:#define V_T_RRD(x) ((x) << S_T_RRD) dev/cxgbe/common/t4_regs.h:#define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD) dev/cxgbe/common/t4_regs.h:#define V_T_RTP(x) ((x) << S_T_RTP) dev/cxgbe/common/t4_regs.h:#define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP) dev/cxgbe/common/t4_regs.h:#define V_T_WR(x) ((x) << S_T_WR) dev/cxgbe/common/t4_regs.h:#define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR) dev/cxgbe/common/t4_regs.h:#define V_T_WTR(x) ((x) << S_T_WTR) dev/cxgbe/common/t4_regs.h:#define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR) dev/cxgbe/common/t4_regs.h:#define V_T_EXSR(x) ((x) << S_T_EXSR) dev/cxgbe/common/t4_regs.h:#define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR) dev/cxgbe/common/t4_regs.h:#define V_T_XP(x) ((x) << S_T_XP) dev/cxgbe/common/t4_regs.h:#define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP) dev/cxgbe/common/t4_regs.h:#define V_T_XPDLL(x) ((x) << S_T_XPDLL) dev/cxgbe/common/t4_regs.h:#define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL) dev/cxgbe/common/t4_regs.h:#define V_T_ZQCS(x) ((x) << S_T_ZQCS) dev/cxgbe/common/t4_regs.h:#define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS) dev/cxgbe/common/t4_regs.h:#define V_T_ZQCSI(x) ((x) << S_T_ZQCSI) dev/cxgbe/common/t4_regs.h:#define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI) dev/cxgbe/common/t4_regs.h:#define V_T_DQS(x) ((x) << S_T_DQS) dev/cxgbe/common/t4_regs.h:#define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS) dev/cxgbe/common/t4_regs.h:#define V_T_CKSRE(x) ((x) << S_T_CKSRE) dev/cxgbe/common/t4_regs.h:#define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE) dev/cxgbe/common/t4_regs.h:#define V_T_CKSRX(x) ((x) << S_T_CKSRX) dev/cxgbe/common/t4_regs.h:#define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX) dev/cxgbe/common/t4_regs.h:#define V_T_CKE(x) ((x) << S_T_CKE) dev/cxgbe/common/t4_regs.h:#define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE) dev/cxgbe/common/t4_regs.h:#define V_T_MOD(x) ((x) << S_T_MOD) dev/cxgbe/common/t4_regs.h:#define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD) dev/cxgbe/common/t4_regs.h:#define V_RSTHOLD(x) ((x) << S_RSTHOLD) dev/cxgbe/common/t4_regs.h:#define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD) dev/cxgbe/common/t4_regs.h:#define V_T_ZQCL(x) ((x) << S_T_ZQCL) dev/cxgbe/common/t4_regs.h:#define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL) dev/cxgbe/common/t4_regs.h:#define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC) dev/cxgbe/common/t4_regs.h:#define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC) dev/cxgbe/common/t4_regs.h:#define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK) dev/cxgbe/common/t4_regs.h:#define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK) dev/cxgbe/common/t4_regs.h:#define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK) dev/cxgbe/common/t4_regs.h:#define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK) dev/cxgbe/common/t4_regs.h:#define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW) dev/cxgbe/common/t4_regs.h:#define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW) dev/cxgbe/common/t4_regs.h:#define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK) dev/cxgbe/common/t4_regs.h:#define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK) dev/cxgbe/common/t4_regs.h:#define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL) dev/cxgbe/common/t4_regs.h:#define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL) dev/cxgbe/common/t4_regs.h:#define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK) dev/cxgbe/common/t4_regs.h:#define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK) dev/cxgbe/common/t4_regs.h:#define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW) dev/cxgbe/common/t4_regs.h:#define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW) dev/cxgbe/common/t4_regs.h:#define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK) dev/cxgbe/common/t4_regs.h:#define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK) dev/cxgbe/common/t4_regs.h:#define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL) dev/cxgbe/common/t4_regs.h:#define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL) dev/cxgbe/common/t4_regs.h:#define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS) dev/cxgbe/common/t4_regs.h:#define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS) dev/cxgbe/common/t4_regs.h:#define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE) dev/cxgbe/common/t4_regs.h:#define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE) dev/cxgbe/common/t4_regs.h:#define V_DTU_NALEN(x) ((x) << S_DTU_NALEN) dev/cxgbe/common/t4_regs.h:#define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN) dev/cxgbe/common/t4_regs.h:#define V_EA_RANK(x) ((x) << S_EA_RANK) dev/cxgbe/common/t4_regs.h:#define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK) dev/cxgbe/common/t4_regs.h:#define V_EA_ROW(x) ((x) << S_EA_ROW) dev/cxgbe/common/t4_regs.h:#define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW) dev/cxgbe/common/t4_regs.h:#define V_EA_BANK(x) ((x) << S_EA_BANK) dev/cxgbe/common/t4_regs.h:#define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK) dev/cxgbe/common/t4_regs.h:#define V_EA_COLUMN(x) ((x) << S_EA_COLUMN) dev/cxgbe/common/t4_regs.h:#define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN) dev/cxgbe/common/t4_regs.h:#define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE) dev/cxgbe/common/t4_regs.h:#define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE) dev/cxgbe/common/t4_regs.h:#define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE) dev/cxgbe/common/t4_regs.h:#define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE) dev/cxgbe/common/t4_regs.h:#define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON) dev/cxgbe/common/t4_regs.h:#define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON) dev/cxgbe/common/t4_regs.h:#define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY) dev/cxgbe/common/t4_regs.h:#define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY) dev/cxgbe/common/t4_regs.h:#define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON) dev/cxgbe/common/t4_regs.h:#define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON) dev/cxgbe/common/t4_regs.h:#define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY) dev/cxgbe/common/t4_regs.h:#define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY) dev/cxgbe/common/t4_regs.h:#define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI) dev/cxgbe/common/t4_regs.h:#define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI) dev/cxgbe/common/t4_regs.h:#define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL) dev/cxgbe/common/t4_regs.h:#define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL) dev/cxgbe/common/t4_regs.h:#define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT) dev/cxgbe/common/t4_regs.h:#define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT) dev/cxgbe/common/t4_regs.h:#define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN) dev/cxgbe/common/t4_regs.h:#define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN) dev/cxgbe/common/t4_regs.h:#define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT) dev/cxgbe/common/t4_regs.h:#define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT) dev/cxgbe/common/t4_regs.h:#define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT) dev/cxgbe/common/t4_regs.h:#define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT) dev/cxgbe/common/t4_regs.h:#define V_WLRANK(x) ((x) << S_WLRANK) dev/cxgbe/common/t4_regs.h:#define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK) dev/cxgbe/common/t4_regs.h:#define V_FDEPTH(x) ((x) << S_FDEPTH) dev/cxgbe/common/t4_regs.h:#define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH) dev/cxgbe/common/t4_regs.h:#define V_LPFDEPTH(x) ((x) << S_LPFDEPTH) dev/cxgbe/common/t4_regs.h:#define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH) dev/cxgbe/common/t4_regs.h:#define V_PRD(x) ((x) << S_PRD) dev/cxgbe/common/t4_regs.h:#define G_PRD(x) (((x) >> S_PRD) & M_PRD) dev/cxgbe/common/t4_regs.h:#define V_DFLTDLY(x) ((x) << S_DFLTDLY) dev/cxgbe/common/t4_regs.h:#define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY) dev/cxgbe/common/t4_regs.h:#define V_ISEL(x) ((x) << S_ISEL) dev/cxgbe/common/t4_regs.h:#define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL) dev/cxgbe/common/t4_regs.h:#define V_PSCALE(x) ((x) << S_PSCALE) dev/cxgbe/common/t4_regs.h:#define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE) dev/cxgbe/common/t4_regs.h:#define V_RSTCLKS(x) ((x) << S_RSTCLKS) dev/cxgbe/common/t4_regs.h:#define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS) dev/cxgbe/common/t4_regs.h:#define V_RSTCXKS(x) ((x) << S_RSTCXKS) dev/cxgbe/common/t4_regs.h:#define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS) dev/cxgbe/common/t4_regs.h:#define V_TESTA(x) ((x) << S_TESTA) dev/cxgbe/common/t4_regs.h:#define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA) dev/cxgbe/common/t4_regs.h:#define V_BDIV(x) ((x) << S_BDIV) dev/cxgbe/common/t4_regs.h:#define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV) dev/cxgbe/common/t4_regs.h:#define V_TESTD(x) ((x) << S_TESTD) dev/cxgbe/common/t4_regs.h:#define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD) dev/cxgbe/common/t4_regs.h:#define V_CKCLKEN(x) ((x) << S_CKCLKEN) dev/cxgbe/common/t4_regs.h:#define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN) dev/cxgbe/common/t4_regs.h:#define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY) dev/cxgbe/common/t4_regs.h:#define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY) dev/cxgbe/common/t4_regs.h:#define V_WL_DLY(x) ((x) << S_WL_DLY) dev/cxgbe/common/t4_regs.h:#define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY) dev/cxgbe/common/t4_regs.h:#define V_DLY(x) ((x) << S_DLY) dev/cxgbe/common/t4_regs.h:#define G_DLY(x) (((x) >> S_DLY) & M_DLY) dev/cxgbe/common/t4_regs.h:#define V_MAXDLY(x) ((x) << S_MAXDLY) dev/cxgbe/common/t4_regs.h:#define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY) dev/cxgbe/common/t4_regs.h:#define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY) dev/cxgbe/common/t4_regs.h:#define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY) dev/cxgbe/common/t4_regs.h:#define V_DP_DLY(x) ((x) << S_DP_DLY) dev/cxgbe/common/t4_regs.h:#define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY) dev/cxgbe/common/t4_regs.h:#define V_RANK(x) ((x) << S_RANK) dev/cxgbe/common/t4_regs.h:#define G_RANK(x) (((x) >> S_RANK) & M_RANK) dev/cxgbe/common/t4_regs.h:#define V_DTOSEL(x) ((x) << S_DTOSEL) dev/cxgbe/common/t4_regs.h:#define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL) dev/cxgbe/common/t4_regs.h:#define V_ECC_UECNT(x) ((x) << S_ECC_UECNT) dev/cxgbe/common/t4_regs.h:#define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT) dev/cxgbe/common/t4_regs.h:#define V_STATIC_DEN(x) ((x) << S_STATIC_DEN) dev/cxgbe/common/t4_regs.h:#define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN) dev/cxgbe/common/t4_regs.h:#define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH) dev/cxgbe/common/t4_regs.h:#define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH) dev/cxgbe/common/t4_regs.h:#define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT) dev/cxgbe/common/t4_regs.h:#define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT) dev/cxgbe/common/t4_regs.h:#define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT) dev/cxgbe/common/t4_regs.h:#define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT) dev/cxgbe/common/t4_regs.h:#define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT) dev/cxgbe/common/t4_regs.h:#define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT) dev/cxgbe/common/t4_regs.h:#define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP) dev/cxgbe/common/t4_regs.h:#define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE) dev/cxgbe/common/t4_regs.h:#define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE) dev/cxgbe/common/t4_regs.h:#define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT) dev/cxgbe/common/t4_regs.h:#define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT) dev/cxgbe/common/t4_regs.h:#define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT) dev/cxgbe/common/t4_regs.h:#define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT) dev/cxgbe/common/t4_regs.h:#define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT) dev/cxgbe/common/t4_regs.h:#define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT) dev/cxgbe/common/t4_regs.h:#define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT) dev/cxgbe/common/t4_regs.h:#define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT) dev/cxgbe/common/t4_regs.h:#define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE) dev/cxgbe/common/t4_regs.h:#define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE) dev/cxgbe/common/t4_regs.h:#define V_HMA_BASE(x) ((x) << S_HMA_BASE) dev/cxgbe/common/t4_regs.h:#define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE) dev/cxgbe/common/t4_regs.h:#define V_HMA_SIZE(x) ((x) << S_HMA_SIZE) dev/cxgbe/common/t4_regs.h:#define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE) dev/cxgbe/common/t4_regs.h:#define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE) dev/cxgbe/common/t4_regs.h:#define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE) dev/cxgbe/common/t4_regs.h:#define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS) dev/cxgbe/common/t4_regs.h:#define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM) dev/cxgbe/common/t4_regs.h:#define V_BONUS_REG(x) ((x) << S_BONUS_REG) dev/cxgbe/common/t4_regs.h:#define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG) dev/cxgbe/common/t4_regs.h:#define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE) dev/cxgbe/common/t4_regs.h:#define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE) dev/cxgbe/common/t4_regs.h:#define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM) dev/cxgbe/common/t4_regs.h:#define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_EXPANSION_EE(x) ((x) << S_FUTURE_EXPANSION_EE) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_EXPANSION_EE(x) (((x) >> S_FUTURE_EXPANSION_EE) & M_FUTURE_EXPANSION_EE) dev/cxgbe/common/t4_regs.h:#define V_FL_LIMIT(x) ((x) << S_FL_LIMIT) dev/cxgbe/common/t4_regs.h:#define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT) dev/cxgbe/common/t4_regs.h:#define V_MEM_WIDTH(x) ((x) << S_MEM_WIDTH) dev/cxgbe/common/t4_regs.h:#define G_MEM_WIDTH(x) (((x) >> S_MEM_WIDTH) & M_MEM_WIDTH) dev/cxgbe/common/t4_regs.h:#define V_CLIENT(x) ((x) << S_CLIENT) dev/cxgbe/common/t4_regs.h:#define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT) dev/cxgbe/common/t4_regs.h:#define V_DELAY(x) ((x) << S_DELAY) dev/cxgbe/common/t4_regs.h:#define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY) dev/cxgbe/common/t4_regs.h:#define V_CNT_VAL(x) ((x) << S_CNT_VAL) dev/cxgbe/common/t4_regs.h:#define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_CEXPANSION_WTE(x) ((x) << S_FUTURE_CEXPANSION_WTE) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_CEXPANSION_WTE(x) (((x) >> S_FUTURE_CEXPANSION_WTE) & M_FUTURE_CEXPANSION_WTE) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_CEXPANSION_WTS(x) ((x) << S_FUTURE_CEXPANSION_WTS) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_CEXPANSION_WTS(x) (((x) >> S_FUTURE_CEXPANSION_WTS) & M_FUTURE_CEXPANSION_WTS) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_CEXPANSION_RTE(x) ((x) << S_FUTURE_CEXPANSION_RTE) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_CEXPANSION_RTE(x) (((x) >> S_FUTURE_CEXPANSION_RTE) & M_FUTURE_CEXPANSION_RTE) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_CEXPANSION_RTS(x) ((x) << S_FUTURE_CEXPANSION_RTS) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_CEXPANSION_RTS(x) (((x) >> S_FUTURE_CEXPANSION_RTS) & M_FUTURE_CEXPANSION_RTS) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS) dev/cxgbe/common/t4_regs.h:#define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE) dev/cxgbe/common/t4_regs.h:#define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE) dev/cxgbe/common/t4_regs.h:#define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT) dev/cxgbe/common/t4_regs.h:#define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT) dev/cxgbe/common/t4_regs.h:#define V_WR_TIM(x) ((x) << S_WR_TIM) dev/cxgbe/common/t4_regs.h:#define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM) dev/cxgbe/common/t4_regs.h:#define V_RD_WIN(x) ((x) << S_RD_WIN) dev/cxgbe/common/t4_regs.h:#define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN) dev/cxgbe/common/t4_regs.h:#define V_WR_WIN(x) ((x) << S_WR_WIN) dev/cxgbe/common/t4_regs.h:#define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE) dev/cxgbe/common/t4_regs.h:#define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS) dev/cxgbe/common/t4_regs.h:#define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS) dev/cxgbe/common/t4_regs.h:#define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE) dev/cxgbe/common/t4_regs.h:#define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE) dev/cxgbe/common/t4_regs.h:#define V_PTFLITCNT(x) ((x) << S_PTFLITCNT) dev/cxgbe/common/t4_regs.h:#define G_PTFLITCNT(x) (((x) >> S_PTFLITCNT) & M_PTFLITCNT) dev/cxgbe/common/t4_regs.h:#define V_PRFLITCNT(x) ((x) << S_PRFLITCNT) dev/cxgbe/common/t4_regs.h:#define G_PRFLITCNT(x) (((x) >> S_PRFLITCNT) & M_PRFLITCNT) dev/cxgbe/common/t4_regs.h:#define V_REFFREQ(x) ((x) << S_REFFREQ) dev/cxgbe/common/t4_regs.h:#define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ) dev/cxgbe/common/t4_regs.h:#define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC) dev/cxgbe/common/t4_regs.h:#define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC) dev/cxgbe/common/t4_regs.h:#define V_MBGENERIC(x) ((x) << S_MBGENERIC) dev/cxgbe/common/t4_regs.h:#define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC) dev/cxgbe/common/t4_regs.h:#define V_UPGEN(x) ((x) << S_UPGEN) dev/cxgbe/common/t4_regs.h:#define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN) dev/cxgbe/common/t4_regs.h:#define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR) dev/cxgbe/common/t4_regs.h:#define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR) dev/cxgbe/common/t4_regs.h:#define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE) dev/cxgbe/common/t4_regs.h:#define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE) dev/cxgbe/common/t4_regs.h:#define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT) dev/cxgbe/common/t4_regs.h:#define V_CIMQSIZE(x) ((x) << S_CIMQSIZE) dev/cxgbe/common/t4_regs.h:#define V_CIMQBASE(x) ((x) << S_CIMQBASE) dev/cxgbe/common/t4_regs.h:#define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH) dev/cxgbe/common/t4_regs.h:#define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA) dev/cxgbe/common/t4_regs.h:#define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA) dev/cxgbe/common/t4_regs.h:#define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA) dev/cxgbe/common/t4_regs.h:#define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA) dev/cxgbe/common/t4_regs.h:#define V_ZONE_DST(x) ((x) << S_ZONE_DST) dev/cxgbe/common/t4_regs.h:#define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST) dev/cxgbe/common/t4_regs.h:#define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN) dev/cxgbe/common/t4_regs.h:#define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN) dev/cxgbe/common/t4_regs.h:#define V_BOOTLEN(x) ((x) << S_BOOTLEN) dev/cxgbe/common/t4_regs.h:#define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN) dev/cxgbe/common/t4_regs.h:#define V_GLBLTTICK(x) ((x) << S_GLBLTTICK) dev/cxgbe/common/t4_regs.h:#define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK) dev/cxgbe/common/t4_regs.h:#define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT) dev/cxgbe/common/t4_regs.h:#define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT) dev/cxgbe/common/t4_regs.h:#define V_DADDRTIMEOUTTYPE(x) ((x) << S_DADDRTIMEOUTTYPE) dev/cxgbe/common/t4_regs.h:#define G_DADDRTIMEOUTTYPE(x) (((x) >> S_DADDRTIMEOUTTYPE) & M_DADDRTIMEOUTTYPE) dev/cxgbe/common/t4_regs.h:#define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL) dev/cxgbe/common/t4_regs.h:#define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL) dev/cxgbe/common/t4_regs.h:#define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE) dev/cxgbe/common/t4_regs.h:#define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE) dev/cxgbe/common/t4_regs.h:#define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK) dev/cxgbe/common/t4_regs.h:#define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK) dev/cxgbe/common/t4_regs.h:#define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK) dev/cxgbe/common/t4_regs.h:#define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK) dev/cxgbe/common/t4_regs.h:#define V_DUPMASK(x) ((x) << S_DUPMASK) dev/cxgbe/common/t4_regs.h:#define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK) dev/cxgbe/common/t4_regs.h:#define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK) dev/cxgbe/common/t4_regs.h:#define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK) dev/cxgbe/common/t4_regs.h:#define V_PERREN(x) ((x) << S_PERREN) dev/cxgbe/common/t4_regs.h:#define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN) dev/cxgbe/common/t4_regs.h:#define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE) dev/cxgbe/common/t4_regs.h:#define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE) dev/cxgbe/common/t4_regs.h:#define V_CIM_PCIE_PKT_ERR_CODE(x) ((x) << S_CIM_PCIE_PKT_ERR_CODE) dev/cxgbe/common/t4_regs.h:#define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE) dev/cxgbe/common/t4_regs.h:#define V_PORTQFCEN(x) ((x) << S_PORTQFCEN) dev/cxgbe/common/t4_regs.h:#define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN) dev/cxgbe/common/t4_regs.h:#define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT) dev/cxgbe/common/t4_regs.h:#define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT) dev/cxgbe/common/t4_regs.h:#define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT) dev/cxgbe/common/t4_regs.h:#define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE) dev/cxgbe/common/t4_regs.h:#define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE) dev/cxgbe/common/t4_regs.h:#define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE) dev/cxgbe/common/t4_regs.h:#define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE) dev/cxgbe/common/t4_regs.h:#define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN) dev/cxgbe/common/t4_regs.h:#define V_TSMPMODE(x) ((x) << S_TSMPMODE) dev/cxgbe/common/t4_regs.h:#define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE) dev/cxgbe/common/t4_regs.h:#define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT) dev/cxgbe/common/t4_regs.h:#define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT) dev/cxgbe/common/t4_regs.h:#define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH) dev/cxgbe/common/t4_regs.h:#define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH) dev/cxgbe/common/t4_regs.h:#define V_ECNTHRESH(x) ((x) << S_ECNTHRESH) dev/cxgbe/common/t4_regs.h:#define G_ECNTHRESH(x) (((x) >> S_ECNTHRESH) & M_ECNTHRESH) dev/cxgbe/common/t4_regs.h:#define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED) dev/cxgbe/common/t4_regs.h:#define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED) dev/cxgbe/common/t4_regs.h:#define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO) dev/cxgbe/common/t4_regs.h:#define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO) dev/cxgbe/common/t4_regs.h:#define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE) dev/cxgbe/common/t4_regs.h:#define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE) dev/cxgbe/common/t4_regs.h:#define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO) dev/cxgbe/common/t4_regs.h:#define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO) dev/cxgbe/common/t4_regs.h:#define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE) dev/cxgbe/common/t4_regs.h:#define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE) dev/cxgbe/common/t4_regs.h:#define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT) dev/cxgbe/common/t4_regs.h:#define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT) dev/cxgbe/common/t4_regs.h:#define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE) dev/cxgbe/common/t4_regs.h:#define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE) dev/cxgbe/common/t4_regs.h:#define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART) dev/cxgbe/common/t4_regs.h:#define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART) dev/cxgbe/common/t4_regs.h:#define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA) dev/cxgbe/common/t4_regs.h:#define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA) dev/cxgbe/common/t4_regs.h:#define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR) dev/cxgbe/common/t4_regs.h:#define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR) dev/cxgbe/common/t4_regs.h:#define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE) dev/cxgbe/common/t4_regs.h:#define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE) dev/cxgbe/common/t4_regs.h:#define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE) dev/cxgbe/common/t4_regs.h:#define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE) dev/cxgbe/common/t4_regs.h:#define V_MAXRTT(x) ((x) << S_MAXRTT) dev/cxgbe/common/t4_regs.h:#define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT) dev/cxgbe/common/t4_regs.h:#define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX) dev/cxgbe/common/t4_regs.h:#define V_ROWVALUE(x) ((x) << S_ROWVALUE) dev/cxgbe/common/t4_regs.h:#define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE) dev/cxgbe/common/t4_regs.h:#define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX) dev/cxgbe/common/t4_regs.h:#define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX) dev/cxgbe/common/t4_regs.h:#define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX) dev/cxgbe/common/t4_regs.h:#define V_MASKFILTER(x) ((x) << S_MASKFILTER) dev/cxgbe/common/t4_regs.h:#define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER) dev/cxgbe/common/t4_regs.h:#define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH) dev/cxgbe/common/t4_regs.h:#define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH) dev/cxgbe/common/t4_regs.h:#define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK) dev/cxgbe/common/t4_regs.h:#define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK) dev/cxgbe/common/t4_regs.h:#define V_HASHDELAY(x) ((x) << S_HASHDELAY) dev/cxgbe/common/t4_regs.h:#define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY) dev/cxgbe/common/t4_regs.h:#define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR) dev/cxgbe/common/t4_regs.h:#define V_KEYMODE(x) ((x) << S_KEYMODE) dev/cxgbe/common/t4_regs.h:#define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR) dev/cxgbe/common/t4_regs.h:#define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX) dev/cxgbe/common/t4_regs.h:#define V_QUEUE(x) ((x) << S_QUEUE) dev/cxgbe/common/t4_regs.h:#define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE) dev/cxgbe/common/t4_regs.h:#define V_TIMERMODE(x) ((x) << S_TIMERMODE) dev/cxgbe/common/t4_regs.h:#define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN) dev/cxgbe/common/t4_regs.h:#define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN) dev/cxgbe/common/t4_regs.h:#define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN) dev/cxgbe/common/t4_regs.h:#define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN) dev/cxgbe/common/t4_regs.h:#define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR) dev/cxgbe/common/t4_regs.h:#define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR) dev/cxgbe/common/t4_regs.h:#define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE) dev/cxgbe/common/t4_regs.h:#define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE) dev/cxgbe/common/t4_regs.h:#define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR) dev/cxgbe/common/t4_regs.h:#define V_DBGLAMODE(x) ((x) << S_DBGLAMODE) dev/cxgbe/common/t4_regs.h:#define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR) dev/cxgbe/common/t4_regs.h:#define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT) dev/cxgbe/common/t4_regs.h:#define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT) dev/cxgbe/common/t4_regs.h:#define V_LINEADDRESS(x) ((x) << S_LINEADDRESS) dev/cxgbe/common/t4_regs.h:#define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS) dev/cxgbe/common/t4_regs.h:#define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD) dev/cxgbe/common/t4_regs.h:#define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD) dev/cxgbe/common/t4_regs.h:#define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN) dev/cxgbe/common/t4_regs.h:#define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN) dev/cxgbe/common/t4_regs.h:#define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN) dev/cxgbe/common/t4_regs.h:#define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN) dev/cxgbe/common/t4_regs.h:#define V_IVFWIDTH(x) ((x) << S_IVFWIDTH) dev/cxgbe/common/t4_regs.h:#define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH) dev/cxgbe/common/t4_regs.h:#define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE) dev/cxgbe/common/t4_regs.h:#define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE) dev/cxgbe/common/t4_regs.h:#define V_VFLKPIDX(x) ((x) << S_VFLKPIDX) dev/cxgbe/common/t4_regs.h:#define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX) dev/cxgbe/common/t4_regs.h:#define V_KEYINDEX(x) ((x) << S_KEYINDEX) dev/cxgbe/common/t4_regs.h:#define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX) dev/cxgbe/common/t4_regs.h:#define V_CQFCTYPE(x) ((x) << S_CQFCTYPE) dev/cxgbe/common/t4_regs.h:#define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE) dev/cxgbe/common/t4_regs.h:#define V_VLANTYPE(x) ((x) << S_VLANTYPE) dev/cxgbe/common/t4_regs.h:#define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE) dev/cxgbe/common/t4_regs.h:#define V_VXLANPORT(x) ((x) << S_VXLANPORT) dev/cxgbe/common/t4_regs.h:#define G_VXLANPORT(x) (((x) >> S_VXLANPORT) & M_VXLANPORT) dev/cxgbe/common/t4_regs.h:#define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP) dev/cxgbe/common/t4_regs.h:#define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP) dev/cxgbe/common/t4_regs.h:#define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE) dev/cxgbe/common/t4_regs.h:#define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE) dev/cxgbe/common/t4_regs.h:#define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP) dev/cxgbe/common/t4_regs.h:#define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP) dev/cxgbe/common/t4_regs.h:#define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP) dev/cxgbe/common/t4_regs.h:#define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP) dev/cxgbe/common/t4_regs.h:#define V_TLSMODE(x) ((x) << S_TLSMODE) dev/cxgbe/common/t4_regs.h:#define G_TLSMODE(x) (((x) >> S_TLSMODE) & M_TLSMODE) dev/cxgbe/common/t4_regs.h:#define V_USERMODE(x) ((x) << S_USERMODE) dev/cxgbe/common/t4_regs.h:#define G_USERMODE(x) (((x) >> S_USERMODE) & M_USERMODE) dev/cxgbe/common/t4_regs.h:#define V_FCOEMODE(x) ((x) << S_FCOEMODE) dev/cxgbe/common/t4_regs.h:#define G_FCOEMODE(x) (((x) >> S_FCOEMODE) & M_FCOEMODE) dev/cxgbe/common/t4_regs.h:#define V_IANDPMODE(x) ((x) << S_IANDPMODE) dev/cxgbe/common/t4_regs.h:#define G_IANDPMODE(x) (((x) >> S_IANDPMODE) & M_IANDPMODE) dev/cxgbe/common/t4_regs.h:#define V_RDDPMODE(x) ((x) << S_RDDPMODE) dev/cxgbe/common/t4_regs.h:#define G_RDDPMODE(x) (((x) >> S_RDDPMODE) & M_RDDPMODE) dev/cxgbe/common/t4_regs.h:#define V_IWARPMODE(x) ((x) << S_IWARPMODE) dev/cxgbe/common/t4_regs.h:#define G_IWARPMODE(x) (((x) >> S_IWARPMODE) & M_IWARPMODE) dev/cxgbe/common/t4_regs.h:#define V_ISCSIMODE(x) ((x) << S_ISCSIMODE) dev/cxgbe/common/t4_regs.h:#define G_ISCSIMODE(x) (((x) >> S_ISCSIMODE) & M_ISCSIMODE) dev/cxgbe/common/t4_regs.h:#define V_DDPMODE(x) ((x) << S_DDPMODE) dev/cxgbe/common/t4_regs.h:#define G_DDPMODE(x) (((x) >> S_DDPMODE) & M_DDPMODE) dev/cxgbe/common/t4_regs.h:#define V_PASSMODE(x) ((x) << S_PASSMODE) dev/cxgbe/common/t4_regs.h:#define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE) dev/cxgbe/common/t4_regs.h:#define V_WRCNTIDLE(x) ((x) << S_WRCNTIDLE) dev/cxgbe/common/t4_regs.h:#define G_WRCNTIDLE(x) (((x) >> S_WRCNTIDLE) & M_WRCNTIDLE) dev/cxgbe/common/t4_regs.h:#define G_RDTHRESHOLD(x) (((x) >> S_RDTHRESHOLD) & M_RDTHRESHOLD) dev/cxgbe/common/t4_regs.h:#define G_WRTHRTHRESH(x) (((x) >> S_WRTHRTHRESH) & M_WRTHRTHRESH) dev/cxgbe/common/t4_regs.h:#define V_VXLANFLAGS(x) ((x) << S_VXLANFLAGS) dev/cxgbe/common/t4_regs.h:#define G_VXLANFLAGS(x) (((x) >> S_VXLANFLAGS) & M_VXLANFLAGS) dev/cxgbe/common/t4_regs.h:#define V_VXLANTYPE(x) ((x) << S_VXLANTYPE) dev/cxgbe/common/t4_regs.h:#define G_VXLANTYPE(x) (((x) >> S_VXLANTYPE) & M_VXLANTYPE) dev/cxgbe/common/t4_regs.h:#define V_GREFLAGS(x) ((x) << S_GREFLAGS) dev/cxgbe/common/t4_regs.h:#define G_GREFLAGS(x) (((x) >> S_GREFLAGS) & M_GREFLAGS) dev/cxgbe/common/t4_regs.h:#define V_GRETYPE(x) ((x) << S_GRETYPE) dev/cxgbe/common/t4_regs.h:#define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE) dev/cxgbe/common/t4_regs.h:#define V_CPCMDCONG(x) ((x) << S_CPCMDCONG) dev/cxgbe/common/t4_regs.h:#define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG) dev/cxgbe/common/t4_regs.h:#define V_EPCMDCONG(x) ((x) << S_EPCMDCONG) dev/cxgbe/common/t4_regs.h:#define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG) dev/cxgbe/common/t4_regs.h:#define V_CPCMDVALID(x) ((x) << S_CPCMDVALID) dev/cxgbe/common/t4_regs.h:#define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID) dev/cxgbe/common/t4_regs.h:#define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL) dev/cxgbe/common/t4_regs.h:#define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL) dev/cxgbe/common/t4_regs.h:#define V_EPCMDVALID(x) ((x) << S_EPCMDVALID) dev/cxgbe/common/t4_regs.h:#define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID) dev/cxgbe/common/t4_regs.h:#define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL) dev/cxgbe/common/t4_regs.h:#define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL) dev/cxgbe/common/t4_regs.h:#define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT) dev/cxgbe/common/t4_regs.h:#define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT) dev/cxgbe/common/t4_regs.h:#define V_LINENUMBER(x) ((x) << S_LINENUMBER) dev/cxgbe/common/t4_regs.h:#define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER) dev/cxgbe/common/t4_regs.h:#define V_TIDVALUE(x) ((x) << S_TIDVALUE) dev/cxgbe/common/t4_regs.h:#define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE) dev/cxgbe/common/t4_regs.h:#define V_SRC(x) ((x) << S_SRC) dev/cxgbe/common/t4_regs.h:#define G_SRC(x) (((x) >> S_SRC) & M_SRC) dev/cxgbe/common/t4_regs.h:#define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT) dev/cxgbe/common/t4_regs.h:#define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT) dev/cxgbe/common/t4_regs.h:#define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT) dev/cxgbe/common/t4_regs.h:#define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT) dev/cxgbe/common/t4_regs.h:#define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT) dev/cxgbe/common/t4_regs.h:#define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT) dev/cxgbe/common/t4_regs.h:#define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT) dev/cxgbe/common/t4_regs.h:#define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT) dev/cxgbe/common/t4_regs.h:#define V_CPLCMDIN(x) ((x) << S_CPLCMDIN) dev/cxgbe/common/t4_regs.h:#define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN) dev/cxgbe/common/t4_regs.h:#define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY) dev/cxgbe/common/t4_regs.h:#define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY) dev/cxgbe/common/t4_regs.h:#define V_ENGINESTATE(x) ((x) << S_ENGINESTATE) dev/cxgbe/common/t4_regs.h:#define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE) dev/cxgbe/common/t4_regs.h:#define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW) dev/cxgbe/common/t4_regs.h:#define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW) dev/cxgbe/common/t4_regs.h:#define V_RXMACPORT(x) ((x) << S_RXMACPORT) dev/cxgbe/common/t4_regs.h:#define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT) dev/cxgbe/common/t4_regs.h:#define V_TXECHANNEL(x) ((x) << S_TXECHANNEL) dev/cxgbe/common/t4_regs.h:#define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL) dev/cxgbe/common/t4_regs.h:#define V_RXECHANNEL(x) ((x) << S_RXECHANNEL) dev/cxgbe/common/t4_regs.h:#define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL) dev/cxgbe/common/t4_regs.h:#define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL) dev/cxgbe/common/t4_regs.h:#define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL) dev/cxgbe/common/t4_regs.h:#define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL) dev/cxgbe/common/t4_regs.h:#define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL) dev/cxgbe/common/t4_regs.h:#define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT) dev/cxgbe/common/t4_regs.h:#define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT) dev/cxgbe/common/t4_regs.h:#define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE) dev/cxgbe/common/t4_regs.h:#define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE) dev/cxgbe/common/t4_regs.h:#define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE) dev/cxgbe/common/t4_regs.h:#define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE) dev/cxgbe/common/t4_regs.h:#define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF) dev/cxgbe/common/t4_regs.h:#define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF) dev/cxgbe/common/t4_regs.h:#define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG) dev/cxgbe/common/t4_regs.h:#define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG) dev/cxgbe/common/t4_regs.h:#define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG) dev/cxgbe/common/t4_regs.h:#define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG) dev/cxgbe/common/t4_regs.h:#define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG) dev/cxgbe/common/t4_regs.h:#define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG) dev/cxgbe/common/t4_regs.h:#define V_TXHDRCNG(x) ((x) << S_TXHDRCNG) dev/cxgbe/common/t4_regs.h:#define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG) dev/cxgbe/common/t4_regs.h:#define V_TXMODXOFF(x) ((x) << S_TXMODXOFF) dev/cxgbe/common/t4_regs.h:#define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF) dev/cxgbe/common/t4_regs.h:#define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF) dev/cxgbe/common/t4_regs.h:#define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF) dev/cxgbe/common/t4_regs.h:#define V_RXSGECNG(x) ((x) << S_RXSGECNG) dev/cxgbe/common/t4_regs.h:#define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG) dev/cxgbe/common/t4_regs.h:#define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG) dev/cxgbe/common/t4_regs.h:#define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG) dev/cxgbe/common/t4_regs.h:#define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG) dev/cxgbe/common/t4_regs.h:#define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG) dev/cxgbe/common/t4_regs.h:#define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG) dev/cxgbe/common/t4_regs.h:#define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG) dev/cxgbe/common/t4_regs.h:#define V_RXHDRCNG(x) ((x) << S_RXHDRCNG) dev/cxgbe/common/t4_regs.h:#define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG) dev/cxgbe/common/t4_regs.h:#define V_RXMODXOFF(x) ((x) << S_RXMODXOFF) dev/cxgbe/common/t4_regs.h:#define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF) dev/cxgbe/common/t4_regs.h:#define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_STATE(x) ((x) << S_STATE) dev/cxgbe/common/t4_regs.h:#define G_STATE(x) (((x) >> S_STATE) & M_STATE) dev/cxgbe/common/t4_regs.h:#define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT) dev/cxgbe/common/t4_regs.h:#define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT) dev/cxgbe/common/t4_regs.h:#define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT) dev/cxgbe/common/t4_regs.h:#define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT) dev/cxgbe/common/t4_regs.h:#define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT) dev/cxgbe/common/t4_regs.h:#define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT) dev/cxgbe/common/t4_regs.h:#define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT) dev/cxgbe/common/t4_regs.h:#define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT) dev/cxgbe/common/t4_regs.h:#define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT) dev/cxgbe/common/t4_regs.h:#define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT) dev/cxgbe/common/t4_regs.h:#define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR) dev/cxgbe/common/t4_regs.h:#define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR) dev/cxgbe/common/t4_regs.h:#define V_MAPINDEX(x) ((x) << S_MAPINDEX) dev/cxgbe/common/t4_regs.h:#define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX) dev/cxgbe/common/t4_regs.h:#define V_MAPVALUERD(x) ((x) << S_MAPVALUERD) dev/cxgbe/common/t4_regs.h:#define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD) dev/cxgbe/common/t4_regs.h:#define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_IPSOPCNT(x) ((x) << S_IPSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_IPEOPCNT(x) ((x) << S_IPEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE) dev/cxgbe/common/t4_regs.h:#define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE) dev/cxgbe/common/t4_regs.h:#define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_CPLLIMIT(x) ((x) << S_CPLLIMIT) dev/cxgbe/common/t4_regs.h:#define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT) dev/cxgbe/common/t4_regs.h:#define V_ETHLIMIT(x) ((x) << S_ETHLIMIT) dev/cxgbe/common/t4_regs.h:#define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT) dev/cxgbe/common/t4_regs.h:#define V_IPLIMIT(x) ((x) << S_IPLIMIT) dev/cxgbe/common/t4_regs.h:#define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT) dev/cxgbe/common/t4_regs.h:#define V_TCPLIMIT(x) ((x) << S_TCPLIMIT) dev/cxgbe/common/t4_regs.h:#define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT) dev/cxgbe/common/t4_regs.h:#define V_EALLDONE(x) ((x) << S_EALLDONE) dev/cxgbe/common/t4_regs.h:#define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE) dev/cxgbe/common/t4_regs.h:#define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE) dev/cxgbe/common/t4_regs.h:#define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE) dev/cxgbe/common/t4_regs.h:#define V_EDBDONE(x) ((x) << S_EDBDONE) dev/cxgbe/common/t4_regs.h:#define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE) dev/cxgbe/common/t4_regs.h:#define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE) dev/cxgbe/common/t4_regs.h:#define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE) dev/cxgbe/common/t4_regs.h:#define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE) dev/cxgbe/common/t4_regs.h:#define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE) dev/cxgbe/common/t4_regs.h:#define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE) dev/cxgbe/common/t4_regs.h:#define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE) dev/cxgbe/common/t4_regs.h:#define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE) dev/cxgbe/common/t4_regs.h:#define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE) dev/cxgbe/common/t4_regs.h:#define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE) dev/cxgbe/common/t4_regs.h:#define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE) dev/cxgbe/common/t4_regs.h:#define V_ETXERROR(x) ((x) << S_ETXERROR) dev/cxgbe/common/t4_regs.h:#define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR) dev/cxgbe/common/t4_regs.h:#define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR) dev/cxgbe/common/t4_regs.h:#define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR) dev/cxgbe/common/t4_regs.h:#define V_ETXVALID(x) ((x) << S_ETXVALID) dev/cxgbe/common/t4_regs.h:#define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID) dev/cxgbe/common/t4_regs.h:#define V_ETXFULL(x) ((x) << S_ETXFULL) dev/cxgbe/common/t4_regs.h:#define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL) dev/cxgbe/common/t4_regs.h:#define V_TXERRORCNT(x) ((x) << S_TXERRORCNT) dev/cxgbe/common/t4_regs.h:#define G_TXERRORCNT(x) (((x) >> S_TXERRORCNT) & M_TXERRORCNT) dev/cxgbe/common/t4_regs.h:#define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXSOPCNT(x) ((x) << S_TXSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXEOPCNT(x) ((x) << S_TXEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE) dev/cxgbe/common/t4_regs.h:#define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE) dev/cxgbe/common/t4_regs.h:#define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE) dev/cxgbe/common/t4_regs.h:#define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE) dev/cxgbe/common/t4_regs.h:#define V_DDPSTATE(x) ((x) << S_DDPSTATE) dev/cxgbe/common/t4_regs.h:#define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE) dev/cxgbe/common/t4_regs.h:#define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE) dev/cxgbe/common/t4_regs.h:#define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE) dev/cxgbe/common/t4_regs.h:#define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT) dev/cxgbe/common/t4_regs.h:#define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT) dev/cxgbe/common/t4_regs.h:#define V_CTXERROR(x) ((x) << S_CTXERROR) dev/cxgbe/common/t4_regs.h:#define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR) dev/cxgbe/common/t4_regs.h:#define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR) dev/cxgbe/common/t4_regs.h:#define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR) dev/cxgbe/common/t4_regs.h:#define V_CPLRXERROR(x) ((x) << S_CPLRXERROR) dev/cxgbe/common/t4_regs.h:#define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR) dev/cxgbe/common/t4_regs.h:#define V_CPLTXERROR(x) ((x) << S_CPLTXERROR) dev/cxgbe/common/t4_regs.h:#define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR) dev/cxgbe/common/t4_regs.h:#define V_CPRSERROR(x) ((x) << S_CPRSERROR) dev/cxgbe/common/t4_regs.h:#define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR) dev/cxgbe/common/t4_regs.h:#define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID) dev/cxgbe/common/t4_regs.h:#define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID) dev/cxgbe/common/t4_regs.h:#define V_DDP_AFULL(x) ((x) << S_DDP_AFULL) dev/cxgbe/common/t4_regs.h:#define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL) dev/cxgbe/common/t4_regs.h:#define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP) dev/cxgbe/common/t4_regs.h:#define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP) dev/cxgbe/common/t4_regs.h:#define V_ETAGTYPE(x) ((x) << S_ETAGTYPE) dev/cxgbe/common/t4_regs.h:#define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE) dev/cxgbe/common/t4_regs.h:#define V_CALLDONE(x) ((x) << S_CALLDONE) dev/cxgbe/common/t4_regs.h:#define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE) dev/cxgbe/common/t4_regs.h:#define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE) dev/cxgbe/common/t4_regs.h:#define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE) dev/cxgbe/common/t4_regs.h:#define V_CPLDDONE(x) ((x) << S_CPLDDONE) dev/cxgbe/common/t4_regs.h:#define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE) dev/cxgbe/common/t4_regs.h:#define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE) dev/cxgbe/common/t4_regs.h:#define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE) dev/cxgbe/common/t4_regs.h:#define V_CDBDONE(x) ((x) << S_CDBDONE) dev/cxgbe/common/t4_regs.h:#define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE) dev/cxgbe/common/t4_regs.h:#define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE) dev/cxgbe/common/t4_regs.h:#define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE) dev/cxgbe/common/t4_regs.h:#define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE) dev/cxgbe/common/t4_regs.h:#define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE) dev/cxgbe/common/t4_regs.h:#define V_CARBVALID(x) ((x) << S_CARBVALID) dev/cxgbe/common/t4_regs.h:#define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID) dev/cxgbe/common/t4_regs.h:#define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE) dev/cxgbe/common/t4_regs.h:#define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE) dev/cxgbe/common/t4_regs.h:#define V_TRCSOPCNT(x) ((x) << S_TRCSOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TRCSOPCNT(x) (((x) >> S_TRCSOPCNT) & M_TRCSOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TRCEOPCNT(x) ((x) << S_TRCEOPCNT) dev/cxgbe/common/t4_regs.h:#define G_TRCEOPCNT(x) (((x) >> S_TRCEOPCNT) & M_TRCEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_TRCFLTHIT(x) ((x) << S_TRCFLTHIT) dev/cxgbe/common/t4_regs.h:#define G_TRCFLTHIT(x) (((x) >> S_TRCFLTHIT) & M_TRCFLTHIT) dev/cxgbe/common/t4_regs.h:#define V_TRCRNTPKT(x) ((x) << S_TRCRNTPKT) dev/cxgbe/common/t4_regs.h:#define G_TRCRNTPKT(x) (((x) >> S_TRCRNTPKT) & M_TRCRNTPKT) dev/cxgbe/common/t4_regs.h:#define V_TRCPKTLEN(x) ((x) << S_TRCPKTLEN) dev/cxgbe/common/t4_regs.h:#define G_TRCPKTLEN(x) (((x) >> S_TRCPKTLEN) & M_TRCPKTLEN) dev/cxgbe/common/t4_regs.h:#define V_ETHTYPEQINQ(x) ((x) << S_ETHTYPEQINQ) dev/cxgbe/common/t4_regs.h:#define G_ETHTYPEQINQ(x) (((x) >> S_ETHTYPEQINQ) & M_ETHTYPEQINQ) dev/cxgbe/common/t4_regs.h:#define V_ETHTYPEVLAN(x) ((x) << S_ETHTYPEVLAN) dev/cxgbe/common/t4_regs.h:#define G_ETHTYPEVLAN(x) (((x) >> S_ETHTYPEVLAN) & M_ETHTYPEVLAN) dev/cxgbe/common/t4_regs.h:#define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE) dev/cxgbe/common/t4_regs.h:#define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE) dev/cxgbe/common/t4_regs.h:#define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA) dev/cxgbe/common/t4_regs.h:#define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA) dev/cxgbe/common/t4_regs.h:#define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL) dev/cxgbe/common/t4_regs.h:#define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL) dev/cxgbe/common/t4_regs.h:#define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ) dev/cxgbe/common/t4_regs.h:#define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ) dev/cxgbe/common/t4_regs.h:#define V_MEMSEL_ULPTX(x) ((x) << S_MEMSEL_ULPTX) dev/cxgbe/common/t4_regs.h:#define G_MEMSEL_ULPTX(x) (((x) >> S_MEMSEL_ULPTX) & M_MEMSEL_ULPTX) dev/cxgbe/common/t4_regs.h:#define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL) dev/cxgbe/common/t4_regs.h:#define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL) dev/cxgbe/common/t4_regs.h:#define V_INTF_SEL(x) ((x) << S_INTF_SEL) dev/cxgbe/common/t4_regs.h:#define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL) dev/cxgbe/common/t4_regs.h:#define V_NUM_FLITS(x) ((x) << S_NUM_FLITS) dev/cxgbe/common/t4_regs.h:#define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS) dev/cxgbe/common/t4_regs.h:#define V_CLR_DROP(x) ((x) << S_CLR_DROP) dev/cxgbe/common/t4_regs.h:#define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP) dev/cxgbe/common/t4_regs.h:#define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN) dev/cxgbe/common/t4_regs.h:#define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN) dev/cxgbe/common/t4_regs.h:#define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN) dev/cxgbe/common/t4_regs.h:#define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN) dev/cxgbe/common/t4_regs.h:#define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN) dev/cxgbe/common/t4_regs.h:#define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN) dev/cxgbe/common/t4_regs.h:#define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN) dev/cxgbe/common/t4_regs.h:#define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN) dev/cxgbe/common/t4_regs.h:#define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR) dev/cxgbe/common/t4_regs.h:#define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR) dev/cxgbe/common/t4_regs.h:#define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH) dev/cxgbe/common/t4_regs.h:#define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH) dev/cxgbe/common/t4_regs.h:#define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY) dev/cxgbe/common/t4_regs.h:#define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY) dev/cxgbe/common/t4_regs.h:#define V_PMDBGADDR(x) ((x) << S_PMDBGADDR) dev/cxgbe/common/t4_regs.h:#define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR) dev/cxgbe/common/t4_regs.h:#define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP) dev/cxgbe/common/t4_regs.h:#define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP) dev/cxgbe/common/t4_regs.h:#define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT) dev/cxgbe/common/t4_regs.h:#define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT) dev/cxgbe/common/t4_regs.h:#define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT) dev/cxgbe/common/t4_regs.h:#define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT) dev/cxgbe/common/t4_regs.h:#define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT) dev/cxgbe/common/t4_regs.h:#define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT) dev/cxgbe/common/t4_regs.h:#define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB) dev/cxgbe/common/t4_regs.h:#define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB) dev/cxgbe/common/t4_regs.h:#define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN) dev/cxgbe/common/t4_regs.h:#define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN) dev/cxgbe/common/t4_regs.h:#define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD) dev/cxgbe/common/t4_regs.h:#define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD) dev/cxgbe/common/t4_regs.h:#define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR) dev/cxgbe/common/t4_regs.h:#define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR) dev/cxgbe/common/t4_regs.h:#define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD) dev/cxgbe/common/t4_regs.h:#define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD) dev/cxgbe/common/t4_regs.h:#define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY) dev/cxgbe/common/t4_regs.h:#define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY) dev/cxgbe/common/t4_regs.h:#define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE) dev/cxgbe/common/t4_regs.h:#define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE) dev/cxgbe/common/t4_regs.h:#define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH) dev/cxgbe/common/t4_regs.h:#define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH) dev/cxgbe/common/t4_regs.h:#define V_RX_LINE(x) ((x) << S_RX_LINE) dev/cxgbe/common/t4_regs.h:#define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE) dev/cxgbe/common/t4_regs.h:#define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL) dev/cxgbe/common/t4_regs.h:#define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL) dev/cxgbe/common/t4_regs.h:#define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY) dev/cxgbe/common/t4_regs.h:#define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY) dev/cxgbe/common/t4_regs.h:#define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY) dev/cxgbe/common/t4_regs.h:#define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY) dev/cxgbe/common/t4_regs.h:#define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD) dev/cxgbe/common/t4_regs.h:#define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD) dev/cxgbe/common/t4_regs.h:#define V_DUPLICATE(x) ((x) << S_DUPLICATE) dev/cxgbe/common/t4_regs.h:#define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE) dev/cxgbe/common/t4_regs.h:#define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL) dev/cxgbe/common/t4_regs.h:#define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL) dev/cxgbe/common/t4_regs.h:#define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL) dev/cxgbe/common/t4_regs.h:#define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL) dev/cxgbe/common/t4_regs.h:#define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID) dev/cxgbe/common/t4_regs.h:#define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID) dev/cxgbe/common/t4_regs.h:#define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL) dev/cxgbe/common/t4_regs.h:#define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL) dev/cxgbe/common/t4_regs.h:#define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID) dev/cxgbe/common/t4_regs.h:#define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID) dev/cxgbe/common/t4_regs.h:#define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL) dev/cxgbe/common/t4_regs.h:#define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL) dev/cxgbe/common/t4_regs.h:#define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY) dev/cxgbe/common/t4_regs.h:#define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY) dev/cxgbe/common/t4_regs.h:#define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL) dev/cxgbe/common/t4_regs.h:#define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY) dev/cxgbe/common/t4_regs.h:#define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY) dev/cxgbe/common/t4_regs.h:#define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD) dev/cxgbe/common/t4_regs.h:#define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD) dev/cxgbe/common/t4_regs.h:#define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN) dev/cxgbe/common/t4_regs.h:#define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN) dev/cxgbe/common/t4_regs.h:#define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD) dev/cxgbe/common/t4_regs.h:#define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD) dev/cxgbe/common/t4_regs.h:#define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR) dev/cxgbe/common/t4_regs.h:#define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR) dev/cxgbe/common/t4_regs.h:#define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD) dev/cxgbe/common/t4_regs.h:#define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD) dev/cxgbe/common/t4_regs.h:#define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY) dev/cxgbe/common/t4_regs.h:#define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY) dev/cxgbe/common/t4_regs.h:#define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE) dev/cxgbe/common/t4_regs.h:#define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE) dev/cxgbe/common/t4_regs.h:#define V_PCMD_CH(x) ((x) << S_PCMD_CH) dev/cxgbe/common/t4_regs.h:#define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH) dev/cxgbe/common/t4_regs.h:#define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC) dev/cxgbe/common/t4_regs.h:#define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC) dev/cxgbe/common/t4_regs.h:#define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID) dev/cxgbe/common/t4_regs.h:#define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL) dev/cxgbe/common/t4_regs.h:#define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL) dev/cxgbe/common/t4_regs.h:#define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY) dev/cxgbe/common/t4_regs.h:#define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY) dev/cxgbe/common/t4_regs.h:#define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY) dev/cxgbe/common/t4_regs.h:#define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY) dev/cxgbe/common/t4_regs.h:#define V_PCMD_CMD(x) ((x) << S_PCMD_CMD) dev/cxgbe/common/t4_regs.h:#define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD) dev/cxgbe/common/t4_regs.h:#define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID) dev/cxgbe/common/t4_regs.h:#define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID) dev/cxgbe/common/t4_regs.h:#define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL) dev/cxgbe/common/t4_regs.h:#define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL) dev/cxgbe/common/t4_regs.h:#define V_OESPI_VALID(x) ((x) << S_OESPI_VALID) dev/cxgbe/common/t4_regs.h:#define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID) dev/cxgbe/common/t4_regs.h:#define V_OESPI_FULL(x) ((x) << S_OESPI_FULL) dev/cxgbe/common/t4_regs.h:#define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL) dev/cxgbe/common/t4_regs.h:#define V_C_RXVALID(x) ((x) << S_C_RXVALID) dev/cxgbe/common/t4_regs.h:#define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID) dev/cxgbe/common/t4_regs.h:#define V_C_RXAFULL(x) ((x) << S_C_RXAFULL) dev/cxgbe/common/t4_regs.h:#define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL) dev/cxgbe/common/t4_regs.h:#define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY) dev/cxgbe/common/t4_regs.h:#define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY) dev/cxgbe/common/t4_regs.h:#define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP) dev/cxgbe/common/t4_regs.h:#define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP) dev/cxgbe/common/t4_regs.h:#define V_TIMEUNIT(x) ((x) << S_TIMEUNIT) dev/cxgbe/common/t4_regs.h:#define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT) dev/cxgbe/common/t4_regs.h:#define V_REGSENDOFF(x) ((x) << S_REGSENDOFF) dev/cxgbe/common/t4_regs.h:#define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF) dev/cxgbe/common/t4_regs.h:#define V_REGSENDON(x) ((x) << S_REGSENDON) dev/cxgbe/common/t4_regs.h:#define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON) dev/cxgbe/common/t4_regs.h:#define V_SGESENDEN(x) ((x) << S_SGESENDEN) dev/cxgbe/common/t4_regs.h:#define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN) dev/cxgbe/common/t4_regs.h:#define V_RXSENDEN(x) ((x) << S_RXSENDEN) dev/cxgbe/common/t4_regs.h:#define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN) dev/cxgbe/common/t4_regs.h:#define V_REGHALTON(x) ((x) << S_REGHALTON) dev/cxgbe/common/t4_regs.h:#define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON) dev/cxgbe/common/t4_regs.h:#define V_RXHALTEN(x) ((x) << S_RXHALTEN) dev/cxgbe/common/t4_regs.h:#define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN) dev/cxgbe/common/t4_regs.h:#define V_REGSENDING(x) ((x) << S_REGSENDING) dev/cxgbe/common/t4_regs.h:#define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING) dev/cxgbe/common/t4_regs.h:#define V_SGESENDING(x) ((x) << S_SGESENDING) dev/cxgbe/common/t4_regs.h:#define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING) dev/cxgbe/common/t4_regs.h:#define V_RXSENDING(x) ((x) << S_RXSENDING) dev/cxgbe/common/t4_regs.h:#define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING) dev/cxgbe/common/t4_regs.h:#define V_REGHALTED(x) ((x) << S_REGHALTED) dev/cxgbe/common/t4_regs.h:#define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED) dev/cxgbe/common/t4_regs.h:#define V_RXHALTED(x) ((x) << S_RXHALTED) dev/cxgbe/common/t4_regs.h:#define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED) dev/cxgbe/common/t4_regs.h:#define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L) dev/cxgbe/common/t4_regs.h:#define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L) dev/cxgbe/common/t4_regs.h:#define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE) dev/cxgbe/common/t4_regs.h:#define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE) dev/cxgbe/common/t4_regs.h:#define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK) dev/cxgbe/common/t4_regs.h:#define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK) dev/cxgbe/common/t4_regs.h:#define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE) dev/cxgbe/common/t4_regs.h:#define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE) dev/cxgbe/common/t4_regs.h:#define V_RSS_CTRL(x) ((x) << S_RSS_CTRL) dev/cxgbe/common/t4_regs.h:#define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL) dev/cxgbe/common/t4_regs.h:#define V_QUE_NUM(x) ((x) << S_QUE_NUM) dev/cxgbe/common/t4_regs.h:#define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM) dev/cxgbe/common/t4_regs.h:#define V_FIXED_PF(x) ((x) << S_FIXED_PF) dev/cxgbe/common/t4_regs.h:#define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF) dev/cxgbe/common/t4_regs.h:#define V_FIXED_VF(x) ((x) << S_FIXED_VF) dev/cxgbe/common/t4_regs.h:#define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF) dev/cxgbe/common/t4_regs.h:#define V_TS_VLD(x) ((x) << S_TS_VLD) dev/cxgbe/common/t4_regs.h:#define G_TS_VLD(x) (((x) >> S_TS_VLD) & M_TS_VLD) dev/cxgbe/common/t4_regs.h:#define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL) dev/cxgbe/common/t4_regs.h:#define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL) dev/cxgbe/common/t4_regs.h:#define V_CREDIT(x) ((x) << S_CREDIT) dev/cxgbe/common/t4_regs.h:#define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT) dev/cxgbe/common/t4_regs.h:#define V_FIFOTH(x) ((x) << S_FIFOTH) dev/cxgbe/common/t4_regs.h:#define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH) dev/cxgbe/common/t4_regs.h:#define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT) dev/cxgbe/common/t4_regs.h:#define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT) dev/cxgbe/common/t4_regs.h:#define V_OUT_TH(x) ((x) << S_OUT_TH) dev/cxgbe/common/t4_regs.h:#define G_OUT_TH(x) (((x) >> S_OUT_TH) & M_OUT_TH) dev/cxgbe/common/t4_regs.h:#define V_IN_TH(x) ((x) << S_IN_TH) dev/cxgbe/common/t4_regs.h:#define G_IN_TH(x) (((x) >> S_IN_TH) & M_IN_TH) dev/cxgbe/common/t4_regs.h:#define V_OFF_PENDING(x) ((x) << S_OFF_PENDING) dev/cxgbe/common/t4_regs.h:#define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING) dev/cxgbe/common/t4_regs.h:#define V_ON_PENDING(x) ((x) << S_ON_PENDING) dev/cxgbe/common/t4_regs.h:#define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING) dev/cxgbe/common/t4_regs.h:#define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP) dev/cxgbe/common/t4_regs.h:#define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP) dev/cxgbe/common/t4_regs.h:#define V_PRIORITY(x) ((x) << S_PRIORITY) dev/cxgbe/common/t4_regs.h:#define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY) dev/cxgbe/common/t4_regs.h:#define V_PF(x) ((x) << S_PF) dev/cxgbe/common/t4_regs.h:#define V_VF(x) ((x) << S_VF) dev/cxgbe/common/t4_regs.h:#define V_PROTOCOLID(x) ((x) << S_PROTOCOLID) dev/cxgbe/common/t4_regs.h:#define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID) dev/cxgbe/common/t4_regs.h:#define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO) dev/cxgbe/common/t4_regs.h:#define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO) dev/cxgbe/common/t4_regs.h:#define V_TAG(x) ((x) << S_TAG) dev/cxgbe/common/t4_regs.h:#define G_TAG(x) (((x) >> S_TAG) & M_TAG) dev/cxgbe/common/t4_regs.h:#define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL) dev/cxgbe/common/t4_regs.h:#define V_NUMPORTS(x) ((x) << S_NUMPORTS) dev/cxgbe/common/t4_regs.h:#define V_SPEEDMODE(x) ((x) << S_SPEEDMODE) dev/cxgbe/common/t4_regs.h:#define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE) dev/cxgbe/common/t4_regs.h:#define V_WEIGHT(x) ((x) << S_WEIGHT) dev/cxgbe/common/t4_regs.h:#define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT) dev/cxgbe/common/t4_regs.h:#define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT) dev/cxgbe/common/t4_regs.h:#define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT) dev/cxgbe/common/t4_regs.h:#define V_DBGSEL_H(x) ((x) << S_DBGSEL_H) dev/cxgbe/common/t4_regs.h:#define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H) dev/cxgbe/common/t4_regs.h:#define V_DBGSEL_L(x) ((x) << S_DBGSEL_L) dev/cxgbe/common/t4_regs.h:#define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L) dev/cxgbe/common/t4_regs.h:#define V_TOPSPARE(x) ((x) << S_TOPSPARE) dev/cxgbe/common/t4_regs.h:#define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE) dev/cxgbe/common/t4_regs.h:#define V_ADDRMASK(x) ((x) << S_ADDRMASK) dev/cxgbe/common/t4_regs.h:#define G_ADDRMASK(x) (((x) >> S_ADDRMASK) & M_ADDRMASK) dev/cxgbe/common/t4_regs.h:#define V_TP_SOURCE(x) ((x) << S_TP_SOURCE) dev/cxgbe/common/t4_regs.h:#define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE) dev/cxgbe/common/t4_regs.h:#define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE) dev/cxgbe/common/t4_regs.h:#define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE) dev/cxgbe/common/t4_regs.h:#define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO) dev/cxgbe/common/t4_regs.h:#define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO) dev/cxgbe/common/t4_regs.h:#define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO) dev/cxgbe/common/t4_regs.h:#define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL) dev/cxgbe/common/t4_regs.h:#define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL) dev/cxgbe/common/t4_regs.h:#define V_BUBBLEERR(x) ((x) << S_BUBBLEERR) dev/cxgbe/common/t4_regs.h:#define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR) dev/cxgbe/common/t4_regs.h:#define V_SPI(x) ((x) << S_SPI) dev/cxgbe/common/t4_regs.h:#define G_SPI(x) (((x) >> S_SPI) & M_SPI) dev/cxgbe/common/t4_regs.h:#define V_SECNT(x) ((x) << S_SECNT) dev/cxgbe/common/t4_regs.h:#define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT) dev/cxgbe/common/t4_regs.h:#define V_BUBBLECLR(x) ((x) << S_BUBBLECLR) dev/cxgbe/common/t4_regs.h:#define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR) dev/cxgbe/common/t4_regs.h:#define V_LPBKSECNT(x) ((x) << S_LPBKSECNT) dev/cxgbe/common/t4_regs.h:#define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT) dev/cxgbe/common/t4_regs.h:#define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR) dev/cxgbe/common/t4_regs.h:#define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR) dev/cxgbe/common/t4_regs.h:#define V_SUBPRTH(x) ((x) << S_SUBPRTH) dev/cxgbe/common/t4_regs.h:#define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH) dev/cxgbe/common/t4_regs.h:#define V_PORTH(x) ((x) << S_PORTH) dev/cxgbe/common/t4_regs.h:#define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH) dev/cxgbe/common/t4_regs.h:#define V_SUBPRTL(x) ((x) << S_SUBPRTL) dev/cxgbe/common/t4_regs.h:#define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL) dev/cxgbe/common/t4_regs.h:#define V_PORTL(x) ((x) << S_PORTL) dev/cxgbe/common/t4_regs.h:#define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL) dev/cxgbe/common/t4_regs.h:#define V_RXVF(x) ((x) << S_RXVF) dev/cxgbe/common/t4_regs.h:#define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF) dev/cxgbe/common/t4_regs.h:#define V_TXVF(x) ((x) << S_TXVF) dev/cxgbe/common/t4_regs.h:#define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF) dev/cxgbe/common/t4_regs.h:#define V_RXPF(x) ((x) << S_RXPF) dev/cxgbe/common/t4_regs.h:#define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF) dev/cxgbe/common/t4_regs.h:#define V_TXPF(x) ((x) << S_TXPF) dev/cxgbe/common/t4_regs.h:#define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF) dev/cxgbe/common/t4_regs.h:#define V_RXPORT(x) ((x) << S_RXPORT) dev/cxgbe/common/t4_regs.h:#define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT) dev/cxgbe/common/t4_regs.h:#define V_LBPORT(x) ((x) << S_LBPORT) dev/cxgbe/common/t4_regs.h:#define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT) dev/cxgbe/common/t4_regs.h:#define V_TXPORT(x) ((x) << S_TXPORT) dev/cxgbe/common/t4_regs.h:#define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT) dev/cxgbe/common/t4_regs.h:#define V_TX(x) ((x) << S_TX) dev/cxgbe/common/t4_regs.h:#define G_TX(x) (((x) >> S_TX) & M_TX) dev/cxgbe/common/t4_regs.h:#define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO) dev/cxgbe/common/t4_regs.h:#define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO) dev/cxgbe/common/t4_regs.h:#define V_DROP(x) ((x) << S_DROP) dev/cxgbe/common/t4_regs.h:#define G_DROP(x) (((x) >> S_DROP) & M_DROP) dev/cxgbe/common/t4_regs.h:#define V_TXCH(x) ((x) << S_TXCH) dev/cxgbe/common/t4_regs.h:#define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH) dev/cxgbe/common/t4_regs.h:#define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO) dev/cxgbe/common/t4_regs.h:#define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO) dev/cxgbe/common/t4_regs.h:#define V_LPBK(x) ((x) << S_LPBK) dev/cxgbe/common/t4_regs.h:#define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK) dev/cxgbe/common/t4_regs.h:#define V_NQ(x) ((x) << S_NQ) dev/cxgbe/common/t4_regs.h:#define G_NQ(x) (((x) >> S_NQ) & M_NQ) dev/cxgbe/common/t4_regs.h:#define G_PV(x) (((x) >> S_PV) & M_PV) dev/cxgbe/common/t4_regs.h:#define V_MAC(x) ((x) << S_MAC) dev/cxgbe/common/t4_regs.h:#define G_MAC(x) (((x) >> S_MAC) & M_MAC) dev/cxgbe/common/t4_regs.h:#define V_STATMEMSEL(x) ((x) << S_STATMEMSEL) dev/cxgbe/common/t4_regs.h:#define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL) dev/cxgbe/common/t4_regs.h:#define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH) dev/cxgbe/common/t4_regs.h:#define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH) dev/cxgbe/common/t4_regs.h:#define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL) dev/cxgbe/common/t4_regs.h:#define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL) dev/cxgbe/common/t4_regs.h:#define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH) dev/cxgbe/common/t4_regs.h:#define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH) dev/cxgbe/common/t4_regs.h:#define V_BGRX(x) ((x) << S_BGRX) dev/cxgbe/common/t4_regs.h:#define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX) dev/cxgbe/common/t4_regs.h:#define V_PTLPBK(x) ((x) << S_PTLPBK) dev/cxgbe/common/t4_regs.h:#define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK) dev/cxgbe/common/t4_regs.h:#define V_PTTX(x) ((x) << S_PTTX) dev/cxgbe/common/t4_regs.h:#define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX) dev/cxgbe/common/t4_regs.h:#define V_PTRX(x) ((x) << S_PTRX) dev/cxgbe/common/t4_regs.h:#define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX) dev/cxgbe/common/t4_regs.h:#define V_PFTX(x) ((x) << S_PFTX) dev/cxgbe/common/t4_regs.h:#define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX) dev/cxgbe/common/t4_regs.h:#define V_PFRX(x) ((x) << S_PFRX) dev/cxgbe/common/t4_regs.h:#define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX) dev/cxgbe/common/t4_regs.h:#define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL) dev/cxgbe/common/t4_regs.h:#define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER) dev/cxgbe/common/t4_regs.h:#define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE) dev/cxgbe/common/t4_regs.h:#define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE) dev/cxgbe/common/t4_regs.h:#define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT) dev/cxgbe/common/t4_regs.h:#define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT) dev/cxgbe/common/t4_regs.h:#define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT) dev/cxgbe/common/t4_regs.h:#define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT) dev/cxgbe/common/t4_regs.h:#define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL) dev/cxgbe/common/t4_regs.h:#define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL) dev/cxgbe/common/t4_regs.h:#define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO) dev/cxgbe/common/t4_regs.h:#define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM) dev/cxgbe/common/t4_regs.h:#define V_VFFILTMASK(x) ((x) << S_VFFILTMASK) dev/cxgbe/common/t4_regs.h:#define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK) dev/cxgbe/common/t4_regs.h:#define V_VFFILTDATA(x) ((x) << S_VFFILTDATA) dev/cxgbe/common/t4_regs.h:#define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA) dev/cxgbe/common/t4_regs.h:#define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN) dev/cxgbe/common/t4_regs.h:#define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN) dev/cxgbe/common/t4_regs.h:#define V_PLWEIGHT(x) ((x) << S_PLWEIGHT) dev/cxgbe/common/t4_regs.h:#define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT) dev/cxgbe/common/t4_regs.h:#define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT) dev/cxgbe/common/t4_regs.h:#define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT) dev/cxgbe/common/t4_regs.h:#define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT) dev/cxgbe/common/t4_regs.h:#define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT) dev/cxgbe/common/t4_regs.h:#define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL) dev/cxgbe/common/t4_regs.h:#define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL) dev/cxgbe/common/t4_regs.h:#define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY) dev/cxgbe/common/t4_regs.h:#define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY) dev/cxgbe/common/t4_regs.h:#define V_CLS_INDEX(x) ((x) << S_CLS_INDEX) dev/cxgbe/common/t4_regs.h:#define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX) dev/cxgbe/common/t4_regs.h:#define V_CLS_VF(x) ((x) << S_CLS_VF) dev/cxgbe/common/t4_regs.h:#define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF) dev/cxgbe/common/t4_regs.h:#define V_CLS_PF(x) ((x) << S_CLS_PF) dev/cxgbe/common/t4_regs.h:#define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF) dev/cxgbe/common/t4_regs.h:#define V_CLS_MATCH(x) ((x) << S_CLS_MATCH) dev/cxgbe/common/t4_regs.h:#define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH) dev/cxgbe/common/t4_regs.h:#define V_CLS_SPARE(x) ((x) << S_CLS_SPARE) dev/cxgbe/common/t4_regs.h:#define G_CLS_SPARE(x) (((x) >> S_CLS_SPARE) & M_CLS_SPARE) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCMACDAHI(x) ((x) << S_CLSTRCMACDAHI) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCMACDAHI(x) (((x) >> S_CLSTRCMACDAHI) & M_CLSTRCMACDAHI) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCMACSAHI(x) ((x) << S_CLSTRCMACSAHI) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCMACSAHI(x) (((x) >> S_CLSTRCMACSAHI) & M_CLSTRCMACSAHI) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCVLANID(x) ((x) << S_CLSTRCVLANID) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCVLANID(x) (((x) >> S_CLSTRCVLANID) & M_CLSTRCVLANID) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCREQPORT(x) ((x) << S_CLSTRCREQPORT) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCREQPORT(x) (((x) >> S_CLSTRCREQPORT) & M_CLSTRCREQPORT) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCVNI(x) ((x) << S_CLSTRCVNI) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCVNI(x) (((x) >> S_CLSTRCVNI) & M_CLSTRCVNI) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCPRIORITY(x) ((x) << S_CLSTRCPRIORITY) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCPRIORITY(x) (((x) >> S_CLSTRCPRIORITY) & M_CLSTRCPRIORITY) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCPORTMAP(x) ((x) << S_CLSTRCPORTMAP) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCPORTMAP(x) (((x) >> S_CLSTRCPORTMAP) & M_CLSTRCPORTMAP) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCMATCH(x) ((x) << S_CLSTRCMATCH) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCMATCH(x) (((x) >> S_CLSTRCMATCH) & M_CLSTRCMATCH) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCINDEX(x) ((x) << S_CLSTRCINDEX) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCINDEX(x) (((x) >> S_CLSTRCINDEX) & M_CLSTRCINDEX) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCPF(x) ((x) << S_CLSTRCPF) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCPF(x) (((x) >> S_CLSTRCPF) & M_CLSTRCPF) dev/cxgbe/common/t4_regs.h:#define V_CLSTRCVF(x) ((x) << S_CLSTRCVF) dev/cxgbe/common/t4_regs.h:#define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF) dev/cxgbe/common/t4_regs.h:#define V_VLAN_MASK(x) ((x) << S_VLAN_MASK) dev/cxgbe/common/t4_regs.h:#define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK) dev/cxgbe/common/t4_regs.h:#define V_VLANPF(x) ((x) << S_VLANPF) dev/cxgbe/common/t4_regs.h:#define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF) dev/cxgbe/common/t4_regs.h:#define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE) dev/cxgbe/common/t4_regs.h:#define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE) dev/cxgbe/common/t4_regs.h:#define V_PORTMAP(x) ((x) << S_PORTMAP) dev/cxgbe/common/t4_regs.h:#define V_TCAMYH(x) ((x) << S_TCAMYH) dev/cxgbe/common/t4_regs.h:#define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH) dev/cxgbe/common/t4_regs.h:#define V_VIDL(x) ((x) << S_VIDL) dev/cxgbe/common/t4_regs.h:#define V_DMACH(x) ((x) << S_DMACH) dev/cxgbe/common/t4_regs.h:#define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX) dev/cxgbe/common/t4_regs.h:#define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM) dev/cxgbe/common/t4_regs.h:#define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE) dev/cxgbe/common/t4_regs.h:#define V_TCAMXH(x) ((x) << S_TCAMXH) dev/cxgbe/common/t4_regs.h:#define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH) dev/cxgbe/common/t4_regs.h:#define V_BLK_SNDR(x) ((x) << S_BLK_SNDR) dev/cxgbe/common/t4_regs.h:#define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR) dev/cxgbe/common/t4_regs.h:#define V_CMPRS(x) ((x) << S_CMPRS) dev/cxgbe/common/t4_regs.h:#define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS) dev/cxgbe/common/t4_regs.h:#define V_SNF(x) ((x) << S_SNF) dev/cxgbe/common/t4_regs.h:#define G_SNF(x) (((x) >> S_SNF) & M_SNF) dev/cxgbe/common/t4_regs.h:#define V_DEST_SELECT(x) ((x) << S_DEST_SELECT) dev/cxgbe/common/t4_regs.h:#define G_DEST_SELECT(x) (((x) >> S_DEST_SELECT) & M_DEST_SELECT) dev/cxgbe/common/t4_regs.h:#define V_USED(x) ((x) << S_USED) dev/cxgbe/common/t4_regs.h:#define V_ALLOC(x) ((x) << S_ALLOC) dev/cxgbe/common/t4_regs.h:#define V_MAX(x) ((x) << S_MAX) dev/cxgbe/common/t4_regs.h:#define G_MAX(x) (((x) >> S_MAX) & M_MAX) dev/cxgbe/common/t4_regs.h:#define V_BORW(x) ((x) << S_BORW) dev/cxgbe/common/t4_regs.h:#define G_BORW(x) (((x) >> S_BORW) & M_BORW) dev/cxgbe/common/t4_regs.h:#define V_QUOTA(x) ((x) << S_QUOTA) dev/cxgbe/common/t4_regs.h:#define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA) dev/cxgbe/common/t4_regs.h:#define V_SHR_USED(x) ((x) << S_SHR_USED) dev/cxgbe/common/t4_regs.h:#define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED) dev/cxgbe/common/t4_regs.h:#define G_TH(x) (((x) >> S_TH) & M_TH) dev/cxgbe/common/t4_regs.h:#define V_DROP_WT(x) ((x) << S_DROP_WT) dev/cxgbe/common/t4_regs.h:#define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT) dev/cxgbe/common/t4_regs.h:#define V_TRUNC_WT(x) ((x) << S_TRUNC_WT) dev/cxgbe/common/t4_regs.h:#define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT) dev/cxgbe/common/t4_regs.h:#define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN) dev/cxgbe/common/t4_regs.h:#define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN) dev/cxgbe/common/t4_regs.h:#define V_OCH_DROP(x) ((x) << S_OCH_DROP) dev/cxgbe/common/t4_regs.h:#define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP) dev/cxgbe/common/t4_regs.h:#define V_STOP(x) ((x) << S_STOP) dev/cxgbe/common/t4_regs.h:#define G_STOP(x) (((x) >> S_STOP) & M_STOP) dev/cxgbe/common/t4_regs.h:#define V_THRESH(x) ((x) << S_THRESH) dev/cxgbe/common/t4_regs.h:#define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH) dev/cxgbe/common/t4_regs.h:#define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT) dev/cxgbe/common/t4_regs.h:#define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT) dev/cxgbe/common/t4_regs.h:#define V_TH_HIGH(x) ((x) << S_TH_HIGH) dev/cxgbe/common/t4_regs.h:#define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH) dev/cxgbe/common/t4_regs.h:#define V_TH_LOW(x) ((x) << S_TH_LOW) dev/cxgbe/common/t4_regs.h:#define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW) dev/cxgbe/common/t4_regs.h:#define V_ETYPE(x) ((x) << S_ETYPE) dev/cxgbe/common/t4_regs.h:#define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE) dev/cxgbe/common/t4_regs.h:#define V_DA(x) ((x) << S_DA) dev/cxgbe/common/t4_regs.h:#define G_DA(x) (((x) >> S_DA) & M_DA) dev/cxgbe/common/t4_regs.h:#define V_LPBK_WT(x) ((x) << S_LPBK_WT) dev/cxgbe/common/t4_regs.h:#define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT) dev/cxgbe/common/t4_regs.h:#define V_MAC_WT(x) ((x) << S_MAC_WT) dev/cxgbe/common/t4_regs.h:#define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT) dev/cxgbe/common/t4_regs.h:#define V_OUTEN(x) ((x) << S_OUTEN) dev/cxgbe/common/t4_regs.h:#define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN) dev/cxgbe/common/t4_regs.h:#define V_MTU(x) ((x) << S_MTU) dev/cxgbe/common/t4_regs.h:#define G_MTU(x) (((x) >> S_MTU) & M_MTU) dev/cxgbe/common/t4_regs.h:#define V_PFVF(x) ((x) << S_PFVF) dev/cxgbe/common/t4_regs.h:#define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF) dev/cxgbe/common/t4_regs.h:#define V_ATTR_PF(x) ((x) << S_ATTR_PF) dev/cxgbe/common/t4_regs.h:#define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF) dev/cxgbe/common/t4_regs.h:#define V_VLAN_ID(x) ((x) << S_VLAN_ID) dev/cxgbe/common/t4_regs.h:#define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID) dev/cxgbe/common/t4_regs.h:#define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR) dev/cxgbe/common/t4_regs.h:#define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR) dev/cxgbe/common/t4_regs.h:#define V_PF_EN(x) ((x) << S_PF_EN) dev/cxgbe/common/t4_regs.h:#define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN) dev/cxgbe/common/t4_regs.h:#define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP) dev/cxgbe/common/t4_regs.h:#define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP) dev/cxgbe/common/t4_regs.h:#define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM) dev/cxgbe/common/t4_regs.h:#define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM) dev/cxgbe/common/t4_regs.h:#define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM) dev/cxgbe/common/t4_regs.h:#define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM) dev/cxgbe/common/t4_regs.h:#define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN) dev/cxgbe/common/t4_regs.h:#define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN) dev/cxgbe/common/t4_regs.h:#define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN) dev/cxgbe/common/t4_regs.h:#define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN) dev/cxgbe/common/t4_regs.h:#define V_LENERR(x) ((x) << S_LENERR) dev/cxgbe/common/t4_regs.h:#define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR) dev/cxgbe/common/t4_regs.h:#define V_SPIERR(x) ((x) << S_SPIERR) dev/cxgbe/common/t4_regs.h:#define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR) dev/cxgbe/common/t4_regs.h:#define V_ST_NCSI(x) ((x) << S_ST_NCSI) dev/cxgbe/common/t4_regs.h:#define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI) dev/cxgbe/common/t4_regs.h:#define V_ST_TP(x) ((x) << S_ST_TP) dev/cxgbe/common/t4_regs.h:#define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP) dev/cxgbe/common/t4_regs.h:#define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL) dev/cxgbe/common/t4_regs.h:#define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL) dev/cxgbe/common/t4_regs.h:#define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT) dev/cxgbe/common/t4_regs.h:#define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT) dev/cxgbe/common/t4_regs.h:#define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL) dev/cxgbe/common/t4_regs.h:#define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL) dev/cxgbe/common/t4_regs.h:#define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE) dev/cxgbe/common/t4_regs.h:#define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE) dev/cxgbe/common/t4_regs.h:#define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT) dev/cxgbe/common/t4_regs.h:#define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT) dev/cxgbe/common/t4_regs.h:#define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN) dev/cxgbe/common/t4_regs.h:#define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN) dev/cxgbe/common/t4_regs.h:#define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN) dev/cxgbe/common/t4_regs.h:#define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN) dev/cxgbe/common/t4_regs.h:#define V_MAC_USED(x) ((x) << S_MAC_USED) dev/cxgbe/common/t4_regs.h:#define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED) dev/cxgbe/common/t4_regs.h:#define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC) dev/cxgbe/common/t4_regs.h:#define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC) dev/cxgbe/common/t4_regs.h:#define V_LPBK_USED(x) ((x) << S_LPBK_USED) dev/cxgbe/common/t4_regs.h:#define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED) dev/cxgbe/common/t4_regs.h:#define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC) dev/cxgbe/common/t4_regs.h:#define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC) dev/cxgbe/common/t4_regs.h:#define V_CONG_TH(x) ((x) << S_CONG_TH) dev/cxgbe/common/t4_regs.h:#define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH) dev/cxgbe/common/t4_regs.h:#define V_GRE(x) ((x) << S_GRE) dev/cxgbe/common/t4_regs.h:#define G_GRE(x) (((x) >> S_GRE) & M_GRE) dev/cxgbe/common/t4_regs.h:#define V_VXLAN(x) ((x) << S_VXLAN) dev/cxgbe/common/t4_regs.h:#define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN) dev/cxgbe/common/t4_regs.h:#define V_GENEVE(x) ((x) << S_GENEVE) dev/cxgbe/common/t4_regs.h:#define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE) dev/cxgbe/common/t4_regs.h:#define V_PROT_TYPE(x) ((x) << S_PROT_TYPE) dev/cxgbe/common/t4_regs.h:#define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE) dev/cxgbe/common/t4_regs.h:#define V_SAP_VALUE(x) ((x) << S_SAP_VALUE) dev/cxgbe/common/t4_regs.h:#define G_SAP_VALUE(x) (((x) >> S_SAP_VALUE) & M_SAP_VALUE) dev/cxgbe/common/t4_regs.h:#define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE) dev/cxgbe/common/t4_regs.h:#define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE) dev/cxgbe/common/t4_regs.h:#define V_CTL_VALUE(x) ((x) << S_CTL_VALUE) dev/cxgbe/common/t4_regs.h:#define G_CTL_VALUE(x) (((x) >> S_CTL_VALUE) & M_CTL_VALUE) dev/cxgbe/common/t4_regs.h:#define V_ORG_VALUE(x) ((x) << S_ORG_VALUE) dev/cxgbe/common/t4_regs.h:#define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE) dev/cxgbe/common/t4_regs.h:#define V_VNI(x) ((x) << S_VNI) dev/cxgbe/common/t4_regs.h:#define G_VNI(x) (((x) >> S_VNI) & M_VNI) dev/cxgbe/common/t4_regs.h:#define V_VXLAN_FLAG_MASK(x) ((x) << S_VXLAN_FLAG_MASK) dev/cxgbe/common/t4_regs.h:#define G_VXLAN_FLAG_MASK(x) (((x) >> S_VXLAN_FLAG_MASK) & M_VXLAN_FLAG_MASK) dev/cxgbe/common/t4_regs.h:#define V_VXLAN_FLAG(x) ((x) << S_VXLAN_FLAG) dev/cxgbe/common/t4_regs.h:#define G_VXLAN_FLAG(x) (((x) >> S_VXLAN_FLAG) & M_VXLAN_FLAG) dev/cxgbe/common/t4_regs.h:#define V_GRE_VER(x) ((x) << S_GRE_VER) dev/cxgbe/common/t4_regs.h:#define G_GRE_VER(x) (((x) >> S_GRE_VER) & M_GRE_VER) dev/cxgbe/common/t4_regs.h:#define V_GENEVE_VER(x) ((x) << S_GENEVE_VER) dev/cxgbe/common/t4_regs.h:#define G_GENEVE_VER(x) (((x) >> S_GENEVE_VER) & M_GENEVE_VER) dev/cxgbe/common/t4_regs.h:#define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX) dev/cxgbe/common/t4_regs.h:#define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX) dev/cxgbe/common/t4_regs.h:#define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA) dev/cxgbe/common/t4_regs.h:#define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA) dev/cxgbe/common/t4_regs.h:#define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET) dev/cxgbe/common/t4_regs.h:#define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET) dev/cxgbe/common/t4_regs.h:#define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE) dev/cxgbe/common/t4_regs.h:#define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE) dev/cxgbe/common/t4_regs.h:#define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID) dev/cxgbe/common/t4_regs.h:#define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID) dev/cxgbe/common/t4_regs.h:#define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID) dev/cxgbe/common/t4_regs.h:#define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID) dev/cxgbe/common/t4_regs.h:#define V_DEVICEID(x) ((x) << S_DEVICEID) dev/cxgbe/common/t4_regs.h:#define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID) dev/cxgbe/common/t4_regs.h:#define V_INTERFACE(x) ((x) << S_INTERFACE) dev/cxgbe/common/t4_regs.h:#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE) dev/cxgbe/common/t4_regs.h:#define V_DEVICECAP(x) ((x) << S_DEVICECAP) dev/cxgbe/common/t4_regs.h:#define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP) dev/cxgbe/common/t4_regs.h:#define V_VERSIONID(x) ((x) << S_VERSIONID) dev/cxgbe/common/t4_regs.h:#define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID) dev/cxgbe/common/t4_regs.h:#define V_VENDORID(x) ((x) << S_VENDORID) dev/cxgbe/common/t4_regs.h:#define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID) dev/cxgbe/common/t4_regs.h:#define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG) dev/cxgbe/common/t4_regs.h:#define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG) dev/cxgbe/common/t4_regs.h:#define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG) dev/cxgbe/common/t4_regs.h:#define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG) dev/cxgbe/common/t4_regs.h:#define V_MDIDATA(x) ((x) << S_MDIDATA) dev/cxgbe/common/t4_regs.h:#define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA) dev/cxgbe/common/t4_regs.h:#define V_MDIOP(x) ((x) << S_MDIOP) dev/cxgbe/common/t4_regs.h:#define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP) dev/cxgbe/common/t4_regs.h:#define V_STOPBITS(x) ((x) << S_STOPBITS) dev/cxgbe/common/t4_regs.h:#define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS) dev/cxgbe/common/t4_regs.h:#define V_PARITY(x) ((x) << S_PARITY) dev/cxgbe/common/t4_regs.h:#define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY) dev/cxgbe/common/t4_regs.h:#define V_DATABITS(x) ((x) << S_DATABITS) dev/cxgbe/common/t4_regs.h:#define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS) dev/cxgbe/common/t4_regs.h:#define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV) dev/cxgbe/common/t4_regs.h:#define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV) dev/cxgbe/common/t4_regs.h:#define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE) dev/cxgbe/common/t4_regs.h:#define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE) dev/cxgbe/common/t4_regs.h:#define V_ULPRX_TID(x) ((x) << S_ULPRX_TID) dev/cxgbe/common/t4_regs.h:#define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID) dev/cxgbe/common/t4_regs.h:#define V_SEL_H(x) ((x) << S_SEL_H) dev/cxgbe/common/t4_regs.h:#define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H) dev/cxgbe/common/t4_regs.h:#define V_SEL_L(x) ((x) << S_SEL_L) dev/cxgbe/common/t4_regs.h:#define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L) dev/cxgbe/common/t4_regs.h:#define V_RD_PTR(x) ((x) << S_RD_PTR) dev/cxgbe/common/t4_regs.h:#define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR) dev/cxgbe/common/t4_regs.h:#define V_WR_PTR(x) ((x) << S_WR_PTR) dev/cxgbe/common/t4_regs.h:#define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR) dev/cxgbe/common/t4_regs.h:#define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO) dev/cxgbe/common/t4_regs.h:#define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO) dev/cxgbe/common/t4_regs.h:#define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO) dev/cxgbe/common/t4_regs.h:#define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO) dev/cxgbe/common/t4_regs.h:#define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO) dev/cxgbe/common/t4_regs.h:#define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO) dev/cxgbe/common/t4_regs.h:#define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO) dev/cxgbe/common/t4_regs.h:#define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO) dev/cxgbe/common/t4_regs.h:#define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE) dev/cxgbe/common/t4_regs.h:#define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE) dev/cxgbe/common/t4_regs.h:#define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE) dev/cxgbe/common/t4_regs.h:#define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE) dev/cxgbe/common/t4_regs.h:#define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT) dev/cxgbe/common/t4_regs.h:#define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT) dev/cxgbe/common/t4_regs.h:#define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN) dev/cxgbe/common/t4_regs.h:#define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN) dev/cxgbe/common/t4_regs.h:#define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN) dev/cxgbe/common/t4_regs.h:#define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN) dev/cxgbe/common/t4_regs.h:#define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN) dev/cxgbe/common/t4_regs.h:#define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN) dev/cxgbe/common/t4_regs.h:#define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT) dev/cxgbe/common/t4_regs.h:#define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT) dev/cxgbe/common/t4_regs.h:#define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT) dev/cxgbe/common/t4_regs.h:#define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT) dev/cxgbe/common/t4_regs.h:#define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT) dev/cxgbe/common/t4_regs.h:#define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT) dev/cxgbe/common/t4_regs.h:#define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT) dev/cxgbe/common/t4_regs.h:#define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT) dev/cxgbe/common/t4_regs.h:#define V_TLS_RX_REG_OFF_ADDR(x) ((x) << S_TLS_RX_REG_OFF_ADDR) dev/cxgbe/common/t4_regs.h:#define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR) dev/cxgbe/common/t4_regs.h:#define V_PORTXMAP(x) ((x) << S_PORTXMAP) dev/cxgbe/common/t4_regs.h:#define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP) dev/cxgbe/common/t4_regs.h:#define V_SOURCEBUS(x) ((x) << S_SOURCEBUS) dev/cxgbe/common/t4_regs.h:#define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS) dev/cxgbe/common/t4_regs.h:#define V_SOURCEPF(x) ((x) << S_SOURCEPF) dev/cxgbe/common/t4_regs.h:#define V_VFID(x) ((x) << S_VFID) dev/cxgbe/common/t4_regs.h:#define G_VFID(x) (((x) >> S_VFID) & M_VFID) dev/cxgbe/common/t4_regs.h:#define V_CHIPID(x) ((x) << S_CHIPID) dev/cxgbe/common/t4_regs.h:#define V_MAPNCSI(x) ((x) << S_MAPNCSI) dev/cxgbe/common/t4_regs.h:#define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI) dev/cxgbe/common/t4_regs.h:#define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT) dev/cxgbe/common/t4_regs.h:#define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT) dev/cxgbe/common/t4_regs.h:#define V_MAPMI(x) ((x) << S_MAPMI) dev/cxgbe/common/t4_regs.h:#define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI) dev/cxgbe/common/t4_regs.h:#define V_MAPSMB(x) ((x) << S_MAPSMB) dev/cxgbe/common/t4_regs.h:#define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB) dev/cxgbe/common/t4_regs.h:#define V_MAPDBG(x) ((x) << S_MAPDBG) dev/cxgbe/common/t4_regs.h:#define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG) dev/cxgbe/common/t4_regs.h:#define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED) dev/cxgbe/common/t4_regs.h:#define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED) dev/cxgbe/common/t4_regs.h:#define V_LTSSM(x) ((x) << S_LTSSM) dev/cxgbe/common/t4_regs.h:#define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM) dev/cxgbe/common/t4_regs.h:#define V_SPEED_PL(x) ((x) << S_SPEED_PL) dev/cxgbe/common/t4_regs.h:#define G_SPEED_PL(x) (((x) >> S_SPEED_PL) & M_SPEED_PL) dev/cxgbe/common/t4_regs.h:#define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS) dev/cxgbe/common/t4_regs.h:#define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS) dev/cxgbe/common/t4_regs.h:#define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL) dev/cxgbe/common/t4_regs.h:#define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL) dev/cxgbe/common/t4_regs.h:#define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS) dev/cxgbe/common/t4_regs.h:#define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS) dev/cxgbe/common/t4_regs.h:#define V_ENABLEPF(x) ((x) << S_ENABLEPF) dev/cxgbe/common/t4_regs.h:#define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF) dev/cxgbe/common/t4_regs.h:#define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS) dev/cxgbe/common/t4_regs.h:#define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS) dev/cxgbe/common/t4_regs.h:#define V_SEMSRCPF(x) ((x) << S_SEMSRCPF) dev/cxgbe/common/t4_regs.h:#define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF) dev/cxgbe/common/t4_regs.h:#define V_PF_ENABLE(x) ((x) << S_PF_ENABLE) dev/cxgbe/common/t4_regs.h:#define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE) dev/cxgbe/common/t4_regs.h:#define V_LIMITADDR(x) ((x) << S_LIMITADDR) dev/cxgbe/common/t4_regs.h:#define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR) dev/cxgbe/common/t4_regs.h:#define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR) dev/cxgbe/common/t4_regs.h:#define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR) dev/cxgbe/common/t4_regs.h:#define V_MODINDX(x) ((x) << S_MODINDX) dev/cxgbe/common/t4_regs.h:#define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX) dev/cxgbe/common/t4_regs.h:#define V_MODOFFSET(x) ((x) << S_MODOFFSET) dev/cxgbe/common/t4_regs.h:#define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET) dev/cxgbe/common/t4_regs.h:#define V_FLR_PF(x) ((x) << S_FLR_PF) dev/cxgbe/common/t4_regs.h:#define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF) dev/cxgbe/common/t4_regs.h:#define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define V_PL_TOADDR(x) ((x) << S_PL_TOADDR) dev/cxgbe/common/t4_regs.h:#define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR) dev/cxgbe/common/t4_regs.h:#define V_PL_TOBUS(x) ((x) << S_PL_TOBUS) dev/cxgbe/common/t4_regs.h:#define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS) dev/cxgbe/common/t4_regs.h:#define V_PL_TOPF(x) ((x) << S_PL_TOPF) dev/cxgbe/common/t4_regs.h:#define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF) dev/cxgbe/common/t4_regs.h:#define V_PL_TORID(x) ((x) << S_PL_TORID) dev/cxgbe/common/t4_regs.h:#define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID) dev/cxgbe/common/t4_regs.h:#define V_PL_TOVFID(x) ((x) << S_PL_TOVFID) dev/cxgbe/common/t4_regs.h:#define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID) dev/cxgbe/common/t4_regs.h:#define V_REGION_EN(x) ((x) << S_REGION_EN) dev/cxgbe/common/t4_regs.h:#define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN) dev/cxgbe/common/t4_regs.h:#define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL) dev/cxgbe/common/t4_regs.h:#define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL) dev/cxgbe/common/t4_regs.h:#define V_CMDLIMIT(x) ((x) << S_CMDLIMIT) dev/cxgbe/common/t4_regs.h:#define G_CMDLIMIT(x) (((x) >> S_CMDLIMIT) & M_CMDLIMIT) dev/cxgbe/common/t4_regs.h:#define V_ATINDX(x) ((x) << S_ATINDX) dev/cxgbe/common/t4_regs.h:#define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX) dev/cxgbe/common/t4_regs.h:#define V_FTINDX(x) ((x) << S_FTINDX) dev/cxgbe/common/t4_regs.h:#define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX) dev/cxgbe/common/t4_regs.h:#define V_NFTINDX(x) ((x) << S_NFTINDX) dev/cxgbe/common/t4_regs.h:#define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX) dev/cxgbe/common/t4_regs.h:#define V_CLIPTINDX(x) ((x) << S_CLIPTINDX) dev/cxgbe/common/t4_regs.h:#define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX) dev/cxgbe/common/t4_regs.h:#define V_HFTINDX(x) ((x) << S_HFTINDX) dev/cxgbe/common/t4_regs.h:#define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX) dev/cxgbe/common/t4_regs.h:#define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE) dev/cxgbe/common/t4_regs.h:#define V_HASHSIZE(x) ((x) << S_HASHSIZE) dev/cxgbe/common/t4_regs.h:#define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE) dev/cxgbe/common/t4_regs.h:#define V_NUMHASHBKT(x) ((x) << S_NUMHASHBKT) dev/cxgbe/common/t4_regs.h:#define G_NUMHASHBKT(x) (((x) >> S_NUMHASHBKT) & M_NUMHASHBKT) dev/cxgbe/common/t4_regs.h:#define V_HASHTBLSIZE(x) ((x) << S_HASHTBLSIZE) dev/cxgbe/common/t4_regs.h:#define G_HASHTBLSIZE(x) (((x) >> S_HASHTBLSIZE) & M_HASHTBLSIZE) dev/cxgbe/common/t4_regs.h:#define V_MIN_ATCAM_ENTS(x) ((x) << S_MIN_ATCAM_ENTS) dev/cxgbe/common/t4_regs.h:#define G_MIN_ATCAM_ENTS(x) (((x) >> S_MIN_ATCAM_ENTS) & M_MIN_ATCAM_ENTS) dev/cxgbe/common/t4_regs.h:#define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR) dev/cxgbe/common/t4_regs.h:#define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR) dev/cxgbe/common/t4_regs.h:#define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE) dev/cxgbe/common/t4_regs.h:#define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE) dev/cxgbe/common/t4_regs.h:#define V_CMD_CMP_MASK(x) ((x) << S_CMD_CMP_MASK) dev/cxgbe/common/t4_regs.h:#define G_CMD_CMP_MASK(x) (((x) >> S_CMD_CMP_MASK) & M_CMD_CMP_MASK) dev/cxgbe/common/t4_regs.h:#define V_TID_CMP_MASK(x) ((x) << S_TID_CMP_MASK) dev/cxgbe/common/t4_regs.h:#define G_TID_CMP_MASK(x) (((x) >> S_TID_CMP_MASK) & M_TID_CMP_MASK) dev/cxgbe/common/t4_regs.h:#define V_CMD_CMP(x) ((x) << S_CMD_CMP) dev/cxgbe/common/t4_regs.h:#define G_CMD_CMP(x) (((x) >> S_CMD_CMP) & M_CMD_CMP) dev/cxgbe/common/t4_regs.h:#define V_TID_CMP(x) ((x) << S_TID_CMP) dev/cxgbe/common/t4_regs.h:#define G_TID_CMP(x) (((x) >> S_TID_CMP) & M_TID_CMP) dev/cxgbe/common/t4_regs.h:#define V_INTINDEX(x) ((x) << S_INTINDEX) dev/cxgbe/common/t4_regs.h:#define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX) dev/cxgbe/common/t4_regs.h:#define V_ERR_CID(x) ((x) << S_ERR_CID) dev/cxgbe/common/t4_regs.h:#define G_ERR_CID(x) (((x) >> S_ERR_CID) & M_ERR_CID) dev/cxgbe/common/t4_regs.h:#define V_ERR_PROT(x) ((x) << S_ERR_PROT) dev/cxgbe/common/t4_regs.h:#define G_ERR_PROT(x) (((x) >> S_ERR_PROT) & M_ERR_PROT) dev/cxgbe/common/t4_regs.h:#define V_ERR_TID(x) ((x) << S_ERR_TID) dev/cxgbe/common/t4_regs.h:#define G_ERR_TID(x) (((x) >> S_ERR_TID) & M_ERR_TID) dev/cxgbe/common/t4_regs.h:#define V_INTCMD(x) ((x) << S_INTCMD) dev/cxgbe/common/t4_regs.h:#define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD) dev/cxgbe/common/t4_regs.h:#define V_MAX_HASH_ENTS(x) ((x) << S_MAX_HASH_ENTS) dev/cxgbe/common/t4_regs.h:#define G_MAX_HASH_ENTS(x) (((x) >> S_MAX_HASH_ENTS) & M_MAX_HASH_ENTS) dev/cxgbe/common/t4_regs.h:#define V_SUCCESS(x) ((x) << S_SUCCESS) dev/cxgbe/common/t4_regs.h:#define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS) dev/cxgbe/common/t4_regs.h:#define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC) dev/cxgbe/common/t4_regs.h:#define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC) dev/cxgbe/common/t4_regs.h:#define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC) dev/cxgbe/common/t4_regs.h:#define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC) dev/cxgbe/common/t4_regs.h:#define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT) dev/cxgbe/common/t4_regs.h:#define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT) dev/cxgbe/common/t4_regs.h:#define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT) dev/cxgbe/common/t4_regs.h:#define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT) dev/cxgbe/common/t4_regs.h:#define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT) dev/cxgbe/common/t4_regs.h:#define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT) dev/cxgbe/common/t4_regs.h:#define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT) dev/cxgbe/common/t4_regs.h:#define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT) dev/cxgbe/common/t4_regs.h:#define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT) dev/cxgbe/common/t4_regs.h:#define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT) dev/cxgbe/common/t4_regs.h:#define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT) dev/cxgbe/common/t4_regs.h:#define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT) dev/cxgbe/common/t4_regs.h:#define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR) dev/cxgbe/common/t4_regs.h:#define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR) dev/cxgbe/common/t4_regs.h:#define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR) dev/cxgbe/common/t4_regs.h:#define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR) dev/cxgbe/common/t4_regs.h:#define V_SRCH_RGN_HIT(x) ((x) << S_SRCH_RGN_HIT) dev/cxgbe/common/t4_regs.h:#define G_SRCH_RGN_HIT(x) (((x) >> S_SRCH_RGN_HIT) & M_SRCH_RGN_HIT) dev/cxgbe/common/t4_regs.h:#define V_CLIP_FAIL(x) ((x) << S_CLIP_FAIL) dev/cxgbe/common/t4_regs.h:#define G_CLIP_FAIL(x) (((x) >> S_CLIP_FAIL) & M_CLIP_FAIL) dev/cxgbe/common/t4_regs.h:#define V_LIP_ZERO_ERR(x) ((x) << S_LIP_ZERO_ERR) dev/cxgbe/common/t4_regs.h:#define G_LIP_ZERO_ERR(x) (((x) >> S_LIP_ZERO_ERR) & M_LIP_ZERO_ERR) dev/cxgbe/common/t4_regs.h:#define V_UNKNOWN_CMD(x) ((x) << S_UNKNOWN_CMD) dev/cxgbe/common/t4_regs.h:#define G_UNKNOWN_CMD(x) (((x) >> S_UNKNOWN_CMD) & M_UNKNOWN_CMD) dev/cxgbe/common/t4_regs.h:#define V_CMD_TID_ERR(x) ((x) << S_CMD_TID_ERR) dev/cxgbe/common/t4_regs.h:#define G_CMD_TID_ERR(x) (((x) >> S_CMD_TID_ERR) & M_CMD_TID_ERR) dev/cxgbe/common/t4_regs.h:#define V_INTERNAL_ERR(x) ((x) << S_INTERNAL_ERR) dev/cxgbe/common/t4_regs.h:#define G_INTERNAL_ERR(x) (((x) >> S_INTERNAL_ERR) & M_INTERNAL_ERR) dev/cxgbe/common/t4_regs.h:#define V_SRAM_SRVR_HIT_ACTF(x) ((x) << S_SRAM_SRVR_HIT_ACTF) dev/cxgbe/common/t4_regs.h:#define G_SRAM_SRVR_HIT_ACTF(x) (((x) >> S_SRAM_SRVR_HIT_ACTF) & M_SRAM_SRVR_HIT_ACTF) dev/cxgbe/common/t4_regs.h:#define V_TCAM_SRVR_HIT_ACTF(x) ((x) << S_TCAM_SRVR_HIT_ACTF) dev/cxgbe/common/t4_regs.h:#define G_TCAM_SRVR_HIT_ACTF(x) (((x) >> S_TCAM_SRVR_HIT_ACTF) & M_TCAM_SRVR_HIT_ACTF) dev/cxgbe/common/t4_regs.h:#define V_INVLDRD(x) ((x) << S_INVLDRD) dev/cxgbe/common/t4_regs.h:#define G_INVLDRD(x) (((x) >> S_INVLDRD) & M_INVLDRD) dev/cxgbe/common/t4_regs.h:#define V_TUPLZERO(x) ((x) << S_TUPLZERO) dev/cxgbe/common/t4_regs.h:#define G_TUPLZERO(x) (((x) >> S_TUPLZERO) & M_TUPLZERO) dev/cxgbe/common/t4_regs.h:#define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH) dev/cxgbe/common/t4_regs.h:#define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH) dev/cxgbe/common/t4_regs.h:#define V_RSPCNTLE(x) ((x) << S_RSPCNTLE) dev/cxgbe/common/t4_regs.h:#define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE) dev/cxgbe/common/t4_regs.h:#define V_REQCNTLE(x) ((x) << S_REQCNTLE) dev/cxgbe/common/t4_regs.h:#define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE) dev/cxgbe/common/t4_regs.h:#define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE) dev/cxgbe/common/t4_regs.h:#define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE) dev/cxgbe/common/t4_regs.h:#define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE) dev/cxgbe/common/t4_regs.h:#define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE) dev/cxgbe/common/t4_regs.h:#define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE) dev/cxgbe/common/t4_regs.h:#define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE) dev/cxgbe/common/t4_regs.h:#define V_DBGICMD(x) ((x) << S_DBGICMD) dev/cxgbe/common/t4_regs.h:#define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD) dev/cxgbe/common/t4_regs.h:#define V_DBGITINDEX(x) ((x) << S_DBGITINDEX) dev/cxgbe/common/t4_regs.h:#define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX) dev/cxgbe/common/t4_regs.h:#define V_DBGITID(x) ((x) << S_DBGITID) dev/cxgbe/common/t4_regs.h:#define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID) dev/cxgbe/common/t4_regs.h:#define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD) dev/cxgbe/common/t4_regs.h:#define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD) dev/cxgbe/common/t4_regs.h:#define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX) dev/cxgbe/common/t4_regs.h:#define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX) dev/cxgbe/common/t4_regs.h:#define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID) dev/cxgbe/common/t4_regs.h:#define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID) dev/cxgbe/common/t4_regs.h:#define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX) dev/cxgbe/common/t4_regs.h:#define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX) dev/cxgbe/common/t4_regs.h:#define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR) dev/cxgbe/common/t4_regs.h:#define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR) dev/cxgbe/common/t4_regs.h:#define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE) dev/cxgbe/common/t4_regs.h:#define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE) dev/cxgbe/common/t4_regs.h:#define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR) dev/cxgbe/common/t4_regs.h:#define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR) dev/cxgbe/common/t4_regs.h:#define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE) dev/cxgbe/common/t4_regs.h:#define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE) dev/cxgbe/common/t4_regs.h:#define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR) dev/cxgbe/common/t4_regs.h:#define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR) dev/cxgbe/common/t4_regs.h:#define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE) dev/cxgbe/common/t4_regs.h:#define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE) dev/cxgbe/common/t4_regs.h:#define V_LEMEMSEL(x) ((x) << S_LEMEMSEL) dev/cxgbe/common/t4_regs.h:#define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL) dev/cxgbe/common/t4_regs.h:#define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE) dev/cxgbe/common/t4_regs.h:#define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE) dev/cxgbe/common/t4_regs.h:#define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE) dev/cxgbe/common/t4_regs.h:#define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE) dev/cxgbe/common/t4_regs.h:#define V_VFINDEX(x) ((x) << S_VFINDEX) dev/cxgbe/common/t4_regs.h:#define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX) dev/cxgbe/common/t4_regs.h:#define V_SRCHHADDR(x) ((x) << S_SRCHHADDR) dev/cxgbe/common/t4_regs.h:#define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR) dev/cxgbe/common/t4_regs.h:#define V_SRCHLADDR(x) ((x) << S_SRCHLADDR) dev/cxgbe/common/t4_regs.h:#define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR) dev/cxgbe/common/t4_regs.h:#define V_WIREEN(x) ((x) << S_WIREEN) dev/cxgbe/common/t4_regs.h:#define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN) dev/cxgbe/common/t4_regs.h:#define V_STRP_CRC(x) ((x) << S_STRP_CRC) dev/cxgbe/common/t4_regs.h:#define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC) dev/cxgbe/common/t4_regs.h:#define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE) dev/cxgbe/common/t4_regs.h:#define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE) dev/cxgbe/common/t4_regs.h:#define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE) dev/cxgbe/common/t4_regs.h:#define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE) dev/cxgbe/common/t4_regs.h:#define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT) dev/cxgbe/common/t4_regs.h:#define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT) dev/cxgbe/common/t4_regs.h:#define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT) dev/cxgbe/common/t4_regs.h:#define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR) dev/cxgbe/common/t4_regs.h:#define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR) dev/cxgbe/common/t4_regs.h:#define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR) dev/cxgbe/common/t4_regs.h:#define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR) dev/cxgbe/common/t4_regs.h:#define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT) dev/cxgbe/common/t4_regs.h:#define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT) dev/cxgbe/common/t4_regs.h:#define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN) dev/cxgbe/common/t4_regs.h:#define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN) dev/cxgbe/common/t4_regs.h:#define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT) dev/cxgbe/common/t4_regs.h:#define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT) dev/cxgbe/common/t4_regs.h:#define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN) dev/cxgbe/common/t4_regs.h:#define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN) dev/cxgbe/common/t4_regs.h:#define V_PAUSEHWM(x) ((x) << S_PAUSEHWM) dev/cxgbe/common/t4_regs.h:#define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM) dev/cxgbe/common/t4_regs.h:#define V_PAUSELWM(x) ((x) << S_PAUSELWM) dev/cxgbe/common/t4_regs.h:#define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM) dev/cxgbe/common/t4_regs.h:#define V_DEBUGSEL(x) ((x) << S_DEBUGSEL) dev/cxgbe/common/t4_regs.h:#define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL) dev/cxgbe/common/t4_regs.h:#define V_PKG_ID(x) ((x) << S_PKG_ID) dev/cxgbe/common/t4_regs.h:#define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID) dev/cxgbe/common/t4_regs.h:#define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET) dev/cxgbe/common/t4_regs.h:#define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET) dev/cxgbe/common/t4_regs.h:#define V_PCLKDIV(x) ((x) << S_PCLKDIV) dev/cxgbe/common/t4_regs.h:#define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV) dev/cxgbe/common/t4_regs.h:#define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR) dev/cxgbe/common/t4_regs.h:#define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR) dev/cxgbe/common/t4_regs.h:#define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR) dev/cxgbe/common/t4_regs.h:#define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR) dev/cxgbe/common/t4_regs.h:#define V_PAUSETIME(x) ((x) << S_PAUSETIME) dev/cxgbe/common/t4_regs.h:#define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME) dev/cxgbe/common/t4_regs.h:#define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD) dev/cxgbe/common/t4_regs.h:#define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD) dev/cxgbe/common/t4_regs.h:#define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK) dev/cxgbe/common/t4_regs.h:#define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK) dev/cxgbe/common/t4_regs.h:#define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES) dev/cxgbe/common/t4_regs.h:#define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES) dev/cxgbe/common/t4_regs.h:#define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES) dev/cxgbe/common/t4_regs.h:#define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES) dev/cxgbe/common/t4_regs.h:#define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK) dev/cxgbe/common/t4_regs.h:#define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK) dev/cxgbe/common/t4_regs.h:#define V_RXFCSERR(x) ((x) << S_RXFCSERR) dev/cxgbe/common/t4_regs.h:#define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR) dev/cxgbe/common/t4_regs.h:#define V_RXALIGNERR(x) ((x) << S_RXALIGNERR) dev/cxgbe/common/t4_regs.h:#define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR) dev/cxgbe/common/t4_regs.h:#define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES) dev/cxgbe/common/t4_regs.h:#define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES) dev/cxgbe/common/t4_regs.h:#define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS) dev/cxgbe/common/t4_regs.h:#define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS) dev/cxgbe/common/t4_regs.h:#define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS) dev/cxgbe/common/t4_regs.h:#define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS) dev/cxgbe/common/t4_regs.h:#define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR) dev/cxgbe/common/t4_regs.h:#define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR) dev/cxgbe/common/t4_regs.h:#define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS) dev/cxgbe/common/t4_regs.h:#define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS) dev/cxgbe/common/t4_regs.h:#define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR) dev/cxgbe/common/t4_regs.h:#define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR) dev/cxgbe/common/t4_regs.h:#define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT) dev/cxgbe/common/t4_regs.h:#define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT) dev/cxgbe/common/t4_regs.h:#define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR) dev/cxgbe/common/t4_regs.h:#define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR) dev/cxgbe/common/t4_regs.h:#define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR) dev/cxgbe/common/t4_regs.h:#define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR) dev/cxgbe/common/t4_regs.h:#define V_RXJABBERERR(x) ((x) << S_RXJABBERERR) dev/cxgbe/common/t4_regs.h:#define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR) dev/cxgbe/common/t4_regs.h:#define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR) dev/cxgbe/common/t4_regs.h:#define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR) dev/cxgbe/common/t4_regs.h:#define V_SQETESTERR(x) ((x) << S_SQETESTERR) dev/cxgbe/common/t4_regs.h:#define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR) dev/cxgbe/common/t4_regs.h:#define V_LENGTHERR(x) ((x) << S_LENGTHERR) dev/cxgbe/common/t4_regs.h:#define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR) dev/cxgbe/common/t4_regs.h:#define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES) dev/cxgbe/common/t4_regs.h:#define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES) dev/cxgbe/common/t4_regs.h:#define V_MATCHHIGH(x) ((x) << S_MATCHHIGH) dev/cxgbe/common/t4_regs.h:#define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH) dev/cxgbe/common/t4_regs.h:#define V_TYPEID(x) ((x) << S_TYPEID) dev/cxgbe/common/t4_regs.h:#define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID) dev/cxgbe/common/t4_regs.h:#define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM) dev/cxgbe/common/t4_regs.h:#define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM) dev/cxgbe/common/t4_regs.h:#define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT) dev/cxgbe/common/t4_regs.h:#define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT) dev/cxgbe/common/t4_regs.h:#define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT) dev/cxgbe/common/t4_regs.h:#define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT) dev/cxgbe/common/t4_regs.h:#define V_ARPIPADDR(x) ((x) << S_ARPIPADDR) dev/cxgbe/common/t4_regs.h:#define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR) dev/cxgbe/common/t4_regs.h:#define V_PARTREF(x) ((x) << S_PARTREF) dev/cxgbe/common/t4_regs.h:#define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF) dev/cxgbe/common/t4_regs.h:#define V_DESREV(x) ((x) << S_DESREV) dev/cxgbe/common/t4_regs.h:#define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV) dev/cxgbe/common/t4_regs.h:#define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL) dev/cxgbe/common/t4_regs.h:#define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL) dev/cxgbe/common/t4_regs.h:#define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL) dev/cxgbe/common/t4_regs.h:#define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL) dev/cxgbe/common/t4_regs.h:#define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL) dev/cxgbe/common/t4_regs.h:#define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL) dev/cxgbe/common/t4_regs.h:#define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI) dev/cxgbe/common/t4_regs.h:#define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI) dev/cxgbe/common/t4_regs.h:#define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO) dev/cxgbe/common/t4_regs.h:#define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO) dev/cxgbe/common/t4_regs.h:#define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL) dev/cxgbe/common/t4_regs.h:#define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL) dev/cxgbe/common/t4_regs.h:#define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV) dev/cxgbe/common/t4_regs.h:#define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV) dev/cxgbe/common/t4_regs.h:#define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV) dev/cxgbe/common/t4_regs.h:#define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV) dev/cxgbe/common/t4_regs.h:#define V_INSTANCENUM(x) ((x) << S_INSTANCENUM) dev/cxgbe/common/t4_regs.h:#define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM) dev/cxgbe/common/t4_regs.h:#define V_TX_IPG(x) ((x) << S_TX_IPG) dev/cxgbe/common/t4_regs.h:#define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG) dev/cxgbe/common/t4_regs.h:#define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT) dev/cxgbe/common/t4_regs.h:#define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT) dev/cxgbe/common/t4_regs.h:#define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT) dev/cxgbe/common/t4_regs.h:#define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT) dev/cxgbe/common/t4_regs.h:#define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT) dev/cxgbe/common/t4_regs.h:#define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT) dev/cxgbe/common/t4_regs.h:#define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT) dev/cxgbe/common/t4_regs.h:#define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT) dev/cxgbe/common/t4_regs.h:#define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA) dev/cxgbe/common/t4_regs.h:#define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA) dev/cxgbe/common/t4_regs.h:#define V_TXSOP(x) ((x) << S_TXSOP) dev/cxgbe/common/t4_regs.h:#define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP) dev/cxgbe/common/t4_regs.h:#define V_TXEOP(x) ((x) << S_TXEOP) dev/cxgbe/common/t4_regs.h:#define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP) dev/cxgbe/common/t4_regs.h:#define V_RXSOP(x) ((x) << S_RXSOP) dev/cxgbe/common/t4_regs.h:#define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP) dev/cxgbe/common/t4_regs.h:#define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT) dev/cxgbe/common/t4_regs.h:#define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT) dev/cxgbe/common/t4_regs.h:#define V_CTRL(x) ((x) << S_CTRL) dev/cxgbe/common/t4_regs.h:#define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL) dev/cxgbe/common/t4_regs.h:#define V_HWM(x) ((x) << S_HWM) dev/cxgbe/common/t4_regs.h:#define G_HWM(x) (((x) >> S_HWM) & M_HWM) dev/cxgbe/common/t4_regs.h:#define V_LWM(x) ((x) << S_LWM) dev/cxgbe/common/t4_regs.h:#define G_LWM(x) (((x) >> S_LWM) & M_LWM) dev/cxgbe/common/t4_regs.h:#define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS) dev/cxgbe/common/t4_regs.h:#define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL) dev/cxgbe/common/t4_regs.h:#define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL) dev/cxgbe/common/t4_regs.h:#define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG) dev/cxgbe/common/t4_regs.h:#define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG) dev/cxgbe/common/t4_regs.h:#define V_CRCCAL(x) ((x) << S_CRCCAL) dev/cxgbe/common/t4_regs.h:#define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL) dev/cxgbe/common/t4_regs.h:#define V_RXCRCCAL(x) ((x) << S_RXCRCCAL) dev/cxgbe/common/t4_regs.h:#define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL) dev/cxgbe/common/t4_regs.h:#define V_FRAMETYPE(x) ((x) << S_FRAMETYPE) dev/cxgbe/common/t4_regs.h:#define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE) dev/cxgbe/common/t4_regs.h:#define V_OPERATION(x) ((x) << S_OPERATION) dev/cxgbe/common/t4_regs.h:#define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION) dev/cxgbe/common/t4_regs.h:#define V_PORTADDR(x) ((x) << S_PORTADDR) dev/cxgbe/common/t4_regs.h:#define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR) dev/cxgbe/common/t4_regs.h:#define V_DEVADDR(x) ((x) << S_DEVADDR) dev/cxgbe/common/t4_regs.h:#define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR) dev/cxgbe/common/t4_regs.h:#define V_RESRV(x) ((x) << S_RESRV) dev/cxgbe/common/t4_regs.h:#define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV) dev/cxgbe/common/t4_regs.h:#define V_MODULEID(x) ((x) << S_MODULEID) dev/cxgbe/common/t4_regs.h:#define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID) dev/cxgbe/common/t4_regs.h:#define V_MODULEREV(x) ((x) << S_MODULEREV) dev/cxgbe/common/t4_regs.h:#define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV) dev/cxgbe/common/t4_regs.h:#define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX) dev/cxgbe/common/t4_regs.h:#define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX) dev/cxgbe/common/t4_regs.h:#define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX) dev/cxgbe/common/t4_regs.h:#define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX) dev/cxgbe/common/t4_regs.h:#define V_TEST_SEL(x) ((x) << S_TEST_SEL) dev/cxgbe/common/t4_regs.h:#define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL) dev/cxgbe/common/t4_regs.h:#define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR) dev/cxgbe/common/t4_regs.h:#define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR) dev/cxgbe/common/t4_regs.h:#define V_TESTSEL(x) ((x) << S_TESTSEL) dev/cxgbe/common/t4_regs.h:#define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL) dev/cxgbe/common/t4_regs.h:#define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER) dev/cxgbe/common/t4_regs.h:#define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER) dev/cxgbe/common/t4_regs.h:#define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER) dev/cxgbe/common/t4_regs.h:#define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER) dev/cxgbe/common/t4_regs.h:#define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT) dev/cxgbe/common/t4_regs.h:#define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT) dev/cxgbe/common/t4_regs.h:#define V_BER_COUNT(x) ((x) << S_BER_COUNT) dev/cxgbe/common/t4_regs.h:#define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT) dev/cxgbe/common/t4_regs.h:#define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT) dev/cxgbe/common/t4_regs.h:#define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT) dev/cxgbe/common/t4_regs.h:#define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE) dev/cxgbe/common/t4_regs.h:#define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE) dev/cxgbe/common/t4_regs.h:#define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE) dev/cxgbe/common/t4_regs.h:#define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE) dev/cxgbe/common/t4_regs.h:#define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD) dev/cxgbe/common/t4_regs.h:#define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD) dev/cxgbe/common/t4_regs.h:#define V_NP_INFO(x) ((x) << S_NP_INFO) dev/cxgbe/common/t4_regs.h:#define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO) dev/cxgbe/common/t4_regs.h:#define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI) dev/cxgbe/common/t4_regs.h:#define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI) dev/cxgbe/common/t4_regs.h:#define V_LFSR_INIT(x) ((x) << S_LFSR_INIT) dev/cxgbe/common/t4_regs.h:#define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT) dev/cxgbe/common/t4_regs.h:#define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define V_MODULE_ID(x) ((x) << S_MODULE_ID) dev/cxgbe/common/t4_regs.h:#define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID) dev/cxgbe/common/t4_regs.h:#define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION) dev/cxgbe/common/t4_regs.h:#define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION) dev/cxgbe/common/t4_regs.h:#define V_MAN_DEC(x) ((x) << S_MAN_DEC) dev/cxgbe/common/t4_regs.h:#define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC) dev/cxgbe/common/t4_regs.h:#define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT) dev/cxgbe/common/t4_regs.h:#define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT) dev/cxgbe/common/t4_regs.h:#define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT) dev/cxgbe/common/t4_regs.h:#define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT) dev/cxgbe/common/t4_regs.h:#define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK) dev/cxgbe/common/t4_regs.h:#define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK) dev/cxgbe/common/t4_regs.h:#define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK) dev/cxgbe/common/t4_regs.h:#define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK) dev/cxgbe/common/t4_regs.h:#define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE) dev/cxgbe/common/t4_regs.h:#define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE) dev/cxgbe/common/t4_regs.h:#define V_TFSM_STATE(x) ((x) << S_TFSM_STATE) dev/cxgbe/common/t4_regs.h:#define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE) dev/cxgbe/common/t4_regs.h:#define V_BWSEL(x) ((x) << S_BWSEL) dev/cxgbe/common/t4_regs.h:#define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL) dev/cxgbe/common/t4_regs.h:#define V_RTSEL(x) ((x) << S_RTSEL) dev/cxgbe/common/t4_regs.h:#define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL) dev/cxgbe/common/t4_regs.h:#define V_TPSEL(x) ((x) << S_TPSEL) dev/cxgbe/common/t4_regs.h:#define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL) dev/cxgbe/common/t4_regs.h:#define V_SLEW(x) ((x) << S_SLEW) dev/cxgbe/common/t4_regs.h:#define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW) dev/cxgbe/common/t4_regs.h:#define V_FFE(x) ((x) << S_FFE) dev/cxgbe/common/t4_regs.h:#define G_FFE(x) (((x) >> S_FFE) & M_FFE) dev/cxgbe/common/t4_regs.h:#define V_IDAC(x) ((x) << S_IDAC) dev/cxgbe/common/t4_regs.h:#define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC) dev/cxgbe/common/t4_regs.h:#define V_STBY(x) ((x) << S_STBY) dev/cxgbe/common/t4_regs.h:#define G_STBY(x) (((x) >> S_STBY) & M_STBY) dev/cxgbe/common/t4_regs.h:#define V_PON(x) ((x) << S_PON) dev/cxgbe/common/t4_regs.h:#define G_PON(x) (((x) >> S_PON) & M_PON) dev/cxgbe/common/t4_regs.h:#define V_TXPWR(x) ((x) << S_TXPWR) dev/cxgbe/common/t4_regs.h:#define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR) dev/cxgbe/common/t4_regs.h:#define V_TXPOL(x) ((x) << S_TXPOL) dev/cxgbe/common/t4_regs.h:#define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL) dev/cxgbe/common/t4_regs.h:#define V_NTXPOL(x) ((x) << S_NTXPOL) dev/cxgbe/common/t4_regs.h:#define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL) dev/cxgbe/common/t4_regs.h:#define V_OPVAL(x) ((x) << S_OPVAL) dev/cxgbe/common/t4_regs.h:#define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL) dev/cxgbe/common/t4_regs.h:#define V_PDAC(x) ((x) << S_PDAC) dev/cxgbe/common/t4_regs.h:#define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC) dev/cxgbe/common/t4_regs.h:#define V_CURSD(x) ((x) << S_CURSD) dev/cxgbe/common/t4_regs.h:#define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD) dev/cxgbe/common/t4_regs.h:#define V_XDATA(x) ((x) << S_XDATA) dev/cxgbe/common/t4_regs.h:#define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA) dev/cxgbe/common/t4_regs.h:#define V_EXTADDR(x) ((x) << S_EXTADDR) dev/cxgbe/common/t4_regs.h:#define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR) dev/cxgbe/common/t4_regs.h:#define V_XADDR(x) ((x) << S_XADDR) dev/cxgbe/common/t4_regs.h:#define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR) dev/cxgbe/common/t4_regs.h:#define V_DMSEL(x) ((x) << S_DMSEL) dev/cxgbe/common/t4_regs.h:#define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL) dev/cxgbe/common/t4_regs.h:#define V_RRATE(x) ((x) << S_RRATE) dev/cxgbe/common/t4_regs.h:#define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE) dev/cxgbe/common/t4_regs.h:#define V_PRBSSEL(x) ((x) << S_PRBSSEL) dev/cxgbe/common/t4_regs.h:#define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL) dev/cxgbe/common/t4_regs.h:#define V_FTHROT(x) ((x) << S_FTHROT) dev/cxgbe/common/t4_regs.h:#define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT) dev/cxgbe/common/t4_regs.h:#define V_FILTCTL(x) ((x) << S_FILTCTL) dev/cxgbe/common/t4_regs.h:#define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL) dev/cxgbe/common/t4_regs.h:#define V_RSRVO(x) ((x) << S_RSRVO) dev/cxgbe/common/t4_regs.h:#define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO) dev/cxgbe/common/t4_regs.h:#define V_TMSCAL(x) ((x) << S_TMSCAL) dev/cxgbe/common/t4_regs.h:#define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL) dev/cxgbe/common/t4_regs.h:#define V_PHOFFS(x) ((x) << S_PHOFFS) dev/cxgbe/common/t4_regs.h:#define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS) dev/cxgbe/common/t4_regs.h:#define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT) dev/cxgbe/common/t4_regs.h:#define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT) dev/cxgbe/common/t4_regs.h:#define V_RAOOFF(x) ((x) << S_RAOOFF) dev/cxgbe/common/t4_regs.h:#define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF) dev/cxgbe/common/t4_regs.h:#define V_RAEOFF(x) ((x) << S_RAEOFF) dev/cxgbe/common/t4_regs.h:#define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF) dev/cxgbe/common/t4_regs.h:#define V_RDOFF(x) ((x) << S_RDOFF) dev/cxgbe/common/t4_regs.h:#define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF) dev/cxgbe/common/t4_regs.h:#define V_SIGNSD(x) ((x) << S_SIGNSD) dev/cxgbe/common/t4_regs.h:#define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD) dev/cxgbe/common/t4_regs.h:#define V_DACSD(x) ((x) << S_DACSD) dev/cxgbe/common/t4_regs.h:#define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD) dev/cxgbe/common/t4_regs.h:#define V_SDLVL(x) ((x) << S_SDLVL) dev/cxgbe/common/t4_regs.h:#define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL) dev/cxgbe/common/t4_regs.h:#define V_SPIFMT(x) ((x) << S_SPIFMT) dev/cxgbe/common/t4_regs.h:#define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT) dev/cxgbe/common/t4_regs.h:#define V_DFEPWR(x) ((x) << S_DFEPWR) dev/cxgbe/common/t4_regs.h:#define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR) dev/cxgbe/common/t4_regs.h:#define V_ESAMP(x) ((x) << S_ESAMP) dev/cxgbe/common/t4_regs.h:#define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP) dev/cxgbe/common/t4_regs.h:#define V_DSAMP(x) ((x) << S_DSAMP) dev/cxgbe/common/t4_regs.h:#define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP) dev/cxgbe/common/t4_regs.h:#define V_SMODE(x) ((x) << S_SMODE) dev/cxgbe/common/t4_regs.h:#define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE) dev/cxgbe/common/t4_regs.h:#define V_ASAMPQ(x) ((x) << S_ASAMPQ) dev/cxgbe/common/t4_regs.h:#define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ) dev/cxgbe/common/t4_regs.h:#define V_ASAMP(x) ((x) << S_ASAMP) dev/cxgbe/common/t4_regs.h:#define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP) dev/cxgbe/common/t4_regs.h:#define V_POLE(x) ((x) << S_POLE) dev/cxgbe/common/t4_regs.h:#define G_POLE(x) (((x) >> S_POLE) & M_POLE) dev/cxgbe/common/t4_regs.h:#define V_PEAK(x) ((x) << S_PEAK) dev/cxgbe/common/t4_regs.h:#define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK) dev/cxgbe/common/t4_regs.h:#define V_VOFFSN(x) ((x) << S_VOFFSN) dev/cxgbe/common/t4_regs.h:#define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN) dev/cxgbe/common/t4_regs.h:#define V_VOFFA(x) ((x) << S_VOFFA) dev/cxgbe/common/t4_regs.h:#define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA) dev/cxgbe/common/t4_regs.h:#define V_VGAIN(x) ((x) << S_VGAIN) dev/cxgbe/common/t4_regs.h:#define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN) dev/cxgbe/common/t4_regs.h:#define V_AMAXT(x) ((x) << S_AMAXT) dev/cxgbe/common/t4_regs.h:#define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT) dev/cxgbe/common/t4_regs.h:#define V_AOFFO(x) ((x) << S_AOFFO) dev/cxgbe/common/t4_regs.h:#define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO) dev/cxgbe/common/t4_regs.h:#define V_AOFFE(x) ((x) << S_AOFFE) dev/cxgbe/common/t4_regs.h:#define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE) dev/cxgbe/common/t4_regs.h:#define V_DACAN(x) ((x) << S_DACAN) dev/cxgbe/common/t4_regs.h:#define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN) dev/cxgbe/common/t4_regs.h:#define V_DACAP(x) ((x) << S_DACAP) dev/cxgbe/common/t4_regs.h:#define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP) dev/cxgbe/common/t4_regs.h:#define V_DACAZ(x) ((x) << S_DACAZ) dev/cxgbe/common/t4_regs.h:#define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ) dev/cxgbe/common/t4_regs.h:#define V_DACAM(x) ((x) << S_DACAM) dev/cxgbe/common/t4_regs.h:#define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM) dev/cxgbe/common/t4_regs.h:#define V_ADSN(x) ((x) << S_ADSN) dev/cxgbe/common/t4_regs.h:#define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN) dev/cxgbe/common/t4_regs.h:#define V_ADMAG(x) ((x) << S_ADMAG) dev/cxgbe/common/t4_regs.h:#define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG) dev/cxgbe/common/t4_regs.h:#define V_MINWIDTH(x) ((x) << S_MINWIDTH) dev/cxgbe/common/t4_regs.h:#define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH) dev/cxgbe/common/t4_regs.h:#define V_MINAMP(x) ((x) << S_MINAMP) dev/cxgbe/common/t4_regs.h:#define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP) dev/cxgbe/common/t4_regs.h:#define V_EMMD(x) ((x) << S_EMMD) dev/cxgbe/common/t4_regs.h:#define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD) dev/cxgbe/common/t4_regs.h:#define V_DPCTGT(x) ((x) << S_DPCTGT) dev/cxgbe/common/t4_regs.h:#define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT) dev/cxgbe/common/t4_regs.h:#define V_OAE(x) ((x) << S_OAE) dev/cxgbe/common/t4_regs.h:#define G_OAE(x) (((x) >> S_OAE) & M_OAE) dev/cxgbe/common/t4_regs.h:#define V_OLS(x) ((x) << S_OLS) dev/cxgbe/common/t4_regs.h:#define G_OLS(x) (((x) >> S_OLS) & M_OLS) dev/cxgbe/common/t4_regs.h:#define V_OES(x) ((x) << S_OES) dev/cxgbe/common/t4_regs.h:#define G_OES(x) (((x) >> S_OES) & M_OES) dev/cxgbe/common/t4_regs.h:#define V_ODEC(x) ((x) << S_ODEC) dev/cxgbe/common/t4_regs.h:#define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC) dev/cxgbe/common/t4_regs.h:#define V_BSELO(x) ((x) << S_BSELO) dev/cxgbe/common/t4_regs.h:#define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO) dev/cxgbe/common/t4_regs.h:#define V_BSELI(x) ((x) << S_BSELI) dev/cxgbe/common/t4_regs.h:#define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI) dev/cxgbe/common/t4_regs.h:#define V_ATST(x) ((x) << S_ATST) dev/cxgbe/common/t4_regs.h:#define G_ATST(x) (((x) >> S_ATST) & M_ATST) dev/cxgbe/common/t4_regs.h:#define V_CPISEL(x) ((x) << S_CPISEL) dev/cxgbe/common/t4_regs.h:#define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL) dev/cxgbe/common/t4_regs.h:#define V_BGCTL(x) ((x) << S_BGCTL) dev/cxgbe/common/t4_regs.h:#define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL) dev/cxgbe/common/t4_regs.h:#define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY) dev/cxgbe/common/t4_regs.h:#define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY) dev/cxgbe/common/t4_regs.h:#define V_IBQEMPTY(x) ((x) << S_IBQEMPTY) dev/cxgbe/common/t4_regs.h:#define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY) dev/cxgbe/common/t4_regs.h:#define V_OBQGEN(x) ((x) << S_OBQGEN) dev/cxgbe/common/t4_regs.h:#define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN) dev/cxgbe/common/t4_regs.h:#define V_OBQFULL(x) ((x) << S_OBQFULL) dev/cxgbe/common/t4_regs.h:#define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL) dev/cxgbe/common/t4_regs.h:#define V_QUEID(x) ((x) << S_QUEID) dev/cxgbe/common/t4_regs.h:#define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID) dev/cxgbe/common/t4_regs.h:#define V_IBQRDADDR(x) ((x) << S_IBQRDADDR) dev/cxgbe/common/t4_regs.h:#define V_IBQWRADDR(x) ((x) << S_IBQWRADDR) dev/cxgbe/common/t4_regs.h:#define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS) dev/cxgbe/common/t4_regs.h:#define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT) dev/cxgbe/common/t4_regs.h:#define V_QUESOPCNT(x) ((x) << S_QUESOPCNT) dev/cxgbe/common/t4_regs.h:#define V_OBQID(x) ((x) << S_OBQID) dev/cxgbe/common/t4_regs.h:#define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID) dev/cxgbe/common/t4_regs.h:#define V_QUERDADDR(x) ((x) << S_QUERDADDR) dev/cxgbe/common/t4_regs.h:#define V_QUEWRADDR(x) ((x) << S_QUEWRADDR) dev/cxgbe/common/t4_regs.h:#define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR) dev/cxgbe/common/t4_regs.h:#define V_QUESIZE(x) ((x) << S_QUESIZE) dev/cxgbe/common/t4_regs.h:#define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE) dev/cxgbe/common/t4_regs.h:#define V_QUEBASE(x) ((x) << S_QUEBASE) dev/cxgbe/common/t4_regs.h:#define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE) dev/cxgbe/common/t4_regs.h:#define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR) dev/cxgbe/common/t4_regs.h:#define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR) dev/cxgbe/common/t4_regs.h:#define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER) dev/cxgbe/common/t4_regs.h:#define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER) dev/cxgbe/common/t4_regs.h:#define V_MBPFINT(x) ((x) << S_MBPFINT) dev/cxgbe/common/t4_regs.h:#define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT) dev/cxgbe/common/t4_regs.h:#define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR) dev/cxgbe/common/t4_regs.h:#define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR) dev/cxgbe/common/t4_regs.h:#define V_FLSRC(x) ((x) << S_FLSRC) dev/cxgbe/common/t4_regs.h:#define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC) dev/cxgbe/common/t4_regs.h:#define V_SESRC(x) ((x) << S_SESRC) dev/cxgbe/common/t4_regs.h:#define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC) dev/cxgbe/common/t4_regs.h:#define V_UPPF(x) ((x) << S_UPPF) dev/cxgbe/common/t4_regs.h:#define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF) dev/cxgbe/common/t4_regs.h:#define V_UPRID(x) ((x) << S_UPRID) dev/cxgbe/common/t4_regs.h:#define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID) dev/cxgbe/common/t4_regs.h:#define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY) dev/cxgbe/common/t4_regs.h:#define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY) dev/cxgbe/common/t4_regs.h:#define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT) dev/cxgbe/common/t4_regs.h:#define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT) dev/cxgbe/common/t4_regs.h:#define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY) dev/cxgbe/common/t4_regs.h:#define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY) dev/cxgbe/common/t4_regs.h:#define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD) dev/cxgbe/common/t4_regs.h:#define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD) dev/cxgbe/common/t4_regs.h:#define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH) dev/cxgbe/common/t4_regs.h:#define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH) dev/cxgbe/common/t4_regs.h:#define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM) dev/cxgbe/common/t4_regs.h:#define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM) dev/cxgbe/common/t4_regs.h:#define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT) dev/cxgbe/common/t4_regs.h:#define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT) dev/cxgbe/common/t4_regs.h:#define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC) dev/cxgbe/common/t4_regs.h:#define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC) dev/cxgbe/common/t4_regs.h:#define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT) dev/cxgbe/common/t4_regs.h:#define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT) dev/cxgbe/common/t4_regs.h:#define V_GENTIMERACT(x) ((x) << S_GENTIMERACT) dev/cxgbe/common/t4_regs.h:#define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT) dev/cxgbe/common/t4_regs.h:#define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG) dev/cxgbe/common/t4_regs.h:#define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG) dev/cxgbe/common/t4_regs.h:#define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK) dev/cxgbe/common/t4_regs.h:#define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK) dev/cxgbe/common/t4_regs.h:#define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL) dev/cxgbe/common/t4_regs.h:#define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL) dev/cxgbe/common/t4_regs.h:#define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX) dev/cxgbe/common/t4_regs.h:#define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX) dev/cxgbe/common/t4_regs.h:#define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR) dev/cxgbe/common/t4_regs.h:#define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR) dev/cxgbe/common/t4_regs.h:#define V_TSCHNLRTSEL(x) ((x) << S_TSCHNLRTSEL) dev/cxgbe/common/t4_regs.h:#define G_TSCHNLRTSEL(x) (((x) >> S_TSCHNLRTSEL) & M_TSCHNLRTSEL) dev/cxgbe/common/t4_regs.h:#define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT) dev/cxgbe/common/t4_regs.h:#define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT) dev/cxgbe/common/t4_regs.h:#define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL) dev/cxgbe/common/t4_regs.h:#define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL) dev/cxgbe/common/t4_regs.h:#define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX) dev/cxgbe/common/t4_regs.h:#define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX) dev/cxgbe/common/t4_regs.h:#define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR) dev/cxgbe/common/t4_regs.h:#define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR) dev/cxgbe/common/t4_regs.h:#define V_TSCCLRTSEL(x) ((x) << S_TSCCLRTSEL) dev/cxgbe/common/t4_regs.h:#define G_TSCCLRTSEL(x) (((x) >> S_TSCCLRTSEL) & M_TSCCLRTSEL) dev/cxgbe/common/t4_regs.h:#define V_TSCCLWRR(x) ((x) << S_TSCCLWRR) dev/cxgbe/common/t4_regs.h:#define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR) dev/cxgbe/common/t4_regs.h:#define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT) dev/cxgbe/common/t4_regs.h:#define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT) dev/cxgbe/common/t4_regs.h:#define V_PAUSEVECSEL(x) ((x) << S_PAUSEVECSEL) dev/cxgbe/common/t4_regs.h:#define G_PAUSEVECSEL(x) (((x) >> S_PAUSEVECSEL) & M_PAUSEVECSEL) dev/cxgbe/common/t4_regs.h:#define V_MPSPAUSEMASK(x) ((x) << S_MPSPAUSEMASK) dev/cxgbe/common/t4_regs.h:#define G_MPSPAUSEMASK(x) (((x) >> S_MPSPAUSEMASK) & M_MPSPAUSEMASK) dev/cxgbe/common/t4_regs.h:#define V_SLOW_TIMEOUT(x) ((x) << S_SLOW_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define G_SLOW_TIMEOUT(x) (((x) >> S_SLOW_TIMEOUT) & M_SLOW_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT) dev/cxgbe/common/t4_regs.h:#define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL) dev/cxgbe/common/t4_regs.h:#define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL) dev/cxgbe/common/t4_regs.h:#define V_PORT_MAP(x) ((x) << S_PORT_MAP) dev/cxgbe/common/t4_regs.h:#define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL) dev/cxgbe/common/t4_regs.h:#define V_AN_ENA(x) ((x) << S_AN_ENA) dev/cxgbe/common/t4_regs.h:#define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA) dev/cxgbe/common/t4_regs.h:#define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA) dev/cxgbe/common/t4_regs.h:#define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA) dev/cxgbe/common/t4_regs.h:#define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA) dev/cxgbe/common/t4_regs.h:#define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA) dev/cxgbe/common/t4_regs.h:#define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL) dev/cxgbe/common/t4_regs.h:#define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL) dev/cxgbe/common/t4_regs.h:#define V_REF_CLK_SEL(x) ((x) << S_REF_CLK_SEL) dev/cxgbe/common/t4_regs.h:#define G_REF_CLK_SEL(x) (((x) >> S_REF_CLK_SEL) & M_REF_CLK_SEL) dev/cxgbe/common/t4_regs.h:#define V_MAC_FPGA_PTP_PORT(x) ((x) << S_MAC_FPGA_PTP_PORT) dev/cxgbe/common/t4_regs.h:#define G_MAC_FPGA_PTP_PORT(x) (((x) >> S_MAC_FPGA_PTP_PORT) & M_MAC_FPGA_PTP_PORT) dev/cxgbe/common/t4_regs.h:#define V_AEC_SYS_LANE_SELECT_O(x) ((x) << S_AEC_SYS_LANE_SELECT_O) dev/cxgbe/common/t4_regs.h:#define G_AEC_SYS_LANE_SELECT_O(x) (((x) >> S_AEC_SYS_LANE_SELECT_O) & M_AEC_SYS_LANE_SELECT_O) dev/cxgbe/common/t4_regs.h:#define V_AEC_RX_LANE_ID_O(x) ((x) << S_AEC_RX_LANE_ID_O) dev/cxgbe/common/t4_regs.h:#define G_AEC_RX_LANE_ID_O(x) (((x) >> S_AEC_RX_LANE_ID_O) & M_AEC_RX_LANE_ID_O) dev/cxgbe/common/t4_regs.h:#define V_CTL_FSM_CUR_STATE(x) ((x) << S_CTL_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define G_CTL_FSM_CUR_STATE(x) (((x) >> S_CTL_FSM_CUR_STATE) & M_CTL_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define V_CIN_FSM_CUR_STATE(x) ((x) << S_CIN_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define G_CIN_FSM_CUR_STATE(x) (((x) >> S_CIN_FSM_CUR_STATE) & M_CIN_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define V_CRI_FSM_CUR_STATE(x) ((x) << S_CRI_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define G_CRI_FSM_CUR_STATE(x) (((x) >> S_CRI_FSM_CUR_STATE) & M_CRI_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define V_LCK_FSM_CUR_STATE(x) ((x) << S_LCK_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define G_LCK_FSM_CUR_STATE(x) (((x) >> S_LCK_FSM_CUR_STATE) & M_LCK_FSM_CUR_STATE) dev/cxgbe/common/t4_regs.h:#define V_FPGA_LOCK(x) ((x) << S_FPGA_LOCK) dev/cxgbe/common/t4_regs.h:#define G_FPGA_LOCK(x) (((x) >> S_FPGA_LOCK) & M_FPGA_LOCK) dev/cxgbe/common/t4_regs.h:#define V_AN_SELECT(x) ((x) << S_AN_SELECT) dev/cxgbe/common/t4_regs.h:#define G_AN_SELECT(x) (((x) >> S_AN_SELECT) & M_AN_SELECT) dev/cxgbe/common/t4_regs.h:#define V_SGMII_SG_SPEED(x) ((x) << S_SGMII_SG_SPEED) dev/cxgbe/common/t4_regs.h:#define G_SGMII_SG_SPEED(x) (((x) >> S_SGMII_SG_SPEED) & M_SGMII_SG_SPEED) dev/cxgbe/common/t4_regs.h:#define V_BLK_STB_VAL(x) ((x) << S_BLK_STB_VAL) dev/cxgbe/common/t4_regs.h:#define G_BLK_STB_VAL(x) (((x) >> S_BLK_STB_VAL) & M_BLK_STB_VAL) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_SEL(x) ((x) << S_DEBUG_SEL) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_SEL(x) (((x) >> S_DEBUG_SEL) & M_DEBUG_SEL) dev/cxgbe/common/t4_regs.h:#define V_SGMII_LOOP(x) ((x) << S_SGMII_LOOP) dev/cxgbe/common/t4_regs.h:#define G_SGMII_LOOP(x) (((x) >> S_SGMII_LOOP) & M_SGMII_LOOP) dev/cxgbe/common/t4_regs.h:#define V_SGMII_TX_LANE_CKMULT(x) ((x) << S_SGMII_TX_LANE_CKMULT) dev/cxgbe/common/t4_regs.h:#define G_SGMII_TX_LANE_CKMULT(x) (((x) >> S_SGMII_TX_LANE_CKMULT) & M_SGMII_TX_LANE_CKMULT) dev/cxgbe/common/t4_regs.h:#define V_SGMII_TX_LANE_THRESH(x) ((x) << S_SGMII_TX_LANE_THRESH) dev/cxgbe/common/t4_regs.h:#define G_SGMII_TX_LANE_THRESH(x) (((x) >> S_SGMII_TX_LANE_THRESH) & M_SGMII_TX_LANE_THRESH) dev/cxgbe/common/t4_regs.h:#define V_MEMSEL_PERR(x) ((x) << S_MEMSEL_PERR) dev/cxgbe/common/t4_regs.h:#define G_MEMSEL_PERR(x) (((x) >> S_MEMSEL_PERR) & M_MEMSEL_PERR) dev/cxgbe/common/t4_regs.h:#define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL) dev/cxgbe/common/t4_regs.h:#define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN) dev/cxgbe/common/t4_regs.h:#define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN) dev/cxgbe/common/t4_regs.h:#define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP) dev/cxgbe/common/t4_regs.h:#define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP) dev/cxgbe/common/t4_regs.h:#define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB) dev/cxgbe/common/t4_regs.h:#define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB) dev/cxgbe/common/t4_regs.h:#define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA) dev/cxgbe/common/t4_regs.h:#define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA) dev/cxgbe/common/t4_regs.h:#define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB) dev/cxgbe/common/t4_regs.h:#define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB) dev/cxgbe/common/t4_regs.h:#define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA) dev/cxgbe/common/t4_regs.h:#define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA) dev/cxgbe/common/t4_regs.h:#define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA) dev/cxgbe/common/t4_regs.h:#define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA) dev/cxgbe/common/t4_regs.h:#define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB) dev/cxgbe/common/t4_regs.h:#define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB) dev/cxgbe/common/t4_regs.h:#define V_HSSREFDIVA(x) ((x) << S_HSSREFDIVA) dev/cxgbe/common/t4_regs.h:#define G_HSSREFDIVA(x) (((x) >> S_HSSREFDIVA) & M_HSSREFDIVA) dev/cxgbe/common/t4_regs.h:#define V_HSSREFDIVB(x) ((x) << S_HSSREFDIVB) dev/cxgbe/common/t4_regs.h:#define G_HSSREFDIVB(x) (((x) >> S_HSSREFDIVB) & M_HSSREFDIVB) dev/cxgbe/common/t4_regs.h:#define V_TOV(x) ((x) << S_TOV) dev/cxgbe/common/t4_regs.h:#define G_TOV(x) (((x) >> S_TOV) & M_TOV) dev/cxgbe/common/t4_regs.h:#define V_TSU(x) ((x) << S_TSU) dev/cxgbe/common/t4_regs.h:#define G_TSU(x) (((x) >> S_TSU) & M_TSU) dev/cxgbe/common/t4_regs.h:#define V_IPW(x) ((x) << S_IPW) dev/cxgbe/common/t4_regs.h:#define G_IPW(x) (((x) >> S_IPW) & M_IPW) dev/cxgbe/common/t4_regs.h:#define V_RUNT(x) ((x) << S_RUNT) dev/cxgbe/common/t4_regs.h:#define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT) dev/cxgbe/common/t4_regs.h:#define V_TS_ID(x) ((x) << S_TS_ID) dev/cxgbe/common/t4_regs.h:#define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID) dev/cxgbe/common/t4_regs.h:#define V_EEE_CTRL(x) ((x) << S_EEE_CTRL) dev/cxgbe/common/t4_regs.h:#define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL) dev/cxgbe/common/t4_regs.h:#define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER) dev/cxgbe/common/t4_regs.h:#define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER) dev/cxgbe/common/t4_regs.h:#define V_HSS_TIMER(x) ((x) << S_HSS_TIMER) dev/cxgbe/common/t4_regs.h:#define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER) dev/cxgbe/common/t4_regs.h:#define V_WAKE_CNT(x) ((x) << S_WAKE_CNT) dev/cxgbe/common/t4_regs.h:#define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT) dev/cxgbe/common/t4_regs.h:#define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_Y_TICK(x) ((x) << S_Y_TICK) dev/cxgbe/common/t4_regs.h:#define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK) dev/cxgbe/common/t4_regs.h:#define V_X_TICK(x) ((x) << S_X_TICK) dev/cxgbe/common/t4_regs.h:#define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK) dev/cxgbe/common/t4_regs.h:#define V_CUSTREV(x) ((x) << S_CUSTREV) dev/cxgbe/common/t4_regs.h:#define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV) dev/cxgbe/common/t4_regs.h:#define V_VER(x) ((x) << S_VER) dev/cxgbe/common/t4_regs.h:#define G_VER(x) (((x) >> S_VER) & M_VER) dev/cxgbe/common/t4_regs.h:#define V_MTIP_REV(x) ((x) << S_MTIP_REV) dev/cxgbe/common/t4_regs.h:#define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV) dev/cxgbe/common/t4_regs.h:#define V_MACADDRHI(x) ((x) << S_MACADDRHI) dev/cxgbe/common/t4_regs.h:#define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI) dev/cxgbe/common/t4_regs.h:#define V_LEN(x) ((x) << S_LEN) dev/cxgbe/common/t4_regs.h:#define G_LEN(x) (((x) >> S_LEN) & M_LEN) dev/cxgbe/common/t4_regs.h:#define V_AVAIL(x) ((x) << S_AVAIL) dev/cxgbe/common/t4_regs.h:#define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL) dev/cxgbe/common/t4_regs.h:#define V_EMPTY(x) ((x) << S_EMPTY) dev/cxgbe/common/t4_regs.h:#define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY) dev/cxgbe/common/t4_regs.h:#define V_ALMSTFULL(x) ((x) << S_ALMSTFULL) dev/cxgbe/common/t4_regs.h:#define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL) dev/cxgbe/common/t4_regs.h:#define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY) dev/cxgbe/common/t4_regs.h:#define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY) dev/cxgbe/common/t4_regs.h:#define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR) dev/cxgbe/common/t4_regs.h:#define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR) dev/cxgbe/common/t4_regs.h:#define V_IPG(x) ((x) << S_IPG) dev/cxgbe/common/t4_regs.h:#define G_IPG(x) (((x) >> S_IPG) & M_IPG) dev/cxgbe/common/t4_regs.h:#define V_MACCRDRST(x) ((x) << S_MACCRDRST) dev/cxgbe/common/t4_regs.h:#define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST) dev/cxgbe/common/t4_regs.h:#define V_INITCREDIT(x) ((x) << S_INITCREDIT) dev/cxgbe/common/t4_regs.h:#define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT) dev/cxgbe/common/t4_regs.h:#define V_STATUS(x) ((x) << S_STATUS) dev/cxgbe/common/t4_regs.h:#define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS) dev/cxgbe/common/t4_regs.h:#define V_CUSPEED(x) ((x) << S_CUSPEED) dev/cxgbe/common/t4_regs.h:#define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED) dev/cxgbe/common/t4_regs.h:#define V_SET_LEN(x) ((x) << S_SET_LEN) dev/cxgbe/common/t4_regs.h:#define G_SET_LEN(x) (((x) >> S_SET_LEN) & M_SET_LEN) dev/cxgbe/common/t4_regs.h:#define V_FRM_LEN_SET(x) ((x) << S_FRM_LEN_SET) dev/cxgbe/common/t4_regs.h:#define G_FRM_LEN_SET(x) (((x) >> S_FRM_LEN_SET) & M_FRM_LEN_SET) dev/cxgbe/common/t4_regs.h:#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL) dev/cxgbe/common/t4_regs.h:#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL) dev/cxgbe/common/t4_regs.h:#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY) dev/cxgbe/common/t4_regs.h:#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY) dev/cxgbe/common/t4_regs.h:#define V_CLK_DIVISOR(x) ((x) << S_CLK_DIVISOR) dev/cxgbe/common/t4_regs.h:#define G_CLK_DIVISOR(x) (((x) >> S_CLK_DIVISOR) & M_CLK_DIVISOR) dev/cxgbe/common/t4_regs.h:#define V_HOLD_TIME_SETTING(x) ((x) << S_HOLD_TIME_SETTING) dev/cxgbe/common/t4_regs.h:#define G_HOLD_TIME_SETTING(x) (((x) >> S_HOLD_TIME_SETTING) & M_HOLD_TIME_SETTING) dev/cxgbe/common/t4_regs.h:#define V_PORT_PHY_ADDR(x) ((x) << S_PORT_PHY_ADDR) dev/cxgbe/common/t4_regs.h:#define G_PORT_PHY_ADDR(x) (((x) >> S_PORT_PHY_ADDR) & M_PORT_PHY_ADDR) dev/cxgbe/common/t4_regs.h:#define V_DEVICE_REG_ADDR(x) ((x) << S_DEVICE_REG_ADDR) dev/cxgbe/common/t4_regs.h:#define G_DEVICE_REG_ADDR(x) (((x) >> S_DEVICE_REG_ADDR) & M_DEVICE_REG_ADDR) dev/cxgbe/common/t4_regs.h:#define V_MDIO_DATA(x) ((x) << S_MDIO_DATA) dev/cxgbe/common/t4_regs.h:#define G_MDIO_DATA(x) (((x) >> S_MDIO_DATA) & M_MDIO_DATA) dev/cxgbe/common/t4_regs.h:#define V_COUNT_LO(x) ((x) << S_COUNT_LO) dev/cxgbe/common/t4_regs.h:#define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO) dev/cxgbe/common/t4_regs.h:#define V_COUNT_HI(x) ((x) << S_COUNT_HI) dev/cxgbe/common/t4_regs.h:#define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI) dev/cxgbe/common/t4_regs.h:#define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED) dev/cxgbe/common/t4_regs.h:#define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED) dev/cxgbe/common/t4_regs.h:#define V_STATUS_BIT(x) ((x) << S_STATUS_BIT) dev/cxgbe/common/t4_regs.h:#define G_STATUS_BIT(x) (((x) >> S_STATUS_BIT) & M_STATUS_BIT) dev/cxgbe/common/t4_regs.h:#define V_IF_MODE(x) ((x) << S_IF_MODE) dev/cxgbe/common/t4_regs.h:#define G_IF_MODE(x) (((x) >> S_IF_MODE) & M_IF_MODE) dev/cxgbe/common/t4_regs.h:#define V_IF_STATUS_MODE(x) ((x) << S_IF_STATUS_MODE) dev/cxgbe/common/t4_regs.h:#define G_IF_STATUS_MODE(x) (((x) >> S_IF_STATUS_MODE) & M_IF_STATUS_MODE) dev/cxgbe/common/t4_regs.h:#define V_ACTIVE(x) ((x) << S_ACTIVE) dev/cxgbe/common/t4_regs.h:#define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE) dev/cxgbe/common/t4_regs.h:#define V_MODE_CTL(x) ((x) << S_MODE_CTL) dev/cxgbe/common/t4_regs.h:#define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL) dev/cxgbe/common/t4_regs.h:#define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL) dev/cxgbe/common/t4_regs.h:#define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL) dev/cxgbe/common/t4_regs.h:#define V_NP_TX(x) ((x) << S_NP_TX) dev/cxgbe/common/t4_regs.h:#define G_NP_TX(x) (((x) >> S_NP_TX) & M_NP_TX) dev/cxgbe/common/t4_regs.h:#define V_COL_CNT(x) ((x) << S_COL_CNT) dev/cxgbe/common/t4_regs.h:#define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT) dev/cxgbe/common/t4_regs.h:#define V_LP_NP_RX(x) ((x) << S_LP_NP_RX) dev/cxgbe/common/t4_regs.h:#define G_LP_NP_RX(x) (((x) >> S_LP_NP_RX) & M_LP_NP_RX) dev/cxgbe/common/t4_regs.h:#define V_EXTENDED_STATUS(x) ((x) << S_EXTENDED_STATUS) dev/cxgbe/common/t4_regs.h:#define G_EXTENDED_STATUS(x) (((x) >> S_EXTENDED_STATUS) & M_EXTENDED_STATUS) dev/cxgbe/common/t4_regs.h:#define V_SCRATCH(x) ((x) << S_SCRATCH) dev/cxgbe/common/t4_regs.h:#define G_SCRATCH(x) (((x) >> S_SCRATCH) & M_SCRATCH) dev/cxgbe/common/t4_regs.h:#define V_SGMII_VER(x) ((x) << S_SGMII_VER) dev/cxgbe/common/t4_regs.h:#define G_SGMII_VER(x) (((x) >> S_SGMII_VER) & M_SGMII_VER) dev/cxgbe/common/t4_regs.h:#define V_SGMII_REV(x) ((x) << S_SGMII_REV) dev/cxgbe/common/t4_regs.h:#define G_SGMII_REV(x) (((x) >> S_SGMII_REV) & M_SGMII_REV) dev/cxgbe/common/t4_regs.h:#define V_LINK_TIMER_LO(x) ((x) << S_LINK_TIMER_LO) dev/cxgbe/common/t4_regs.h:#define G_LINK_TIMER_LO(x) (((x) >> S_LINK_TIMER_LO) & M_LINK_TIMER_LO) dev/cxgbe/common/t4_regs.h:#define V_LINK_TIMER_HI(x) ((x) << S_LINK_TIMER_HI) dev/cxgbe/common/t4_regs.h:#define G_LINK_TIMER_HI(x) (((x) >> S_LINK_TIMER_HI) & M_LINK_TIMER_HI) dev/cxgbe/common/t4_regs.h:#define V_PCS_TYPE_SELECTION(x) ((x) << S_PCS_TYPE_SELECTION) dev/cxgbe/common/t4_regs.h:#define G_PCS_TYPE_SELECTION(x) (((x) >> S_PCS_TYPE_SELECTION) & M_PCS_TYPE_SELECTION) dev/cxgbe/common/t4_regs.h:#define V_DEVICE_PRESENT(x) ((x) << S_DEVICE_PRESENT) dev/cxgbe/common/t4_regs.h:#define G_DEVICE_PRESENT(x) (((x) >> S_DEVICE_PRESENT) & M_DEVICE_PRESENT) dev/cxgbe/common/t4_regs.h:#define V_PCS_PACKAGE_IDENTIFIER_LO(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_LO) dev/cxgbe/common/t4_regs.h:#define G_PCS_PACKAGE_IDENTIFIER_LO(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_LO) & M_PCS_PACKAGE_IDENTIFIER_LO) dev/cxgbe/common/t4_regs.h:#define V_PCS_PACKAGE_IDENTIFIER_HI(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_HI) dev/cxgbe/common/t4_regs.h:#define G_PCS_PACKAGE_IDENTIFIER_HI(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_HI) & M_PCS_PACKAGE_IDENTIFIER_HI) dev/cxgbe/common/t4_regs.h:#define V_BERBER_COUNTER(x) ((x) << S_BERBER_COUNTER) dev/cxgbe/common/t4_regs.h:#define G_BERBER_COUNTER(x) (((x) >> S_BERBER_COUNTER) & M_BERBER_COUNTER) dev/cxgbe/common/t4_regs.h:#define V_TEST_PATTERN_ERR_CNTR(x) ((x) << S_TEST_PATTERN_ERR_CNTR) dev/cxgbe/common/t4_regs.h:#define G_TEST_PATTERN_ERR_CNTR(x) (((x) >> S_TEST_PATTERN_ERR_CNTR) & M_TEST_PATTERN_ERR_CNTR) dev/cxgbe/common/t4_regs.h:#define V_PCS_TYPE_SEL(x) ((x) << S_PCS_TYPE_SEL) dev/cxgbe/common/t4_regs.h:#define G_PCS_TYPE_SEL(x) (((x) >> S_PCS_TYPE_SEL) & M_PCS_TYPE_SEL) dev/cxgbe/common/t4_regs.h:#define V_BER_CNT(x) ((x) << S_BER_CNT) dev/cxgbe/common/t4_regs.h:#define G_BER_CNT(x) (((x) >> S_BER_CNT) & M_BER_CNT) dev/cxgbe/common/t4_regs.h:#define V_ERR_BL_CNT(x) ((x) << S_ERR_BL_CNT) dev/cxgbe/common/t4_regs.h:#define G_ERR_BL_CNT(x) (((x) >> S_ERR_BL_CNT) & M_ERR_BL_CNT) dev/cxgbe/common/t4_regs.h:#define V_TP_ERR_CNTR(x) ((x) << S_TP_ERR_CNTR) dev/cxgbe/common/t4_regs.h:#define G_TP_ERR_CNTR(x) (((x) >> S_TP_ERR_CNTR) & M_TP_ERR_CNTR) dev/cxgbe/common/t4_regs.h:#define V_BER_HI_ORDER_CNT(x) ((x) << S_BER_HI_ORDER_CNT) dev/cxgbe/common/t4_regs.h:#define G_BER_HI_ORDER_CNT(x) (((x) >> S_BER_HI_ORDER_CNT) & M_BER_HI_ORDER_CNT) dev/cxgbe/common/t4_regs.h:#define V_ERR_BLK_CNTR(x) ((x) << S_ERR_BLK_CNTR) dev/cxgbe/common/t4_regs.h:#define G_ERR_BLK_CNTR(x) (((x) >> S_ERR_BLK_CNTR) & M_ERR_BLK_CNTR) dev/cxgbe/common/t4_regs.h:#define V_CLK_DIV(x) ((x) << S_CLK_DIV) dev/cxgbe/common/t4_regs.h:#define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV) dev/cxgbe/common/t4_regs.h:#define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME) dev/cxgbe/common/t4_regs.h:#define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME) dev/cxgbe/common/t4_regs.h:#define V_PORT_ADDR(x) ((x) << S_PORT_ADDR) dev/cxgbe/common/t4_regs.h:#define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR) dev/cxgbe/common/t4_regs.h:#define V_DEV_ADDR(x) ((x) << S_DEV_ADDR) dev/cxgbe/common/t4_regs.h:#define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR) dev/cxgbe/common/t4_regs.h:#define V_DATA_WORD(x) ((x) << S_DATA_WORD) dev/cxgbe/common/t4_regs.h:#define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD) dev/cxgbe/common/t4_regs.h:#define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR) dev/cxgbe/common/t4_regs.h:#define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR) dev/cxgbe/common/t4_regs.h:#define V_VLANTAG(x) ((x) << S_VLANTAG) dev/cxgbe/common/t4_regs.h:#define G_VLANTAG(x) (((x) >> S_VLANTAG) & CXGBE_M_VLANTAG) dev/cxgbe/common/t4_regs.h:#define V_BER_COUNTER(x) ((x) << S_BER_COUNTER) dev/cxgbe/common/t4_regs.h:#define G_BER_COUNTER(x) (((x) >> S_BER_COUNTER) & M_BER_COUNTER) dev/cxgbe/common/t4_regs.h:#define V_ERRORED_BLOCKS_CNTR(x) ((x) << S_ERRORED_BLOCKS_CNTR) dev/cxgbe/common/t4_regs.h:#define G_ERRORED_BLOCKS_CNTR(x) (((x) >> S_ERRORED_BLOCKS_CNTR) & M_ERRORED_BLOCKS_CNTR) dev/cxgbe/common/t4_regs.h:#define V_BASE_R_TEST_ERR_CNT(x) ((x) << S_BASE_R_TEST_ERR_CNT) dev/cxgbe/common/t4_regs.h:#define G_BASE_R_TEST_ERR_CNT(x) (((x) >> S_BASE_R_TEST_ERR_CNT) & M_BASE_R_TEST_ERR_CNT) dev/cxgbe/common/t4_regs.h:#define V_BER_HIGH_ORDER_CNT(x) ((x) << S_BER_HIGH_ORDER_CNT) dev/cxgbe/common/t4_regs.h:#define G_BER_HIGH_ORDER_CNT(x) (((x) >> S_BER_HIGH_ORDER_CNT) & M_BER_HIGH_ORDER_CNT) dev/cxgbe/common/t4_regs.h:#define V_ERR_BLKS_CNTR(x) ((x) << S_ERR_BLKS_CNTR) dev/cxgbe/common/t4_regs.h:#define G_ERR_BLKS_CNTR(x) (((x) >> S_ERR_BLKS_CNTR) & M_ERR_BLKS_CNTR) dev/cxgbe/common/t4_regs.h:#define V_PCS_SPEED(x) ((x) << S_PCS_SPEED) dev/cxgbe/common/t4_regs.h:#define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED) dev/cxgbe/common/t4_regs.h:#define V_PCSTYPE(x) ((x) << S_PCSTYPE) dev/cxgbe/common/t4_regs.h:#define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE) dev/cxgbe/common/t4_regs.h:#define V_RESEREVED(x) ((x) << S_RESEREVED) dev/cxgbe/common/t4_regs.h:#define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED) dev/cxgbe/common/t4_regs.h:#define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT) dev/cxgbe/common/t4_regs.h:#define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT) dev/cxgbe/common/t4_regs.h:#define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT) dev/cxgbe/common/t4_regs.h:#define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT) dev/cxgbe/common/t4_regs.h:#define V_SEEDA(x) ((x) << S_SEEDA) dev/cxgbe/common/t4_regs.h:#define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA) dev/cxgbe/common/t4_regs.h:#define V_SEEDB(x) ((x) << S_SEEDB) dev/cxgbe/common/t4_regs.h:#define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB) dev/cxgbe/common/t4_regs.h:#define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT) dev/cxgbe/common/t4_regs.h:#define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT) dev/cxgbe/common/t4_regs.h:#define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI) dev/cxgbe/common/t4_regs.h:#define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI) dev/cxgbe/common/t4_regs.h:#define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI) dev/cxgbe/common/t4_regs.h:#define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI) dev/cxgbe/common/t4_regs.h:#define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT) dev/cxgbe/common/t4_regs.h:#define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT) dev/cxgbe/common/t4_regs.h:#define V_MAP(x) ((x) << S_MAP) dev/cxgbe/common/t4_regs.h:#define G_MAP(x) (((x) >> S_MAP) & M_MAP) dev/cxgbe/common/t4_regs.h:#define V_CORE_REVISION(x) ((x) << S_CORE_REVISION) dev/cxgbe/common/t4_regs.h:#define G_CORE_REVISION(x) (((x) >> S_CORE_REVISION) & M_CORE_REVISION) dev/cxgbe/common/t4_regs.h:#define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY) dev/cxgbe/common/t4_regs.h:#define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY) dev/cxgbe/common/t4_regs.h:#define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE) dev/cxgbe/common/t4_regs.h:#define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE) dev/cxgbe/common/t4_regs.h:#define V_SELECTOR(x) ((x) << S_SELECTOR) dev/cxgbe/common/t4_regs.h:#define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR) dev/cxgbe/common/t4_regs.h:#define V_RS_RS_FEC_CCW_LO(x) ((x) << S_RS_RS_FEC_CCW_LO) dev/cxgbe/common/t4_regs.h:#define G_RS_RS_FEC_CCW_LO(x) (((x) >> S_RS_RS_FEC_CCW_LO) & M_RS_RS_FEC_CCW_LO) dev/cxgbe/common/t4_regs.h:#define V_TX_NONCE(x) ((x) << S_TX_NONCE) dev/cxgbe/common/t4_regs.h:#define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE) dev/cxgbe/common/t4_regs.h:#define V_RS_RS_FEC_CCW_HI(x) ((x) << S_RS_RS_FEC_CCW_HI) dev/cxgbe/common/t4_regs.h:#define G_RS_RS_FEC_CCW_HI(x) (((x) >> S_RS_RS_FEC_CCW_HI) & M_RS_RS_FEC_CCW_HI) dev/cxgbe/common/t4_regs.h:#define V_RS_RS_FEC_NCCW_LO(x) ((x) << S_RS_RS_FEC_NCCW_LO) dev/cxgbe/common/t4_regs.h:#define G_RS_RS_FEC_NCCW_LO(x) (((x) >> S_RS_RS_FEC_NCCW_LO) & M_RS_RS_FEC_NCCW_LO) dev/cxgbe/common/t4_regs.h:#define V_RS_RS_FEC_NCCW_HI(x) ((x) << S_RS_RS_FEC_NCCW_HI) dev/cxgbe/common/t4_regs.h:#define G_RS_RS_FEC_NCCW_HI(x) (((x) >> S_RS_RS_FEC_NCCW_HI) & M_RS_RS_FEC_NCCW_HI) dev/cxgbe/common/t4_regs.h:#define V_PMA_MAPPING(x) ((x) << S_PMA_MAPPING) dev/cxgbe/common/t4_regs.h:#define G_PMA_MAPPING(x) (((x) >> S_PMA_MAPPING) & M_PMA_MAPPING) dev/cxgbe/common/t4_regs.h:#define V_MS_COUNT(x) ((x) << S_MS_COUNT) dev/cxgbe/common/t4_regs.h:#define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT) dev/cxgbe/common/t4_regs.h:#define V_MU(x) ((x) << S_MU) dev/cxgbe/common/t4_regs.h:#define G_MU(x) (((x) >> S_MU) & M_MU) dev/cxgbe/common/t4_regs.h:#define V_UNFORMATED(x) ((x) << S_UNFORMATED) dev/cxgbe/common/t4_regs.h:#define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED) dev/cxgbe/common/t4_regs.h:#define V_DESKEW_EMPTY(x) ((x) << S_DESKEW_EMPTY) dev/cxgbe/common/t4_regs.h:#define G_DESKEW_EMPTY(x) (((x) >> S_DESKEW_EMPTY) & M_DESKEW_EMPTY) dev/cxgbe/common/t4_regs.h:#define V_AMPS_LOCK(x) ((x) << S_AMPS_LOCK) dev/cxgbe/common/t4_regs.h:#define G_AMPS_LOCK(x) (((x) >> S_AMPS_LOCK) & M_AMPS_LOCK) dev/cxgbe/common/t4_regs.h:#define V_RS_FEC_VENDOR_REVISION(x) ((x) << S_RS_FEC_VENDOR_REVISION) dev/cxgbe/common/t4_regs.h:#define G_RS_FEC_VENDOR_REVISION(x) (((x) >> S_RS_FEC_VENDOR_REVISION) & M_RS_FEC_VENDOR_REVISION) dev/cxgbe/common/t4_regs.h:#define V_RS_FEC_VENDOR_TX_TEST_KEY(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_KEY) dev/cxgbe/common/t4_regs.h:#define G_RS_FEC_VENDOR_TX_TEST_KEY(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_KEY) & M_RS_FEC_VENDOR_TX_TEST_KEY) dev/cxgbe/common/t4_regs.h:#define V_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_SYMBOLS) dev/cxgbe/common/t4_regs.h:#define G_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_SYMBOLS) & M_RS_FEC_VENDOR_TX_TEST_SYMBOLS) dev/cxgbe/common/t4_regs.h:#define V_RS_FEC_VENDOR_TX_TEST_PATTERN(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_PATTERN) dev/cxgbe/common/t4_regs.h:#define G_RS_FEC_VENDOR_TX_TEST_PATTERN(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_PATTERN) & M_RS_FEC_VENDOR_TX_TEST_PATTERN) dev/cxgbe/common/t4_regs.h:#define V_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_TRIGGER) dev/cxgbe/common/t4_regs.h:#define G_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_TRIGGER) & M_RS_FEC_VENDOR_TX_TEST_TRIGGER) dev/cxgbe/common/t4_regs.h:#define V_SET_WAIT_TIMER(x) ((x) << S_SET_WAIT_TIMER) dev/cxgbe/common/t4_regs.h:#define G_SET_WAIT_TIMER(x) (((x) >> S_SET_WAIT_TIMER) & M_SET_WAIT_TIMER) dev/cxgbe/common/t4_regs.h:#define V_INIT_METH(x) ((x) << S_INIT_METH) dev/cxgbe/common/t4_regs.h:#define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH) dev/cxgbe/common/t4_regs.h:#define V_CE_DECS(x) ((x) << S_CE_DECS) dev/cxgbe/common/t4_regs.h:#define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS) dev/cxgbe/common/t4_regs.h:#define V_INIT_CNT(x) ((x) << S_INIT_CNT) dev/cxgbe/common/t4_regs.h:#define G_INIT_CNT(x) (((x) >> S_INIT_CNT) & M_INIT_CNT) dev/cxgbe/common/t4_regs.h:#define V_GAIN_TH(x) ((x) << S_GAIN_TH) dev/cxgbe/common/t4_regs.h:#define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH) dev/cxgbe/common/t4_regs.h:#define V_AMIN_TH(x) ((x) << S_AMIN_TH) dev/cxgbe/common/t4_regs.h:#define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH) dev/cxgbe/common/t4_regs.h:#define V_DPC_METH(x) ((x) << S_DPC_METH) dev/cxgbe/common/t4_regs.h:#define G_DPC_METH(x) (((x) >> S_DPC_METH) & M_DPC_METH) dev/cxgbe/common/t4_regs.h:#define V_ACC_LIM(x) ((x) << S_ACC_LIM) dev/cxgbe/common/t4_regs.h:#define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM) dev/cxgbe/common/t4_regs.h:#define V_CNV_LIM(x) ((x) << S_CNV_LIM) dev/cxgbe/common/t4_regs.h:#define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM) dev/cxgbe/common/t4_regs.h:#define V_TOG_LIM(x) ((x) << S_TOG_LIM) dev/cxgbe/common/t4_regs.h:#define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM) dev/cxgbe/common/t4_regs.h:#define V_AET_STAT(x) ((x) << S_AET_STAT) dev/cxgbe/common/t4_regs.h:#define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT) dev/cxgbe/common/t4_regs.h:#define V_NEU_STATE(x) ((x) << S_NEU_STATE) dev/cxgbe/common/t4_regs.h:#define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE) dev/cxgbe/common/t4_regs.h:#define V_CTRL_STATE(x) ((x) << S_CTRL_STATE) dev/cxgbe/common/t4_regs.h:#define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE) dev/cxgbe/common/t4_regs.h:#define V_CTRL_STAT(x) ((x) << S_CTRL_STAT) dev/cxgbe/common/t4_regs.h:#define G_CTRL_STAT(x) (((x) >> S_CTRL_STAT) & M_CTRL_STAT) dev/cxgbe/common/t4_regs.h:#define V_FRAME_LOCK_CNT(x) ((x) << S_FRAME_LOCK_CNT) dev/cxgbe/common/t4_regs.h:#define G_FRAME_LOCK_CNT(x) (((x) >> S_FRAME_LOCK_CNT) & M_FRAME_LOCK_CNT) dev/cxgbe/common/t4_regs.h:#define V_DPC_TIME_LIM(x) ((x) << S_DPC_TIME_LIM) dev/cxgbe/common/t4_regs.h:#define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM) dev/cxgbe/common/t4_regs.h:#define V_SPSEL(x) ((x) << S_SPSEL) dev/cxgbe/common/t4_regs.h:#define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL) dev/cxgbe/common/t4_regs.h:#define V_RPOS(x) ((x) << S_RPOS) dev/cxgbe/common/t4_regs.h:#define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS) dev/cxgbe/common/t4_regs.h:#define V_CALSSTN(x) ((x) << S_CALSSTN) dev/cxgbe/common/t4_regs.h:#define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN) dev/cxgbe/common/t4_regs.h:#define V_CALSSTP(x) ((x) << S_CALSSTP) dev/cxgbe/common/t4_regs.h:#define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP) dev/cxgbe/common/t4_regs.h:#define V_DRTOL(x) ((x) << S_DRTOL) dev/cxgbe/common/t4_regs.h:#define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL) dev/cxgbe/common/t4_regs.h:#define V_NXTPOL(x) ((x) << S_NXTPOL) dev/cxgbe/common/t4_regs.h:#define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL) dev/cxgbe/common/t4_regs.h:#define V_SASCMD(x) ((x) << S_SASCMD) dev/cxgbe/common/t4_regs.h:#define G_SASCMD(x) (((x) >> S_SASCMD) & M_SASCMD) dev/cxgbe/common/t4_regs.h:#define V_ATUNEN(x) ((x) << S_ATUNEN) dev/cxgbe/common/t4_regs.h:#define G_ATUNEN(x) (((x) >> S_ATUNEN) & M_ATUNEN) dev/cxgbe/common/t4_regs.h:#define V_ATUNEP(x) ((x) << S_ATUNEP) dev/cxgbe/common/t4_regs.h:#define G_ATUNEP(x) (((x) >> S_ATUNEP) & M_ATUNEP) dev/cxgbe/common/t4_regs.h:#define V_MAINSC(x) ((x) << S_MAINSC) dev/cxgbe/common/t4_regs.h:#define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC) dev/cxgbe/common/t4_regs.h:#define V_POSTSC(x) ((x) << S_POSTSC) dev/cxgbe/common/t4_regs.h:#define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC) dev/cxgbe/common/t4_regs.h:#define V_PRESC(x) ((x) << S_PRESC) dev/cxgbe/common/t4_regs.h:#define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC) dev/cxgbe/common/t4_regs.h:#define V_ATSIGN(x) ((x) << S_ATSIGN) dev/cxgbe/common/t4_regs.h:#define G_ATSIGN(x) (((x) >> S_ATSIGN) & M_ATSIGN) dev/cxgbe/common/t4_regs.h:#define V_DCCOFFSET(x) ((x) << S_DCCOFFSET) dev/cxgbe/common/t4_regs.h:#define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET) dev/cxgbe/common/t4_regs.h:#define V_DCCSTEP(x) ((x) << S_DCCSTEP) dev/cxgbe/common/t4_regs.h:#define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP) dev/cxgbe/common/t4_regs.h:#define V_DCCASTEP(x) ((x) << S_DCCASTEP) dev/cxgbe/common/t4_regs.h:#define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP) dev/cxgbe/common/t4_regs.h:#define V_DCCSIGN(x) ((x) << S_DCCSIGN) dev/cxgbe/common/t4_regs.h:#define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN) dev/cxgbe/common/t4_regs.h:#define V_DCCAMP(x) ((x) << S_DCCAMP) dev/cxgbe/common/t4_regs.h:#define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP) dev/cxgbe/common/t4_regs.h:#define V_DCCASIGN(x) ((x) << S_DCCASIGN) dev/cxgbe/common/t4_regs.h:#define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN) dev/cxgbe/common/t4_regs.h:#define V_DCCAAMP(x) ((x) << S_DCCAAMP) dev/cxgbe/common/t4_regs.h:#define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP) dev/cxgbe/common/t4_regs.h:#define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL) dev/cxgbe/common/t4_regs.h:#define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL) dev/cxgbe/common/t4_regs.h:#define V_LPITERM(x) ((x) << S_LPITERM) dev/cxgbe/common/t4_regs.h:#define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM) dev/cxgbe/common/t4_regs.h:#define V_LPIPRCD(x) ((x) << S_LPIPRCD) dev/cxgbe/common/t4_regs.h:#define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD) dev/cxgbe/common/t4_regs.h:#define V_TX_LINKA_DCCSTEP_CTL(x) ((x) << S_TX_LINKA_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define G_TX_LINKA_DCCSTEP_CTL(x) (((x) >> S_TX_LINKA_DCCSTEP_CTL) & M_TX_LINKA_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define V_OSIGN(x) ((x) << S_OSIGN) dev/cxgbe/common/t4_regs.h:#define G_OSIGN(x) (((x) >> S_OSIGN) & M_OSIGN) dev/cxgbe/common/t4_regs.h:#define V_TUNEBIT(x) ((x) << S_TUNEBIT) dev/cxgbe/common/t4_regs.h:#define G_TUNEBIT(x) (((x) >> S_TUNEBIT) & M_TUNEBIT) dev/cxgbe/common/t4_regs.h:#define V_DATAPOS(x) ((x) << S_DATAPOS) dev/cxgbe/common/t4_regs.h:#define G_DATAPOS(x) (((x) >> S_DATAPOS) & M_DATAPOS) dev/cxgbe/common/t4_regs.h:#define V_SEGSEL(x) ((x) << S_SEGSEL) dev/cxgbe/common/t4_regs.h:#define G_SEGSEL(x) (((x) >> S_SEGSEL) & M_SEGSEL) dev/cxgbe/common/t4_regs.h:#define V_TAPSEL(x) ((x) << S_TAPSEL) dev/cxgbe/common/t4_regs.h:#define G_TAPSEL(x) (((x) >> S_TAPSEL) & M_TAPSEL) dev/cxgbe/common/t4_regs.h:#define V_SDOVRD(x) ((x) << S_SDOVRD) dev/cxgbe/common/t4_regs.h:#define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD) dev/cxgbe/common/t4_regs.h:#define V_SLEWCODE(x) ((x) << S_SLEWCODE) dev/cxgbe/common/t4_regs.h:#define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE) dev/cxgbe/common/t4_regs.h:#define V_WCNT(x) ((x) << S_WCNT) dev/cxgbe/common/t4_regs.h:#define G_WCNT(x) (((x) >> S_WCNT) & M_WCNT) dev/cxgbe/common/t4_regs.h:#define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL) dev/cxgbe/common/t4_regs.h:#define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL) dev/cxgbe/common/t4_regs.h:#define V_JTAGAMPL(x) ((x) << S_JTAGAMPL) dev/cxgbe/common/t4_regs.h:#define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL) dev/cxgbe/common/t4_regs.h:#define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define G_TX_LINKB_DCCSTEP_CTL(x) (((x) >> S_TX_LINKB_DCCSTEP_CTL) & M_TX_LINKB_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define V_PATSEL(x) ((x) << S_PATSEL) dev/cxgbe/common/t4_regs.h:#define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL) dev/cxgbe/common/t4_regs.h:#define V_PPOL(x) ((x) << S_PPOL) dev/cxgbe/common/t4_regs.h:#define G_PPOL(x) (((x) >> S_PPOL) & M_PPOL) dev/cxgbe/common/t4_regs.h:#define V_PCLKSEL(x) ((x) << S_PCLKSEL) dev/cxgbe/common/t4_regs.h:#define G_PCLKSEL(x) (((x) >> S_PCLKSEL) & M_PCLKSEL) dev/cxgbe/common/t4_regs.h:#define V_ROTA(x) ((x) << S_ROTA) dev/cxgbe/common/t4_regs.h:#define G_ROTA(x) (((x) >> S_ROTA) & M_ROTA) dev/cxgbe/common/t4_regs.h:#define V_ROTD(x) ((x) << S_ROTD) dev/cxgbe/common/t4_regs.h:#define G_ROTD(x) (((x) >> S_ROTD) & M_ROTD) dev/cxgbe/common/t4_regs.h:#define V_FREQFW(x) ((x) << S_FREQFW) dev/cxgbe/common/t4_regs.h:#define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW) dev/cxgbe/common/t4_regs.h:#define V_ROTE(x) ((x) << S_ROTE) dev/cxgbe/common/t4_regs.h:#define G_ROTE(x) (((x) >> S_ROTE) & M_ROTE) dev/cxgbe/common/t4_regs.h:#define V_RAOFFF(x) ((x) << S_RAOFFF) dev/cxgbe/common/t4_regs.h:#define G_RAOFFF(x) (((x) >> S_RAOFFF) & M_RAOFFF) dev/cxgbe/common/t4_regs.h:#define V_RAOFF(x) ((x) << S_RAOFF) dev/cxgbe/common/t4_regs.h:#define G_RAOFF(x) (((x) >> S_RAOFF) & M_RAOFF) dev/cxgbe/common/t4_regs.h:#define V_RBOOFF(x) ((x) << S_RBOOFF) dev/cxgbe/common/t4_regs.h:#define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF) dev/cxgbe/common/t4_regs.h:#define V_RBEOFF(x) ((x) << S_RBEOFF) dev/cxgbe/common/t4_regs.h:#define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF) dev/cxgbe/common/t4_regs.h:#define V_RASEL(x) ((x) << S_RASEL) dev/cxgbe/common/t4_regs.h:#define G_RASEL(x) (((x) >> S_RASEL) & M_RASEL) dev/cxgbe/common/t4_regs.h:#define V_WGAIN(x) ((x) << S_WGAIN) dev/cxgbe/common/t4_regs.h:#define G_WGAIN(x) (((x) >> S_WGAIN) & M_WGAIN) dev/cxgbe/common/t4_regs.h:#define V_IQSEP(x) ((x) << S_IQSEP) dev/cxgbe/common/t4_regs.h:#define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP) dev/cxgbe/common/t4_regs.h:#define V_DUTYQ(x) ((x) << S_DUTYQ) dev/cxgbe/common/t4_regs.h:#define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ) dev/cxgbe/common/t4_regs.h:#define V_DUTYI(x) ((x) << S_DUTYI) dev/cxgbe/common/t4_regs.h:#define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI) dev/cxgbe/common/t4_regs.h:#define V_PMCFG(x) ((x) << S_PMCFG) dev/cxgbe/common/t4_regs.h:#define G_PMCFG(x) (((x) >> S_PMCFG) & M_PMCFG) dev/cxgbe/common/t4_regs.h:#define V_PMOFFTIME(x) ((x) << S_PMOFFTIME) dev/cxgbe/common/t4_regs.h:#define G_PMOFFTIME(x) (((x) >> S_PMOFFTIME) & M_PMOFFTIME) dev/cxgbe/common/t4_regs.h:#define V_SERVREF(x) ((x) << S_SERVREF) dev/cxgbe/common/t4_regs.h:#define G_SERVREF(x) (((x) >> S_SERVREF) & M_SERVREF) dev/cxgbe/common/t4_regs.h:#define V_IQAMP(x) ((x) << S_IQAMP) dev/cxgbe/common/t4_regs.h:#define G_IQAMP(x) (((x) >> S_IQAMP) & M_IQAMP) dev/cxgbe/common/t4_regs.h:#define V_DTHR(x) ((x) << S_DTHR) dev/cxgbe/common/t4_regs.h:#define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR) dev/cxgbe/common/t4_regs.h:#define V_SNUL(x) ((x) << S_SNUL) dev/cxgbe/common/t4_regs.h:#define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL) dev/cxgbe/common/t4_regs.h:#define V_DASEL(x) ((x) << S_DASEL) dev/cxgbe/common/t4_regs.h:#define G_DASEL(x) (((x) >> S_DASEL) & M_DASEL) dev/cxgbe/common/t4_regs.h:#define V_ACCPLGAIN(x) ((x) << S_ACCPLGAIN) dev/cxgbe/common/t4_regs.h:#define G_ACCPLGAIN(x) (((x) >> S_ACCPLGAIN) & M_ACCPLGAIN) dev/cxgbe/common/t4_regs.h:#define V_ACCPLREF(x) ((x) << S_ACCPLREF) dev/cxgbe/common/t4_regs.h:#define G_ACCPLREF(x) (((x) >> S_ACCPLREF) & M_ACCPLREF) dev/cxgbe/common/t4_regs.h:#define V_ACCPLSTEP(x) ((x) << S_ACCPLSTEP) dev/cxgbe/common/t4_regs.h:#define G_ACCPLSTEP(x) (((x) >> S_ACCPLSTEP) & M_ACCPLSTEP) dev/cxgbe/common/t4_regs.h:#define V_ACCPLASTEP(x) ((x) << S_ACCPLASTEP) dev/cxgbe/common/t4_regs.h:#define G_ACCPLASTEP(x) (((x) >> S_ACCPLASTEP) & M_ACCPLASTEP) dev/cxgbe/common/t4_regs.h:#define V_ACCPLBIAS(x) ((x) << S_ACCPLBIAS) dev/cxgbe/common/t4_regs.h:#define G_ACCPLBIAS(x) (((x) >> S_ACCPLBIAS) & M_ACCPLBIAS) dev/cxgbe/common/t4_regs.h:#define V_UNPKPKA(x) ((x) << S_UNPKPKA) dev/cxgbe/common/t4_regs.h:#define G_UNPKPKA(x) (((x) >> S_UNPKPKA) & M_UNPKPKA) dev/cxgbe/common/t4_regs.h:#define V_UNPKVGA(x) ((x) << S_UNPKVGA) dev/cxgbe/common/t4_regs.h:#define G_UNPKVGA(x) (((x) >> S_UNPKVGA) & M_UNPKVGA) dev/cxgbe/common/t4_regs.h:#define V_OVRTAILS(x) ((x) << S_OVRTAILS) dev/cxgbe/common/t4_regs.h:#define G_OVRTAILS(x) (((x) >> S_OVRTAILS) & M_OVRTAILS) dev/cxgbe/common/t4_regs.h:#define V_OVRTAILV(x) ((x) << S_OVRTAILV) dev/cxgbe/common/t4_regs.h:#define G_OVRTAILV(x) (((x) >> S_OVRTAILV) & M_OVRTAILV) dev/cxgbe/common/t4_regs.h:#define V_CDRANLGSW(x) ((x) << S_CDRANLGSW) dev/cxgbe/common/t4_regs.h:#define G_CDRANLGSW(x) (((x) >> S_CDRANLGSW) & M_CDRANLGSW) dev/cxgbe/common/t4_regs.h:#define V_PFLAG(x) ((x) << S_PFLAG) dev/cxgbe/common/t4_regs.h:#define G_PFLAG(x) (((x) >> S_PFLAG) & M_PFLAG) dev/cxgbe/common/t4_regs.h:#define V_DCDIND(x) ((x) << S_DCDIND) dev/cxgbe/common/t4_regs.h:#define G_DCDIND(x) (((x) >> S_DCDIND) & M_DCDIND) dev/cxgbe/common/t4_regs.h:#define V_DCCIND(x) ((x) << S_DCCIND) dev/cxgbe/common/t4_regs.h:#define G_DCCIND(x) (((x) >> S_DCCIND) & M_DCCIND) dev/cxgbe/common/t4_regs.h:#define V_LOFCH(x) ((x) << S_LOFCH) dev/cxgbe/common/t4_regs.h:#define G_LOFCH(x) (((x) >> S_LOFCH) & M_LOFCH) dev/cxgbe/common/t4_regs.h:#define V_LOFU(x) ((x) << S_LOFU) dev/cxgbe/common/t4_regs.h:#define G_LOFU(x) (((x) >> S_LOFU) & M_LOFU) dev/cxgbe/common/t4_regs.h:#define V_LOFL(x) ((x) << S_LOFL) dev/cxgbe/common/t4_regs.h:#define G_LOFL(x) (((x) >> S_LOFL) & M_LOFL) dev/cxgbe/common/t4_regs.h:#define V_LOFE(x) ((x) << S_LOFE) dev/cxgbe/common/t4_regs.h:#define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE) dev/cxgbe/common/t4_regs.h:#define V_HBISTSP(x) ((x) << S_HBISTSP) dev/cxgbe/common/t4_regs.h:#define G_HBISTSP(x) (((x) >> S_HBISTSP) & M_HBISTSP) dev/cxgbe/common/t4_regs.h:#define V_HSEL(x) ((x) << S_HSEL) dev/cxgbe/common/t4_regs.h:#define G_HSEL(x) (((x) >> S_HSEL) & M_HSEL) dev/cxgbe/common/t4_regs.h:#define V_ACCIND(x) ((x) << S_ACCIND) dev/cxgbe/common/t4_regs.h:#define G_ACCIND(x) (((x) >> S_ACCIND) & M_ACCIND) dev/cxgbe/common/t4_regs.h:#define V_ACCRD(x) ((x) << S_ACCRD) dev/cxgbe/common/t4_regs.h:#define G_ACCRD(x) (((x) >> S_ACCRD) & M_ACCRD) dev/cxgbe/common/t4_regs.h:#define V_LFTGT(x) ((x) << S_LFTGT) dev/cxgbe/common/t4_regs.h:#define G_LFTGT(x) (((x) >> S_LFTGT) & M_LFTGT) dev/cxgbe/common/t4_regs.h:#define V_LCURR(x) ((x) << S_LCURR) dev/cxgbe/common/t4_regs.h:#define G_LCURR(x) (((x) >> S_LCURR) & M_LCURR) dev/cxgbe/common/t4_regs.h:#define V_OFFAMP(x) ((x) << S_OFFAMP) dev/cxgbe/common/t4_regs.h:#define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP) dev/cxgbe/common/t4_regs.h:#define V_OFFSN(x) ((x) << S_OFFSN) dev/cxgbe/common/t4_regs.h:#define G_OFFSN(x) (((x) >> S_OFFSN) & M_OFFSN) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKANLGSW(x) ((x) << S_RX_LINKANLGSW) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKANLGSW(x) (((x) >> S_RX_LINKANLGSW) & M_RX_LINKANLGSW) dev/cxgbe/common/t4_regs.h:#define V_ISTRIMS(x) ((x) << S_ISTRIMS) dev/cxgbe/common/t4_regs.h:#define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS) dev/cxgbe/common/t4_regs.h:#define V_ISTRIM(x) ((x) << S_ISTRIM) dev/cxgbe/common/t4_regs.h:#define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM) dev/cxgbe/common/t4_regs.h:#define V_INTDAC(x) ((x) << S_INTDAC) dev/cxgbe/common/t4_regs.h:#define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC) dev/cxgbe/common/t4_regs.h:#define V_INTDACEGS(x) ((x) << S_INTDACEGS) dev/cxgbe/common/t4_regs.h:#define G_INTDACEGS(x) (((x) >> S_INTDACEGS) & M_INTDACEGS) dev/cxgbe/common/t4_regs.h:#define V_INTDACE(x) ((x) << S_INTDACE) dev/cxgbe/common/t4_regs.h:#define G_INTDACE(x) (((x) >> S_INTDACE) & M_INTDACE) dev/cxgbe/common/t4_regs.h:#define V_INTDACGS(x) ((x) << S_INTDACGS) dev/cxgbe/common/t4_regs.h:#define G_INTDACGS(x) (((x) >> S_INTDACGS) & M_INTDACGS) dev/cxgbe/common/t4_regs.h:#define V_MINWDTH(x) ((x) << S_MINWDTH) dev/cxgbe/common/t4_regs.h:#define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH) dev/cxgbe/common/t4_regs.h:#define V_SMQM(x) ((x) << S_SMQM) dev/cxgbe/common/t4_regs.h:#define G_SMQM(x) (((x) >> S_SMQM) & M_SMQM) dev/cxgbe/common/t4_regs.h:#define V_SMQ(x) ((x) << S_SMQ) dev/cxgbe/common/t4_regs.h:#define G_SMQ(x) (((x) >> S_SMQ) & M_SMQ) dev/cxgbe/common/t4_regs.h:#define V_EMCNT(x) ((x) << S_EMCNT) dev/cxgbe/common/t4_regs.h:#define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT) dev/cxgbe/common/t4_regs.h:#define V_APDF(x) ((x) << S_APDF) dev/cxgbe/common/t4_regs.h:#define G_APDF(x) (((x) >> S_APDF) & M_APDF) dev/cxgbe/common/t4_regs.h:#define V_H_EN(x) ((x) << S_H_EN) dev/cxgbe/common/t4_regs.h:#define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKA_INDEX_DFE_TC(x) ((x) << S_RX_LINKA_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKA_INDEX_DFE_TC(x) (((x) >> S_RX_LINKA_INDEX_DFE_TC) & M_RX_LINKA_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKA_INDEX_DFE_TAP(x) ((x) << S_RX_LINKA_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKA_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKA_INDEX_DFE_TAP) & M_RX_LINKA_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define V_CSIND(x) ((x) << S_CSIND) dev/cxgbe/common/t4_regs.h:#define G_CSIND(x) (((x) >> S_CSIND) & M_CSIND) dev/cxgbe/common/t4_regs.h:#define V_CSVAL(x) ((x) << S_CSVAL) dev/cxgbe/common/t4_regs.h:#define G_CSVAL(x) (((x) >> S_CSVAL) & M_CSVAL) dev/cxgbe/common/t4_regs.h:#define V_DCDSTEP(x) ((x) << S_DCDSTEP) dev/cxgbe/common/t4_regs.h:#define G_DCDSTEP(x) (((x) >> S_DCDSTEP) & M_DCDSTEP) dev/cxgbe/common/t4_regs.h:#define V_DCDSIGN(x) ((x) << S_DCDSIGN) dev/cxgbe/common/t4_regs.h:#define G_DCDSIGN(x) (((x) >> S_DCDSIGN) & M_DCDSIGN) dev/cxgbe/common/t4_regs.h:#define V_DCDAMP(x) ((x) << S_DCDAMP) dev/cxgbe/common/t4_regs.h:#define G_DCDAMP(x) (((x) >> S_DCDAMP) & M_DCDAMP) dev/cxgbe/common/t4_regs.h:#define V_PRBSMODE(x) ((x) << S_PRBSMODE) dev/cxgbe/common/t4_regs.h:#define G_PRBSMODE(x) (((x) >> S_PRBSMODE) & M_PRBSMODE) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKA_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKA_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKA_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKA_DCCSTEP_RXCTL) & M_RX_LINKA_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define V_QCCSTEP(x) ((x) << S_QCCSTEP) dev/cxgbe/common/t4_regs.h:#define G_QCCSTEP(x) (((x) >> S_QCCSTEP) & M_QCCSTEP) dev/cxgbe/common/t4_regs.h:#define V_QCCSIGN(x) ((x) << S_QCCSIGN) dev/cxgbe/common/t4_regs.h:#define G_QCCSIGN(x) (((x) >> S_QCCSIGN) & M_QCCSIGN) dev/cxgbe/common/t4_regs.h:#define V_QCDAMP(x) ((x) << S_QCDAMP) dev/cxgbe/common/t4_regs.h:#define G_QCDAMP(x) (((x) >> S_QCDAMP) & M_QCDAMP) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKB_INDEX_DFE_TC(x) ((x) << S_RX_LINKB_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKB_INDEX_DFE_TC(x) (((x) >> S_RX_LINKB_INDEX_DFE_TC) & M_RX_LINKB_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKB_INDEX_DFE_TAP(x) ((x) << S_RX_LINKB_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKB_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKB_INDEX_DFE_TAP) & M_RX_LINKB_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKB_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKB_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKB_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKB_DCCSTEP_RXCTL) & M_RX_LINKB_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define G_TX_LINKC_DCCSTEP_CTL(x) (((x) >> S_TX_LINKC_DCCSTEP_CTL) & M_TX_LINKC_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define G_TX_LINKD_DCCSTEP_CTL(x) (((x) >> S_TX_LINKD_DCCSTEP_CTL) & M_TX_LINKD_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKC_INDEX_DFE_TC(x) ((x) << S_RX_LINKC_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKC_INDEX_DFE_TC(x) (((x) >> S_RX_LINKC_INDEX_DFE_TC) & M_RX_LINKC_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKC_INDEX_DFE_TAP(x) ((x) << S_RX_LINKC_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKC_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKC_INDEX_DFE_TAP) & M_RX_LINKC_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKC_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKC_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKC_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKC_DCCSTEP_RXCTL) & M_RX_LINKC_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKD_INDEX_DFE_TC(x) ((x) << S_RX_LINKD_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKD_INDEX_DFE_TC(x) (((x) >> S_RX_LINKD_INDEX_DFE_TC) & M_RX_LINKD_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKD_INDEX_DFE_TAP(x) ((x) << S_RX_LINKD_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKD_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKD_INDEX_DFE_TAP) & M_RX_LINKD_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKD_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKD_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKD_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKD_DCCSTEP_RXCTL) & M_RX_LINKD_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define V_REFISINK(x) ((x) << S_REFISINK) dev/cxgbe/common/t4_regs.h:#define G_REFISINK(x) (((x) >> S_REFISINK) & M_REFISINK) dev/cxgbe/common/t4_regs.h:#define V_REFISRC(x) ((x) << S_REFISRC) dev/cxgbe/common/t4_regs.h:#define G_REFISRC(x) (((x) >> S_REFISRC) & M_REFISRC) dev/cxgbe/common/t4_regs.h:#define V_REFVREG(x) ((x) << S_REFVREG) dev/cxgbe/common/t4_regs.h:#define G_REFVREG(x) (((x) >> S_REFVREG) & M_REFVREG) dev/cxgbe/common/t4_regs.h:#define V_VBGENDOC(x) ((x) << S_VBGENDOC) dev/cxgbe/common/t4_regs.h:#define G_VBGENDOC(x) (((x) >> S_VBGENDOC) & M_VBGENDOC) dev/cxgbe/common/t4_regs.h:#define V_VREFTUNE(x) ((x) << S_VREFTUNE) dev/cxgbe/common/t4_regs.h:#define G_VREFTUNE(x) (((x) >> S_VREFTUNE) & M_VREFTUNE) dev/cxgbe/common/t4_regs.h:#define V_ISVAL(x) ((x) << S_ISVAL) dev/cxgbe/common/t4_regs.h:#define G_ISVAL(x) (((x) >> S_ISVAL) & M_ISVAL) dev/cxgbe/common/t4_regs.h:#define V_GTORLT(x) ((x) << S_GTORLT) dev/cxgbe/common/t4_regs.h:#define G_GTORLT(x) (((x) >> S_GTORLT) & M_GTORLT) dev/cxgbe/common/t4_regs.h:#define V_LLIM(x) ((x) << S_LLIM) dev/cxgbe/common/t4_regs.h:#define G_LLIM(x) (((x) >> S_LLIM) & M_LLIM) dev/cxgbe/common/t4_regs.h:#define V_LMSK(x) ((x) << S_LMSK) dev/cxgbe/common/t4_regs.h:#define G_LMSK(x) (((x) >> S_LMSK) & M_LMSK) dev/cxgbe/common/t4_regs.h:#define V_HLIM(x) ((x) << S_HLIM) dev/cxgbe/common/t4_regs.h:#define G_HLIM(x) (((x) >> S_HLIM) & M_HLIM) dev/cxgbe/common/t4_regs.h:#define V_HMSK(x) ((x) << S_HMSK) dev/cxgbe/common/t4_regs.h:#define G_HMSK(x) (((x) >> S_HMSK) & M_HMSK) dev/cxgbe/common/t4_regs.h:#define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define G_TX_LINK_BCST_DCCSTEP_CTL(x) (((x) >> S_TX_LINK_BCST_DCCSTEP_CTL) & M_TX_LINK_BCST_DCCSTEP_CTL) dev/cxgbe/common/t4_regs.h:#define V_RX_LINK_BCST_INDEX_DFE_TC(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define G_RX_LINK_BCST_INDEX_DFE_TC(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TC) & M_RX_LINK_BCST_INDEX_DFE_TC) dev/cxgbe/common/t4_regs.h:#define V_RX_LINK_BCST_INDEX_DFE_TAP(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define G_RX_LINK_BCST_INDEX_DFE_TAP(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TAP) & M_RX_LINK_BCST_INDEX_DFE_TAP) dev/cxgbe/common/t4_regs.h:#define V_RX_LINK_BCST_DCCSTEP_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define G_RX_LINK_BCST_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINK_BCST_DCCSTEP_RXCTL) & M_RX_LINK_BCST_DCCSTEP_RXCTL) dev/cxgbe/common/t4_regs.h:#define V_SPEDIV(x) ((x) << S_SPEDIV) dev/cxgbe/common/t4_regs.h:#define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV) dev/cxgbe/common/t4_regs.h:#define V_PCKSEL(x) ((x) << S_PCKSEL) dev/cxgbe/common/t4_regs.h:#define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL) dev/cxgbe/common/t4_regs.h:#define V_VBST(x) ((x) << S_VBST) dev/cxgbe/common/t4_regs.h:#define G_VBST(x) (((x) >> S_VBST) & M_VBST) dev/cxgbe/common/t4_regs.h:#define V_REFDIV(x) ((x) << S_REFDIV) dev/cxgbe/common/t4_regs.h:#define G_REFDIV(x) (((x) >> S_REFDIV) & M_REFDIV) dev/cxgbe/common/t4_regs.h:#define V_DIVSEL(x) ((x) << S_DIVSEL) dev/cxgbe/common/t4_regs.h:#define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL) dev/cxgbe/common/t4_regs.h:#define V_CONFIG(x) ((x) << S_CONFIG) dev/cxgbe/common/t4_regs.h:#define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG) dev/cxgbe/common/t4_regs.h:#define V_STEP(x) ((x) << S_STEP) dev/cxgbe/common/t4_regs.h:#define G_STEP(x) (((x) >> S_STEP) & M_STEP) dev/cxgbe/common/t4_regs.h:#define V_VMMAX(x) ((x) << S_VMMAX) dev/cxgbe/common/t4_regs.h:#define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKA_INDEX_DFE_EN(x) ((x) << S_RX_LINKA_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKA_INDEX_DFE_EN(x) (((x) >> S_RX_LINKA_INDEX_DFE_EN) & M_RX_LINKA_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKB_INDEX_DFE_EN(x) ((x) << S_RX_LINKB_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKC_INDEX_DFE_EN(x) ((x) << S_RX_LINKC_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define V_RX_LINKD_INDEX_DFE_EN(x) ((x) << S_RX_LINKD_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define V_RX_LINK_BCST_INDEX_DFE_EN(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN) dev/cxgbe/common/t4_regs.h:#define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING) dev/cxgbe/common/t4_regs.h:#define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING) dev/cxgbe/common/t4_regs.h:#define V_LP_TRIG(x) ((x) << S_LP_TRIG) dev/cxgbe/common/t4_regs.h:#define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG) dev/cxgbe/common/t4_regs.h:#define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL) dev/cxgbe/common/t4_regs.h:#define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL) dev/cxgbe/common/t4_regs.h:#define V_HW_IDLE(x) ((x) << S_HW_IDLE) dev/cxgbe/common/t4_regs.h:#define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE) dev/cxgbe/common/t4_regs.h:#define V_SR_IDLE(x) ((x) << S_SR_IDLE) dev/cxgbe/common/t4_regs.h:#define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE) dev/cxgbe/common/t4_regs.h:#define V_PMUM(x) ((x) << S_PMUM) dev/cxgbe/common/t4_regs.h:#define G_PMUM(x) (((x) >> S_PMUM) & M_PMUM) dev/cxgbe/common/t4_regs.h:#define V_QDEPTH(x) ((x) << S_QDEPTH) dev/cxgbe/common/t4_regs.h:#define G_QDEPTH(x) (((x) >> S_QDEPTH) & M_QDEPTH) dev/cxgbe/common/t4_regs.h:#define V_ECC_MUX(x) ((x) << S_ECC_MUX) dev/cxgbe/common/t4_regs.h:#define G_ECC_MUX(x) (((x) >> S_ECC_MUX) & M_ECC_MUX) dev/cxgbe/common/t4_regs.h:#define V_CE_THRESHOLD(x) ((x) << S_CE_THRESHOLD) dev/cxgbe/common/t4_regs.h:#define G_CE_THRESHOLD(x) (((x) >> S_CE_THRESHOLD) & M_CE_THRESHOLD) dev/cxgbe/common/t4_regs.h:#define V_CLK_DISABLE(x) ((x) << S_CLK_DISABLE) dev/cxgbe/common/t4_regs.h:#define G_CLK_DISABLE(x) (((x) >> S_CLK_DISABLE) & M_CLK_DISABLE) dev/cxgbe/common/t4_regs.h:#define V_RESET_RANK(x) ((x) << S_RESET_RANK) dev/cxgbe/common/t4_regs.h:#define G_RESET_RANK(x) (((x) >> S_RESET_RANK) & M_RESET_RANK) dev/cxgbe/common/t4_regs.h:#define V_PM_ENABLE(x) ((x) << S_PM_ENABLE) dev/cxgbe/common/t4_regs.h:#define G_PM_ENABLE(x) (((x) >> S_PM_ENABLE) & M_PM_ENABLE) dev/cxgbe/common/t4_regs.h:#define V_RD_DEFREF_CNT(x) ((x) << S_RD_DEFREF_CNT) dev/cxgbe/common/t4_regs.h:#define G_RD_DEFREF_CNT(x) (((x) >> S_RD_DEFREF_CNT) & M_RD_DEFREF_CNT) dev/cxgbe/common/t4_regs.h:#define V_ZQCL_OP(x) ((x) << S_ZQCL_OP) dev/cxgbe/common/t4_regs.h:#define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP) dev/cxgbe/common/t4_regs.h:#define V_ZQCL_MA(x) ((x) << S_ZQCL_MA) dev/cxgbe/common/t4_regs.h:#define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA) dev/cxgbe/common/t4_regs.h:#define V_ZQCS_OP(x) ((x) << S_ZQCS_OP) dev/cxgbe/common/t4_regs.h:#define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP) dev/cxgbe/common/t4_regs.h:#define V_ZQCS_MA(x) ((x) << S_ZQCS_MA) dev/cxgbe/common/t4_regs.h:#define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA) dev/cxgbe/common/t4_regs.h:#define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA) dev/cxgbe/common/t4_regs.h:#define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA) dev/cxgbe/common/t4_regs.h:#define V_ROW_WIDTH(x) ((x) << S_ROW_WIDTH) dev/cxgbe/common/t4_regs.h:#define G_ROW_WIDTH(x) (((x) >> S_ROW_WIDTH) & M_ROW_WIDTH) dev/cxgbe/common/t4_regs.h:#define V_ADDR_MODE(x) ((x) << S_ADDR_MODE) dev/cxgbe/common/t4_regs.h:#define G_ADDR_MODE(x) (((x) >> S_ADDR_MODE) & M_ADDR_MODE) dev/cxgbe/common/t4_regs.h:#define V_U_T_WR(x) ((x) << S_U_T_WR) dev/cxgbe/common/t4_regs.h:#define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR) dev/cxgbe/common/t4_regs.h:#define V_T_RSTL(x) ((x) << S_T_RSTL) dev/cxgbe/common/t4_regs.h:#define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL) dev/cxgbe/common/t4_regs.h:#define V_T_MRR(x) ((x) << S_T_MRR) dev/cxgbe/common/t4_regs.h:#define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR) dev/cxgbe/common/t4_regs.h:#define V_T_CKESR(x) ((x) << S_T_CKESR) dev/cxgbe/common/t4_regs.h:#define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR) dev/cxgbe/common/t4_regs.h:#define CXGBE_V_WAIT(x) ((x) << S_WAIT) dev/cxgbe/common/t4_regs.h:#define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT) dev/cxgbe/common/t4_regs.h:#define V_T_DPD(x) ((x) << S_T_DPD) dev/cxgbe/common/t4_regs.h:#define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD) dev/cxgbe/common/t4_regs.h:#define V_CMD(x) ((x) << S_CMD) dev/cxgbe/common/t4_regs.h:#define G_CMD(x) (((x) >> S_CMD) & M_CMD) dev/cxgbe/common/t4_regs.h:#define V_BANK(x) ((x) << S_BANK) dev/cxgbe/common/t4_regs.h:#define G_BANK(x) (((x) >> S_BANK) & M_BANK) dev/cxgbe/common/t4_regs.h:#define V_REFI(x) ((x) << S_REFI) dev/cxgbe/common/t4_regs.h:#define G_REFI(x) (((x) >> S_REFI) & M_REFI) dev/cxgbe/common/t4_regs.h:#define V_T_RFC_XPR(x) ((x) << S_T_RFC_XPR) dev/cxgbe/common/t4_regs.h:#define G_T_RFC_XPR(x) (((x) >> S_T_RFC_XPR) & M_T_RFC_XPR) dev/cxgbe/common/t4_regs.h:#define V_T_WTRO(x) ((x) << S_T_WTRO) dev/cxgbe/common/t4_regs.h:#define G_T_WTRO(x) (((x) >> S_T_WTRO) & M_T_WTRO) dev/cxgbe/common/t4_regs.h:#define V_T_RTWO(x) ((x) << S_T_RTWO) dev/cxgbe/common/t4_regs.h:#define G_T_RTWO(x) (((x) >> S_T_RTWO) & M_T_RTWO) dev/cxgbe/common/t4_regs.h:#define V_T_RTW_ADJ(x) ((x) << S_T_RTW_ADJ) dev/cxgbe/common/t4_regs.h:#define G_T_RTW_ADJ(x) (((x) >> S_T_RTW_ADJ) & M_T_RTW_ADJ) dev/cxgbe/common/t4_regs.h:#define V_T_WTWO(x) ((x) << S_T_WTWO) dev/cxgbe/common/t4_regs.h:#define G_T_WTWO(x) (((x) >> S_T_WTWO) & M_T_WTWO) dev/cxgbe/common/t4_regs.h:#define V_T_RTRO(x) ((x) << S_T_RTRO) dev/cxgbe/common/t4_regs.h:#define G_T_RTRO(x) (((x) >> S_T_RTRO) & M_T_RTRO) dev/cxgbe/common/t4_regs.h:#define V_T_PL(x) ((x) << S_T_PL) dev/cxgbe/common/t4_regs.h:#define G_T_PL(x) (((x) >> S_T_PL) & M_T_PL) dev/cxgbe/common/t4_regs.h:#define V_T_WTR_S(x) ((x) << S_T_WTR_S) dev/cxgbe/common/t4_regs.h:#define G_T_WTR_S(x) (((x) >> S_T_WTR_S) & M_T_WTR_S) dev/cxgbe/common/t4_regs.h:#define V_FAW_ADJ(x) ((x) << S_FAW_ADJ) dev/cxgbe/common/t4_regs.h:#define G_FAW_ADJ(x) (((x) >> S_FAW_ADJ) & M_FAW_ADJ) dev/cxgbe/common/t4_regs.h:#define V_T_RRD_L(x) ((x) << S_T_RRD_L) dev/cxgbe/common/t4_regs.h:#define G_T_RRD_L(x) (((x) >> S_T_RRD_L) & M_T_RRD_L) dev/cxgbe/common/t4_regs.h:#define V_T_XSDLL(x) ((x) << S_T_XSDLL) dev/cxgbe/common/t4_regs.h:#define G_T_XSDLL(x) (((x) >> S_T_XSDLL) & M_T_XSDLL) dev/cxgbe/common/t4_regs.h:#define V_T_RDDATA_EN(x) ((x) << S_T_RDDATA_EN) dev/cxgbe/common/t4_regs.h:#define G_T_RDDATA_EN(x) (((x) >> S_T_RDDATA_EN) & M_T_RDDATA_EN) dev/cxgbe/common/t4_regs.h:#define V_T_SYS_RDLAT(x) ((x) << S_T_SYS_RDLAT) dev/cxgbe/common/t4_regs.h:#define G_T_SYS_RDLAT(x) (((x) >> S_T_SYS_RDLAT) & M_T_SYS_RDLAT) dev/cxgbe/common/t4_regs.h:#define V_T_CCD_L(x) ((x) << S_T_CCD_L) dev/cxgbe/common/t4_regs.h:#define G_T_CCD_L(x) (((x) >> S_T_CCD_L) & M_T_CCD_L) dev/cxgbe/common/t4_regs.h:#define V_T_CCD(x) ((x) << S_T_CCD) dev/cxgbe/common/t4_regs.h:#define G_T_CCD(x) (((x) >> S_T_CCD) & M_T_CCD) dev/cxgbe/common/t4_regs.h:#define V_T_CPDED(x) ((x) << S_T_CPDED) dev/cxgbe/common/t4_regs.h:#define G_T_CPDED(x) (((x) >> S_T_CPDED) & M_T_CPDED) dev/cxgbe/common/t4_regs.h:#define V_T_PHY_WRDATA(x) ((x) << S_T_PHY_WRDATA) dev/cxgbe/common/t4_regs.h:#define G_T_PHY_WRDATA(x) (((x) >> S_T_PHY_WRDATA) & M_T_PHY_WRDATA) dev/cxgbe/common/t4_regs.h:#define V_T_PHY_WRLAT(x) ((x) << S_T_PHY_WRLAT) dev/cxgbe/common/t4_regs.h:#define G_T_PHY_WRLAT(x) (((x) >> S_T_PHY_WRLAT) & M_T_PHY_WRLAT) dev/cxgbe/common/t4_regs.h:#define V_T_SYS_RDLAT_DBG(x) ((x) << S_T_SYS_RDLAT_DBG) dev/cxgbe/common/t4_regs.h:#define G_T_SYS_RDLAT_DBG(x) (((x) >> S_T_SYS_RDLAT_DBG) & M_T_SYS_RDLAT_DBG) dev/cxgbe/common/t4_regs.h:#define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY) dev/cxgbe/common/t4_regs.h:#define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY) dev/cxgbe/common/t4_regs.h:#define V_WR_RTP(x) ((x) << S_WR_RTP) dev/cxgbe/common/t4_regs.h:#define G_WR_RTP(x) (((x) >> S_WR_RTP) & M_WR_RTP) dev/cxgbe/common/t4_regs.h:#define V_BL(x) ((x) << S_BL) dev/cxgbe/common/t4_regs.h:#define G_BL(x) (((x) >> S_BL) & M_BL) dev/cxgbe/common/t4_regs.h:#define V_AL(x) ((x) << S_AL) dev/cxgbe/common/t4_regs.h:#define G_AL(x) (((x) >> S_AL) & M_AL) dev/cxgbe/common/t4_regs.h:#define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R) dev/cxgbe/common/t4_regs.h:#define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R) dev/cxgbe/common/t4_regs.h:#define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W) dev/cxgbe/common/t4_regs.h:#define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W) dev/cxgbe/common/t4_regs.h:#define V_RTT_WR(x) ((x) << S_RTT_WR) dev/cxgbe/common/t4_regs.h:#define G_RTT_WR(x) (((x) >> S_RTT_WR) & M_RTT_WR) dev/cxgbe/common/t4_regs.h:#define V_CWL(x) ((x) << S_CWL) dev/cxgbe/common/t4_regs.h:#define G_CWL(x) (((x) >> S_CWL) & M_CWL) dev/cxgbe/common/t4_regs.h:#define V_PASR(x) ((x) << S_PASR) dev/cxgbe/common/t4_regs.h:#define G_PASR(x) (((x) >> S_PASR) & M_PASR) dev/cxgbe/common/t4_regs.h:#define V_MPR_RD_FMT(x) ((x) << S_MPR_RD_FMT) dev/cxgbe/common/t4_regs.h:#define G_MPR_RD_FMT(x) (((x) >> S_MPR_RD_FMT) & M_MPR_RD_FMT) dev/cxgbe/common/t4_regs.h:#define V_FGR_MODE(x) ((x) << S_FGR_MODE) dev/cxgbe/common/t4_regs.h:#define G_FGR_MODE(x) (((x) >> S_FGR_MODE) & M_FGR_MODE) dev/cxgbe/common/t4_regs.h:#define V_MPR_SEL(x) ((x) << S_MPR_SEL) dev/cxgbe/common/t4_regs.h:#define G_MPR_SEL(x) (((x) >> S_MPR_SEL) & M_MPR_SEL) dev/cxgbe/common/t4_regs.h:#define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA) dev/cxgbe/common/t4_regs.h:#define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA) dev/cxgbe/common/t4_regs.h:#define V_CS_LAT_MODE(x) ((x) << S_CS_LAT_MODE) dev/cxgbe/common/t4_regs.h:#define G_CS_LAT_MODE(x) (((x) >> S_CS_LAT_MODE) & M_CS_LAT_MODE) dev/cxgbe/common/t4_regs.h:#define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT) dev/cxgbe/common/t4_regs.h:#define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT) dev/cxgbe/common/t4_regs.h:#define V_RTT_PARK(x) ((x) << S_RTT_PARK) dev/cxgbe/common/t4_regs.h:#define G_RTT_PARK(x) (((x) >> S_RTT_PARK) & M_RTT_PARK) dev/cxgbe/common/t4_regs.h:#define V_PAR_LAT_MODE(x) ((x) << S_PAR_LAT_MODE) dev/cxgbe/common/t4_regs.h:#define G_PAR_LAT_MODE(x) (((x) >> S_PAR_LAT_MODE) & M_PAR_LAT_MODE) dev/cxgbe/common/t4_regs.h:#define V_TCCD_L(x) ((x) << S_TCCD_L) dev/cxgbe/common/t4_regs.h:#define G_TCCD_L(x) (((x) >> S_TCCD_L) & M_TCCD_L) dev/cxgbe/common/t4_regs.h:#define V_VREF_DQ_VALUE(x) ((x) << S_VREF_DQ_VALUE) dev/cxgbe/common/t4_regs.h:#define G_VREF_DQ_VALUE(x) (((x) >> S_VREF_DQ_VALUE) & M_VREF_DQ_VALUE) dev/cxgbe/common/t4_regs.h:#define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN) dev/cxgbe/common/t4_regs.h:#define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN) dev/cxgbe/common/t4_regs.h:#define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT) dev/cxgbe/common/t4_regs.h:#define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT) dev/cxgbe/common/t4_regs.h:#define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN) dev/cxgbe/common/t4_regs.h:#define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN) dev/cxgbe/common/t4_regs.h:#define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX) dev/cxgbe/common/t4_regs.h:#define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX) dev/cxgbe/common/t4_regs.h:#define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY) dev/cxgbe/common/t4_regs.h:#define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY) dev/cxgbe/common/t4_regs.h:#define V_TREFMSKI(x) ((x) << S_TREFMSKI) dev/cxgbe/common/t4_regs.h:#define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI) dev/cxgbe/common/t4_regs.h:#define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL) dev/cxgbe/common/t4_regs.h:#define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL) dev/cxgbe/common/t4_regs.h:#define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE) dev/cxgbe/common/t4_regs.h:#define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE) dev/cxgbe/common/t4_regs.h:#define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL) dev/cxgbe/common/t4_regs.h:#define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL) dev/cxgbe/common/t4_regs.h:#define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE) dev/cxgbe/common/t4_regs.h:#define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE) dev/cxgbe/common/t4_regs.h:#define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE) dev/cxgbe/common/t4_regs.h:#define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE) dev/cxgbe/common/t4_regs.h:#define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE) dev/cxgbe/common/t4_regs.h:#define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE) dev/cxgbe/common/t4_regs.h:#define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN) dev/cxgbe/common/t4_regs.h:#define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN) dev/cxgbe/common/t4_regs.h:#define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN) dev/cxgbe/common/t4_regs.h:#define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN) dev/cxgbe/common/t4_regs.h:#define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN) dev/cxgbe/common/t4_regs.h:#define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN) dev/cxgbe/common/t4_regs.h:#define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE) dev/cxgbe/common/t4_regs.h:#define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE) dev/cxgbe/common/t4_regs.h:#define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO) dev/cxgbe/common/t4_regs.h:#define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO) dev/cxgbe/common/t4_regs.h:#define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE) dev/cxgbe/common/t4_regs.h:#define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE) dev/cxgbe/common/t4_regs.h:#define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE) dev/cxgbe/common/t4_regs.h:#define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE) dev/cxgbe/common/t4_regs.h:#define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD) dev/cxgbe/common/t4_regs.h:#define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD) dev/cxgbe/common/t4_regs.h:#define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP) dev/cxgbe/common/t4_regs.h:#define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP) dev/cxgbe/common/t4_regs.h:#define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD) dev/cxgbe/common/t4_regs.h:#define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD) dev/cxgbe/common/t4_regs.h:#define V_PHYUPD_ERR(x) ((x) << S_PHYUPD_ERR) dev/cxgbe/common/t4_regs.h:#define G_PHYUPD_ERR(x) (((x) >> S_PHYUPD_ERR) & M_PHYUPD_ERR) dev/cxgbe/common/t4_regs.h:#define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN) dev/cxgbe/common/t4_regs.h:#define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN) dev/cxgbe/common/t4_regs.h:#define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE) dev/cxgbe/common/t4_regs.h:#define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE) dev/cxgbe/common/t4_regs.h:#define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL) dev/cxgbe/common/t4_regs.h:#define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL) dev/cxgbe/common/t4_regs.h:#define V_BUF_USE_TH(x) ((x) << S_BUF_USE_TH) dev/cxgbe/common/t4_regs.h:#define G_BUF_USE_TH(x) (((x) >> S_BUF_USE_TH) & M_BUF_USE_TH) dev/cxgbe/common/t4_regs.h:#define V_MC_IDLE_TH(x) ((x) << S_MC_IDLE_TH) dev/cxgbe/common/t4_regs.h:#define G_MC_IDLE_TH(x) (((x) >> S_MC_IDLE_TH) & M_MC_IDLE_TH) dev/cxgbe/common/t4_regs.h:#define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT) dev/cxgbe/common/t4_regs.h:#define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT) dev/cxgbe/common/t4_regs.h:#define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT) dev/cxgbe/common/t4_regs.h:#define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT) dev/cxgbe/common/t4_regs.h:#define V_WR_HI_TH(x) ((x) << S_WR_HI_TH) dev/cxgbe/common/t4_regs.h:#define G_WR_HI_TH(x) (((x) >> S_WR_HI_TH) & M_WR_HI_TH) dev/cxgbe/common/t4_regs.h:#define V_WR_MID_TH(x) ((x) << S_WR_MID_TH) dev/cxgbe/common/t4_regs.h:#define G_WR_MID_TH(x) (((x) >> S_WR_MID_TH) & M_WR_MID_TH) dev/cxgbe/common/t4_regs.h:#define V_RD_HI_TH(x) ((x) << S_RD_HI_TH) dev/cxgbe/common/t4_regs.h:#define G_RD_HI_TH(x) (((x) >> S_RD_HI_TH) & M_RD_HI_TH) dev/cxgbe/common/t4_regs.h:#define V_RD_MID_TH(x) ((x) << S_RD_MID_TH) dev/cxgbe/common/t4_regs.h:#define G_RD_MID_TH(x) (((x) >> S_RD_MID_TH) & M_RD_MID_TH) dev/cxgbe/common/t4_regs.h:#define V_BURST_LEN(x) ((x) << S_BURST_LEN) dev/cxgbe/common/t4_regs.h:#define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN) dev/cxgbe/common/t4_regs.h:#define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK) dev/cxgbe/common/t4_regs.h:#define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK) dev/cxgbe/common/t4_regs.h:#define V_USER_MASK_ECC(x) ((x) << S_USER_MASK_ECC) dev/cxgbe/common/t4_regs.h:#define G_USER_MASK_ECC(x) (((x) >> S_USER_MASK_ECC) & M_USER_MASK_ECC) dev/cxgbe/common/t4_regs.h:#define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE) dev/cxgbe/common/t4_regs.h:#define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE) dev/cxgbe/common/t4_regs.h:#define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE) dev/cxgbe/common/t4_regs.h:#define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE) dev/cxgbe/common/t4_regs.h:#define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE) dev/cxgbe/common/t4_regs.h:#define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE) dev/cxgbe/common/t4_regs.h:#define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT) dev/cxgbe/common/t4_regs.h:#define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT) dev/cxgbe/common/t4_regs.h:#define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL) dev/cxgbe/common/t4_regs.h:#define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL) dev/cxgbe/common/t4_regs.h:#define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL) dev/cxgbe/common/t4_regs.h:#define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL) dev/cxgbe/common/t4_regs.h:#define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL) dev/cxgbe/common/t4_regs.h:#define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL) dev/cxgbe/common/t4_regs.h:#define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL) dev/cxgbe/common/t4_regs.h:#define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL) dev/cxgbe/common/t4_regs.h:#define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND) dev/cxgbe/common/t4_regs.h:#define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND) dev/cxgbe/common/t4_regs.h:#define V_PRBS_WAIT(x) ((x) << S_PRBS_WAIT) dev/cxgbe/common/t4_regs.h:#define G_PRBS_WAIT(x) (((x) >> S_PRBS_WAIT) & M_PRBS_WAIT) dev/cxgbe/common/t4_regs.h:#define V_SS_QUAD(x) ((x) << S_SS_QUAD) dev/cxgbe/common/t4_regs.h:#define G_SS_QUAD(x) (((x) >> S_SS_QUAD) & M_SS_QUAD) dev/cxgbe/common/t4_regs.h:#define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL) dev/cxgbe/common/t4_regs.h:#define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL) dev/cxgbe/common/t4_regs.h:#define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED) dev/cxgbe/common/t4_regs.h:#define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED) dev/cxgbe/common/t4_regs.h:#define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE) dev/cxgbe/common/t4_regs.h:#define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE) dev/cxgbe/common/t4_regs.h:#define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE) dev/cxgbe/common/t4_regs.h:#define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE) dev/cxgbe/common/t4_regs.h:#define V_ERROR(x) ((x) << S_ERROR) dev/cxgbe/common/t4_regs.h:#define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR) dev/cxgbe/common/t4_regs.h:#define V_SYSCLK_RDCLK_OFFSET(x) ((x) << S_SYSCLK_RDCLK_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_SYSCLK_RDCLK_OFFSET) & M_SYSCLK_RDCLK_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_SYSCLK_DQSCLK_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_SYSCLK_DQSCLK_OFFSET) & M_SYSCLK_DQSCLK_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_DQS_ALIGN_SM(x) ((x) << S_DQS_ALIGN_SM) dev/cxgbe/common/t4_regs.h:#define G_DQS_ALIGN_SM(x) (((x) >> S_DQS_ALIGN_SM) & M_DQS_ALIGN_SM) dev/cxgbe/common/t4_regs.h:#define V_DQS_ALIGN_CNTR(x) ((x) << S_DQS_ALIGN_CNTR) dev/cxgbe/common/t4_regs.h:#define G_DQS_ALIGN_CNTR(x) (((x) >> S_DQS_ALIGN_CNTR) & M_DQS_ALIGN_CNTR) dev/cxgbe/common/t4_regs.h:#define V_DQS_ALIGN_ITER_CNTR(x) ((x) << S_DQS_ALIGN_ITER_CNTR) dev/cxgbe/common/t4_regs.h:#define G_DQS_ALIGN_ITER_CNTR(x) (((x) >> S_DQS_ALIGN_ITER_CNTR) & M_DQS_ALIGN_ITER_CNTR) dev/cxgbe/common/t4_regs.h:#define V_CALIBRATE_BIT(x) ((x) << S_CALIBRATE_BIT) dev/cxgbe/common/t4_regs.h:#define G_CALIBRATE_BIT(x) (((x) >> S_CALIBRATE_BIT) & M_CALIBRATE_BIT) dev/cxgbe/common/t4_regs.h:#define V_DQS_ALIGN_QUAD(x) ((x) << S_DQS_ALIGN_QUAD) dev/cxgbe/common/t4_regs.h:#define G_DQS_ALIGN_QUAD(x) (((x) >> S_DQS_ALIGN_QUAD) & M_DQS_ALIGN_QUAD) dev/cxgbe/common/t4_regs.h:#define V_DQS_QUAD_CONFIG(x) ((x) << S_DQS_QUAD_CONFIG) dev/cxgbe/common/t4_regs.h:#define G_DQS_QUAD_CONFIG(x) (((x) >> S_DQS_QUAD_CONFIG) & M_DQS_QUAD_CONFIG) dev/cxgbe/common/t4_regs.h:#define V_OPERATE_MODE(x) ((x) << S_OPERATE_MODE) dev/cxgbe/common/t4_regs.h:#define G_OPERATE_MODE(x) (((x) >> S_OPERATE_MODE) & M_OPERATE_MODE) dev/cxgbe/common/t4_regs.h:#define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_WR_DELAY(x) ((x) << S_WR_DELAY) dev/cxgbe/common/t4_regs.h:#define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY) dev/cxgbe/common/t4_regs.h:#define V_FAIL_PASS_VALUE(x) ((x) << S_FAIL_PASS_VALUE) dev/cxgbe/common/t4_regs.h:#define G_FAIL_PASS_VALUE(x) (((x) >> S_FAIL_PASS_VALUE) & M_FAIL_PASS_VALUE) dev/cxgbe/common/t4_regs.h:#define V_PASS_FAIL_VALUE(x) ((x) << S_PASS_FAIL_VALUE) dev/cxgbe/common/t4_regs.h:#define G_PASS_FAIL_VALUE(x) (((x) >> S_PASS_FAIL_VALUE) & M_PASS_FAIL_VALUE) dev/cxgbe/common/t4_regs.h:#define V_DESIRED_EDGE_CNTR_TARGET_HIGH(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_HIGH) dev/cxgbe/common/t4_regs.h:#define G_DESIRED_EDGE_CNTR_TARGET_HIGH(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_HIGH) & M_DESIRED_EDGE_CNTR_TARGET_HIGH) dev/cxgbe/common/t4_regs.h:#define V_DESIRED_EDGE_CNTR_TARGET_LOW(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_LOW) dev/cxgbe/common/t4_regs.h:#define G_DESIRED_EDGE_CNTR_TARGET_LOW(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_LOW) & M_DESIRED_EDGE_CNTR_TARGET_LOW) dev/cxgbe/common/t4_regs.h:#define V_REFERENCE(x) ((x) << S_REFERENCE) dev/cxgbe/common/t4_regs.h:#define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE) dev/cxgbe/common/t4_regs.h:#define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW) dev/cxgbe/common/t4_regs.h:#define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW) dev/cxgbe/common/t4_regs.h:#define V_POST_CURSOR(x) ((x) << S_POST_CURSOR) dev/cxgbe/common/t4_regs.h:#define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR) dev/cxgbe/common/t4_regs.h:#define V_SLEW_CTL(x) ((x) << S_SLEW_CTL) dev/cxgbe/common/t4_regs.h:#define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL) dev/cxgbe/common/t4_regs.h:#define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR) dev/cxgbe/common/t4_regs.h:#define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR) dev/cxgbe/common/t4_regs.h:#define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR) dev/cxgbe/common/t4_regs.h:#define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR) dev/cxgbe/common/t4_regs.h:#define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE) dev/cxgbe/common/t4_regs.h:#define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE) dev/cxgbe/common/t4_regs.h:#define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR) dev/cxgbe/common/t4_regs.h:#define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR) dev/cxgbe/common/t4_regs.h:#define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE) dev/cxgbe/common/t4_regs.h:#define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE) dev/cxgbe/common/t4_regs.h:#define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL) dev/cxgbe/common/t4_regs.h:#define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL) dev/cxgbe/common/t4_regs.h:#define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE) dev/cxgbe/common/t4_regs.h:#define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE) dev/cxgbe/common/t4_regs.h:#define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE) dev/cxgbe/common/t4_regs.h:#define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE) dev/cxgbe/common/t4_regs.h:#define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR) dev/cxgbe/common/t4_regs.h:#define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR) dev/cxgbe/common/t4_regs.h:#define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE) dev/cxgbe/common/t4_regs.h:#define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE) dev/cxgbe/common/t4_regs.h:#define V_ADR_TEST_MODE(x) ((x) << S_ADR_TEST_MODE) dev/cxgbe/common/t4_regs.h:#define G_ADR_TEST_MODE(x) (((x) >> S_ADR_TEST_MODE) & M_ADR_TEST_MODE) dev/cxgbe/common/t4_regs.h:#define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE) dev/cxgbe/common/t4_regs.h:#define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE) dev/cxgbe/common/t4_regs.h:#define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK) dev/cxgbe/common/t4_regs.h:#define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK) dev/cxgbe/common/t4_regs.h:#define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT) dev/cxgbe/common/t4_regs.h:#define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT) dev/cxgbe/common/t4_regs.h:#define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS) dev/cxgbe/common/t4_regs.h:#define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS) dev/cxgbe/common/t4_regs.h:#define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL) dev/cxgbe/common/t4_regs.h:#define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL) dev/cxgbe/common/t4_regs.h:#define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_) dev/cxgbe/common/t4_regs.h:#define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_) dev/cxgbe/common/t4_regs.h:#define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_) dev/cxgbe/common/t4_regs.h:#define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_) dev/cxgbe/common/t4_regs.h:#define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS) dev/cxgbe/common/t4_regs.h:#define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS) dev/cxgbe/common/t4_regs.h:#define V_OUTPUT_DRIVER_FORCE_VALUE(x) ((x) << S_OUTPUT_DRIVER_FORCE_VALUE) dev/cxgbe/common/t4_regs.h:#define G_OUTPUT_DRIVER_FORCE_VALUE(x) (((x) >> S_OUTPUT_DRIVER_FORCE_VALUE) & M_OUTPUT_DRIVER_FORCE_VALUE) dev/cxgbe/common/t4_regs.h:#define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE) dev/cxgbe/common/t4_regs.h:#define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE) dev/cxgbe/common/t4_regs.h:#define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE) dev/cxgbe/common/t4_regs.h:#define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE) dev/cxgbe/common/t4_regs.h:#define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER) dev/cxgbe/common/t4_regs.h:#define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER) dev/cxgbe/common/t4_regs.h:#define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE) dev/cxgbe/common/t4_regs.h:#define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE) dev/cxgbe/common/t4_regs.h:#define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER) dev/cxgbe/common/t4_regs.h:#define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER) dev/cxgbe/common/t4_regs.h:#define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR) dev/cxgbe/common/t4_regs.h:#define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR) dev/cxgbe/common/t4_regs.h:#define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE) dev/cxgbe/common/t4_regs.h:#define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE) dev/cxgbe/common/t4_regs.h:#define V_DDRPHY_PROTOCOL(x) ((x) << S_DDRPHY_PROTOCOL) dev/cxgbe/common/t4_regs.h:#define G_DDRPHY_PROTOCOL(x) (((x) >> S_DDRPHY_PROTOCOL) & M_DDRPHY_PROTOCOL) dev/cxgbe/common/t4_regs.h:#define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_MEMORY_TYPE(x) ((x) << S_MEMORY_TYPE) dev/cxgbe/common/t4_regs.h:#define G_MEMORY_TYPE(x) (((x) >> S_MEMORY_TYPE) & M_MEMORY_TYPE) dev/cxgbe/common/t4_regs.h:#define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK) dev/cxgbe/common/t4_regs.h:#define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK) dev/cxgbe/common/t4_regs.h:#define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK) dev/cxgbe/common/t4_regs.h:#define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK) dev/cxgbe/common/t4_regs.h:#define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING) dev/cxgbe/common/t4_regs.h:#define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING) dev/cxgbe/common/t4_regs.h:#define V_PVTP(x) ((x) << S_PVTP) dev/cxgbe/common/t4_regs.h:#define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP) dev/cxgbe/common/t4_regs.h:#define V_PVTN(x) ((x) << S_PVTN) dev/cxgbe/common/t4_regs.h:#define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN) dev/cxgbe/common/t4_regs.h:#define V_ANALOG_PD_DIV(x) ((x) << S_ANALOG_PD_DIV) dev/cxgbe/common/t4_regs.h:#define G_ANALOG_PD_DIV(x) (((x) >> S_ANALOG_PD_DIV) & M_ANALOG_PD_DIV) dev/cxgbe/common/t4_regs.h:#define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT) dev/cxgbe/common/t4_regs.h:#define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT) dev/cxgbe/common/t4_regs.h:#define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL) dev/cxgbe/common/t4_regs.h:#define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL) dev/cxgbe/common/t4_regs.h:#define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL) dev/cxgbe/common/t4_regs.h:#define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL) dev/cxgbe/common/t4_regs.h:#define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR) dev/cxgbe/common/t4_regs.h:#define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE) dev/cxgbe/common/t4_regs.h:#define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE) dev/cxgbe/common/t4_regs.h:#define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG) dev/cxgbe/common/t4_regs.h:#define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG) dev/cxgbe/common/t4_regs.h:#define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN) dev/cxgbe/common/t4_regs.h:#define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN) dev/cxgbe/common/t4_regs.h:#define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE) dev/cxgbe/common/t4_regs.h:#define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE) dev/cxgbe/common/t4_regs.h:#define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE) dev/cxgbe/common/t4_regs.h:#define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE) dev/cxgbe/common/t4_regs.h:#define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE) dev/cxgbe/common/t4_regs.h:#define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE) dev/cxgbe/common/t4_regs.h:#define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE) dev/cxgbe/common/t4_regs.h:#define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE) dev/cxgbe/common/t4_regs.h:#define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES) dev/cxgbe/common/t4_regs.h:#define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES) dev/cxgbe/common/t4_regs.h:#define V_MRS_CMD_SPACE(x) ((x) << S_MRS_CMD_SPACE) dev/cxgbe/common/t4_regs.h:#define G_MRS_CMD_SPACE(x) (((x) >> S_MRS_CMD_SPACE) & M_MRS_CMD_SPACE) dev/cxgbe/common/t4_regs.h:#define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS) dev/cxgbe/common/t4_regs.h:#define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS) dev/cxgbe/common/t4_regs.h:#define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW) dev/cxgbe/common/t4_regs.h:#define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW) dev/cxgbe/common/t4_regs.h:#define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE) dev/cxgbe/common/t4_regs.h:#define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE) dev/cxgbe/common/t4_regs.h:#define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE) dev/cxgbe/common/t4_regs.h:#define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE) dev/cxgbe/common/t4_regs.h:#define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD) dev/cxgbe/common/t4_regs.h:#define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD) dev/cxgbe/common/t4_regs.h:#define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE) dev/cxgbe/common/t4_regs.h:#define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE) dev/cxgbe/common/t4_regs.h:#define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE) dev/cxgbe/common/t4_regs.h:#define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE) dev/cxgbe/common/t4_regs.h:#define V_FW_WR_RD(x) ((x) << S_FW_WR_RD) dev/cxgbe/common/t4_regs.h:#define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD) dev/cxgbe/common/t4_regs.h:#define V_BIG_STEP(x) ((x) << S_BIG_STEP) dev/cxgbe/common/t4_regs.h:#define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP) dev/cxgbe/common/t4_regs.h:#define V_SMALL_STEP(x) ((x) << S_SMALL_STEP) dev/cxgbe/common/t4_regs.h:#define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP) dev/cxgbe/common/t4_regs.h:#define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY) dev/cxgbe/common/t4_regs.h:#define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY) dev/cxgbe/common/t4_regs.h:#define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES) dev/cxgbe/common/t4_regs.h:#define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES) dev/cxgbe/common/t4_regs.h:#define V_FW_RD_WR(x) ((x) << S_FW_RD_WR) dev/cxgbe/common/t4_regs.h:#define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR) dev/cxgbe/common/t4_regs.h:#define V_TWR_MPR(x) ((x) << S_TWR_MPR) dev/cxgbe/common/t4_regs.h:#define G_TWR_MPR(x) (((x) >> S_TWR_MPR) & M_TWR_MPR) dev/cxgbe/common/t4_regs.h:#define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON) dev/cxgbe/common/t4_regs.h:#define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON) dev/cxgbe/common/t4_regs.h:#define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF) dev/cxgbe/common/t4_regs.h:#define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF) dev/cxgbe/common/t4_regs.h:#define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI) dev/cxgbe/common/t4_regs.h:#define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI) dev/cxgbe/common/t4_regs.h:#define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL) dev/cxgbe/common/t4_regs.h:#define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL) dev/cxgbe/common/t4_regs.h:#define V_MT_GLOBAL_PHY_OFFSET(x) ((x) << S_MT_GLOBAL_PHY_OFFSET) dev/cxgbe/common/t4_regs.h:#define G_MT_GLOBAL_PHY_OFFSET(x) (((x) >> S_MT_GLOBAL_PHY_OFFSET) & M_MT_GLOBAL_PHY_OFFSET) dev/cxgbe/common/t4_regs.h:#define V_MT_DQ_SEL_QUAD(x) ((x) << S_MT_DQ_SEL_QUAD) dev/cxgbe/common/t4_regs.h:#define G_MT_DQ_SEL_QUAD(x) (((x) >> S_MT_DQ_SEL_QUAD) & M_MT_DQ_SEL_QUAD) dev/cxgbe/common/t4_regs.h:#define V_MT_PVTP(x) ((x) << S_MT_PVTP) dev/cxgbe/common/t4_regs.h:#define G_MT_PVTP(x) (((x) >> S_MT_PVTP) & M_MT_PVTP) dev/cxgbe/common/t4_regs.h:#define V_MT_PVTN(x) ((x) << S_MT_PVTN) dev/cxgbe/common/t4_regs.h:#define G_MT_PVTN(x) (((x) >> S_MT_PVTN) & M_MT_PVTN) dev/cxgbe/common/t4_regs.h:#define V_CFG(x) ((x) << S_CFG) dev/cxgbe/common/t4_regs.h:#define G_CFG(x) (((x) >> S_CFG) & M_CFG) dev/cxgbe/common/t4_regs.h:#define V_ECC_ADDR(x) ((x) << S_ECC_ADDR) dev/cxgbe/common/t4_regs.h:#define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR) dev/cxgbe/common/t4_regs.h:#define V_L_SEL(x) ((x) << S_L_SEL) dev/cxgbe/common/t4_regs.h:#define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL) dev/cxgbe/common/t4_regs.h:#define V_CLIENT_EN(x) ((x) << S_CLIENT_EN) dev/cxgbe/common/t4_regs.h:#define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN) dev/cxgbe/common/t4_regs.h:#define V_FID(x) ((x) << S_FID) dev/cxgbe/common/t4_regs.h:#define G_FID(x) (((x) >> S_FID) & M_FID) dev/cxgbe/common/t4_regs.h:#define V_C_FID(x) ((x) << S_C_FID) dev/cxgbe/common/t4_regs.h:#define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID) dev/cxgbe/common/t4_regs.h:#define V_C_VAL(x) ((x) << S_C_VAL) dev/cxgbe/common/t4_regs.h:#define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL) dev/cxgbe/common/t4_regs.h:#define V_C_SEL(x) ((x) << S_C_SEL) dev/cxgbe/common/t4_regs.h:#define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL) dev/cxgbe/common/t4_regs.h:#define V_QDR_CLKPHASE(x) ((x) << S_QDR_CLKPHASE) dev/cxgbe/common/t4_regs.h:#define G_QDR_CLKPHASE(x) (((x) >> S_QDR_CLKPHASE) & M_QDR_CLKPHASE) dev/cxgbe/common/t4_regs.h:#define V_MAXOPSPERTRC(x) ((x) << S_MAXOPSPERTRC) dev/cxgbe/common/t4_regs.h:#define G_MAXOPSPERTRC(x) (((x) >> S_MAXOPSPERTRC) & M_MAXOPSPERTRC) dev/cxgbe/common/t4_regs.h:#define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES) dev/cxgbe/common/t4_regs.h:#define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES) dev/cxgbe/common/t4_regs.h:#define V_MCMDADDR(x) ((x) << S_MCMDADDR) dev/cxgbe/common/t4_regs.h:#define G_MCMDADDR(x) (((x) >> S_MCMDADDR) & M_MCMDADDR) dev/cxgbe/common/t4_regs.h:#define V_MCMDLEN(x) ((x) << S_MCMDLEN) dev/cxgbe/common/t4_regs.h:#define G_MCMDLEN(x) (((x) >> S_MCMDLEN) & M_MCMDLEN) dev/cxgbe/common/t4_regs.h:#define V_MWDATA(x) ((x) << S_MWDATA) dev/cxgbe/common/t4_regs.h:#define G_MWDATA(x) (((x) >> S_MWDATA) & M_MWDATA) dev/cxgbe/common/t4_regs.h:#define V_MRSPDATA(x) ((x) << S_MRSPDATA) dev/cxgbe/common/t4_regs.h:#define G_MRSPDATA(x) (((x) >> S_MRSPDATA) & M_MRSPDATA) dev/cxgbe/common/t4_regs.h:#define V_BCMDADDR(x) ((x) << S_BCMDADDR) dev/cxgbe/common/t4_regs.h:#define G_BCMDADDR(x) (((x) >> S_BCMDADDR) & M_BCMDADDR) dev/cxgbe/common/t4_regs.h:#define V_BCMDLEN(x) ((x) << S_BCMDLEN) dev/cxgbe/common/t4_regs.h:#define G_BCMDLEN(x) (((x) >> S_BCMDLEN) & M_BCMDLEN) dev/cxgbe/common/t4_regs.h:#define V_BWDATA(x) ((x) << S_BWDATA) dev/cxgbe/common/t4_regs.h:#define G_BWDATA(x) (((x) >> S_BWDATA) & M_BWDATA) dev/cxgbe/common/t4_regs.h:#define V_BRSPDATA(x) ((x) << S_BRSPDATA) dev/cxgbe/common/t4_regs.h:#define G_BRSPDATA(x) (((x) >> S_BRSPDATA) & M_BRSPDATA) dev/cxgbe/common/t4_regs.h:#define V_EDRAMADDR(x) ((x) << S_EDRAMADDR) dev/cxgbe/common/t4_regs.h:#define G_EDRAMADDR(x) (((x) >> S_EDRAMADDR) & M_EDRAMADDR) dev/cxgbe/common/t4_regs.h:#define V_EDRAMDWSN(x) ((x) << S_EDRAMDWSN) dev/cxgbe/common/t4_regs.h:#define G_EDRAMDWSN(x) (((x) >> S_EDRAMDWSN) & M_EDRAMDWSN) dev/cxgbe/common/t4_regs.h:#define V_EDRAMCRA(x) ((x) << S_EDRAMCRA) dev/cxgbe/common/t4_regs.h:#define G_EDRAMCRA(x) (((x) >> S_EDRAMCRA) & M_EDRAMCRA) dev/cxgbe/common/t4_regs.h:#define V_EDRAMWDATA(x) ((x) << S_EDRAMWDATA) dev/cxgbe/common/t4_regs.h:#define G_EDRAMWDATA(x) (((x) >> S_EDRAMWDATA) & M_EDRAMWDATA) dev/cxgbe/common/t4_regs.h:#define V_EDRAMWBYTEEN(x) ((x) << S_EDRAMWBYTEEN) dev/cxgbe/common/t4_regs.h:#define G_EDRAMWBYTEEN(x) (((x) >> S_EDRAMWBYTEEN) & M_EDRAMWBYTEEN) dev/cxgbe/common/t4_regs.h:#define V_RDDQ_RDCNT(x) ((x) << S_RDDQ_RDCNT) dev/cxgbe/common/t4_regs.h:#define G_RDDQ_RDCNT(x) (((x) >> S_RDDQ_RDCNT) & M_RDDQ_RDCNT) dev/cxgbe/common/t4_regs.h:#define V_CMDFSM(x) ((x) << S_CMDFSM) dev/cxgbe/common/t4_regs.h:#define G_CMDFSM(x) (((x) >> S_CMDFSM) & M_CMDFSM) dev/cxgbe/common/t4_regs.h:#define V_ECMDLEN(x) ((x) << S_ECMDLEN) dev/cxgbe/common/t4_regs.h:#define G_ECMDLEN(x) (((x) >> S_ECMDLEN) & M_ECMDLEN) dev/cxgbe/common/t4_regs.h:#define V_ECMDADDR(x) ((x) << S_ECMDADDR) dev/cxgbe/common/t4_regs.h:#define G_ECMDADDR(x) (((x) >> S_ECMDADDR) & M_ECMDADDR) dev/cxgbe/common/t4_regs.h:#define V_REFPTR(x) ((x) << S_REFPTR) dev/cxgbe/common/t4_regs.h:#define G_REFPTR(x) (((x) >> S_REFPTR) & M_REFPTR) dev/cxgbe/common/t4_regs.h:#define V_REFCNT(x) ((x) << S_REFCNT) dev/cxgbe/common/t4_regs.h:#define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT) dev/cxgbe/common/t4_regs.h:#define V_TPH(x) ((x) << S_TPH) dev/cxgbe/common/t4_regs.h:#define G_TPH(x) (((x) >> S_TPH) & M_TPH) dev/cxgbe/common/t4_regs.h:#define V_DCA(x) ((x) << S_DCA) dev/cxgbe/common/t4_regs.h:#define G_DCA(x) (((x) >> S_DCA) & M_DCA) dev/cxgbe/common/t4_regs.h:#define V_E_SEL(x) ((x) << S_E_SEL) dev/cxgbe/common/t4_regs.h:#define G_E_SEL(x) (((x) >> S_E_SEL) & M_E_SEL) dev/cxgbe/common/t4_regs.h:#define V_VA(x) ((x) << S_VA) dev/cxgbe/common/t4_regs.h:#define G_VA(x) (((x) >> S_VA) & M_VA) dev/cxgbe/common/t4_regs.h:#define V_REGION(x) ((x) << S_REGION) dev/cxgbe/common/t4_regs.h:#define G_REGION(x) (((x) >> S_REGION) & M_REGION) dev/cxgbe/common/t4_regs.h:#define V_EDC_FSM(x) ((x) << S_EDC_FSM) dev/cxgbe/common/t4_regs.h:#define G_EDC_FSM(x) (((x) >> S_EDC_FSM) & M_EDC_FSM) dev/cxgbe/common/t4_regs.h:#define V_RAS_FSM_SLV(x) ((x) << S_RAS_FSM_SLV) dev/cxgbe/common/t4_regs.h:#define G_RAS_FSM_SLV(x) (((x) >> S_RAS_FSM_SLV) & M_RAS_FSM_SLV) dev/cxgbe/common/t4_regs.h:#define V_FC_FSM(x) ((x) << S_FC_FSM) dev/cxgbe/common/t4_regs.h:#define G_FC_FSM(x) (((x) >> S_FC_FSM) & M_FC_FSM) dev/cxgbe/common/t4_regs.h:#define V_COOKIE_ARB_FSM(x) ((x) << S_COOKIE_ARB_FSM) dev/cxgbe/common/t4_regs.h:#define G_COOKIE_ARB_FSM(x) (((x) >> S_COOKIE_ARB_FSM) & M_COOKIE_ARB_FSM) dev/cxgbe/common/t4_regs.h:#define V_PCIE_CHUNK_FSM(x) ((x) << S_PCIE_CHUNK_FSM) dev/cxgbe/common/t4_regs.h:#define G_PCIE_CHUNK_FSM(x) (((x) >> S_PCIE_CHUNK_FSM) & M_PCIE_CHUNK_FSM) dev/cxgbe/common/t4_regs.h:#define V_WTRANSFER_FSM(x) ((x) << S_WTRANSFER_FSM) dev/cxgbe/common/t4_regs.h:#define G_WTRANSFER_FSM(x) (((x) >> S_WTRANSFER_FSM) & M_WTRANSFER_FSM) dev/cxgbe/common/t4_regs.h:#define V_WD_FSM(x) ((x) << S_WD_FSM) dev/cxgbe/common/t4_regs.h:#define G_WD_FSM(x) (((x) >> S_WD_FSM) & M_WD_FSM) dev/cxgbe/common/t4_regs.h:#define V_RD_FSM(x) ((x) << S_RD_FSM) dev/cxgbe/common/t4_regs.h:#define G_RD_FSM(x) (((x) >> S_RD_FSM) & M_RD_FSM) dev/cxgbe/common/t4_regs.h:#define V_SYNC_FSM(x) ((x) << S_SYNC_FSM) dev/cxgbe/common/t4_regs.h:#define G_SYNC_FSM(x) (((x) >> S_SYNC_FSM) & M_SYNC_FSM) dev/cxgbe/common/t4_regs.h:#define V_OCHK_FSM(x) ((x) << S_OCHK_FSM) dev/cxgbe/common/t4_regs.h:#define G_OCHK_FSM(x) (((x) >> S_OCHK_FSM) & M_OCHK_FSM) dev/cxgbe/common/t4_regs.h:#define V_TLB_FSM(x) ((x) << S_TLB_FSM) dev/cxgbe/common/t4_regs.h:#define G_TLB_FSM(x) (((x) >> S_TLB_FSM) & M_TLB_FSM) dev/cxgbe/common/t4_regs.h:#define V_PIO_FSM(x) ((x) << S_PIO_FSM) dev/cxgbe/common/t4_regs.h:#define G_PIO_FSM(x) (((x) >> S_PIO_FSM) & M_PIO_FSM) dev/cxgbe/common/t4_regs.h:#define V_PCIE_LEN(x) ((x) << S_PCIE_LEN) dev/cxgbe/common/t4_regs.h:#define G_PCIE_LEN(x) (((x) >> S_PCIE_LEN) & M_PCIE_LEN) dev/cxgbe/common/t4_regs.h:#define V_MA_CLNT(x) ((x) << S_MA_CLNT) dev/cxgbe/common/t4_regs.h:#define G_MA_CLNT(x) (((x) >> S_MA_CLNT) & M_MA_CLNT) dev/cxgbe/common/t4_regs.h:#define V_MA_LEN(x) ((x) << S_MA_LEN) dev/cxgbe/common/t4_regs.h:#define G_MA_LEN(x) (((x) >> S_MA_LEN) & M_MA_LEN) dev/cxgbe/common/t4_regs.h:#define V_LKP_DESC_SEL(x) ((x) << S_LKP_DESC_SEL) dev/cxgbe/common/t4_regs.h:#define G_LKP_DESC_SEL(x) (((x) >> S_LKP_DESC_SEL) & M_LKP_DESC_SEL) dev/cxgbe/common/t4_regs.h:#define V_WR_EOP_CNT(x) ((x) << S_WR_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_WR_EOP_CNT(x) (((x) >> S_WR_EOP_CNT) & M_WR_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_RD_SOP_CNT(x) ((x) << S_RD_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_RD_SOP_CNT(x) (((x) >> S_RD_SOP_CNT) & M_RD_SOP_CNT) dev/cxgbe/common/t4_regs.h:#define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT) dev/cxgbe/common/t4_regs.h:#define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT) dev/cxgbe/common/t4_regs_values.h:#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE) dev/cxgbe/common/t4_regs_values.h:#define G_CONMCTXT_CNGTPMODE(x) \ dev/cxgbe/common/t4_regs_values.h:#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP) dev/cxgbe/common/t4_regs_values.h:#define G_CONMCTXT_CNGCHMAP(x) \ dev/cxgbe/common/t4_regs_values.h:#define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF) dev/cxgbe/common/t4_regs_values.h:#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) dev/cxgbe/common/t4_regs_values.h:#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) dev/cxgbe/common/t4_tcb.h:#define V_TCB_T_FLAGS(x) ((__u64)(x) << S_TCB_T_FLAGS) dev/cxgbe/common/t4_tcb.h:#define V_TCB_RSS_INFO(x) ((x) << S_TCB_RSS_INFO) dev/cxgbe/common/t4_tcb.h:#define V_TCB_SND_REC_RAW(x) ((__u64)(x) << S_TCB_SND_REC_RAW) dev/cxgbe/common/t4_tcb.h:#define V_TCB_MAIN_SLUSH(x) ((x) << S_TCB_MAIN_SLUSH) dev/cxgbe/common/t4_tcb.h:#define V_TCB_ULP_EXT(x) ((x) << S_TCP_ULP_EXT) dev/cxgbe/common/t4_tcb.h:#define V_TF_DACK_NOT_ACKED(x) ((x) << S_TF_DACK_NOT_ACKED) dev/cxgbe/common/t4_tcb.h:#define V_TF_RX_FLOW_CONTROL_DDP(x) ((x) << S_TF_RX_FLOW_CONTROL_DDP) dev/cxgbe/common/t4_tcb.h:#define V_TF_TX_QUIESCE(x) ((x) << S_TF_TX_QUIESCE) dev/cxgbe/common/t4_tcb.h:#define V_TF_RX_QUIESCE(x) ((x) << S_TF_RX_QUIESCE) dev/cxgbe/common/t4_tcb.h:#define V_TF_MASK_HASH(x) ((x) << S_TF_MASK_HASH) dev/cxgbe/common/t4_tcb.h:#define V_TF_DIRECT_STEER_HASH(x) ((x) << S_TF_DIRECT_STEER_HASH) dev/cxgbe/common/t4_tcb.h:#define V_TF_TX_QUEUE(x) ((x) << S_TF_TX_QUEUE) dev/cxgbe/common/t4_tcb.h:#define V_TF_REPORT_TID(x) ((x) << S_TF_REPORT_TID) dev/cxgbe/common/t4_tcb.h:#define V_TF_DROP(x) ((x) << S_TF_DROP) dev/cxgbe/common/t4_tcb.h:#define V_TF_DIRECT_STEER(x) ((x) << S_TF_DIRECT_STEER) dev/cxgbe/common/t4_tcb.h:#define V_TF_CORE_FLUSH(x) ((x) << S_TF_CORE_FLUSH) dev/cxgbe/common/t4_tcb.h:#define V_TF_INIT(x) ((__u64)(x) << S_TF_INIT) dev/cxgbe/common/t4_tcb.h:#define V_TF_MOD_SCHD_TX(x) ((__u64)(x) << S_TF_MOD_SCHD_TX) dev/cxgbe/common/t4_tcb.h:#define V_TF_TIMER(x) ((__u64)(x) << S_TF_TIMER) dev/cxgbe/common/t4_tcb.h:#define V_TF_DACK_TIMER(x) ((__u64)(x) << S_TF_DACK_TIMER) dev/cxgbe/common/t4_tcb.h:#define V_TF_PEER_FIN(x) ((__u64)(x) << S_TF_PEER_FIN) dev/cxgbe/common/t4_tcb.h:#define V_TF_TX_COMPACT(x) ((__u64)(x) << S_TF_TX_COMPACT) dev/cxgbe/common/t4_tcb.h:#define V_TF_RX_COMPACT(x) ((__u64)(x) << S_TF_RX_COMPACT) dev/cxgbe/common/t4_tcb.h:#define V_TF_TX_PDU_OUT(x) ((__u64)(x) << S_TF_TX_PDU_OUT) dev/cxgbe/common/t4_tcb.h:#define V_TF_RX_PDU_OUT(x) ((__u64)(x) << S_TF_RX_PDU_OUT) dev/cxgbe/common/t4_tcb.h:#define V_TF_FAST_RECOVERY(x) ((__u64)(x) << S_TF_FAST_RECOVERY) dev/cxgbe/common/t4_tcb.h:#define V_TF_IP_VERSION(x) ((__u64)(x) << S_TF_IP_VERSION) dev/cxgbe/common/t4_tcb.h:#define V_TF_CCTRL_ECN(x) ((__u64)(x) << S_TF_CCTRL_ECN) dev/cxgbe/common/t4_tcb.h:#define V_TF_LPBK(x) ((__u64)(x) << S_TF_LPBK) dev/cxgbe/common/t4_tcb.h:#define V_TF_CCTRL_ECE(x) ((__u64)(x) << S_TF_CCTRL_ECE) dev/cxgbe/common/t4_tcb.h:#define V_TF_REWRITE_DMAC(x) ((__u64)(x) << S_TF_REWRITE_DMAC) dev/cxgbe/common/t4_tcb.h:#define V_TF_CCTRL_CWR(x) ((__u64)(x) << S_TF_CCTRL_CWR) dev/cxgbe/common/t4_tcb.h:#define V_TF_REWRITE_SMAC(x) ((__u64)(x) << S_TF_REWRITE_SMAC) dev/cxgbe/common/t4_tcb.h:#define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR) dev/cxgbe/crypto/t4_crypto.h:#define G_KEY_CONTEXT_CTX_LEN(x) \ dev/cxgbe/crypto/t4_crypto.h:#define G_KEY_CONTEXT_DUAL_CK(x) \ dev/cxgbe/crypto/t4_crypto.h:#define G_KEY_CONTEXT_OPAD_PRESENT(x) \ dev/cxgbe/crypto/t4_crypto.h:#define G_KEY_CONTEXT_SALT_PRESENT(x) \ dev/cxgbe/crypto/t4_crypto.h:#define G_KEY_CONTEXT_CK_SIZE(x) \ dev/cxgbe/crypto/t4_crypto.h:#define G_KEY_CONTEXT_MK_SIZE(x) \ dev/cxgbe/crypto/t4_crypto.h:#define G_KEY_CONTEXT_VALID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_ATOMIC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_FLUSH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_COMPL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_TID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_RQTYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_NOREPLY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_IQ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_DEL_FILTER(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_RPTTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_DROP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_DIRSTEER(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_MASKHASH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_DIRSTEERHASH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_LPBK(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_DMAC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_SMAC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_INSVLAN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_RMVLAN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_HITCNTS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_TXCHAN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_PRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_FRAG(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_FRAGM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_IVLAN_VLD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_OVLAN_VLD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_IVLAN_VLDM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_OVLAN_VLDM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_RX_CHAN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_RX_RPL_IQ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_MACI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_MACIM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_FCOE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_FCOEM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_PORT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_PORTM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_MATCHTYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FILTER_WR_MATCHTYPEM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ETH_TX_EO_WR_TSCLK(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ETH_TX_EO_WR_TSOFF(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_CONNECTION_WR_CPL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FLOWC_WR_NPARAMS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_VALID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_STAGKEY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_STAGSTATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_STAGTYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_PDID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_PERM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_REMINVDIS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_ADDRTYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_MWBINDEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_PS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_QPID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_NOSNOOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_PBLADDR(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_DCA(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_CQE_QPID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_CQE_NOTIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_CQE_STATUS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_CQE_RXTX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_CQE_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_NRES(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_FETCHSZM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_STATUSPGNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_STATUSPGRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_FETCHNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_FETCHRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_HOSTFCMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_CPRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_ONCHIP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_PCIECHN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_DCAEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_DCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_FBMIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_FBMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_EQSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQANDST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQANUS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQANUD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQDROPRSS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQGTSMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQPCIECH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQDCAEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQDCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQCPRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQESIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_RES_WR_IQRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_SEND_WR_SENDOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_BIND_MW_WR_NS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_BIND_MW_WR_DCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_FR_NSMR_WR_NS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RI_WR_MPAREQBIT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_MODIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_FLAGS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_GET_NEXT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_REASON(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_RD_XFER_RDY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_WR_XFER_RDY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_FC_SP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_RPORT_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_NPIV(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_SEQ_DEL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_PRIO_PREEMP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_PREF(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_IMAGE_PAIR(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_ENH_DISC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_RETRY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_CONF_CMPL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_DATA_OVLY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_ERL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_FL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_ELS_CT_WR_SP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_WRITE_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_WRITE_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_WRITE_WR_CP_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_WRITE_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_READ_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_READ_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_READ_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_READ_WR_CP_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_READ_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_CMD_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_CMD_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_CMD_WR_CP_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_CMD_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_POFCOE_TCB_WR_TID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_POFCOE_TCB_WR_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_POFCOE_TCB_WR_PORT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_OP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_VALIDATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_INLINE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PI_ERROR_ERR_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_COMPL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_FLAGS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_EXP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_ADDRSPACE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_CYCLES(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_MSG(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_CTXTFLUSH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_PADDR(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_MMD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_FID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_IDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_RPLCPF(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_MPSID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_CTRL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_LC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_AI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_FN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_SELECT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_NACCESS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_NSET(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_LDST_CMD_PID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RESET_CMD_HALT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_ERR(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_INIT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_MASTERDIS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_MASTERFORCE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_MBASYNCNOT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_STAGE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HELLO_CMD_CLEARINIT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_MNEM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_X(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_XYZ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_YZ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PARAMS_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PFVF_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PFVF_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PFVF_CMD_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PFVF_CMD_CMASK(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_MODIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQSTART(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQSTOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQASYNCH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQANDST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQANUS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQANUD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQANDSTINDEX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQDROPRSS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQGTSMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQPCIECH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQDCAEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQDCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQCPRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQESIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_MODIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_EQSTART(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_EQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_CPRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_IQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_DCAEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_DCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_FBMIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_FBMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_MODIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_EQSTART(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_EQSTOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_FETCHNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_FETCHRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_CPRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_ONCHIP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_PCIECHN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_IQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_DCAEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_DCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_FBMIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_FBMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_EQSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_ETH_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_MODIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_EQSTART(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_CPRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_IQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_DCAEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_DCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_FBMIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_FBMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_MODIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_EQSTART(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_CPRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_IQID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_DCAEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_DCACPU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_FBMIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_FBMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_FUNC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_NORSS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_IDSIIQ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_CMD_IDSEIQ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_FREEMACS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_VALID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_PRIO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_RAW_IDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_DIP_HIT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_VNI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_MAC_CMD_VNI_MASK(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_RXMODE_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_RXMODE_CMD_MTU(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_ENABLE_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_ENABLE_CMD_IEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_ENABLE_CMD_EEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_ENABLE_CMD_LED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_STATS_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_STATS_CMD_NSTATS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_VI_STATS_CMD_IX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_MAC_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_MAC_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_MAC_CMD_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_VLAN_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_VLAN_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_VLAN_CMD_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_ACL_VLAN_CMD_FM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CAP_SPEED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CAP_FC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CAP_ANEG(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_READ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_TXIPG(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_FORCE_PINFO(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_LSTATUS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_LSPEED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_TXPAUSE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_RXPAUSE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_MDIOCAP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_LPTXPAUSE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_LPRXPAUSE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_AUXLINFO_KR(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_DCBXDIS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_APPLY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_ALL_SYNCD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_DCB_VERSION(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_PFC_STATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_ETS_STATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_CMD_APP_STATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_STATS_CMD_NSTATS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_STATS_CMD_BG_BM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_STATS_CMD_TX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_STATS_CMD_IX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_LB_STATS_CMD_IX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_CMD_PCIECH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_PTP_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_IND_TBL_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WATCHDOG_CMD_PFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_WATCHDOG_CMD_VFN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CLIP_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CLIP_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CHNET_IFACE_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CHNET_IFACE_CMD_IFID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_LINK_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_LINK_CMD_FCFI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_LINK_CMD_VNPI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_FCFI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_ALLOC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_MODIFY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_PERSIST(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_VNP_CMD_VNPI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_STATS_CMD_FLOWID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_STATS_CMD_FREE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_STATS_CMD_NSTATS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_STATS_CMD_PORT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_STATS_CMD_IX(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_FCF_CMD_FCFI(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_FCF_CMD_FPMA(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_FCF_CMD_SPMA(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_FCF_CMD_LOGIN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_FCOE_FCF_CMD_PORTID(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_PORT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_FEATURE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_LOCATION(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_CHANGED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_APPLY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_DISABLED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_MORE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_CBS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DEBUG_CMD_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_DIAG_CMD_TYPE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HMA_CMD_MODE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HMA_CMD_PCIE_PARAMS(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HMA_CMD_NADDR(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HMA_CMD_SIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) dev/cxgbe/firmware/t4fw_interface.h:#define G_FW_HMA_CMD_ADDR_SIZE(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) dev/cxgbe/firmware/t4fw_interface.h:#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) dev/cxgbe/firmware/t4fw_interface.h:#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_ASYNCNOT_VLD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_ASYNCNOTINT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_ASYNCNOT(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_MASTER_VLD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_RESET_VLD(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_RESET(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) dev/cxgbe/firmware/t4fw_interface.h:#define G_PCIE_FW_REGISTERED(x) \ dev/cxgbe/firmware/t4fw_interface.h:#define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) dev/cxgbe/iw_cxgbe/iw_cxgbe.h:#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start) dev/cxgbe/iw_cxgbe/t4.h:#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) dev/cxgbe/iw_cxgbe/t4.h:#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) dev/cxgbe/t4_main.c:#define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) dev/cxgbe/t4_main.c:#define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) dev/cxgbe/t4_main.c:#define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) dev/de/dc21040reg.h:#define PCI_VENDORID(x) ((x) & 0xFFFF) dev/de/dc21040reg.h:#define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) dev/de/if_devar.h:#define TULIP_RXMAP_PRESYNC(ri, di) \ dev/de/if_devar.h:#define TULIP_ADDREQUAL(a1, a2) \ dev/de/if_devar.h:#define TULIP_ADDRBRDCST(a1) \ dev/dpaa/bman.h:#define BMAN_PORTAL_CE_PA(base, n) \ dev/dpaa/bman.h:#define BMAN_PORTAL_CI_PA(base, n) \ dev/dpaa/if_dtsec.h:#define DTSEC_MII_LOCK(sc) mtx_lock(&(sc)->sc_mii_lock) dev/dpaa/if_dtsec.h:#define DTSEC_MII_UNLOCK(sc) mtx_unlock(&(sc)->sc_mii_lock) dev/dpaa/qman.h:#define QMAN_PORTAL_CE_PA(base, n) \ dev/dpaa/qman.h:#define QMAN_PORTAL_CI_PA(base, n) \ dev/dpt/dpt.h:#define DptStat_BUSY(x) ((x)->sp_ID_Message) dev/drm/savage_drv.h:#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) dev/drm/savage_drv.h:#define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) dev/drm/savage_drv.h:#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) dev/drm/savage_drv.h:#define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) dev/drm/savage_drv.h:#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) dev/drm/savage_drv.h:#define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) dev/drm/savage_drv.h:#define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) dev/drm/savage_drv.h:#define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) dev/drm/savage_drv.h:#define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) dev/drm/savage_drv.h:#define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) dev/drm/savage_drv.h:#define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) dev/drm/savage_drv.h:#define BCI_LINE_MISC(maj, ym, xp, yp, err) \ dev/drm/savage_drv.h:#define BCI_DRAW_PRIMITIVE(n, type, skip) \ dev/drm/savage_drv.h:#define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) ) dev/drm/sis_drv.h:#define SIS_READ(reg) DRM_READ32(SIS_BASE, reg); dev/drm/sis_drv.h:#define SIS_WRITE(reg, val) DRM_WRITE32(SIS_BASE, reg, val); dev/drm2/drmP.h:#define DRM_LOG(fmt, ...) do { \ dev/drm2/drmP.h:#define DRM_LOG_MODE(fmt, ...) do { \ dev/drm2/drmP.h:#define DRM_LOG_DRIVER(fmt, ...) do { \ dev/drm2/drmP.h:#define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x)) dev/drm2/drmP.h:#define DRM_LOCK_SLEEP(dev, chan, flags, msg, timeout) \ dev/drm2/drm_crtc.h:#define obj_to_mode(x) container_of(x, struct drm_display_mode, base) dev/drm2/drm_fixed.h:#define dfixed_frac(A) ((A).full & ((1 << 12) - 1)) dev/drm2/drm_mm.h:#define drm_mm_for_each_scanned_node_reverse(entry, n, mm) \ dev/drm2/drm_os_freebsd.h:#define __copy_to_user_inatomic_nocache(to, from, n) \ dev/drm2/drm_os_freebsd.h:#define KIB_NOTYET() \ dev/drm2/i915/dvo_ns2501.c:#define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr)) dev/drm2/i915/dvo_sil164.c:#define SILPTR(d) ((SIL164Ptr)(d->DriverPrivate.ptr)) dev/drm2/i915/i915_drv.h:#define transcoder_name(t) ((t) + 'A') dev/drm2/i915/i915_drv.h:#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) dev/drm2/i915/i915_drv.h:#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) dev/drm2/i915/i915_drv.h:#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) dev/drm2/i915/i915_reg.h:#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) dev/drm2/i915/i915_reg.h:#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) dev/drm2/i915/i915_reg.h:#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) dev/drm2/i915/i915_reg.h:#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) dev/drm2/i915/i915_reg.h:#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) dev/drm2/i915/i915_reg.h:#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) dev/drm2/i915/i915_reg.h:#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) dev/drm2/i915/i915_reg.h:#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) dev/drm2/i915/i915_reg.h:#define VLV_TVIDEO_DIP_GCP(pipe) \ dev/drm2/i915/i915_reg.h:#define HSW_TVIDEO_DIP_GCP(pipe) \ dev/drm2/i915/i915_reg.h:#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) dev/drm2/i915/i915_reg.h:#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) dev/drm2/i915/i915_reg.h:#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ dev/drm2/i915/i915_reg.h:#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ dev/drm2/i915/i915_reg.h:#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) dev/drm2/i915/intel_display.c:#define assert_pll_disabled(d, p) assert_pll(d, p, false) dev/drm2/i915/intel_drv.h:#define _wait_for(COND, MS, W, WMSG) ({ \ dev/drm2/radeon/ObjectID.h:#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ dev/drm2/radeon/nid.h:#define NUM_LOWER_PIPES(x) ((x) << 30) dev/drm2/radeon/r600d.h:#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) dev/drm2/radeon/r600d.h:#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) dev/drm2/radeon/r600d.h:#define FRONT_FACE_CHAN(x) ((x)<<9) dev/drm2/radeon/r600d.h:#define FRONT_FACE_ADDR(x) ((x)<<12) dev/drm2/radeon/r600d.h:#define FOG_ADDR(x) ((x)<<17) dev/drm2/radeon/r600d.h:#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) dev/drm2/radeon/r600d.h:#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) dev/drm2/radeon/radeon.h:#define to_radeon_fence(p) ((struct radeon_fence *)(p)) dev/drm2/radeon/radeon.h:#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) dev/drm2/radeon/radeon_drv.h:#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ dev/drm2/radeon/radeon_drv.h:#define RADEON_FLUSH_ZCACHE() do { \ dev/drm2/radeon/radeon_drv.h:#define OUT_RING_TABLE( tab, sz ) do { \ dev/drm2/radeon/rs600d.h:#define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) dev/drm2/radeon/rs600d.h:#define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) dev/drm2/radeon/rs600d.h:#define STATIC_SCREEN_HILEN(x) ((x) << 24) dev/drm2/radeon/rs600d.h:#define STATIC_SCREEN_LOLEN(x) ((x) << 28) dev/drm2/radeon/sid.h:#define ASIC_MAX_TEMP(x) ((x) << 0) dev/drm2/radeon/sid.h:#define CTF_TEMP(x) ((x) << 9) dev/drm2/radeon/sid.h:#define INVALIDATE_CACHE_MODE(x) ((x) << 26) dev/dwc/if_dwc.c:#define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) dev/ed/if_edvar.h:#define ed_nic_inw(sc, port) \ dev/ed/if_edvar.h:#define ed_nic_outw(sc, port, value) \ dev/ed/if_edvar.h:#define ed_nic_insb(sc, port, addr, count) \ dev/ed/if_edvar.h:#define ed_nic_outsb(sc, port, addr, count) \ dev/ed/if_edvar.h:#define ed_nic_insw(sc, port, addr, count) \ dev/ed/if_edvar.h:#define ed_nic_outsw(sc, port, addr, count) \ dev/ed/if_edvar.h:#define ed_nic_insl(sc, port, addr, count) \ dev/ed/if_edvar.h:#define ed_nic_outsl(sc, port, addr, count) \ dev/esp/ncr53c9xvar.h:#define LOGLINE(p) dev/esp/ncr53c9xvar.h:#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc)) dev/etherswitch/arswitch/arswitchvar.h:#define ARSWITCH_TRYLOCK(_sc) \ dev/etherswitch/etherswitch.h:#define ETHERSWITCH_PORTMASK(_port) (1 << (_port)) dev/etherswitch/mtkswitch/mtkswitchvar.h:#define MTK_IS_SWITCH(_sc, _type) \ dev/etherswitch/mtkswitch/mtkswitchvar.h:#define MTKSWITCH_TRYLOCK(_sc) \ dev/etherswitch/mtkswitch/mtkswitchvar.h:#define MTKSWITCH_MOD(_sc, _reg, _clr, _set) \ dev/etherswitch/rtl8366/rtl8366rb.c:#define RTL_LOCK_ASSERT(_sc, _what) mtx_assert(&(_s)c->sc_mtx, (_what)) dev/etherswitch/ukswitch/ukswitch.c:#define UKSWITCH_TRYLOCK(_sc) \ dev/extres/clk/clk.c:#define CLKNODE_SLOCK(_sc) sx_slock(&((_sc)->lock)) dev/extres/regulator/regulator.c:#define REG_TOPO_XASSERT() sx_assert(®node_topo_lock, SA_XLOCKED) dev/extres/regulator/regulator.c:#define REGNODE_SLOCK(_sc) sx_slock(&((_sc)->lock)) dev/fb/fb.c:#define FB_UNIT(dev) dev2unit(dev) dev/fb/fb.c:#define FB_MKMINOR(unit) (u) dev/fb/fbreg.h:#define vidd_probe(unit, adpp, arg, flags) \ dev/fb/fbreg.h:#define vidd_init(unit, adp, flags) \ dev/fb/fbreg.h:#define vidd_fill_rect(adp, val, x, y, cx, cy) \ dev/fb/fbreg.h:#define vidd_bitblt(adp, ...) \ dev/fb/fbreg.h:#define vidd_save_cursor_palette(adp, palette) \ dev/fb/fbreg.h:#define vidd_load_cursor_palette(adp, palette) \ dev/fb/fbreg.h:#define vidd_putp(adp, offset, p, a, size, bpp, bit_ltor1, byte_ltor2) \ dev/ffec/if_ffec.c:#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); dev/firewire/sbp.h:#define ORB_RCN_TMO(x) ((x) << 20) dev/firewire/sbp.h:#define ORB_CMD_PSZ(x) ((x) << 16) dev/gpio/bytgpio.c:#define BYTGPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) dev/gpio/bytgpio.c:#define BYTGPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) dev/gpio/gpiobusvar.h:#define GPIOBUS_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) dev/hifn/hifn7751var.h:#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) dev/hme/if_hme.c:#define HME_ERX_BARRIER(sc, offs, l, f) \ dev/hme/if_hme.c:#define HME_ETX_BARRIER(sc, offs, l, f) \ dev/hme/if_hmereg.h:#define HME_XD_DECODE_TSIZE(flags) \ dev/hptmv/atapi.h:#define mGetStatus(IOPort2) (UCHAR)InPort(&IOPort2->AlternateStatus) dev/hptmv/atapi.h:#define mUnitControl(IOPort2, Value) OutPort(&IOPort2->AlternateStatus,(UCHAR)(Value)) dev/hptmv/atapi.h:#define mGetErrorCode(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->Data+1) dev/hptmv/atapi.h:#define mSetFeaturePort(IOPort,x) OutPort((PUCHAR)&IOPort->Data+1, x) dev/hptmv/atapi.h:#define mSetBlockCount(IOPort,x) OutPort(&IOPort->BlockCount, x) dev/hptmv/atapi.h:#define mGetBlockCount(IOPort) (UCHAR)InPort(&IOPort->BlockCount) dev/hptmv/atapi.h:#define mGetInterruptReason(IOPort) (UCHAR)InPort(&IOPort->BlockCount) dev/hptmv/atapi.h:#define mSetBlockNumber(IOPort,x) OutPort(&IOPort->BlockNumber, x) dev/hptmv/atapi.h:#define mGetBlockNumber(IOPort) (UCHAR)InPort((PUCHAR)&IOPort->BlockNumber) dev/hptmv/atapi.h:#define mGetByteLow(IOPort) (UCHAR)InPort(&IOPort->CylinderLow) dev/hptmv/atapi.h:#define mSetCylinderLow(IOPort,x) OutPort(&IOPort->CylinderLow, x) dev/hptmv/atapi.h:#define mGetByteHigh(IOPort) (UCHAR)InPort(&IOPort->CylinderHigh) dev/hptmv/atapi.h:#define mSetCylinderHigh(IOPort,x) OutPort(&IOPort->CylinderHigh, x) dev/hptmv/atapi.h:#define mGetBaseStatus(IOPort) (UCHAR)InPort(&IOPort->Command) dev/hptmv/atapi.h:#define mGetUnitNumber(IOPort) InPort(&IOPort->DriveSelect) dev/hptmv/atapi.h:#define mIssueCommand(IOPort,Cmd) OutPort(&IOPort->Command, (UCHAR)(Cmd)) dev/hptmv/global.h:#define LongRShift(x, y) (x >> y) dev/hptmv/global.h:#define LongLShift(x, y) (x << y) dev/hptmv/global.h:#define LongRem(x, y) (x % (UINT)(y)) dev/hptmv/global.h:#define LongMul(x, y) (x * y) dev/hptmv/global.h:#define MemoryCopy(a,b,c) memcpy((char *)(a), (char *)(b), (UINT)(c)) dev/hptmv/mvOs.h:#define MV_CPU_WRITE_BUFFER_FLUSH() dev/hptmv/mvOs.h:#define mvOsSemInit(p) (MV_TRUE) dev/hptmv/raid5n.h:#define dataxfer_init(arg) 0 dev/hptmv/raid5n.h:#define dataxfer_add_item(handle, host, cache, bytes, tocache) \ dev/hptmv/raid5n.h:#define dataxfer_exec(handle, done, tag) done(_VBUS_P tag, 0) dev/hptmv/raid5n.h:#define xor_init(arg) 0 dev/hptmv/raid5n.h:#define xor_add_item(handle, dest, src, nsrc, bytes) \ dev/hptmv/raid5n.h:#define xor_exec(handle, done, tag) done(_VBUS_P tag, 0) dev/hptmv/vdevice.h:#define FOR_EACH_CHANNEL_ON_VBUS(_pVBus, _pChan) \ dev/hptmv/vdevice.h:#define FOR_EACH_DEV_ON_VBUS(pVBus, pVDev, i) \ dev/hptmv/vdevice.h:#define FOR_EACH_ARRAY_ON_ALL_VBUS(pVBus, pArray, i) \ dev/hptmv/vdevice.h:#define FOR_EACH_DEV_ON_ALL_VBUS(pVBus, pVDev, i) \ dev/hptmv/vdevice.h:#define OsGetChannelTable(x, y) fGetChannelTable() dev/hptmv/vdevice.h:#define OsGetDeviceTable(x, y) fGetDeviceTable() dev/hptmv/vdevice.h:#define OsRegisterDevice(pVDev) dev/hptmv/vdevice.h:#define OsUnregisterDevice(pVDev) dev/hwpmc/hwpmc_amd.h:#define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) dev/hwpmc/hwpmc_core.h:#define IAP_CMASK(C) (((C) & 0xFF) << 24) dev/hwpmc/hwpmc_riscv.h:#define RISCV_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R)) dev/hwpmc/hwpmc_riscv.h:#define RISCV_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) dev/hwpmc/hwpmc_uncore.h:#define UCP_EVSEL(C) ((C) & 0xFF) dev/hwpmc/hwpmc_uncore.h:#define UCP_CMASK(C) (((C) & 0xFF) << 24) dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_IAF() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_ATOM() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_ATOM_SILVERMONT() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_BROADWELL() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_BROADWELL_XEON() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_SKYLAKE() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_SKYLAKE_XEON() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_CORE() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_WESTMERE() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_HASWELL_XEON() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_HASWELL() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_IVYBRIDGE() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_IVYBRIDGE_XEON() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_SANDYBRIDGE() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_SANDYBRIDGE_XEON() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_BROADWELLUC() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_HASWELLUC() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_WESTMEREUC() \ dev/hwpmc/pmc_events.h:#define __PMC_EV_ALIAS_SANDYBRIDGEUC() \ dev/hyperv/storvsc/hv_vstorage.h:#define VMSTOR_PROTOCOL_MAJOR(VERSION_) (((VERSION_) >> 8) & 0xff) dev/hyperv/storvsc/hv_vstorage.h:#define VMSTOR_PROTOCOL_MINOR(VERSION_) (((VERSION_) ) & 0xff) dev/hyperv/utilities/hv_kvp.c:#define hv_kvp_log_error(...) do { \ dev/hyperv/utilities/hv_snapshot.c:#define hv_vss_log_error(...) do { \ dev/hyperv/utilities/hv_snapshot.h:#define VSS_DEV(VSS) "/dev/"VSS dev/ic/i82586.h:#define IE_ACTION_COMMAND(x) (((x) & IE_CU_COMMAND) == IE_CU_START) dev/ic/quicc.h:#define QUICC_PRAM_SCC_RFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x04) dev/ic/quicc.h:#define QUICC_PRAM_SCC_TFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x05) dev/ic/quicc.h:#define QUICC_PRAM_SCC_MRBLR(u) (QUICC_PRAM_BASE_SCC(u) + 0x06) dev/ic/quicc.h:#define QUICC_PRAM_SCC_RBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x10) dev/ic/quicc.h:#define QUICC_PRAM_SCC_TBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x20) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_MAX_IDL(u) (QUICC_PRAM_BASE_SCC(u) + 0x38) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_IDLC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3a) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_BRKCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x3c) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_PAREC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3e) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_FRMEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x40) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_NOSEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x42) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_BRKEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x44) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_BRKLN(u) (QUICC_PRAM_BASE_SCC(u) + 0x46) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_CC(u,n) (QUICC_PRAM_BASE_SCC(u) + 0x50 + (n)*2) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_RCCM(u) (QUICC_PRAM_BASE_SCC(u) + 0x60) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_RCCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x62) dev/ic/quicc.h:#define QUICC_PRAM_SCC_UART_RLBC(u) (QUICC_PRAM_BASE_SCC(u) + 0x64) dev/ic/quicc.h:#define QUICC_REG_SCC_GSMR_L(u) (QUICC_REG_BASE_SCC(u) + 0x00) dev/ic/quicc.h:#define QUICC_REG_SCC_GSMR_H(u) (QUICC_REG_BASE_SCC(u) + 0x04) dev/ic/quicc.h:#define QUICC_REG_SCC_DSR(u) (QUICC_REG_BASE_SCC(u) + 0x0e) dev/ic/quicc.h:#define QUICC_REG_SCC_SCCS(u) (QUICC_REG_BASE_SCC(u) + 0x17) dev/ida/idavar.h:#define ida_inb(ida, port) \ dev/ida/idavar.h:#define ida_inw(ida, port) \ dev/ida/idavar.h:#define ida_outb(ida, port, val) \ dev/ida/idavar.h:#define ida_outw(ida, port, val) \ dev/if_ndis/if_ndisvar.h:#define NDIS_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->ndis_mtx, t) dev/if_ndis/if_ndisvar.h:#define NDISUSB_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->ndisusb_mtx, t) dev/intel/spi.c:#define INTELSPI_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) dev/ioat/ioat_internal.h:#define ioat_read_chancnt(ioat) \ dev/ioat/ioat_test.c:#define IT_ASSERT() mtx_assert(&ioat_test_lk, MA_OWNED) dev/ipmi/ipmivars.h:#define IPMI_IO_LOCK_ASSERT(sc) mtx_assert(&(sc)->ipmi_io_lock, MA_OWNED) dev/isci/environment.h:#define PLACEMENT_HINTS(...) dev/isci/scil/sati_util.h:#define sati_get_ata_command(the_reg_fis) \ dev/isci/scil/sci_fast_list.h:#define sci_fast_list_get_tail(anchor) \ dev/isci/scil/sci_fast_list.h:#define sci_fast_list_get_prev(element) ((element)->prev) dev/isci/scil/sci_fast_list.h:#define sci_fast_list_is_on_a_list(element) ((element)->owning_list != NULL) dev/isci/scil/sci_pool.h:#define sci_pool_erase(this_pool, type, the_value) \ dev/isci/scil/sci_simple_list.h:#define sci_simple_list_element_init(list_object, element) \ dev/isci/scil/sci_simple_list.h:#define sci_simple_list_get_head(anchor) ((anchor)->list_head) dev/isci/scil/sci_simple_list.h:#define sci_simple_list_get_tail(anchor) ((anchor)->list_tail) dev/isci/scil/sci_simple_list.h:#define sci_simple_list_get_count(anchor) ((anchor)->list_count) dev/isci/scil/sci_simple_list.h:#define sci_simple_list_get_next(element) ((element)->next) dev/isci/scil/sci_simple_list.h:#define sci_simple_list_get_object(element) ((element)->object) dev/isci/scil/scic_sds_controller.c:#define NORMALIZE_PUT_POINTER(x) \ dev/isci/scil/scic_sds_controller_registers.h:#define scu_controller_viit_register_write(controller, index, reg, value) \ dev/isci/scil/scic_sds_controller_registers.h:#define SMU_TCR_READ(controller, value) \ dev/isci/scil/scic_sds_controller_registers.h:#define SMU_TCR_WRITE(controller, value) \ dev/isci/scil/scic_sds_controller_registers.h:#define SMU_CQGR_READ(controller, value) \ dev/isci/scil/scic_sds_controller_registers.h:#define SMU_ICC_READ(controller) \ dev/isci/scil/scic_sds_controller_registers.h:#define SMU_DFC_READ(controller) \ dev/isci/scil/scic_sds_controller_registers.h:#define SMU_CQPR_READ(controller) \ dev/isci/scil/scic_sds_controller_registers.h:#define scic_sds_controller_scu_register_read(controller, reg) \ dev/isci/scil/scic_sds_controller_registers.h:#define scic_sds_controller_scu_register_write(controller, reg, value) \ dev/isci/scil/scic_sds_controller_registers.h:#define SCU_UFQC_READ(controller) \ dev/isci/scil/scic_sds_controller_registers.h:#define SCU_UFQPP_READ(controller) \ dev/isci/scil/scic_sds_controller_registers.h:#define scu_cram_register_read(controller, reg) \ dev/isci/scil/scic_sds_controller_registers.h:#define scu_fbram_register_read(controller, reg) \ dev/isci/scil/scic_sds_controller_registers.h:#define SCU_PTSGRTC_READ(controller) \ dev/isci/scil/scic_sds_library.c:#define SCIC_LIBRARY_CONTROLLER_MEMORY_START(library) \ dev/isci/scil/scic_sds_phy.h:#define scic_sds_phy_is_ready(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_TLADTR_READ(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_TLADTR_WRITE(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_STPTLDARNI_READ(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_SAS_TIPID_READ(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_SAS_TIDNH_READ(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_SAS_TIDNL_READ(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_SAS_CLKSM_READ(phy) \ dev/isci/scil/scic_sds_phy_registers.h:#define SCU_SAS_PHYCAP_READ(phy) \ dev/isci/scil/scic_sds_port.h:#define scic_sds_port_read_phy_assignment(port, phy) \ dev/isci/scil/scic_sds_port_registers.h:#define SCU_PTSxCR_READ(port) \ dev/isci/scil/scic_sds_port_registers.h:#define SCU_PTSxCR_WRITE(port, value) \ dev/isci/scil/scic_sds_remote_device.h:#define scic_sds_remote_device_set_state_handlers(this_device, handlers) \ dev/isci/scil/scic_sds_remote_device.h:#define scic_sds_remote_device_get_ready_substate_machine(this_device) \ dev/isci/scil/scic_sds_remote_node_context.h:#define scic_sds_remote_node_context_get_remote_node_index(rcn) \ dev/isci/scil/scu_completion_codes.h:#define SCU_GET_COMPLETION_STATUS(completion_code) \ dev/isci/scil/scu_completion_codes.h:#define SCU_GET_COMPLETION_SDMA_STATUS(completion_code) \ dev/isci/scil/scu_completion_codes.h:#define SCU_GET_COMPLETION_PEG(completion_code) \ dev/isci/scil/scu_completion_codes.h:#define SCU_GET_COMPLETION_PORT(completion_code) \ dev/isci/scil/scu_registers.h:#define SCU_SET_BIT(name, reg_value) \ dev/isci/scil/scu_registers.h:#define SCU_CLEAR_BIT(name, reg_value) \ dev/isci/scil/scu_registers.h:#define SMU_PCP_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SMU_TCR_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SMU_TCR_GEN_BIT(name, value) \ dev/isci/scil/scu_registers.h:#define SMU_CQPR_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SMU_CQGR_GET_POINTER_SET(value) \ dev/isci/scil/scu_registers.h:#define SMU_DCC_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SMU_DCC_GET_MAX_PEG(value) \ dev/isci/scil/scu_registers.h:#define SMU_DCC_GET_MAX_LP(value) \ dev/isci/scil/scu_registers.h:#define SMU_DCC_GET_MAX_TC(value) \ dev/isci/scil/scu_registers.h:#define SMU_DCC_GET_MAX_RNC(value) \ dev/isci/scil/scu_registers.h:#define SMU_CGUCR_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SMU_RESET_ALL_PROTOCOL_ENGINES() \ dev/isci/scil/scu_registers.h:#define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \ dev/isci/scil/scu_registers.h:#define SMU_RESET_SCU() (0xFFFFFFFF) dev/isci/scil/scu_registers.h:#define SCU_UFQC_QUEUE_SIZE_SET(value) \ dev/isci/scil/scu_registers.h:#define SCU_UFQPP_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_UFQGP_ENABLE(value) \ dev/isci/scil/scu_registers.h:#define SCU_UFQGP_DISABLE(value) \ dev/isci/scil/scu_registers.h:#define SCU_UFQGP_VALUE(bit, value) \ dev/isci/scil/scu_registers.h:#define SCU_PDMACR_GEN_VALUE(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_PDMACR_BE_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_LLSTA_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_MAWTTOV_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_TIPID_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_PHYCAP_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_PHYCAP_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_PSZGCR_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_PSZGCR_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \ dev/isci/scil/scu_registers.h:#define SCU_PEG_SCUVZECR_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_PTSGCR_GEN_VAL(name, val) \ dev/isci/scil/scu_registers.h:#define SCU_RTCR_GEN_VAL(name, val) \ dev/isci/scil/scu_registers.h:#define SCU_RTCCR_GEN_VAL(name, val) \ dev/isci/scil/scu_registers.h:#define SCU_PTSxSR_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_SGICRx_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_SGPBRx_GEN_VAL(name, valueUL) \ dev/isci/scil/scu_registers.h:#define SCU_SGSDLRx_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_SGSDURx_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_SGSIDLRx_GEN_VAL(name, valueUL) \ dev/isci/scil/scu_registers.h:#define SCU_SGSIDURx_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_SGVSCR_GEN_VAL(value) \ dev/isci/scil/scu_registers.h:#define SCU_SGODSR_GEN_VAL(name, value) \ dev/isci/scil/scu_registers.h:#define SCU_SGODSR_GEN_BIT(name) \ dev/isci/scil/scu_registers.h:#define SCU_SAS_LLCTL_GEN_BIT(name) \ dev/isci/scil/scu_task_context.h:#define scu_get_command_request_subtype(x) \ dev/isci/scil/scu_task_context.h:#define scu_get_command_request_full_type(x) \ dev/isci/scil/scu_task_context.h:#define scu_get_command_protocl_engine_group(x) \ dev/isci/scil/scu_task_context.h:#define scu_get_command_reqeust_logical_port(x) \ dev/iscsi_initiator/iscsivar.h:#define CAM_ULOCK(arg) dev/isp/isp_freebsd.h:#define ISP_SET_PC(isp, chan, tag, val) \ dev/isp/ispmbox.h:#define ISP_FCTAPE_ENABLED(isp, chan) \ dev/isp/ispmbox.h:#define SNS_GID_XX_RESP_SIZE(x) ((sizeof (sns_gid_xx_rsp_t)) + ((x - 1) << 2)) dev/isp/ispmbox.h:#define AT_MAKE_TAGID(tid, aep) \ dev/isp/ispmbox.h:#define CT_MAKE_TAGID(tid, ct) \ dev/isp/ispmbox.h:#define AT_HAS_TAG(val) ((val) & (1 << 24)) dev/isp/ispmbox.h:#define AT_GET_TAG(val) (((val) >> 16) & 0xff) dev/isp/ispmbox.h:#define AT_GET_HANDLE(val) ((val) & 0xffff) dev/isp/ispmbox.h:#define IN_MAKE_TAGID(tid, inp) \ dev/isp/ispmbox.h:#define IN_FC_MAKE_TAGID(tid, bus, inst, seqid) \ dev/isp/ispmbox.h:#define FC_TAG_INSERT_INST(tid, inst) \ dev/isp/ispmbox.h:#define GET_IID_VAL(x) (x & 0x3f) dev/isp/ispmbox.h:#define GET_BUS_VAL(x) ((x >> 7) & 0x1) dev/isp/ispmbox.h:#define SET_IID_VAL(y, x) y = ((y & ~0x3f) | (x & 0x3f)) dev/isp/ispmbox.h:#define SET_BUS_VAL(y, x) y = ((y & 0x3f) | ((x & 0x1) << 7)) dev/isp/ispreg.h:#define ISP_NMBOX_BMASK(isp) \ dev/isp/ispreg.h:#define ISP_INTS_ENABLED(isp) \ dev/isp/ispreg.h:#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) dev/isp/ispreg.h:#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) dev/isp/ispvar.h:#define ISP_CLRBITS(isp, reg, val) \ dev/isp/ispvar.h:#define ISP_QAVAIL(isp) \ dev/isp/ispvar.h:#define ISP_FW_MAJOR(code) ((code >> 24) & 0xff) dev/isp/ispvar.h:#define ISP_FW_MINOR(code) ((code >> 16) & 0xff) dev/isp/ispvar.h:#define ISP_FW_MICRO(code) ((code >> 8) & 0xff) dev/iwm/if_iwm.c:#define IWM_RIDX_IS_OFDM(_i_) ((_i_) >= IWM_RIDX_OFDM) dev/iwm/if_iwm.c:#define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ dev/iwm/if_iwm.c:#define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ dev/iwm/if_iwmreg.h:#define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) dev/iwm/if_iwmreg.h:#define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ dev/iwm/if_iwmreg.h:#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ dev/iwm/if_iwmreg.h:#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ dev/iwm/if_iwmreg.h:#define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ dev/iwm/if_iwmreg.h:#define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) dev/iwm/if_iwmreg.h:#define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) dev/iwm/if_iwmreg.h:#define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ dev/iwm/if_iwmreg.h:#define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ dev/iwn/if_iwnreg.h:#define IWN_KFLAG_KID(kid) ((kid) << 8) dev/iwn/if_iwnreg.h:#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) dev/ixgb/if_ixgb_osdep.h:#define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS) dev/ixgbe/ixgbe.h:#define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32) dev/ixgbe/ixgbe.h:#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) dev/ixgbe/ixgbe_type.h:#define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA) dev/ixgbe/ixgbe_type.h:#define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC) dev/ixgbe/ixgbe_type.h:#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL) dev/ixgbe/ixgbe_type.h:#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) dev/ixgbe/ixgbe_type.h:#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ dev/ixgbe/ixgbe_type.h:#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ dev/ixgbe/ixgbe_type.h:#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ dev/ixgbe/ixgbe_type.h:#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ dev/ixgbe/ixgbe_type.h:#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ dev/ixgbe/ixgbe_type.h:#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ dev/ixgbe/ixgbe_type.h:#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ dev/ixgbe/ixgbe_type.h:#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ dev/ixgbe/ixgbe_type.h:#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40)) dev/ixgbe/ixgbe_type.h:#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40)) dev/ixgbe/ixgbe_type.h:#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) dev/ixgbe/ixgbe_type.h:#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) dev/ixgbe/ixgbe_type.h:#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ dev/ixgbe/ixgbe_type.h:#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) dev/ixgbe/ixgbe_type.h:#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) dev/ixgbe/ixgbe_type.h:#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ dev/ixgbe/ixgbe_type.h:#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ dev/ixgbe/ixgbe_type.h:#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ dev/ixgbe/ixgbe_type.h:#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) dev/ixgbe/ixgbe_type.h:#define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10)) dev/ixgbe/ixgbe_type.h:#define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ dev/ixgbe/ixgbe_type.h:#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ dev/ixgbe/ixgbe_type.h:#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ dev/ixgbe/ixgbe_type.h:#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA) dev/ixgbe/ixgbe_type.h:#define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD) dev/ixgbe/ixgbe_type.h:#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ dev/ixgbe/ixgbe_type.h:#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) dev/ixgbe/ixgbe_type.h:#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ dev/ixgbe/ixgbe_type.h:#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) dev/ixgbe/ixgbe_type.h:#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) dev/ixgbe/ixgbe_type.h:#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) dev/ixgbe/ixgbe_type.h:#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) dev/ixgbe/ixgbe_type.h:#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFLINKS(P) (0x042A4 + (0 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRTIMER(P) (0x00048 + (0 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFMAILBOX(P) (0x04C00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRXMEMWRAP(P) (0x03190 + (0 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTEICS(P) (0x00C00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTEIMS(P) (0x00D00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTEIMC(P) (0x00E00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTEIAC(P) (0x00F00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTEIAM(P) (0x04D00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTIVAR(P) (0x12500 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTIVAR_MISC(P) (0x04E00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVTRSCINT(P) (0x12000 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x))) dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \ dev/ixgbe/ixgbe_type.h:#define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918) dev/ixgbe/ixgbe_type.h:#define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C) dev/ixgbe/ixgbe_type.h:#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) dev/ixgbe/ixgbe_vf.h:#define IXGBE_VTRSCINT(x) (0x00180 + (4 * (x))) dev/ixgbe/ixgbe_vf.h:#define IXGBE_VFRSCCTL(x) (0x0102C + (0x40 * (x))) dev/ixl/ixl.h:#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off") dev/ixl/ixl.h:#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) dev/jme/if_jmereg.h:#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) dev/jme/if_jmereg.h:#define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) dev/jme/if_jmereg.h:#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) dev/jme/if_jmereg.h:#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) dev/jme/if_jmereg.h:#define RSSCPU_N_SEL(x) ((1 << (x)) dev/jme/if_jmereg.h:#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) dev/jme/if_jmereg.h:#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) dev/jme/if_jmereg.h:#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) dev/jme/if_jmereg.h:#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) dev/jme/if_jmereg.h:#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) dev/kbd/kbd.c:#define KBD_UNIT(dev) dev2unit(dev) dev/kbd/kbdreg.h:#define KBD_IS_POLLED(k) ((k)->kb_flags & KB_POLLED) dev/kbd/kbdreg.h:#define KBD_POLL(k) ((k)->kb_flags |= KB_POLLED) dev/kbd/kbdreg.h:#define KBD_UNPOLL(k) ((k)->kb_flags &= ~KB_POLLED) dev/kbd/kbdreg.h:#define kbdd_probe(kbd, unit, arg, flags) \ dev/kbd/kbdreg.h:#define kbdd_test_if(kbd) \ dev/kbd/kbdreg.h:#define kbdd_read(kbd, wait) \ dev/kbd/kbdreg.h:#define kbdd_check(kbd) \ dev/kbd/kbdreg.h:#define kbdd_get_state(kbd, buf, len) \ dev/kbd/kbdreg.h:#define kbdd_set_state(kbd, buf, len) \ dev/kbd/kbdreg.h:#define kbdd_diag(kbd, level) \ dev/le/lancereg.h:#define LE_BCNT(x) (~(x) + 1) dev/le/lancereg.h:#define CHIPID_MANFID(x) (((x) >> 1) & 0x3ff) dev/le/lancereg.h:#define CHIPID_PARTID(x) (((x) >> 12) & 0xffff) dev/le/lancereg.h:#define CHIPID_VER(x) (((x) >> 28) & 0x7) dev/liquidio/base/lio_config.h:#define LIO_GET_IQ_MAX_Q_CFG(cfg) ((cfg)->iq.max_iqs) dev/liquidio/base/lio_device.h:#define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) dev/malo/if_malo.h:#define MALO_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED) dev/malo/if_malo.h:#define MALO_RXFREE_INIT(_sc) \ dev/malo/if_malo.h:#define MALO_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->malo_rxlock) dev/malo/if_malo.h:#define MALO_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->malo_rxlock) dev/malo/if_malo.h:#define MALO_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->malo_rxlock) dev/malo/if_malo.h:#define MALO_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->malo_rxlock, \ dev/mge/if_mgevar.h:#define MGE_SMI_LOCK_ASSERT() sx_assert(&sx_smi, SA_XLOCKED) dev/mge/if_mgevar.h:#define SW_SMI_READ_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 11) | (phy << 5) | reg) dev/mge/if_mgevar.h:#define SW_SMI_WRITE_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 10) | (phy << 5) | reg) dev/mge/if_mgevar.h:#define PORT_SERIAL_FORCE_FC(val) (((val) & 3) << 5) /* pause enable & disable frames conf */ dev/mge/if_mgevar.h:#define PORT_SERIAL_FORCE_BP(val) (((val) & 3) << 7) /* transmitting JAM configuration */ dev/mge/if_mgevar.h:#define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16) dev/mge/if_mgevar.h:#define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8)) dev/mii/mii.h:#define BMCR_SPEED(x) ((x) & (BMCR_SPEED0|BMCR_SPEED1)) dev/mlx4/mlx4_en/mlx4_en_netdev.c:#define EN_PORT_ATTR(_name, _mode, _show, _store) \ dev/mlx4/mlx4_ib/mlx4_ib_mcg.c:#define mcg_error(fmt, arg...) pr_err(fmt, ##arg) dev/mlx4/mlx4_ib/mlx4_ib_mcg.c:#define mcg_error_group(group, format, arg...) \ dev/mlx4/qp.h:#define SET_LSO_MSS(mss_hdr_size) cpu_to_be32(mss_hdr_size) dev/mly/mlyvar.h:#define MLY_GET_MBOX(sc, mbox, ptr) \ dev/mmc/host/dwmmc.c:#define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); dev/mmc/host/dwmmc.c:#define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); dev/mmc/host/dwmmc.c:#define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); dev/mmc/mmc.c:#define MMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED); dev/mmc/mmc.c:#define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED); dev/mmc/mmc_ioctl.h:#define mmc_ioc_cmd_set_data(mic, ptr) \ dev/mmc/mmcreg.h:#define SD_IO_RW_FUNC(x) (((x) & 0x7) << 28) dev/mmc/mmcreg.h:#define SD_IO_RW_LEN(x) (((x) & 0xFF) << 0) dev/mmc/mmcreg.h:#define SD_IOE_RW_LEN(x) (((x) & 0x1FF) << 0) dev/mmc/mmcsd.c:#define MMCSD_DISK_ASSERT_LOCKED(_part) \ dev/mmc/mmcsd.c:#define MMCSD_DISK_ASSERT_UNLOCKED(_part) \ dev/mmc/mmcsd.c:#define MMCSD_IOCTL_ASSERT_LOCKED(_part) \ dev/mmc/mmcsd.c:#define MMCSD_IOCLT_ASSERT_UNLOCKED(_part) \ dev/mpr/mpr_sas.h:#define MPR_SET_SINGLE_LUN(req, lun) \ dev/mpr/mprvar.h:#define mpr_vprintf(sc, args...) \ dev/mpr/mprvar.h:#define MPR_PRINTFIELD_END(sc, tag) \ dev/mps/mps_sas.h:#define MPS_SET_SINGLE_LUN(req, lun) \ dev/mps/mpsvar.h:#define mps_vprintf(sc, args...) \ dev/mps/mpsvar.h:#define MPS_PRINTFIELD_END(sc, tag) \ dev/mpt/mpilib/mpi.h:#define MPI_SET_CONTEXT_REPLY_TYPE(x, typ) \ dev/mpt/mpilib/mpi.h:#define MPI_SGE_CHAIN_LENGTH(fl) ((fl) & MPI_SGE_CHAIN_LENGTH_MASK) dev/mpt/mpilib/mpi.h:#define MPI_pSGE_GET_FLAGS(psg) MPI_SGE_GET_FLAGS((psg)->FlagsLength) dev/mpt/mpilib/mpi.h:#define MPI_pSGE_GET_LENGTH(psg) MPI_SGE_LENGTH((psg)->FlagsLength) dev/mpt/mpilib/mpi.h:#define MPI_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI_SGE_SET_FLAGS_LENGTH(f,l) dev/mpt/mpilib/mpi.h:#define MPI_GET_CHAIN_OFFSET(x) ((x&MPI_SGE_CHAIN_OFFSET_MASK)>>MPI_SGE_CHAIN_OFFSET_SHIFT) dev/mpt/mpilib/mpi_lan.h:#define GET_LAN_PACKET_LENGTH(x) (((x) & LAN_REPLY_PACKET_LENGTH_MASK) \ dev/mpt/mpilib/mpi_lan.h:#define SET_LAN_PACKET_LENGTH(x, lth) \ dev/mpt/mpilib/mpi_lan.h:#define GET_LAN_BUCKET_CONTEXT(x) (((x) & LAN_REPLY_BUCKET_CONTEXT_MASK) \ dev/mpt/mpilib/mpi_lan.h:#define SET_LAN_BUCKET_CONTEXT(x, ctx) \ dev/mpt/mpilib/mpi_lan.h:#define GET_LAN_BUFFER_CONTEXT(x) (((x) & LAN_REPLY_BUFFER_CONTEXT_MASK) \ dev/mpt/mpilib/mpi_lan.h:#define SET_LAN_BUFFER_CONTEXT(x, ctx) \ dev/mpt/mpilib/mpi_lan.h:#define GET_LAN_FORM(x) (((x) & LAN_REPLY_FORM_MASK) \ dev/mpt/mpilib/mpi_lan.h:#define SET_LAN_FORM(x, frm) \ dev/mpt/mpilib/mpi_targ.h:#define SET_IO_INDEX(t, i) \ dev/mpt/mpilib/mpi_targ.h:#define SET_INITIATOR_INDEX(t, ii) \ dev/mpt/mpilib/mpi_targ.h:#define GET_ALIAS(x) (((x) & TARGET_MODE_REPLY_ALIAS_MASK) \ dev/mpt/mpilib/mpi_targ.h:#define SET_ALIAS(t, a) ((t) = ((t) & ~TARGET_MODE_REPLY_ALIAS_MASK) | \ dev/mpt/mpilib/mpi_targ.h:#define GET_PORT(x) (((x) & TARGET_MODE_REPLY_PORT_MASK) \ dev/mpt/mpt.h:#define MPT_OWNED(mpt) mtx_owned(&(mpt)->mpt_lock) dev/mpt/mpt.h:#define mpt_lprtc(mpt, level, ...) \ dev/mpt/mpt_reg.h:#define MPT_REPLY_INTR(v) (((v) & MPT_INTR_REPLY_READY) != 0) dev/msk/if_mskreg.h:#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ dev/msk/if_mskreg.h:#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) dev/msk/if_mskreg.h:#define RSS_KEY_ADDR(Port, KeyIndex) \ dev/msk/if_mskreg.h:#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) dev/msk/if_mskreg.h:#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) dev/msk/if_mskreg.h:#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) dev/msk/if_mskreg.h:#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) dev/msk/if_mskreg.h:#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) dev/msk/if_mskreg.h:#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) dev/msk/if_mskreg.h:#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) dev/msk/if_mskreg.h:#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) dev/msk/if_mskreg.h:#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) dev/msk/if_mskreg.h:#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ dev/msk/if_mskreg.h:#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ dev/msk/if_mskreg.h:#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ dev/msk/if_mskreg.h:#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ dev/msk/if_mskreg.h:#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) dev/msk/if_mskreg.h:#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) dev/msk/if_mskreg.h:#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) dev/msk/if_mskreg.h:#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) dev/msk/if_mskreg.h:#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) dev/msk/if_mskreg.h:#define MSK_TX_RING_ADDR(sc, i) \ dev/msk/if_mskreg.h:#define MSK_RX_RING_ADDR(sc, i) \ dev/msk/if_mskreg.h:#define MSK_JUMBO_RX_RING_ADDR(sc, i) \ dev/mvs/mvs.h:#define HC_CFG_COALDIS(p) (1 << ((p) + 24))/* Coalescing Disable*/ dev/mvs/mvs.h:#define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */ dev/mvs/mvs.h:#define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */ dev/mvs/mvs.h:#define EDMA_S_ESTATE(s) (((s) & 0x0000ff00) >> 8) dev/mvs/mvs.h:#define EDMA_CQDCQOS(x) (0x90 + ((x) << 2) dev/mvs/mvs.h:#define DMA_C_DRBC(n) (((n) & 0xffff) << 16) dev/mvs/mvs.h:#define MVS_CRQB_TO_ADDR(slot) ((slot) << MVS_CRQB_SHIFT) dev/mvs/mvs.h:#define MVS_ADDR_TO_CRQB(addr) (((addr) & MVS_CRQB_MASK) >> MVS_CRQB_SHIFT) dev/mvs/mvs.h:#define MVS_CRPB_TO_ADDR(slot) ((slot) << MVS_CRPB_SHIFT) dev/mvs/mvs.h:#define MVS_ADDR_TO_CRPB(addr) (((addr) & MVS_CRPB_MASK) >> MVS_CRPB_SHIFT) dev/mwl/if_mwlvar.h:#define MWL_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED) dev/mwl/if_mwlvar.h:#define MWL_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->sc_rxlock, MA_OWNED) dev/mxge/mcp_gen_header.h:#define MCP_GEN_HEADER_DECL(type, version_str, global_ptr) \ dev/mxge/mxge_mcp.h:#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) dev/my/if_myreg.h:#define MY_TXDATA(x) x->my_ptr->my_frag[x->my_lastdesc].my_data dev/neta/if_mvnetareg.h:#define MVNETA_QUEUE(n) (1 << (n)) dev/neta/if_mvnetareg.h:#define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ dev/neta/if_mvnetareg.h:#define MVNETA_DSCP(n) (0x2420 + ((n) << 2)) dev/neta/if_mvnetareg.h:#define MVNETA_PRXDI(q) (0x1520 + ((q) << 2)) /*P RXqueues Stat Update*/ dev/neta/if_mvnetareg.h:#define MVNETA_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/ dev/neta/if_mvnetareg.h:#define MVNETA_TXMH(n) (0x3d44 + ((n) << 2)) dev/neta/if_mvnetareg.h:#define MVNETA_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/ dev/neta/if_mvnetareg.h:#define MVNETA_BASEADDR_TARGET(target) ((target) & 0xf) dev/neta/if_mvnetareg.h:#define MVNETA_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) dev/neta/if_mvnetareg.h:#define MVNETA_BASEADDR_BASE(base) ((base) & 0xffff0000) dev/neta/if_mvnetareg.h:#define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000) dev/neta/if_mvnetareg.h:#define MVNETA_BARE_EN(win) ((1 << (win)) & MVNETA_BARE_EN_MASK) dev/neta/if_mvnetareg.h:#define MVNETA_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) dev/neta/if_mvnetareg.h:#define MVNETA_PHYADDR_PHYAD(phy) ((phy) & 0x1f) dev/neta/if_mvnetareg.h:#define MVNETA_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f) dev/neta/if_mvnetareg.h:#define MVNETA_EUDID_DIDR(id) ((id) & 0x0f) dev/neta/if_mvnetareg.h:#define MVNETA_EUDID_DATTR(attr) (((attr) & 0xff) << 4) dev/neta/if_mvnetareg.h:#define MVNETA_EUIAE_INTADDR(addr) ((addr) & 0x1ff) dev/neta/if_mvnetareg.h:#define MVNETA_EUIAE_GET_INTADDR(addr) ((addr) & 0x1ff) dev/neta/if_mvnetareg.h:#define MVNETA_PV_VERSION(v) ((v) & 0xff) dev/neta/if_mvnetareg.h:#define MVNETA_PV_GET_VERSION(reg) ((reg) & 0xff) dev/neta/if_mvnetareg.h:#define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) dev/neta/if_mvnetareg.h:#define MVNETA_RQC_EN(n) ((n) << 0) dev/neta/if_mvnetareg.h:#define MVNETA_RQC_DISQ(q) (1 << (8 + (q))) dev/neta/if_mvnetareg.h:#define MVNETA_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0) dev/neta/if_mvnetareg.h:#define MVNETA_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16) dev/neta/if_mvnetareg.h:#define MVNETA_PRXS_ODC(x) (((x) & 0x3fff) << 0) dev/neta/if_mvnetareg.h:#define MVNETA_PRXS_NODC(x) (((x) & 0x3fff) << 16) dev/neta/if_mvnetareg.h:#define MVNETA_TQC_EN(n) ((n) << 0) dev/neta/if_mvnetareg.h:#define MVNETA_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */ dev/neta/if_mvnetareg.h:#define MVNETA_PTXDQS_TBT(x) (((x) & 0x3fff) << 16) dev/neta/if_mvnetareg.h:#define MVNETA_PTXS_TBC(x) (((x) & 0x3fff) << 16) dev/neta/if_mvnetareg.h:#define MVNETA_PTXS_PDC(x) ((x) & 0x3fff) dev/neta/if_mvnetareg.h:#define MVNETA_PTXS_GET_PDC(x) ((x) & 0x3fff) dev/neta/if_mvnetareg.h:#define MVNETA_TXTBC_TBC(x) (((x) & 0x3fff) << 16) dev/neta/if_mvnetareg.h:#define MVNETA_TQFPC_EN(q) (1 << (q)) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXTI_TBTCQ(q) (1 << ((q) + 0)) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXTI_GET_TBTCQ(reg) (((reg) >> 0) & 0xff) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXTI_RDTAQ(q) (1 << ((q) + 16)) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXTI_GET_RDTAQ(reg) (((reg) >> 16) & 0xff) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXI_TBRQ(q) (1 << ((q) + 0)) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXI_GET_TBRQ(reg) (((reg) >> 0) & 0xff) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXI_RPQ(q) (1 << ((q) + 8)) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXI_GET_RPQ(reg) (((reg) >> 8) & 0xff) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXI_RREQ(q) (1 << ((q) + 16)) dev/neta/if_mvnetareg.h:#define MVNETA_PRXTXI_GET_RREQ(reg) (((reg) >> 16) & 0xff) dev/neta/if_mvnetareg.h:#define MVNETA_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */ dev/neta/if_mvnetareg.h:#define MVNETA_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0)) dev/neta/if_mvnetareg.h:#define MVNETA_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8)) dev/neta/if_mvnetareg.h:#define MVNETA_PEUIAE_ADDR(addr) ((addr) & 0x3fff) dev/neta/if_mvnetareg.h:#define MVNETA_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff) dev/neta/if_mvnetavar.h:#define MVNETA_READ_REGION(sc, reg, val, c) \ dev/neta/if_mvnetavar.h:#define KASSERT_BM_MTX(sc) \ dev/netmap/netmap_kern.h:#define netmap_pipe_alloc(_1, _2) 0 dev/netmap/netmap_mem2.c:#define netmap_buf_index(n, v) \ dev/ntb/ntb_hw/ntb_hw_plx.c:#define PNTX_READ(sc, reg) \ dev/ntb/ntb_hw/ntb_hw_plx.c:#define BNTX_READ(sc, reg) \ dev/nxge/include/xge-list.h:#define xge_list_for_each_safe(_p, _n, _h) \ dev/nxge/include/xgehal-fifo.h:#define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32) dev/nxge/include/xgehal-fifo.h:#define XGE_HAL_TXD_INT_NUMBER(val) vBIT(val,34,6) dev/nxge/include/xgehal-mgmt.h:#define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \ dev/nxge/include/xgehal-regs.h:#define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_TX_TRAFFIC_INT_n(n) BIT(n) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RX_TRAFFIC_INT_n(n) BIT(n) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_STATREQTO_VAL(n) TBD dev/nxge/include/xgehal-regs.h:#define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_ENTRY(spdm_overwrite) \ dev/nxge/include/xgehal-regs.h:#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_DW(spdm_overwrite) \ dev/nxge/include/xgehal-regs.h:#define XGE_HAL_SPDM_OVERWRITE_ERR_SPDM_LINE(spdm_overwrite) \ dev/nxge/include/xgehal-regs.h:#define XGE_HAL_SPDM_INT_QW_PER_ENTRY(spdm_structure) \ dev/nxge/include/xgehal-regs.h:#define XGE_HAL_SPDM_PCI_QW_PER_ENTRY(spdm_structure) \ dev/nxge/include/xgehal-regs.h:#define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RTS_DIX_MAP_SCW(val) BIT(val,21) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32) dev/nxge/include/xgehal-regs.h:#define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17) dev/nxge/include/xgehal-ring.h:#define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val dev/nxge/xge-osdep.h:#define xge_os_prefetchw(x) (x=x) dev/oce/oce_hw.h:#define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) dev/oce/oce_hw.h:#define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) dev/oce/oce_hw.h:#define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) dev/oce/oce_hw.h:#define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) dev/oce/oce_if.h:#define for_all_cq_queues(sc, cq, i) \ dev/oce/oce_if.h:#define DBUF_SYNC(obj, flags) \ dev/oce/oce_if.h:#define RING_NUM_PENDING(ring) ring->num_used dev/oce/oce_if.h:#define RING_EMPTY(ring) (ring->num_used == 0) dev/oce/oce_if.h:#define RING_GET_CONSUMER_ITEM_PA(ring, type) \ dev/oce/oce_if.h:#define RING_GET_PRODUCER_ITEM_PA(ring, type) \ dev/oce/oce_if.h:#define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) dev/ow/ow.c:#define OW_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) dev/ow/owc_gpiobus.c:#define OWC_GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) dev/ow/owc_gpiobus.c:#define OWC_GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) dev/pci/pcireg.h:#define PCI_CBBMEMBASE(l) ((l) & ~0xfffff) dev/pci/pcireg.h:#define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff) dev/pci/pcireg.h:#define PCI_CBBIOBASE(l) ((l) & ~0x3) dev/pci/pcireg.h:#define PCI_CBBIOLIMIT(l) ((l) | 0x3) dev/pci/pcireg.h:#define PCIM_EA_BEI_BAR(x) (((x) >> PCIM_EA_BEI_OFFSET) & 0xf) dev/pci/pcireg.h:#define PCIM_EA_SEC_NR(reg) ((reg) & 0xff) dev/pci/pcireg.h:#define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff) dev/pci/pcireg.h:#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) dev/pci/pcireg.h:#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) dev/pci/pcireg.h:#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) dev/pdq/pdqvar.h:#define PDQ_BPFATTACH(sc, t, s) bpfattach(PDQ_IFNET(sc), t, s) dev/pdq/pdqvar.h:#define PDQ_LANADDR_SIZE(sc) (sizeof((sc)->sc_ac.ac_enaddr)) dev/pms/RefTisa/discovery/dm/dmdefs.h:#define DMIsSPCADAP(agr) (DM_VEN_DEV_SPC == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */ dev/pms/RefTisa/discovery/dm/dmdefs.h:#define DMIsSPCv(agr) (DM_VEN_DEV_SPCv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */ dev/pms/RefTisa/discovery/dm/dmdefs.h:#define DMIsSPCve(agr) (DM_VEN_DEV_SPCve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve */ dev/pms/RefTisa/discovery/dm/dmdefs.h:#define DMIsSPCvplus(agr) (DM_VEN_DEV_SPCvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ dev/pms/RefTisa/discovery/dm/dmdefs.h:#define DMIsSPCveplus(agr) (DM_VEN_DEV_SPCveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ dev/pms/RefTisa/discovery/dm/dmdefs.h:#define DMIsSPCADAPvplus(agr) (DM_VEN_DEV_ADAPvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */ dev/pms/RefTisa/discovery/dm/dmdefs.h:#define DMIsSPCADAPveplus(agr) (DM_VEN_DEV_ADAPveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */ dev/pms/RefTisa/discovery/dm/dmlist.h:#define DMLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr) \ dev/pms/RefTisa/discovery/dm/dmlist.h:#define DMLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr) \ dev/pms/RefTisa/discovery/dm/dmlist.h:#define DMLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_SASDEV_IS_STP_INITIATOR(sasDev) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_SASDEV_IS_SSP_TARGET(sasDev) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_SASDEV_IS_STP_TARGET(sasDev) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_SASDEV_IS_SMP_TARGET(sasDev) \ dev/pms/RefTisa/sallsdk/api/sa.h:#define SA_SASDEV_IS_SATA_DEVICE(sasDev) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_IDFRM_PUT_SAS_ADDRESSLO(identFrame, src32) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_IDFRM_PUT_SAS_ADDRESSHI(identFrame, src32) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_REPORT_GENERAL_IS_CONFIGURING(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_REPORT_GENERAL_IS_CONFIGURABLE(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_GET_LINKRATE(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_SSP_INITIATOR(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_STP_INITIATOR(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_SMP_INITIATOR(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_SATA_HOST(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_SSP_TARGET(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_STP_TARGET(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_SMP_TARGET(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_SATA_DEVICE(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_SATA_PORTSELECTOR(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_GET_SAS_ADDRESSHI(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_GET_SAS_ADDRESSLO(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_IS_VIRTUALPHY(pResp) \ dev/pms/RefTisa/sallsdk/api/sa_spec.h:#define SA_DISCRSP_GET_ROUTINGATTRIB(pResp) \ dev/pms/RefTisa/sallsdk/spc/sadefs.h:#define NUM_MEM_CHUNKS(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q/rem+1) : (bit32)(Q/rem)) dev/pms/RefTisa/sallsdk/spc/sadefs.h:#define NUM_QUEUES_IN_MEM(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q%rem) : (bit32)(MAX_QUEUE_EACH_MEM)) dev/pms/RefTisa/sallsdk/spc/sahwreg.h:#define SPC_WRITE_RESET_REG(value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, value); dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c:#define LEFT_BYTE_FAIL(x, v) \ dev/pms/RefTisa/sallsdk/spc/sallist.h:#define saLlistIOGetNext(pList, pLink) (((pLink)->pNext == (pList)->pHead) ? \ dev/pms/RefTisa/sallsdk/spc/sallist.h:#define agObjectBase(baseType,fieldName,fieldPtr) \ dev/pms/RefTisa/sallsdk/spc/spcdefs.h:#define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) /* for SPCV */ dev/pms/RefTisa/sat/src/smdefs.h:#define SM_SET_ESGL_EXTEND(val) \ dev/pms/RefTisa/sat/src/smdefs.h:#define SMIsSPCv(agr) (VEN_DEV_SPCv == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv */ dev/pms/RefTisa/sat/src/smdefs.h:#define SMIsSPCve(agr) (VEN_DEV_SPCve == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve */ dev/pms/RefTisa/sat/src/smdefs.h:#define SMIsSPCvplus(agr) (VEN_DEV_SPCvplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCv+ */ dev/pms/RefTisa/sat/src/smdefs.h:#define SMIsSPCveplus(agr) (VEN_DEV_SPCveplus == ossaHwRegReadConfig32(agr,0 ) ? 1 : 0) /* returns true config space read is SPCve+ */ dev/pms/RefTisa/sat/src/smlist.h:#define SMLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr) \ dev/pms/RefTisa/sat/src/smlist.h:#define SMLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr) \ dev/pms/RefTisa/sat/src/smlist.h:#define SMLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr) \ dev/pms/RefTisa/tisa/sassata/common/tddefs.h:#define TD_GET_PHY_NUMS(input) ((input & 0xF0) >> 4) dev/pms/RefTisa/tisa/sassata/common/tdlist.h:#define TDLIST_NEXT_ENTRY(ptr, type, member) \ dev/pms/RefTisa/tisa/sassata/common/tdlist.h:#define TDLIST_DEQUEUE_FROM_TAIL(atTailHdr,listHdr) \ dev/pms/RefTisa/tisa/sassata/common/tdlist.h:#define TDLIST_ENQUEUE_LIST_AT_TAIL(toAddListHdr, listHdr) \ dev/pms/RefTisa/tisa/sassata/common/tdlist.h:#define TDLIST_ENQUEUE_LIST_AT_HEAD(toAddListHdr, listHdr) \ dev/pms/RefTisa/tisa/sassata/common/tdsatypes.h:#define TD_GET_TIINI_CONTEXT(ti_root) ((itdsaIni_t *)TD_GET_TICONTEXT(ti_root)->itdsaIni) dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h:#define TD_XCHG_CONTEXT_MAX_NUM_XCHGS(ti_root) (TD_XCHG_CONTEXT(ti_root)->maxNumXchgs) dev/pms/RefTisa/tisa/sassata/sas/tgt/ttdglobl.h:#define TD_XCHG_GET_CONTEXT(ti_request) ((ttdsaXchg_t *)(ti_request)->tdData) dev/pms/freebsd/driver/common/lxcommon.h:#define AG_PCI_DEV_INFO(pdev) ( \ dev/pms/freebsd/driver/common/osdebug.h:#define AG_ERROR_MSG(mask, val, format) \ dev/pms/freebsd/driver/common/osstring.h:#define osti_strcat(des, src) strcat((char *)des, (char *)src) dev/pms/freebsd/driver/common/osstring.h:#define osti_strchr(s, n) strchr((char *)s, (int)n) dev/pms/freebsd/driver/common/osstring.h:#define osti_strcmp(s1, s2) strcmp((char *)s1, (char *)s2) dev/pms/freebsd/driver/common/osstring.h:#define osti_strlen(s) strlen((char *)s) dev/pms/freebsd/driver/common/osstring.h:#define osti_strstr(s1, s2) strstr((char *)s1, (char *)s2) dev/pms/freebsd/driver/common/osstring.h:#define osti_isxdigit(c) isxdigit(c) dev/pms/freebsd/driver/common/osstring.h:#define osti_isdigit(c) isdigit(c) dev/pms/freebsd/driver/common/osstring.h:#define osti_islower(c) islower(c) dev/pms/freebsd/driver/common/osstring.h:#define osMemCpy(des, src, n) memcpy((void *)des, (void *)src, (size_t)n) dev/pms/freebsd/driver/common/osstring.h:#define osMemSet(s, c, n) memset((void *)s, (int)c, (size_t)n) dev/pms/freebsd/driver/ini/src/agtiapi.c:#define PMCoffsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) dev/pms/freebsd/driver/ini/src/agtiapi.c:#define AGTIAPI_WWNPRINTK(name, len, format, a...) \ dev/pms/freebsd/driver/ini/src/agtiapi.c:#define AGTIAPI_ERR_WWNPRINTK(name, len, format, a...) \ dev/pms/freebsd/driver/ini/src/agtiapi.c:#define AGTIAPI_CPY_DEV_INFO(root, dev, pDev) \ dev/pms/freebsd/driver/ini/src/agtiapi.c:#define AG_SPIN_LOCK(lock) dev/pms/freebsd/driver/ini/src/agtiapi.c:#define AG_PERF_SPINLOCK_IRQ(lock, flags) dev/pms/freebsd/driver/ini/src/agtiapi.c:#define AG_LOCAL_FLAGS(_flags) unsigned long _flags = 0 dev/ppbus/ppb_msq.h:#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ (reg) }, { (assert) }, { (clear) }}} dev/ppbus/ppb_msq.h:#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ (reg) }, { MS_ASSERT_NONE }, { (clear) }}} dev/ppbus/ppb_msq.h:#define MS_SASS(byte) MS_RASSERT(MS_REG_STR,byte) dev/ppbus/ppb_msq.h:#define MS_BRSTAT(mask_set,mask_clr,offset) \ dev/ppbus/ppb_msq.h:#define MS_ADELAY(mdelay) { MS_OP_ADELAY, {{ (mdelay) }}} dev/ppbus/ppb_msq.h:#define MS_SUBRET(code) { MS_OP_SUBRET, {{ (code) }}} dev/ppbus/ppbio.h:#define ppb_outsb_epp(dev,buf,cnt) \ dev/ppbus/ppbio.h:#define ppb_outsw_epp(dev,buf,cnt) \ dev/ppbus/ppbio.h:#define ppb_outsl_epp(dev,buf,cnt) \ dev/ppbus/ppbio.h:#define ppb_insb_epp(dev,buf,cnt) \ dev/ppbus/ppbio.h:#define ppb_insw_epp(dev,buf,cnt) \ dev/ppbus/ppbio.h:#define ppb_insl_epp(dev,buf,cnt) \ dev/ppc/ppcreg.h:#define r_cnfgB(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGB)) dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_VALLOC(dev, size) qlnx_zalloc(size) dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_LIST_INSERT_ENTRY_AFTER(entry, entry_prev, list) \ dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_LIST_SPLICE_TAIL_INIT(new_list, list) \ dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_BAR_SIZE(dev, bar_id) qlnx_pci_bus_get_bar_size(dev, bar_id) dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_PCI_READ_CONFIG_BYTE(dev, reg, value) \ dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_PCI_READ_CONFIG_DWORD(dev, reg, value) \ dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_PCI_WRITE_CONFIG_BYTE(dev, reg, value) \ dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_PCI_WRITE_CONFIG_DWORD(dev, reg, value) \ dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_SMP_MB(dev) mb() dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_RMB(dev) rmb() dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_NUM_ACTIVE_CPU() mp_ncpus dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_GET_RDMA_SB_ID(p_hwfn, cnq_id) ecore_rdma_get_sb_id(p_hwfn, cnq_id) dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_SPIN_LOCK_IRQSAVE(x,y) {y=0; mtx_lock(x);} dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_SPIN_UNLOCK_IRQSAVE(x,y) {y= 0; mtx_unlock(x);} dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_VF_FILL_ACQUIRE_RESC_REQ(p_hwfn, req, vf_sw_info) {}; dev/qlnx/qlnxe/bcm_osal.h:#define OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(p_hwfn, res) (0) dev/qlnx/qlnxe/ecore.h:#define ECORE_IS_IWARP_PERSONALITY(dev) \ dev/qlnx/qlnxe/ecore.h:#define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \ dev/qlnx/qlnxe/ecore_chain.h:#define is_unusable_next_idx(p, idx) \ dev/qlnx/qlnxe/ecore_iov_api.h:#define IS_PF_SRIOV_ALLOC(p_hwfn) (!!((p_hwfn)->pf_iov_info)) dev/qlnx/qlnxe/ecore_iov_api.h:#define IS_PF_PDA(p_hwfn) 0 /* @@TBD Michalk */ dev/qlnx/qlnxe/ecore_iov_api.h:#define ecore_for_each_vf(_p_hwfn, _i) \ dev/qlnx/qlnxe/ecore_sriov.h:#define ECORE_VF_ABS_ID(p_hwfn, p_vf) (ECORE_PATH_ID(p_hwfn) ? \ dev/qlnx/qlnxe/ecore_utils.h:#define PTR_LO(x) ((u32)(((osal_uintptr_t)(x)) & 0xffffffff)) dev/qlnx/qlnxe/ecore_utils.h:#define PTR_HI(x) ((u32)((((osal_uintptr_t)(x)) >> 16) >> 16)) dev/qlnx/qlnxe/mcp_public.h:#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id*32 + aeu_bit) dev/qlnx/qlnxe/mcp_public.h:#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) dev/qlnx/qlnxe/mcp_public.h:#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) dev/qlnx/qlnxe/mcp_public.h:#define MFW_DRV_UPDATE(shmem_func, msg_id) (u8)((u8*)(MFW_MB_P(shmem_func)->msg))[msg_id]++; dev/qlnx/qlnxe/nvm_map.h:#define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \ dev/qlnx/qlnxe/nvm_map.h:#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK) dev/qlnx/qlnxe/nvm_map.h:#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE) dev/qlnx/qlnxe/nvm_map.h:#define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0)) dev/qlnx/qlnxe/nvm_map.h:#define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + MIM_MAX_SIZE(is_asic)*2) dev/qlnx/qlnxe/pcics_reg_driver.h:#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ dev/qlnx/qlnxe/qlnx_def.h:#define BD_UNMAP_ADDR(bd) HILO_U64(le32toh((bd)->addr.hi), \ dev/qlnx/qlnxe/qlnx_def.h:#define BD_UNMAP_LEN(bd) (le16toh((bd)->nbytes)) dev/qlnx/qlnxe/qlnx_def.h:#define QLNX_MAX_TSS_CNT(ha) ((ha->num_rss) * (ha->num_tc)) dev/qlnx/qlnxe/spad_layout.h:#define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE)) dev/qlnx/qlnxe/spad_layout.h:#define TO_OFFSIZE(_offset, _size) \ dev/qlnx/qlnxe/spad_layout.h:#define NVM_GLOB_VAL(n, m, o) ((NVM_GLOB(n) & m) >> o) dev/qlxgb/qla_hw.h:#define QL_CLEAR_INTERRUPTS(ha) \ dev/qlxgb/qla_os.h:#define QLA_RX_LOCK(ha) mtx_lock(&ha->rx_lock); dev/qlxgb/qla_os.h:#define QLA_RX_UNLOCK(ha) mtx_unlock(&ha->rx_lock); dev/qlxgb/qla_os.h:#define QLA_RXJ_LOCK(ha) mtx_lock(&ha->rxj_lock); dev/qlxgb/qla_os.h:#define QLA_RXJ_UNLOCK(ha) mtx_unlock(&ha->rxj_lock); dev/rl/if_rlreg.h:#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) dev/rl/if_rlreg.h:#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ dev/rl/if_rlreg.h:#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) dev/rl/if_rlreg.h:#define RL_PKTSZ(x) ((x)/* >> 3*/) dev/rp/rp.c:#define RP_ISMULTIPORT(dev) ((dev)->id_flags & 0x1) dev/rp/rp.c:#define RP_MPMASTER(dev) (((dev)->id_flags >> 8) & 0xff) dev/rp/rpreg.h:#define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0) dev/rp/rpvar.h:#define RP_UNIT(x) dv_unit(x) dev/rp/rpvar.h:#define RP_PORT(x) (dev2unit(x) & 0x3f) dev/rt/if_rt.c:#define RT_MS(_v, _f) (((_v) & _f) >> _f##_S) dev/rt/if_rt.c:#define RT_SM(_v, _f) (((_v) << _f##_S) & _f) dev/rtwn/if_rtwn_ridx.h:#define RTWN_RATE_IS_OFDM(rate) \ dev/safe/safevar.h:#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) dev/sdhci/sdhci.c:#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); dev/sec/sec.h:#define SEC_PUT_GENERIC(sc, tab, cnt, wrap, val) \ dev/sf/if_sfreg.h:#define SF_TX_DLIST_ADDR(sc, i) \ dev/sf/if_sfreg.h:#define SF_TX_CLIST_ADDR(sc, i) \ dev/sf/if_sfreg.h:#define SF_RX_DLIST_ADDR(sc, i) \ dev/sf/if_sfreg.h:#define SF_RX_CLIST_ADDR(sc, i) \ dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_PORT_MAC(port) (0x00020000 + (port)) dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type)) dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf)) dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf)) dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf)) dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_PFIOV(port) (0x10170000 + (port)) dev/sfxge/common/ef10_tlv_layout.h:#define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf)) dev/sfxge/common/efsys.h:#define __in_ecount_opt(_n) dev/sfxge/common/efsys.h:#define __in_bcount_opt(_n) dev/sfxge/common/efsys.h:#define __inout_bcount_opt(_n) dev/sfxge/common/efsys.h:#define __inout_bcount_full_opt(_n) dev/sfxge/common/efsys.h:#define EFSYS_MEM_ZERO(_esmp, _size) \ dev/sfxge/common/efsys.h:#define EFSYS_TIMESTAMP(_usp) \ dev/sfxge/common/efsys.h:#define SFXGE_EFSYS_LOCK_ASSERT_OWNED(_eslp) \ dev/sfxge/common/efsys.h:#define EFSYS_STAT_DECR(_knp, _delta) \ dev/sfxge/common/efsys.h:#define EFSYS_STAT_SET(_knp, _val) \ dev/sfxge/common/efx.h:#define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ dev/sfxge/common/efx.h:#define EFX_PCI_FUNCTION(_encp) \ dev/sfxge/common/efx.h:#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) dev/sfxge/common/efx_impl.h:#define EFX_BAR_READQ(_enp, _reg, _eqp) \ dev/sfxge/common/efx_impl.h:#define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ dev/sfxge/common/efx_mcdi.h:#define MCDI_OUT_BYTE(_emr, _ofst) \ dev/sfxge/common/efx_mcdi.h:#define MCDI_CMD_DWORD_FIELD(_edp, _field) \ dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ dev/sfxge/common/efx_regs_mcdi.h:#define EVB_STACK_ID(n) (((n) & 0xff) << 16) dev/sfxge/common/efx_regs_mcdi.h:#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_UART_SEND_DATA_OUT_LEN(num) (16+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_UART_RECV_DATA_IN_LEN(num) (16+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_XPM_WRITE_BYTES_IN_LEN(num) (8+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_XPM_WRITE_SECTOR_IN_LEN(num) (12+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_LEN(num) (0+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LEN(num) (4+2*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LEN(num) (0+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_TSA_BIND_IN_SET_KEY_LEN(num) (4+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_TSA_BIND_OUT_GET_TICKET_LEN(num) (4+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LEN(num) (4+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LEN(num) (8+1*(num)) dev/sfxge/common/efx_regs_mcdi.h:#define MC_CMD_XPM_VERIFY_CONTENTS_OUT_LEN(num) (12+1*(num)) dev/sfxge/common/efx_types.h:#define EFX_BYTE_VAL(_byte) \ dev/sfxge/common/efx_types.h:#define EFX_WORD_VAL(_word) \ dev/sfxge/common/efx_types.h:#define EFX_DWORD_VAL(_dword) \ dev/sfxge/common/efx_types.h:#define EFX_QWORD_VAL(_qword) \ dev/sfxge/common/efx_types.h:#define EFX_OWORD_VAL(_oword) \ dev/sfxge/common/efx_types.h:#define EFX_DWORD_IS_EQUAL(_dword_a, _dword_b) \ dev/sfxge/common/efx_types.h:#define EFX_WORD_IS_EQUAL(_word_a, _word_b) \ dev/sfxge/common/efx_types.h:#define EFX_BYTE_IS_EQUAL(_byte_a, _byte_b) \ dev/sfxge/common/efx_types.h:#define EFX_DWORD_IS_ZERO(_dword) \ dev/sfxge/common/efx_types.h:#define EFX_WORD_IS_ZERO(_word) \ dev/sfxge/common/efx_types.h:#define EFX_BYTE_IS_ZERO(_byte) \ dev/sfxge/common/efx_types.h:#define EFX_DWORD_IS_SET(_dword) \ dev/sfxge/common/efx_types.h:#define EFX_WORD_IS_SET(_word) \ dev/sfxge/common/efx_types.h:#define EFX_BYTE_IS_SET(_byte) \ dev/sfxge/common/efx_types.h:#define EFX_SET_DWORD(_dword) \ dev/sfxge/common/efx_types.h:#define EFX_ZERO_WORD(_word) \ dev/sfxge/common/efx_types.h:#define EFX_SET_WORD(_word) \ dev/sfxge/common/efx_types.h:#define EFX_ZERO_BYTE(_byte) \ dev/sfxge/common/efx_types.h:#define EFX_SET_BYTE(_byte) \ dev/sfxge/common/efx_types.h:#define EFX_SET_WORD_FIELD(_word, _field, _value) \ dev/sfxge/common/efx_types.h:#define EFX_SET_BYTE_FIELD(_byte, _field, _value) \ dev/sfxge/common/efx_types.h:#define EFX_SET_DWORD_BIT(_dword, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_CLEAR_DWORD_BIT(_dword, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_TEST_DWORD_BIT(_dword, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_SET_WORD_BIT(_word, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_CLEAR_WORD_BIT(_word, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_TEST_WORD_BIT(_word, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_SET_BYTE_BIT(_byte, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_CLEAR_BYTE_BIT(_byte, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_TEST_BYTE_BIT(_byte, _bit) \ dev/sfxge/common/efx_types.h:#define EFX_OR_DWORD(_dword1, _dword2) \ dev/sfxge/common/efx_types.h:#define EFX_AND_DWORD(_dword1, _dword2) \ dev/sfxge/common/efx_types.h:#define EFX_OR_WORD(_word1, _word2) \ dev/sfxge/common/efx_types.h:#define EFX_AND_WORD(_word1, _word2) \ dev/sfxge/common/efx_types.h:#define EFX_OR_BYTE(_byte1, _byte2) \ dev/sfxge/common/efx_types.h:#define EFX_AND_BYTE(_byte1, _byte2) \ dev/sfxge/sfxge.h:#define SFXGE_MCDI_LOCK_ASSERT_OWNED(_mcdi) \ dev/sfxge/sfxge_rx.c:#define SFXGE_LRO_CONN_IS_VLAN_ENCAP(c) ((c)->l2_id & SFXGE_LRO_L2_ID_VLAN) dev/siis/siis.h:#define SIIS_GCTL_PIE(n) (1 << (n)) /* Port int enable */ dev/sio/sio.c:#define COM_NOPROBE(flags) ((flags) & 0x40000) dev/sis/if_sisreg.h:#define SIS_ADDR_HI(x) ((uint64_t) (x) >> 32) dev/sk/if_sk.c:#define SK_SETBIT(sc, reg, x) \ dev/sk/if_sk.c:#define SK_CLRBIT(sc, reg, x) \ dev/sk/if_skreg.h:#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE) dev/smbus/smbconf.h:#define smbus_trans(bus,slave,cmd,op,wbuf,wcount,rbuf,rcount,actualp) \ dev/sn/if_snvar.h:#define SN_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); dev/sound/isa/mss.h:#define PMIX_ENT(name, reg_l, pos_l, len_l, reg_r, pos_r, len_r) \ dev/sound/isa/mss.h:#define io_Polled_IO(d) ((d)->io_base+3+4) dev/sound/isa/sb.h:#define DSP_CMD_DMAMODE(stereo, bit16) (0xA0 | (stereo ? 8:0) | (bit16 ? 4:0)) dev/sound/isa/sb.h:#define DSP_CMD_SPKR(on) (0xD1 | (on ? 0:2)) dev/sound/midi/midiq.h:#define MIDIQ_PEEK(head, buf, size) MIDIQ_DEQ_I(head, buf, size, 1, 0) dev/sound/midi/midiq.h:#define MIDIQ_POP(head, size) MIDIQ_DEQ_I(head, &head, size, 0, 1) dev/sound/midi/sequencer.c:#define MIDIUNIT(y) ((dev2unit(y) >> 4) & 0x0f) dev/sound/pci/allegro_reg.h:#define NUM_UNITS( BYTES, UNITLEN ) ((((BYTES+1)>>1) + (UNITLEN-1)) / UNITLEN) dev/sound/pci/atiixp.c:#define atiixp_assert(_sc) snd_mtxassert((_sc)->lock) dev/sound/pci/emuxkireg.h:#define EMU_RECIDX(idxreg) (0x10000000|(idxreg)) dev/sound/pci/emuxkireg.h:#define EMU_DSP_FX(num) (num) dev/sound/pci/emuxkireg.h:#define EMU_DSP_INL(num) (EMU_DSP_IOL(EMU_DSP_INL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_DSP_INR(num) (EMU_DSP_IOR(EMU_DSP_INL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_A_DSP_INL(num) (EMU_DSP_IOL(EMU_A_DSP_INL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_A_DSP_INR(num) (EMU_DSP_IOR(EMU_A_DSP_INL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_DSP_OUTL(num) (EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_DSP_OUTR(num) (EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_A_DSP_OUTL(num) (EMU_DSP_IOL(EMU_A_DSP_OUTL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_A_DSP_OUTR(num) (EMU_DSP_IOR(EMU_A_DSP_OUTL_BASE, num)) dev/sound/pci/emuxkireg.h:#define EMU_DSP_CST(num) (EMU_DSP_CST_BASE + num) dev/sound/pci/emuxkireg.h:#define EMU_A_DSP_CST(num) (EMU_A_DSP_CST_BASE + num) dev/sound/pci/emuxkireg.h:#define EMU_DSP_GPR(num) (EMU_FXGPREGBASE + num) dev/sound/pci/emuxkireg.h:#define EMU_A_DSP_GPR(num) (EMU_A_FXGPREGBASE + num) dev/sound/pci/es137x.c:#define ES_NUMREC(cfgv) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_CONN_SELECT_CONTROL(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_PROCESSING_STATE(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_PROCESSING_STATE(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_COEFF_INDEX(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_AMP_GAIN_MUTE(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX(index) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN(index) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_CONV_FMT(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_L(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_V(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_POWER_STATE(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_POWER_STATE_ACT(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_POWER_STATE_SET(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_POWER_STATE_ACT(ps) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_POWER_STATE_SET(ps) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_CONV_STREAM_CHAN(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_CONV_STREAM_CHAN_STREAM(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_CONV_STREAM_CHAN_CHAN(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_CONV_STREAM_CHAN_STREAM(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_CONV_STREAM_CHAN_CHAN(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_INPUT_CONVERTER_SDI_SELECT(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_INPUT_CONVERTER_SDI_SELECT(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_UNSOLICITED_RESPONSE(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL(rsp) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_GPI_DATA(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_GPI_WAKE_ENABLE_MASK(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_GPI_STICKY_MASK(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_GPIO_WAKE_ENABLE_MASK(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_GPIO_STICKY_MASK(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_BEEP_GENERATION(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_BEEP_GENERATION(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_VOLUME_KNOB(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_SET_VOLUME_KNOB(cad, nid, payload) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_CONV_CHAN_COUNT(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_HDMI_DIP_INDEX(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_HDMI_DIP_DATA(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_HDMI_DIP_XMIT(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_GET_HDMI_CHAN_SLOT(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_CMD_FUNCTION_RESET(cad, nid) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_REVISION_ID_MAJREV(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_REVISION_ID_MINREV(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_FCT_GRP_TYPE_UNSOL(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_AUDIO_WIDGET_CAP_CP(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_INPUT_AMP_CAP_OFFSET(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_PROCESSING_CAP_BENIGN(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA(param) \ dev/sound/pci/hda/hda_reg.h:#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS(param) \ dev/sound/pci/hda/hdaa.c:#define hdaa_lockassert(devinfo) snd_mtxassert((devinfo)->lock) dev/sound/pci/hda/hdaa.c:#define hdaa_lockowned(devinfo) mtx_owned((devinfo)->lock) dev/sound/pci/hda/hdaa.h:#define HDAA_GPIO_KEEP(n) (0x0 << (n * 3)) dev/sound/pci/hda/hdaa.h:#define RANGEQDB(ctl) \ dev/sound/pci/hda/hdac.c:#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) dev/sound/pci/hda/hdac.c:#define hdac_command(a1, a2, a3) \ dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_private.h:#define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss)) dev/sound/pci/hda/hdac_reg.h:#define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss)) dev/sound/pci/hda/hdac_reg.h:#define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss)) dev/sound/pci/hda/hdac_reg.h:#define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss)) dev/sound/pci/hda/hdacc.c:#define hdacc_lockassert(codec) snd_mtxassert((codec)->lock) dev/sound/pci/hda/hdacc.c:#define hdacc_lockowned(codec) mtx_owned((codec)->lock) dev/sound/pci/ich.c:#define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock) dev/sound/pci/vibes.h:#define SV_LOOPBACK_LEVEL(x) ((x) << 2) dev/sound/pci/vibes.h:#define SV_SYNTH_PLLN(x) ((x) & 0x1f) dev/sound/pci/vibes.h:#define SV_SYNTH_PLLR(x) ((x) << 5) dev/sound/pcm/channel.h:#define PCM_SG_TRYLOCK() mtx_trylock(&snd_pcm_syncgroups_mtx) dev/sound/pcm/channel.h:#define CHN_INSERT_HEAD_SAFE(x, y, z) do { \ dev/sound/pcm/channel.h:#define CHN_INSERT_AFTER_SAFE(w, x, y, z) do { \ dev/sound/pcm/channel.h:#define CHN_REMOVE_SAFE(x, y, z) do { \ dev/sound/pcm/channel.h:#define CHN_UNIT(x) (snd_unit2u((x)->unit)) dev/sound/pcm/channel.h:#define CHN_PASSTHROUGH(c) ((c)->flags & CHN_F_PASSTHROUGH) dev/sound/pcm/dsp.c:#define DSP_F_SIMPLEX(x) (!DSP_F_DUPLEX(x)) dev/sound/pcm/feeder.h:#define FEEDMATRIX_MAP(x, y) ((((x) & 0x3f) << 6) | ((y) & 0x3f)) dev/sound/pcm/feeder.h:#define FEEDMATRIX_MAP_SRC(x) ((x) & 0x3f) dev/sound/pcm/feeder.h:#define FEEDMATRIX_MAP_DST(x) (((x) >> 6) & 0x3f) dev/sound/pcm/feeder_rate.c:#define Z_IS_ZOH(i) ((i)->quality == Z_QUALITY_ZOH) dev/sound/pcm/sound.h:#define PCMCHAN(x) (snd_unit2c(dev2unit(x))) dev/sound/pcm/sound.h:#define PCM_TRYLOCK(d) mtx_trylock((d)->lock) dev/speaker/spkr.c:#define dtoi(c) ((c) - '0') dev/ste/if_stereg.h:#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32) dev/ste/if_stereg.h:#define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y) dev/ste/if_stereg.h:#define STE_NEXT(x, y) (x + 1) % y dev/stge/if_stgereg.h:#define TFD_UserPriority(x) (((uint64_t)(x)) << 45) dev/stge/if_stgereg.h:#define RDIC_PriorityThresh(x) ((x) << 10) dev/stge/if_stgereg.h:#define CD_Count(x) ((x) & 0xffff) dev/stge/if_stgereg.h:#define TS_TxFrameId_get(x) ((x) >> 16) dev/sym/sym_defs.h:#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) dev/sym/sym_defs.h:#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) dev/sym/sym_defs.h:#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) dev/sym/sym_defs.h:#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) dev/sym/sym_defs.h:#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) dev/sym/sym_hipd.c:#define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink) dev/sym/sym_hipd.c:#define sym_offb(o) (o) dev/sym/sym_hipd.c:#define sym_offw(o) (o) dev/syscons/syscons.h:#define ISPIXELSC(scp) (((scp)->status \ dev/tdfx/tdfx_io.h:#define _IOV(type,nr) _IOCV(_IOC_NONE,(type),(nr),0) dev/tdfx/tdfx_io.h:#define _IORV(type,nr,size) _IOCV(_IOC_READ,(type),(nr),sizeof(size)) dev/tdfx/tdfx_io.h:#define _IOWV(type,nr,size) _IOCV(_IOC_WRITE,(type),(nr),sizeof(size)) dev/tdfx/tdfx_io.h:#define _IOWRV(type,nr,size) _IOCV(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) dev/terasic/mtl/terasic_mtl.h:#define TERASIC_MTL_LOCK_ASSERT(sc) mtx_assert(&(sc)->mtl_lock, MA_OWNED) dev/ti/if_tireg.h:#define TI_CMD_CMD(cmd) (((((cmd)->ti_cmdx)) >> 24) & 0xff) dev/ti/if_tireg.h:#define TI_CMD_CODE(cmd) (((((cmd)->ti_cmdx)) >> 12) & 0xfff) dev/ti/if_tireg.h:#define TI_CMD_IDX(cmd) ((((cmd)->ti_cmdx)) & 0xfff) dev/ti/if_tireg.h:#define TI_EVENT_IDX(e) (((((e)->ti_eventx))) & 0xfff) dev/tsec/if_tsec.h:#define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \ dev/tsec/if_tsec.h:#define TSEC_IC_LOCK_ASSERT(sc) mtx_assert(&(sc)->ic_lock, MA_OWNED) dev/tsec/if_tsec.h:#define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \ dev/tsec/if_tsecreg.h:#define TSEC_REG_IADDR(n) (TSEC_REG_IADDR0 + (n << 2)) dev/twa/tw_cl_fwif.h:#define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value) do { \ dev/twa/tw_cl_fwif.h:#define TW_CLI_STATUS_ERRORS(x) \ dev/twa/tw_cl_fwif.h:#define BUILD_RES__SEVERITY(res, severity) \ dev/twa/tw_cl_fwif.h:#define GET_HOST_ID(host_id__unit) \ dev/twa/tw_cl_share.h:#define TW_CL_Q_LAST_ITEM(head) \ dev/twa/tw_cl_share.h:#define TW_CL_Q_NEXT_ITEM(head, item) \ dev/twa/tw_cl_share.h:#define TW_CL_Q_PREV_ITEM(head, item) \ dev/tx/if_txreg.h:#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) dev/uart/uart.h:#define UART_FLAGS_FCR_RX_MEDH(f) ((f) & 0x400) dev/uart/uart_dev_msm.h:#define UART_DM_TXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6) dev/uart/uart_dev_msm.h:#define UART_DM_TXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31) dev/uart/uart_dev_msm.h:#define UART_DM_TXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9) dev/uart/uart_dev_msm.h:#define UART_DM_TXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13) dev/uart/uart_dev_msm.h:#define UART_DM_RXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6) dev/uart/uart_dev_msm.h:#define UART_DM_RXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31) dev/uart/uart_dev_msm.h:#define UART_DM_RXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9) dev/uart/uart_dev_msm.h:#define UART_DM_RXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13) dev/ubsec/ubsecreg.h:#define UBS_PCI_RTY(misc) \ dev/ubsec/ubsecreg.h:#define UBS_PCI_TOUT(misc) \ dev/ubsec/ubsecvar.h:#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) dev/usb/controller/atmegadci.h:#define ATMEGA_OTGTCON_VALUE(x) ((x) << 0) dev/usb/controller/atmegadci.h:#define ATMEGA_OTGTCON_PAGE(x) ((x) << 5) dev/usb/controller/atmegadci.h:#define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */ dev/usb/controller/dwc_otgreg.h:#define DOTG_DPTXFSIZ(fifo) (0x0100 + (4*(fifo))) dev/usb/controller/dwc_otgreg.h:#define DOTG_HCDMA(ch) (0x0514 + (32*(ch))) dev/usb/controller/dwc_otgreg.h:#define DOTG_HCDMAI(ch) (0x0514 + (32*(ch))) dev/usb/controller/dwc_otgreg.h:#define DOTG_HCDMAO(ch) (0x0514 + (32*(ch))) dev/usb/controller/dwc_otgreg.h:#define DOTG_HCDMAB(ch) (0x051C + (32*(ch))) dev/usb/controller/dwc_otgreg.h:#define DOTG_DIEPDMA(ep) (0x0914 + (32*(ep))) dev/usb/controller/dwc_otgreg.h:#define DOTG_DTXFSTS(ep) (0x0918 + (32*(ep))) dev/usb/controller/dwc_otgreg.h:#define DOTG_DIEPDMAB(ep) (0x091c + (32*(ep))) dev/usb/controller/dwc_otgreg.h:#define DOTG_DOEPFN(ep) (0x0B04 + (32*(ep))) dev/usb/controller/dwc_otgreg.h:#define DOTG_DOEPINT(ep) (0x0B08 + (32*(ep))) dev/usb/controller/dwc_otgreg.h:#define DOTG_DOEPDMA(ep) (0x0B14 + (32*(ep))) dev/usb/controller/dwc_otgreg.h:#define DOTG_DOEPDMAB(ep) (0x0B1c + (32*(ep))) dev/usb/controller/dwc_otgreg.h:#define GRXSTSRD_FN_GET(x) (((x) >> 21) & 15) dev/usb/controller/dwc_otgreg.h:#define DCFG_DEVSPD_SET(x) ((x) & 0x3) dev/usb/controller/dwc_otgreg.h:#define DOEPCTL_FNUM_SET(n) (((n) & 15) << 22) dev/usb/controller/dwc_otgreg.h:#define DOEPCTL_EPTYPE_SET(n) (((n) & 3) << 18) dev/usb/controller/dwc_otgreg.h:#define DOEPCTL_MPS_SET(n) ((n) & 0x7FF) dev/usb/controller/dwc_otgreg.h:#define DXEPTSIZ_GET_NBYTES(n) (((n) >> 0) & 0x7FFFFF) dev/usb/controller/dwc_otgreg.h:#define ENDPOINT_MASK(x,in) \ dev/usb/controller/ehci.h:#define EHCI_LINK_ADDR(x) ((x) &~ 0x1f) dev/usb/controller/ehci.h:#define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7) dev/usb/controller/ehci.h:#define EHCI_ITD_SET_OFFS(x) (x) dev/usb/controller/ehci.h:#define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xFFF) dev/usb/controller/ehci.h:#define EHCI_SITD_GET_DIR(x) ((x) >> 31) dev/usb/controller/ehci.h:#define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff) dev/usb/controller/ehci.h:#define EHCI_QTD_SET_STATUS(x) ((x) << 0) dev/usb/controller/ehci.h:#define EHCI_QTD_SET_C_PAGE(x) ((x) << 12) dev/usb/controller/ehcireg.h:#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) dev/usb/controller/ehcireg.h:#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ dev/usb/controller/ehcireg.h:#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ dev/usb/controller/ehcireg.h:#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ dev/usb/controller/ehcireg.h:#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ dev/usb/controller/ehcireg.h:#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ dev/usb/controller/ohci.h:#define OHCI_TD_SET_CC(x) ((x) << 28) dev/usb/controller/ohci.h:#define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) /* Transfer length */ dev/usb/controller/ohci.h:#define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) /* Condition Code */ dev/usb/controller/ohcireg.h:#define OHCI_REV_LO(rev) ((rev) & 0xf) dev/usb/controller/ohcireg.h:#define OHCI_REV_HI(rev) (((rev)>>4) & 0xf) dev/usb/controller/ohcireg.h:#define OHCI_REV_LEGACY(rev) ((rev) & 0x100) dev/usb/controller/ohcireg.h:#define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_VEND_ID(x) ((x) & 0xFFFF) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_PROD_ID(x) (((x) >> 16) & 0xFFFF) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_IRQ_LATCH_SET(x) ((x) & 0xFFFF) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_IRQ_LATCH_CLR(x) (((x) << 16) & 0xFFFF0000) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_IRQ_RISE_SET(x) ((x) & 0xFFFF) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_IRQ_RISE_CLR(x) (((x) << 16) & 0xFFFF0000) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_TIMER_LOW_SET(x) ((x) & 0xFFFF) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_TIMER_LOW_CLR(x) (((x) << 16) & 0xFFFF0000) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_TIMER_HIGH_SET(x) ((x) & 0xFFFF) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_TIMER_HIGH_CLR(x) (((x) << 16) & 0xFFFF0000) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_ASYNC_PTD(x) (0xC00 + ((x) * 32)) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_INTR_PTD(x) (0x800 + ((x) * 32)) dev/usb/controller/saf1761_otg_reg.h:#define SOTG_ISOC_PTD(x) (0x400 + ((x) * 32)) dev/usb/controller/uhci.c:#define UHCISTS(sc) UREAD2(sc, UHCI_STS) dev/usb/controller/uhci.h:#define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \ dev/usb/controller/xhcireg.h:#define XHCI_DNCTRL_MASK(n) (1U << (n)) dev/usb/controller/xhcireg.h:#define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ dev/usb/controller/xhcireg.h:#define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */ dev/usb/controller/xhcireg.h:#define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ dev/usb/controller/xhcireg.h:#define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */ dev/usb/controller/xhcireg.h:#define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */ dev/usb/controller/xhcireg.h:#define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */ dev/usb/controller/xhcireg.h:#define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */ dev/usb/controller/xhcireg.h:#define XHCI_ERSTS_GET(x) ((x) & 0xFFFF) dev/usb/controller/xhcireg.h:#define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */ dev/usb/controller/xhcireg.h:#define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */ dev/usb/controller/xhcireg.h:#define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */ dev/usb/controller/xhcireg.h:#define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */ dev/usb/net/if_cdcereg.h:#define CDCE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) dev/usb/net/if_cdcereg.h:#define CDCE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) dev/usb/net/if_cuereg.h:#define CUE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) dev/usb/net/if_cuereg.h:#define CUE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) dev/usb/net/if_iphethvar.h:#define IPHETH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) dev/usb/net/if_iphethvar.h:#define IPHETH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) dev/usb/net/if_kuereg.h:#define KUE_ETHERSTATS(x) UGETDW((x)->sc_desc.kue_etherstats) dev/usb/net/if_kuereg.h:#define KUE_MAXSEG(x) UGETW((x)->sc_desc.kue_maxseg) dev/usb/net/if_kuereg.h:#define KUE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) dev/usb/net/if_kuereg.h:#define KUE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) dev/usb/net/if_mosreg.h:#define MOS_INC(x, y) (x) = (x + 1) % y dev/usb/usb.h:#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7)) dev/usb/usb.h:#define UE_GET_ISO_USAGE(a) ((a) & UE_ISO_USAGE) dev/usb/usb_core.h:#define USB_BUS_SPIN_LOCK_ASSERT(_b, _t) USB_MTX_ASSERT(&(_b)->bus_spin_lock, _t) dev/usb/usb_endian.h:#define UGETB(w) \ dev/usb/usb_endian.h:#define UGETQW(w) \ dev/usb/usb_endian.h:#define USETB(w,v) do { \ dev/usb/usb_endian.h:#define USETQW(w,v) do { \ dev/usb/usb_hub.c:#define UHUB_IS_HIGH_SPEED(sc) (UHUB_PROTO(sc) != UDPROTO_FSHUB) dev/usb/usb_hub.c:#define UHUB_IS_SINGLE_TT(sc) (UHUB_PROTO(sc) == UDPROTO_HSHUBSTT) dev/usb/usb_hub.c:#define UHUB_IS_SUPER_SPEED(sc) (UHUB_PROTO(sc) == UDPROTO_SSHUB) dev/usb/usb_mbuf.h:#define USB_IF_QFULL(ifq) ((ifq)->ifq_len >= (ifq)->ifq_maxlen) dev/usb/usb_mbuf.h:#define USB_IF_QLEN(ifq) ((ifq)->ifq_len) dev/usb/usbdi.h:#define USB_DEV_BCD_GTEQ(lo) /* greater than or equal */ \ dev/usb/usbdi.h:#define USB_DEV_CLASS(dc) \ dev/usb/usbdi.h:#define USB_DEV_SUBCLASS(dsc) \ dev/usb/usbdi.h:#define USB_DEV_PROTOCOL(dp) \ dev/usb/usbdi.h:#define usb_callout_pending(c) callout_pending(&(c)->co) dev/usb/wlan/if_urtw.c:#define urtw_lookup(v, p) \ dev/usb/wlan/if_zydreg.h:#define ZYD_TX_PHY_SIGNAL(x) ((x) & 0xf) dev/videomode/edidreg.h:#define EDID_CHROMA_REDY(ptr) (_CHROMA(ptr, 25, 4, 28)) dev/videomode/edidreg.h:#define EDID_DET_TIMING_HSIZE(ptr) (_HSZ_LO(ptr) | _HSZ_HI(ptr)) dev/videomode/edidreg.h:#define EDID_DET_TIMING_VSIZE(ptr) (_VSZ_LO(ptr) | _VSZ_HI(ptr)) dev/videomode/edidreg.h:#define EDID_DET_TIMING_HBORDER(ptr) ((ptr)[15]) dev/videomode/edidreg.h:#define EDID_DET_TIMING_VBORDER(ptr) ((ptr)[16]) dev/videomode/edidreg.h:#define EDID_DESC_COLOR_WHITEX(ptr) dev/virtio/console/virtio_console.c:#define VTCON_LOCK_ASSERT_NOTOWNED(_sc) \ dev/virtio/network/if_vtnetvar.h:#define VTNET_RXQ_LOCK_ASSERT_NOTOWNED(_rxq) \ dev/virtio/network/if_vtnetvar.h:#define VTNET_TXQ_LOCK_ASSERT_NOTOWNED(_txq) \ dev/vnic/nicvf_queues.h:#define for_each_sq_irq(irq) \ dev/vnic/nicvf_queues.h:#define NICVF_ADDR_ALIGN_LEN(addr, bytes) \ dev/vnic/nicvf_queues.h:#define NICVF_RCV_BUF_ALIGN_LEN(addr) \ dev/vnic/thunder_bgx.h:#define RX_DMACX_CAM_LMACID(x) (x << 49) dev/vnic/thunder_mdio.c:#define MDIO_LOCK_DESTROY(sc) \ dev/vr/if_vrreg.h:#define VR_ADDR_HI(x) ((uint64_t)(x) >> 32) dev/vt/vt.h:#define VTBUF_GET_ROW(vb, r) \ dev/vt/vt.h:#define VTBUF_DIRTYROW(mask, row) \ dev/vt/vt.h:#define VTBUF_DIRTYCOL(mask, col) \ dev/vt/vt.h:#define IS_VT_PROC_MODE(vw) ((vw)->vw_smode.mode == VT_PROCESS) dev/vte/if_vtereg.h:#define VTE_RX_HIDX(x) ((x) & 0x3F) dev/vxge/include/vxge-list.h:#define vxge_list_for_each_prev_safe(_p, _n, _h) \ dev/vxge/include/vxgehal-config.h:#define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_DISABLE(vpid) 0 dev/vxge/include/vxgehal-config.h:#define VXGE_HAL_VPATH_TO_WIRE_PORT_MAP_EN_ENABLE(vpid) mBIT(vpid) dev/vxge/include/vxgehal-config.h:#define VXGE_HAL_TIM_UTIL_SEL_HOST_UTIL_VPATH(n) (32+n) dev/vxge/include/vxgehal-config.h:#define VXGE_HAL_TIM_UTIL_SEL_TIM_UTIL_VPATH(n) 63 dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_HOST_STEER_GET(ctrl0) bVAL2(ctrl0, 16) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_GATHER_CODE_GET(ctrl0) bVAL2(ctrl0, 22) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_GET(ctrl0) bVAL2(ctrl0, 28) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_LSO_FLAG_GET(ctrl0) bVAL1(ctrl0, 30) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_LSO_MSS_GET(ctrl0) bVAL14(ctrl0, 34) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_BUFFER_SIZE_GET(ctrl0) bVAL16(ctrl0, 48) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT(val) vBIT(val, 32, 32) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN_GET(ctrl1) bVAL1(ctrl1, 6) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN_GET(ctrl1) bVAL1(ctrl1, 7) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_VLAN_ENABLE_GET(ctrl1) bVAL1(ctrl1, 15) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 16) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_INT_NUMBER_GET(ctrl1) bVAL6(ctrl1, 34) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST_GET(ctrl1) bVAL1(ctrl1, 46) dev/vxge/include/vxgehal-ll.h:#define VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ_GET(ctrl1) bVAL1(ctrl1, 47) dev/vxge/include/vxgehal-mgmt.h:#define VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x) ((x) & 31) /* First Err Ptr */ dev/vxge/include/vxgehal-mgmt.h:#define VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x) ((x) >> 31) /* Error Hdr Log */ dev/vxge/include/vxgehal-stats.h:#define VXGE_HAL_STATS_LOC_VPATH(n) n dev/vxge/include/vxgehal-stats.h:#define VXGE_HAL_STATS_PORTn_TX_TTL_OCTETS_OFFSET(n) ((0x008+(608*n))>>3) dev/vxge/include/vxgehal-types.h:#define VXGE_HAL_OPAQUE_HANDLE_GET_VPATH_HANDLE(op) ((op)->vpath_handle) dev/vxge/include/vxgehal-types.h:#define VXGE_HAL_OPAQUE_HANDLE_VPATH_HANDLE(op, vrh) (op)->vpath_handle = vrh dev/vxge/include/vxgehal-types.h:#define VXGE_HAL_OPAQUE_HANDLE_GET_HAL_PRIV(op) ((op)->hal_priv) dev/vxge/include/vxgehal-types.h:#define VXGE_HAL_OPAQUE_HANDLE_HAL_PRIV(op, priv) (op)->hal_priv = (u64)priv dev/vxge/include/vxgehal-types.h:#define VXGE_HAL_OPAQUE_HANDLE_GET_CLIENT_PRIV(op) ((op)->client_priv) dev/vxge/include/vxgehal-types.h:#define VXGE_HAL_OPAQUE_HANDLE_CLIENT_PRIV(op, priv) \ dev/vxge/vxge-osdep.h:#define VXGE_LL_IP_FAST_CSUM(hdr, len) 0 dev/vxge/vxge-osdep.h:#define vxge_os_timestamp(buff) { \ dev/vxge/vxge-osdep.h:#define vxge_trace(trace, fmt, args...) \ dev/vxge/vxge-osdep.h:#define vxge_os_prefetchw(x) (x = x) dev/vxge/vxge.h:#define VXGE_MSIX_ALARM_ID(hldev, i) \ dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RXDCM_RESET_IN_PROGRESS_PRC_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RD_REQ_IN_PROGRESS_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RD_REQ_OUTSTANDING_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_KDFC_RESET_IN_PROGRESS_NOA_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_ONE_CFG_VP_RDY(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_TIM_INT_EN_TIM_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_TIM_MASK_INT_DURING_RESET_VPATH(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_TIM_RESET_IN_PROGRESS_TIM_VPATH(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_TIM_OUTSTANDING_BMAP_TIM_VPATH(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MSG_MXP_MR_READY_MP_BOOTED(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MSG_UXP_MR_READY_UP_BOOTED(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT(val)\ dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT(val)\ dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MASK_VECTOR_MASK_VECTOR(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC(val)\ dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_TITAN_ASIC_ID_INITIAL_DEVICE_ID(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION(val) vBIT(val, 48, 8) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_TITAN_ASIC_ID_INITIAL_MINOR_REVISION(val) vBIT(val, 56, 8) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RTI_INT_STATUS_RTI_INT_STATUS(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RTI_INT_MASK_RTI_INT_MASK(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_GEN_CTRL_SPI_NOT_USED(val) vBIT(val, 6, 4) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_OUTSTANDING_READ_OUTSTANDING_READ(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_QCC_RESET_IN_PROGRESS_QCC_VPATH(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_CP_RESET_IN_PROGRESS_CP_VPATH(n) mBIT(n) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_XGMAC_READY_XMACJ_READY(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_FBIF_READY_FAU_READY(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS(val)\ dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_DEBUG_ASSIGNMENTS_VHLABEL(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_DEBUG_ASSIGNMENTS_VPLANE(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_DEBUG_ASSIGNMENTS_FUNC(val) vBIT(val, 19, 5) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RTS_ACCESS_ICMP_EN(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RTS_ACCESS_TCPSYN_EN(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-common-reg.h:#define VXGE_HAL_RTS_ACCESS_IPFRAG_EN(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-device.h:#define VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) { \ dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_NODBW_GET_TYPE(ctrl0) bVAL8(ctrl0, 0) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_NODBW_GET_LAST_TXD_NUMBER(ctrl0) bVAL8(ctrl0, 32) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_NODBW_LIST_NO_SNOOP(val) vBIT(val, 56, 8) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_ODBW_GET_ENTRY_TYPE(ctrl1) bVAL8(ctrl1, 0) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_ODBW_ENTRY_TYPE(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_ODBW_GET_IMMEDIATE_BYTE_COUNT(ctrl1) bVAL8(ctrl1, 8) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_ODBW_IMMEDIATE_BYTE_COUNT(val) vBIT(val, 8, 8) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_MDBW_GET_TYPE(ctrl0) bVAL8(ctrl0, 0) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_MDBW_GET_MESSAGE_BYTE_COUNT(ctrl0) bVAL32(ctrl0, 32) dev/vxge/vxgehal/vxgehal-doorbells.h:#define VXGE_HAL_MDBW_GET_IMMEDIATE_BYTE_COUNT(ctrl1) bVAL8(ctrl1, 8) dev/vxge/vxgehal/vxgehal-fifo.h:#define VXGE_HAL_FIFO_MAX_FRAG_CNT(fifo) fifo->config->max_frags dev/vxge/vxgehal/vxgehal-legacy-reg.h:#define VXGE_HAL_TOC_SWAPPER_FB_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-legacy-reg.h:#define VXGE_HAL_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-legacy-reg.h:#define VXGE_HAL_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-legacy-reg.h:#define VXGE_HAL_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-legacy-reg.h:#define VXGE_HAL_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-legacy-reg.h:#define VXGE_HAL_TOC_FIRST_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-legacy-reg.h:#define VXGE_HAL_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RDA_ECC_SG_REG_RDA_RXD_ERR(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RC_CFG_RXD_ERR_MASK(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_QUEUE_SELECT_NUMBER(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) vBIT(val, 2, 30) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vBIT(val, 2, 10) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vBIT(val, 18, 14) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_WDE_PRM_CTRL_FB_ROW_SIZE(val) vBIT(val, 46, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NOA_CTRL_FRM_PRTY_QUOTA(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vBIT(val, 10, 22) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vBIT(val, 39, 9) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vBIT(val, 55, 9) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_KRNL_USR_CTRL_CODE(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PDA_MONITOR_TYPE(val) vBIT(val, 32, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PDA_MONITOR_VP(val) vBIT(val, 43, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_MP_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_MP_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_MP_MONITOR_TYPE(val) vBIT(val, 32, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_MP_MONITOR_VP(val) vBIT(val, 43, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PE_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PE_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PE_MONITOR_TYPE(val) vBIT(val, 32, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PE_MONITOR_VP(val) vBIT(val, 43, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_PE_MONITOR_IMM_DATA_CNT(val) vBIT(val, 48, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_READ_CNTRL_KDFC_RDCTRL(val) vBIT(val, 14, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_READ_CNTRL_KDFC_ADDR(val) vBIT(val, 49, 15) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFC_MULTI_CYCLE_CTRL_MULTI_CYCLE_SEL(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_AUTHORIZE_ALL_ADDR_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_AUTHORIZE_ALL_VID_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vBIT(val, 9, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vBIT(val, 5, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vBIT(val, 9, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vBIT(val, 21, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_DS(val) vBIT(val, 25, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vBIT(val, 29, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTS_MGR_STEER_VPATH_VECTOR_VPATH_VECTOR(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_TIMESTAMP_USE_LINK_ID(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_TIMESTAMP_INTERVAL(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vBIT(val, 8, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ASIC_NTWK_CFG_PORT_NUM_VP(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vBIT(val, 0, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) vBIT(val, 8, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) vBIT(val, 48, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vBIT(val, 37, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) vBIT(val, 41, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vBIT(val, 44, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vBIT(val, 24, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TRANSCEIVER_RESET_PORT_TCVR_RESET(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ASIC_GPIO_CTRL_XMACJ_GPIO_DATA_IN(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ASIC_GPIO_CTRL_GPIO_DATA_OUT(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ASIC_GPIO_CTRL_GPIO_OUT_EN(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_USDC_VPLANE_SGRP_OWN(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_USDC_CNTRL_MIN_VALUE(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_USDC_READ_CNTRL_USDC_RDCTRL(val) vBIT(val, 14, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_USDC_READ_CNTRL_USDC_ADDR(val) vBIT(val, 49, 15) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_USDC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LSO_ERROR_REG_PCC_LSO_ABORT(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_CXP(val) vBIT(val, 5, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_KDFC(val) vBIT(val, 21, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_MP(val) vBIT(val, 29, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_PE(val) vBIT(val, 37, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_QCC(val) vBIT(val, 45, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PCC_CFG_PCC_ENABLE(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PCC_CFG_PCC_ECC_ENABLE_N(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PCC_CONTROL_FE_ENABLE(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RTDMA_BW_TIMER_TIMER_CTRL(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vBIT(val, 8, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_QUEUE_CFG_INGRESS_FIFO_THR(val) vBIT(val, 60, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_QUEUE_SIZE_Q_SIZE(val) vBIT(val, 0, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_QUEUE_SIZE_Q_LAST_ADD(val) vBIT(val, 24, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_DEFINITION_FM_SIZE(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_DEFINITION_FM_COLUMNS(val) vBIT(val, 14, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_DEFINITION_QUEUE_SPAV_MARGIN(val) vBIT(val, 16, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TRAFFIC_CTRL_OFFLOAD_MAX_FRAMES(val) vBIT(val, 24, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TRAFFIC_CTRL_NOFFLOAD_MAX_FRAMES(val) vBIT(val, 32, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TRAFFIC_CTRL_MSP_MAX_FRAMES(val) vBIT(val, 40, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XFMD_ARB_CTRL_EN_OFF(val) vBIT(val, 15, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XFMD_ARB_CTRL_EN_NOFF(val) vBIT(val, 39, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RD_TRANC_CTRL_ARB(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_ARB_CTRL(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_ARB_TIMER(val) vBIT(val, 8, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_ARB_EN_QHIST(val) vBIT(val, 16, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_ARB_ACT_ARB_QHIST(val) vBIT(val, 28, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_ARB_QHIST_CNT(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_ARB_WR_DELAY_CNT(val) vBIT(val, 52, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FM_ARB_WR_WINDOW_CNT(val) vBIT(val, 56, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ARB_HP_CAL(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ARB_XFMD_LAST_MASK(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ARB_HP_XFMD_PRI(val) vBIT(val, 22, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FBMC_ECC_CFG_ENABLE(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_SG_ERR(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_SG_ERR(val) vBIT(val, 10, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_SG_ERR(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_SG_ERR(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_DB_ERR(val) vBIT(val, 8, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_DB_ERR(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_MSB(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_LSB(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SSCC_CONFIG_TIMEOUT_VALUE(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_MSB(val) vBIT(val, 43, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_LSB(val) vBIT(val, 51, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_DB_ERR(val) vBIT(val, 8, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_SG_ERR(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_DB_ERR(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_DB_ERR(val) vBIT(val, 20, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SRQ_CQRQ_POLL_TIMER(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SRQ_CQRQ_MAX_EOL_POLLS(val) vBIT(val, 32, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_ERR_POLICY_CQM_CQE(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_ERR_POLICY_SQM_WQE(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_ERR_POLICY_SQM_SRQIR(val) vBIT(val, 22, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_VPIN_CQRQ_ID(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_CIN_CQRQ_ID(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_MAX_CQE_GRP_CQRQ_ID(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_CQM_CDR_CQRQ_ID(val) vBIT(val, 48, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_VPIN_SRQ_ID(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_SIN_SRQ_ID(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_MAX_WQE_GRP_SRQ_ID(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_SQM_WDR_SRQ_ID(val) vBIT(val, 48, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_CCM_STATE_SERR(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_HEAD_CQEGRP_ID(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_TAIL_CQEGRP_ID(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_CCM_STATE_SERR(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_HEAD_WQEGRP_ID(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_TAIL_WQEGRP_ID(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_DB_ERR(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_DB_ERR(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_SG_ERR(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_SG_ERR(val) vBIT(val, 20, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_SG_ERR(val) vBIT(val, 9, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_SG_ERR(val) vBIT(val, 11, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_DB_ERR(val) vBIT(val, 41, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_DB_ERR(val) vBIT(val, 43, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SG_ERR(val) vBIT(val, 4, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_SG_ERR(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_DB_ERR(val) vBIT(val, 20, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_DB_ERR(val) vBIT(val, 22, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_TXPE_SG_ERR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_CDP_SG_ERR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_TXPE_DB_ERR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_CDP_DB_ERR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SGRP_ALLOC_SGRP_ALLOC(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SGRP_IWARP_LRO_ALLOC_LAST_IWARP_SGRP(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PE_STATS_CMD_ADDRESS(val) vBIT(val, 21, 11) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PE_STATS_DATA_PE_RETURNED(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXPE_FP_MASK_RXPE_FP_MASK(val) vBIT(val, 18, 46) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_IWARP_COUNTERS_MASTER(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_IWARP_COUNTERS_INTERVAL(val) vBIT(val, 40, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_IWARP_SLOW_COUNTER_MASTER(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_IWARP_TIMERS_TCP_NOW(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_IWARP_TIMERS_TCP_SLOW_CLK(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_LRO_CFG_START_VALUE(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_LRO_COUNTERS_MASTER(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PET_LRO_COUNTERS_INTERVAL(val) vBIT(val, 40, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PE_VP_ACK_BLK_LIMIT(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PE_VP_RIRR_BLK_LIMIT(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PE_VP_LIRR_BLK_LIMIT(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_DLM_CFG_ACK_PTR_AE_LEVEL(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_DLM_CFG_LIRR_PTR_AE_LEVEL(val) vBIT(val, 28, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_DLM_CFG_RIRR_PTR_AE_LEVEL(val) vBIT(val, 44, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_TOWI_CFG_TOWI_CACHE_SIZE(val) vBIT(val, 48, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_TOWI_CFG_TOWI_DMA_THRESHOLD(val) vBIT(val, 56, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_PMON_SAMPLE_PERIOD(val) vBIT(val, 16, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_PMON_DOWNCOUNT_TXPE_REMAINDER(val) vBIT(val, 16, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_PMON_EVENT_TXPE_STALL_CNT(val) vBIT(val, 16, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXPE_PMON_OTHER_TXPE_STALL_CNT(val) vBIT(val, 16, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_OES_PEND_QUEUE_RX_PEND_THRESHOLD(val) vBIT(val, 27, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_OES_PEND_QUEUE_TX_PEND_THRESHOLD(val) vBIT(val, 57, 7) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXDM_DBG_RD_ADDR(val) vBIT(val, 0, 12) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) vBIT(val, 59, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_USER_DOORBELL_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_WQE_OD_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_ACK_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_LIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_RIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_TCE_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_HOQ_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_STAG_VP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_R_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_CQRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_CQE_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_P_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_NCE_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_BYPASS_QUEUE_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_H_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_PBL_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_LIT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_SRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_P_SCR_RECORD_SIZE(val) vBIT(val, 2, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CMC_DEVICE_SELECT_CODE(val) vBIT(val, 5, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 20, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vBIT(val, 54, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vBIT(val, 8, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CP_EXC_CAUSE_CP_CP_CAUSE(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SIZE(val) vBIT(val, 29, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_CFG_SRAM_SPARSE_BASE_ADDR(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_CFG_SRAM_PACKED_BASE_ADDR(val) vBIT(val, 48, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XTMC_MEM_BYPASS_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MSG_DISPATCH_VPATH_CUTOFF(val) vBIT(val, 59, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MSG_EXC_CAUSE_MP_MXP(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MSG_EXC_CAUSE_UP_UXP(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MSG_DIRECT_PIC_UMQ_VPA(val) vBIT(val, 59, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_UMQ_IR_TEST_VPA_NUMBER(val) vBIT(val, 0, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_UMQ_IR_TEST_BYTE_VALUE_START(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_UMQ_BWR_PFCH_INIT_NUMBER(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_UMQ_BWR_EOL_POLL_LATENCY(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) vBIT(val, 18, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_GLOBAL_CFG_ARB_ALG(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_UTILIZATION(val) vBIT(val, 7, 9) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_RX_UTIL_CFG(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_FRAC_UTIL(val) vBIT(val, 20, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_RX_PKT_WEIGHT(val) vBIT(val, 24, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_AUTO_LRO_CONTROL_FRAME_COUNT(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_AUTO_LRO_CONTROL_TIMER_VALUE(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_LAG_CFG_COLL_ALG(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_COL_INDX(val) vBIT(val, 0, 12) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_FLAG(val) vBIT(val, 26, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXC(val) vBIT(val, 28, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXD(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vBIT(val, 22, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_UTILIZATION(val) vBIT(val, 7, 9) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_TX_UTIL_CFG(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_FRAC_UTIL(val) vBIT(val, 20, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_TX_PKT_WEIGHT(val) vBIT(val, 24, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ORP_CFG_FIFO_CREDITS(val) vBIT(val, 5, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ORP_LRO_EVENTS_ORP_LRO_EVENTS(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ORP_BS_EVENTS_ORP_BS_EVENTS(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ORP_IWARP_EVENTS_ORP_IWARP_EVENTS(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_ERR_INJECT_CFG_INJECTOR_ERROR_RATE(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CFG_MODE(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CFG_PERIOD(val) vBIT(val, 8, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CFG_VPATH_VECTOR(val) vBIT(val, 19, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CFG_SRC_VPATH(val) vBIT(val, 39, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CFG_HOST_STEERING(val) vBIT(val, 44, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CFG_IFS_SEL(val) vBIT(val, 47, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_PATTERN_SEL(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DA_SEL(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MIN_LEN(val) vBIT(val, 14, 14) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MAX_LEN(val) vBIT(val, 30, 14) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LT_FIELD(val) vBIT(val, 44, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DATA_SEL(val) vBIT(val, 62, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_FRMGEN_DATA_FRMDATA(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_DISTRIB_DEST_MAP_VPATH(n) mBIT(n) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_ACTIVE_VPLANE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_VPLANE_COUNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SHAREDIO_STATUS_PCI_RX_ILLEGAL_TLP_VPLANE_VAL(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_RMSG(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PCICFG_NO_TO_FUNC_CFG_PCICFG_NO_TO_FUNC_CFG(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RESOURCE_TO_VPLANE_CFG_RESOURCE_TO_VPLANE_CFG(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PCICFG_NO_TO_VPLANE_CFG_PCICFG_NO_TO_VPLANE_CFG(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENERAL_CFG_RST_CPLTO_VAL(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENERAL_CFG_INIT_OSD_COUNT(val) vBIT(val, 12, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENERAL_CFG_INIT_SHC(val) vBIT(val, 20, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENERAL_CFG_INITOSD_VERSION(val) vBIT(val, 29, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENERAL_CFG_FC_UPDT_FREQ_VAL(val) vBIT(val, 36, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_BIST_CFG_JTAG_BIST_COMPLETION_CODE(val) vBIT(val, 8, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SHOW_SRIOV_CAP_SHOW_SRIOV_CAP(val) vBIT(val, 0, 9) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_LINK_RST_WAIT_CNT_LINK_RST_WAIT_CNT(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ARBITER_CFG_CPL_PRIORITY(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ARBITER_CFG_MRD_PRIORITY(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ARBITER_CFG_MWR_PRIORITY(val) vBIT(val, 10, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_VHLABEL_TO_VPLANE_CFG_VHLABEL_TO_VPLANE_CFG(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_WMSG(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RC_RXDMEM_END_OFST_RC_RXDMEM_END_OFST(val) vBIT(val, 49, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_SRPCIM_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_VPATH_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_ADDR_ERR(val) vBIT(val, 2, 22) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_FIFO_NO_ERR(val) vBIT(val, 26, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MSIX_ADDR_MSIX_ADDR(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MSIX_TABLE_DATA(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MSIX_CTL_VECTOR_NO(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) vBIT(val, 13, 51) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ASIC_MODE_PIC(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_INI_TIMEOUT_VAL_MWR(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_INI_TIMEOUT_VAL_MRD(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_READ_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_READ_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_READ_ARBITER_DBLGEN_PRIORITY(val) vBIT(val, 10, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_WRITE_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_WRITE_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_WRITE_ARBITER_STATS_PRIORITY(val) vBIT(val, 10, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_WRITE_ARBITER_MSG_PRIORITY(val) vBIT(val, 14, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKA_SEL(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKB_SEL(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DA_SEL(val) vBIT(val, 10, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DB_SEL(val) vBIT(val, 18, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PIC_DEBUG_CONTROL_DBGA_SEL(val) vBIT(val, 28, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PIC_DEBUG_CONTROL_DBGB_SEL(val) vBIT(val, 32, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_VECTOR_SRPCIM_ALARM_MAP_VECTOR_SRPCIM_ALARM_MAP(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_SPI_CONTROL_KEY(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_SPI_CONTROL_BYTE_CNT(val) vBIT(val, 29, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_SPI_CONTROL_CMD(val) vBIT(val, 32, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_SPI_CONTROL_ADD(val) vBIT(val, 40, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_SPI_DATA_SPI_RWDATA(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_CHIP_FULL_RESET_CHIP_FULL_RESET(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_BF_SW_RESET_BF_SW_RESET(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RIC_TIMEOUT_VAL(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_DATA(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENSTATS_CFG_DTYPE_SEL(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENSTATS_CFG_CLIENT_NO_SEL(val) vBIT(val, 9, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENSTATS_CFG_WR_RD_CPL_SEL(val) vBIT(val, 14, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_GENSTATS_CFG_VPATH_SEL(val) vBIT(val, 31, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PLL_SLIP_COUNTERS_CMG(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PLL_SLIP_COUNTERS_FB(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_PLL_SLIP_COUNTERS_X(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_STC_JHASH_CFG_GOLDEN(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_STC_JHASH_CFG_INIT_VAL(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_HSQ_CFG_BASE_ADDR(val) vBIT(val, 8, 24) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_ERROR(val) vBIT(val, 56, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_DRBELL(val) vBIT(val, 9, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_MSG(val) vBIT(val, 15, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_ONE(val) vBIT(val, 18, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_PCI(val) vBIT(val, 21, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_RTDMA(val) vBIT(val, 24, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_WRDMA(val) vBIT(val, 27, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_XGMAC(val) vBIT(val, 30, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_ALL_FUSE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_ALL_FUSE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_ALL_FUSE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_ALL_FUSE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) vBIT(val, 3, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vBIT(val, 20, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) vBIT(val, 16, 48) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vBIT(val, 0, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vBIT(val, 4, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) vBIT(val, 12, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vBIT(val, 24, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) vBIT(val, 32, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) vBIT(val, 36, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_CON(val) vBIT(val, 37, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_LVL(val) vBIT(val, 55, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_LVL(val) vBIT(val, 19, 5) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_CKO_ALIVE_CON(val) vBIT(val, 28, 2) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_INT_CTL(val) vBIT(val, 33, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_PROP_CTL(val) vBIT(val, 37, 3) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_ADDR(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_DATA(val) vBIT(val, 48, 16) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESP(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESP(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vBIT(val, 24, 4) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_CFG_PORT_RESET_CFG_REGS(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_MGR_CTRL_PORT_ADDR(val) vBIT(val, 15, 9) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_MGR_CTRL_PORT_DATA(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val)\ dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vBIT(val, 8, 8) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_ADAPTIVE_LRO_VPATH_ENABLE_EN(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_VALUE(val) vBIT(val, 2, 6) dev/vxge/vxgehal/vxgehal-mrpcim-reg.h:#define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_USE_HASH_WIDTH(val)\ dev/vxge/vxgehal/vxgehal-pcicfgmgmt-reg.h:#define VXGE_HAL_MSIXGRP_NO_TABLE_SIZE(val) vBIT(val, 5, 11) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) bVAL16(bits, 0) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) bVAL8(bits, 48) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) bVAL8(bits, 56) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_VPLANE(bits) bVAL5(bits, 11) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_DEBUG_ASSIGNMENTS_GET_FUNC(bits) bVAL5(bits, 19) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits)\ dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vBIT(val, 42, 5) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vBIT(val, 47, 2) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) vBIT(val, 49, 15) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_RTDMA_BW_CTRL_GET_DESIRED_BW(bits) bVAL18(bits, 46) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_SHOW_PORT_INFO(bits)\ dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_ASIC_NTWK_VP_CTRL_GET_XMACJ_PORT_NUM(bits) bVAL1(bits, 63) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_CONTROL_ADDR(val) (val<<8) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_EEPROM_NVR_DATA_DATA(val)\ dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_MDIO_GEN_CFG_PORT_MDIO_PHY_PRTAD(val) vBIT(val, 19, 5) dev/vxge/vxgehal/vxgehal-regdefs.h:#define VXGE_HAL_XGXS_STATIC_CFG_PORT_MDIO_DTE_PRTAD(val) vBIT(val, 7, 5) dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_ERR_HEADER_LOG(x) ((x) >> 31) /* Error Header Log */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ dev/vxge/vxgehal/vxgehal-regs.h:#define VXGE_HAL_PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Include in sys budget */ dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_VF_BARGRP_NO_FIRST_VF_OFFSET(val) vBIT(val, 32, 4) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_VF_BARGRP_NO_MASK(val) vBIT(val, 36, 4) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG(val)\ dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG(val)\ dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SEL_SEL(val) vBIT(val, 0, 5) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG(val)\ dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_VPATH_TO_SRPCIM_ALARM_REG_PPIF_VPATH_TO_SRPCIM_ALARM(val)\ dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_USDC_VPL_SGRP_OWN(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_SGRP_ALLOCATED_SGRP_ALLOC(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_SGRP_IWARP_LRO_ALLOCATED_LAST_IWARP_SGRP(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR(val)\ dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val)\ dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_WDE_CFG_ALIGNMENT_PREFERENCE(val) vBIT(val, 30, 2) dev/vxge/vxgehal/vxgehal-srpcim-reg.h:#define VXGE_HAL_WDE_CFG_MEM_WORD_SIZE(val) vBIT(val, 46, 2) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_COMMON_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_VPATH_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_KDFC_INITIAL_OFFSET(val) vBIT(val, 0, 61) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_USDC_INITIAL_OFFSET(val) vBIT(val, 0, 61) dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE(val)\ dev/vxge/vxgehal/vxgehal-toc-reg.h:#define VXGE_HAL_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE(val)\ dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TIM_DEST_ADDR_TIM_DEST_ADDR(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP(val) vBIT(val, 59, 5) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT(val)\ dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RX_MULTI_CAST_STATS_FRAME_DISCARD(val) vBIT(val, 48, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RXD_RETURNED_RXD_RETURNED(val) vBIT(val, 48, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE(val) vBIT(val, 17, 15) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_XMAC_STATS_ACCESS_DATA_XSMGR_DATA(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RTDMA_BW_CTRL_DESIRED_BW(val) vBIT(val, 46, 18) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vBIT(val, 8, 8) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK(val)\ dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(val) vBIT(val, 37, 3) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY(val) vBIT(val, 61, 3) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TIM_WRKLD_CLC_HOST_UTIL(val) vBIT(val, 57, 7) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TIM_BITMAP_MASK(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TIM_REMAP_TO_VPATH_NUM(val) vBIT(val, 11, 5) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TIM_VPATH_MAP_BMAP_ROOT(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_SGRP_ASSIGN_SGRP_ASSIGN(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT(val)\ dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TXPE_PCI_NCE_CFG_NCE_THRESH(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_UMQDMQ_IR_INIT_HOST_WRITE_ADD(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DMQ_IR_INT_NUMBER(val) vBIT(val, 9, 7) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DMQ_IR_INT_BITMAP(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DMQ_BWR_INIT_ADD_HOST(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DMQ_BWR_INIT_BYTE_COUNT(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DMQ_IR_POLICY(val) vBIT(val, 0, 8) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_UMQ_INT_NUMBER(val) vBIT(val, 9, 7) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_UMQ_INT_BITMAP(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_UMQ_BWR_INIT_ADD_HOST(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_UMQ_BWR_INIT_BYTE_COUNT(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_GENDMA_INT_NUMBER(val) vBIT(val, 9, 7) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_GENDMA_INT_BITMAP(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS(val)\ dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_FAU_ADAPTIVE_LRO_FILTER_VLAN_DATA_VLAN_VID(val)\ dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DBG_STATS_RX_MPA_CRC_FAIL_FRMS(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vBIT(val, 16, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DBG_STATS_RX_MPA_LEN_FAIL_FRMS(val) vBIT(val, 32, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DBG_STATS_RX_FAU_RX_WOL_FRMS(val) vBIT(val, 0, 16) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val)\ dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_VPATH_TO_SRPCIM_WMSG_WMSG(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_SRPCIM_TO_VPATH_ALARM_REG_PPIF_ALARM(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN(val) vBIT(val, 6, 2) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_TGT_ILLEGAL_ACCESS_SWIF_REGION(val) vBIT(val, 1, 7) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_STATS_CFG_START_HOST_ADDR(val) vBIT(val, 0, 57) dev/vxge/vxgehal/vxgehal-vpath-reg.h:#define VXGE_HAL_PCI_CONFIG_ACCESS_STATUS_DATA(val) vBIT(val, 32, 32) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_SGRP_OWN_SGRP_OWN(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) vBIT(val, 59, 5) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_USDC_VPATH_OWN_SGRP_OWN(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR(val) vBIT(val, 0, 17) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_WOL_MP_CRC_CRC(val) vBIT(val, 0, 32) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_WOL_MP_MASK_A_MASK(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_WOL_MP_MASK_B_MASK(val) vBIT(val, 0, 64) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG(val) vBIT(val, 16, 4) dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL(val)\ dev/vxge/vxgehal/vxgehal-vpmgmt-reg.h:#define VXGE_HAL_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT(val) vBIT(val, 24, 4) dev/wb/if_wbreg.h:#define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data dev/wi/if_wivar.h:#define WI_RSSI_TO_DBM(sc, rssi) (MIN((sc)->sc_max_rssi, \ dev/wtap/if_wtapvar.h:#define WTAP_NODE(ni) ((struct ath_node *)(ni)) dev/wtap/if_wtapvar.h:#define WTAP_NODE_CONST(ni) ((const struct ath_node *)(ni)) dev/xl/if_xlreg.h:#define xl_rx_goodframes(x) \ dev/xl/if_xlreg.h:#define xl_tx_goodframes(x) \ fs/cuse/cuse_defs.h:#define CUSE_ID_WEBCAMD(what) CUSE_MAKE_ID('W','C',what,0) /* Used by Webcamd. */ fs/cuse/cuse_defs.h:#define CUSE_ID_SUNDTEK(what) CUSE_MAKE_ID('S','K',what,0) /* Used by Sundtek. */ fs/cuse/cuse_defs.h:#define CUSE_ID_UHIDD(what) CUSE_MAKE_ID('U','D',what,0) /* Used by uhidd. */ fs/fuse/fuse_debug.h:#define kdebug_printf(fmt, ...) FS_DEBUG(fmt, ## __VA_ARGS__) fs/fuse/fuse_vnops.c:#define fuse_vm_page_lock(m) vm_page_lock((m)); fs/fuse/fuse_vnops.c:#define fuse_vm_page_unlock(m) vm_page_unlock((m)); fs/nandfs/nandfs.h:#define DPRINTFIF(name, cond, arg) { \ fs/nandfs/nandfs_fs.h:#define NANDFS_SR_DAT_OFFSET(inode_size) NANDFS_SR_MDT_OFFSET(inode_size, 0) fs/nandfs/nandfs_fs.h:#define NANDFS_SR_CPFILE_OFFSET(inode_size) NANDFS_SR_MDT_OFFSET(inode_size, 1) fs/nandfs/nandfs_fs.h:#define NANDFS_SR_SUFILE_OFFSET(inode_size) NANDFS_SR_MDT_OFFSET(inode_size, 2) fs/nandfs/nandfs_fs.h:#define NANDFS_DATA_OFFSET_BYTES(esize) (NANDFS_NFSAREAS * (esize)) fs/nfs/nfs.h:#define NFS_SETTIME(t) do { \ fs/nfs/nfs.h:#define LIST_PREPEND(head, phead, lelm, field) do { \ fs/nfs/nfsdport.h:#define NFSVNO_ISSETMODE(n) ((n)->na_mode != ((mode_t)VNOVAL)) fs/nfs/nfsdport.h:#define NFSVNO_NOTSETATIME(n) ((n)->na_atime.tv_sec == VNOVAL) fs/nfs/nfsdport.h:#define NFSVNO_NOTSETMTIME(n) ((n)->na_mtime.tv_sec == VNOVAL) fs/nfs/nfskpiport.h:#define mbuf_data(m) mtod((m), void *) fs/nfs/nfskpiport.h:#define mbuf_pkthdr_len(m) ((m)->m_pkthdr.len) fs/nfs/nfskpiport.h:#define mbuf_pkthdr_setlen(m, l) ((m)->m_pkthdr.len = (l)) fs/nfs/nfskpiport.h:#define mbuf_pkthdr_setrcvif(m, p) ((m)->m_pkthdr.rcvif = (p)) fs/nfs/nfskpiport.h:#define CAST_DOWN(c, a) ((c) (a)) fs/nfs/nfskpiport.h:#define uio_uio_resid_set(p, v) ((p)->uio_resid = (v)) fs/nfs/nfskpiport.h:#define uio_iov_len(p) ((p)->uio_iov->iov_len) fs/nfs/nfsport.h:#define NFSMGETHDR(m) do { \ fs/nfs/nfsport.h:#define NFSMCLGETHDR(m, w) do { \ fs/nfs/nfsport.h:#define NFSPROCP(p) ((p)->td_proc) fs/nfs/nfsport.h:#define NFSNAMEIDREQUIRED() mtx_assert(&nfs_nameid_mutex, MA_OWNED) fs/nfs/nfsport.h:#define NFSLOCKREQUEST(r) mtx_lock(&((r)->r_mtx)) fs/nfs/nfsport.h:#define NFSUNLOCKREQUEST(r) mtx_unlock(&((r)->r_mtx)) fs/nfs/nfsport.h:#define NFSLOCKSOCKREQ(r) mtx_lock(&((r)->nr_mtx)) fs/nfs/nfsport.h:#define NFSUNLOCKSOCKREQ(r) mtx_unlock(&((r)->nr_mtx)) fs/nfs/nfsport.h:#define NFSSESSIONMUTEXPTR(s) (&((s)->mtx)) fs/nfs/nfsport.h:#define SLIST_END(head) NULL fs/nfs/nfsport.h:#define TAILQ_END(head) NULL fs/nfs/nfsport.h:#define NFSINT_SIGMASK(set) \ fs/nfs/nfsport.h:#define NFSATTRISSETTIME(v, a) ((v)->a.tv_sec != VNOVAL) fs/nfs/nfsport.h:#define NFSHASINTORSOFT(n) ((n)->nm_flag & (NFSMNT_INT | NFSMNT_SOFT)) fs/nfs/nfsport.h:#define NFSHASDUMBTIMR(n) ((n)->nm_flag & NFSMNT_DUMBTIMR) fs/nfs/nfsport.h:#define NFSHASNOCONN(n) ((n)->nm_flag & NFSMNT_MNTD) fs/pseudofs/pseudofs.h:#define PFS_INIT_PROTO(name) \ fs/pseudofs/pseudofs.h:#define PFS_FILL_PROTO(name) \ fs/pseudofs/pseudofs.h:#define PFS_ATTR_PROTO(name) \ fs/pseudofs/pseudofs.h:#define PFS_VIS_PROTO(name) \ fs/pseudofs/pseudofs.h:#define PFS_IOCTL_PROTO(name) \ fs/pseudofs/pseudofs.h:#define PFS_GETEXTATTR_PROTO(name) \ fs/pseudofs/pseudofs.h:#define PFS_CLOSE_PROTO(name) \ fs/pseudofs/pseudofs.h:#define PFS_DESTROY_PROTO(name) \ fs/smbfs/smbfs.h:#define SMBFSTOVFS(smp) ((struct mount *)((smp)->sm_mp)) geom/geom.h:#define g_topology_try_lock() sx_try_xlock(&topology_lock) gnu/dts/arm/exynos3250-pinctrl.dtsi:#define PIN_OUT_SET(_pin, _val, _drv) \ gnu/dts/arm/exynos3250-pinctrl.dtsi:#define PIN_CFG(_pin, _sel, _pull, _drv) \ gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h:#define TEGRA_MAIN_GPIO(port, offset) \ gnu/dts/include/dt-bindings/gpio/tegra186-gpio.h:#define TEGRA_AON_GPIO(port, offset) \ gnu/dts/include/dt-bindings/pinctrl/mt65xx.h:#define MTK_GET_PIN_NO(x) ((x) >> 8) gnu/dts/include/dt-bindings/pinctrl/mt65xx.h:#define MTK_GET_PIN_FUNC(x) ((x) & 0xf) i386/i386/minidump_machdep.c:#define DEV_ALIGN(x) roundup2((off_t)(x), DEV_BSIZE) i386/i386/pmap.c:#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) i386/i386/pmap.c:#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) i386/i386/pmap.c:#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) i386/i386/pmap.c:#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ i386/i386/pmap.c:#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) i386/i386/sys_machdep.c:#define SIZE_FROM_LARGEST_LD(num) (NEW_MAX_LD(num) << 3) i386/include/pcaudioio.h:#define AUDIO_INITINFO(i) memset((void*)i, 0xff, sizeof(audio_info_t)) i386/include/segments.h:#define SEGEX_IDX(s) (((s)>>3)&0x1fff) isa/pnpreg.h:#define PNP_MEM_CONTROL(i) (0x42 * 8*(i)) kern/kern_khelp.c:#define KHELP_LIST_LOCK_ASSERT() rw_assert(&khelp_list_lock, RA_LOCKED) kern/kern_ntptime.c:#define L_ADDHI(v, a) ((v) += (int64_t)(a) << 32) kern/kern_ntptime.c:#define L_NEG(v) ((v) = -(v)) kern/kern_ntptime.c:#define L_ISNEG(v) ((v) < 0) kern/kern_rwlock.c:#define rw_wlocked(rw) (rw_wowner((rw)) == curthread) kern/kern_sysctl.c:#define SYSCTL_WLOCKED() rm_wowned(&sysctllock) kern/kern_sysctl.c:#define SYSCTL_ASSERT_RLOCKED() rm_assert(&sysctllock, RA_RLOCKED) kern/subr_devstat.c:#define DTRACE_DEVSTAT_WAIT_START() SDT_PROBE2(io, , , wait__start, NULL, ds) kern/subr_devstat.c:#define DTRACE_DEVSTAT_WAIT_DONE() SDT_PROBE2(io, , , wait__done, NULL, ds) kern/subr_mchain.c:#define MBPANIC(format, ...) printf("%s(%d): "format, __func__ , \ kern/subr_sbuf.c:#define SBUF_HASROOM(s) ((s)->s_len < (s)->s_size - 1) kern/subr_vmem.c:#define QC_POOL_TO_QCACHE(pool) ((qcache_t *)(pool->pr_qcache)) kern/subr_vmem.c:#define VMEM_TRYLOCK(vm) mtx_trylock(&vm->vm_lock) kern/sysv_msg.c:#define MSQID(ix,ds) ((ix) & 0xffff | (((ds).msg_perm.seq << 16) & 0xffff0000)) kern/sysv_msg.c:#define MSQID_IX(id) ((id) & 0xffff) kern/sysv_msg.c:#define MSQID_SEQ(id) (((id) >> 16) & 0xffff) kern/uipc_usrreq.c:#define UNP_LINK_LOCK_ASSERT() rw_assert(&unp_link_rwlock, \ kgssapi/gssapi.h:#define GSS_CALLING_ERROR(x) \ kgssapi/gssapi.h:#define GSS_ROUTINE_ERROR(x) \ kgssapi/gssapi.h:#define GSS_SUPPLEMENTARY_INFO(x) \ mips/adm5120/adm5120reg.h:#define SW_READ(o) _REG_READ(ADM5120_BASE_SWITCH, o) mips/adm5120/adm5120reg.h:#define SW_WRITE(o, v) _REG_WRITE(ADM5120_BASE_SWITCH,o, v) mips/adm5120/if_admswvar.h:#define ADMSW_NEXTTXH(x) (((x) + 1) & ADMSW_NTXHDESC_MASK) mips/adm5120/if_admswvar.h:#define ADMSW_NEXTRXH(x) (((x) + 1) & ADMSW_NRXHDESC_MASK) mips/alchemy/aureg.h:#define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ mips/alchemy/aureg.h:#define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ mips/alchemy/aureg.h:#define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ mips/atheros/ar531x/ar5312reg.h:#define GETSYSREG(x) REGVAL((x) + AR5312_SYSREG_BASE) mips/atheros/ar531x/ar5312reg.h:#define PUTSYSREG(x,v) (REGVAL((x) + AR5312_SYSREG_BASE)) = (v) mips/atheros/ar531x/ar5312reg.h:#define GETSDRAMREG(x) REGVAL((x) + AR5312_SDRAMCTL_BASE) mips/atheros/ar531x/ar5312reg.h:#define PUTSDRAMREG(x,v) (REGVAL((x) + AR5312_SDRAMCTL_BASE)) = (v) mips/atheros/ar531x/if_arereg.h:#define ARE_PKTSIZE(len) ((len & 0xffff0000) >> 16) mips/atheros/if_argevar.h:#define ARGE_CLEAR_BITS(sc, reg, bits) \ mips/cavium/octe/ethernet-mdio.h:#define MDIO_TRYLOCK() mtx_trylock(&cvm_oct_mdio_mtx) mips/idt/idtreg.h:#define ICU_IRQ_IPEND_REG(irq) \ mips/idt/obio.c:#define GPIO_REG_WRITE(o,v) (GPIO_REG_READ(o)) = (v) mips/include/cdefs.h:#define _MIPS_SIM_NEWABI_P(abi) ((abi) == _MIPS_SIM_NABI32 || \ mips/include/cpuregs.h:#define MIPS_PHYS_TO_XKPHYS(cca,x) \ mips/include/cpuregs.h:#define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \ mips/include/db_machdep.h:#define DB_VALID_BREAKPOINT(addr) (((addr) & 3) == 0) mips/include/locore.h:#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) mips/include/locore.h:#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) mips/include/locore.h:#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) mips/include/locore.h:#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ mips/include/mips_opcode.h:#define MIPS_INST_RS(val) ((val & 0x03e00000) >> 21) mips/include/mips_opcode.h:#define MIPS_INST_IMM(val) ((val & 0x0000ffff)) mips/include/mips_opcode.h:#define MIPS_INST_RD(val) ((val & 0x0000f800) >> 11) mips/include/mips_opcode.h:#define MIPS_INST_SA(val) ((val & 0x000007c0) >> 6) mips/include/mips_opcode.h:#define MIPS_INST_FUNC(val) (val & 0x0000003f) mips/include/mips_opcode.h:#define MIPS_INST_INDEX(val) (val & 0x03ffffff) mips/include/mips_opcode.h:#define MIPS_OPCODE(r, c) (((r & 0x07) << 3) | (c & 0x07)) mips/include/mips_opcode.h:#define MIPS_ROP(r, c) ((r & 0x03) << 3) | (c & 0x07) mips/include/pcpu.h:#define PCPU_LAZY_INC(member) (++PCPUP->pc_ ## member) mips/ingenic/jz4780_pdma.h:#define PDMA_DSA(n) (0x00 + 0x20 * n) /* Channel n Source Address */ mips/ingenic/jz4780_pdma.h:#define PDMA_DTA(n) (0x04 + 0x20 * n) /* Channel n Target Address */ mips/ingenic/jz4780_pdma.h:#define PDMA_DTC(n) (0x08 + 0x20 * n) /* Channel n Transfer Count */ mips/ingenic/jz4780_pdma.h:#define PDMA_DRT(n) (0x0C + 0x20 * n) /* Channel n Request Source */ mips/ingenic/jz4780_pdma.h:#define PDMA_DCM(n) (0x14 + 0x20 * n) /* Channel n Command */ mips/ingenic/jz4780_pdma.h:#define PDMA_DSD(n) (0x1C + 0x20 * n) /* Channel n Stride Difference */ mips/ingenic/jz4780_regs.h:#define JZ_TC_TDHR(n) (0x00000044 + (n * 0x10)) /* HALF compare */ mips/ingenic/jz4780_regs.h:#define JZ_NEMC_SACR(n) (0x30 + (n) * 4) mips/malta/yamon.h:#define YAMON_PRINT_COUNT(s, count) \ mips/malta/yamon.h:#define YAMON_EXIT(rc) ((t_yamon_exit)(YAMON_FUNC(YAMON_EXIT_OFS)))(rc) mips/malta/yamon.h:#define YAMON_PRINT(s) ((t_yamon_print)(YAMON_FUNC(YAMON_PRINT_OFS)))(0, s) mips/malta/yamon.h:#define YAMON_GETCHAR(ch) \ mips/mediatek/mtk_pcie.h:#define MTK_PCIE_ID(_s) (MTK_PCI_PCIE0_ID + (_s)*0x1000) mips/mediatek/mtk_pcie.h:#define MTK_PCIE_SUBID(_s) (MTK_PCI_PCIE0_SUBID + (_s)*0x1000) mips/mediatek/mtk_usb_phy.c:#define USB_PHY_CLR_SET(_sc, _off, _clr, _set) \ mips/mediatek/mtk_usb_phy.c:#define USB_PHY_WRITE_FM(_sc, _off) \ mips/mips/vm_machdep.c:#define ZIDLE_LO(v) ((v) * 2 / 3) mips/mips/vm_machdep.c:#define ZIDLE_HI(v) ((v) * 4 / 5) mips/nlm/dev/net/ucore/ucore.h:#define VAL_PDM(x) (((x) & 0x7) << 0) mips/nlm/dev/net/ucore/ucore.h:#define VAL_DEST(x) (((x) & 0x3ff) << 8) mips/nlm/dev/net/ucore/ucore.h:#define VAL_PDL(x) (((x) & 0xf) << 4) mips/nlm/dev/net/ucore/ucore.h:#define VAL_FSV(x) (x << 19) mips/nlm/dev/net/ucore/ucore.h:#define VAL_FFS(x) (x << 14) mips/nlm/dev/net/xlpge.h:#define XLPGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) mips/nlm/dev/net/xlpge.h:#define XLPGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED) mips/nlm/hal/bridge.h:#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) mips/nlm/hal/fmn.h:#define CMS_CPU_PUSHQ(node, core, thread, vc) \ mips/nlm/hal/fmn.h:#define CMS_POPQ(node, queue) (((node)<<10) | (queue)) mips/nlm/hal/fmn.h:#define CMS_IO_PUSHQ(node, queue) (((node)<<10) | (queue)) mips/nlm/hal/fmn.h:#define CMS_POPQ_QID(i) (128+(i)) mips/nlm/hal/fmn.h:#define CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs) \ mips/nlm/hal/fmn.h:#define XLP_CMS_ON_CHIP_PER_QUEUE_SPACE(node) \ mips/nlm/hal/fmn.h:#define XLP_CMS_TOTAL_SPILL_MEM(node, spilltotmsgs) \ mips/nlm/hal/fmn.h:#define CMS_TOTAL_QUEUE_SIZE(node, spilltotmsgs) \ mips/nlm/hal/gbu.h:#define GBU_CS_BASELIMIT(cs) (0x8+cs) mips/nlm/hal/gbu.h:#define GBU_CS_DEVPARAM(cs) (0x10+cs) mips/nlm/hal/gbu.h:#define nlm_write_gbu_reg(b, r, v) nlm_write_reg(b, r, v) mips/nlm/hal/interlaken.h:#define ILK_TX_CONTROL(block) NAE_REG(block, 5, 0x00) mips/nlm/hal/interlaken.h:#define ILK_TX_RATE_LIMIT(block) NAE_REG(block, 5, 0x01) mips/nlm/hal/interlaken.h:#define ILK_TX_META_CTRL(block) NAE_REG(block, 5, 0x02) mips/nlm/hal/interlaken.h:#define ILK_RX_CTRL(block) NAE_REG(block, 5, 0x03) mips/nlm/hal/interlaken.h:#define ILK_RX_FC_TADDR(block) NAE_REG(block, 5, 0x0d) mips/nlm/hal/iomap.h:#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2) mips/nlm/hal/iomap.h:#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 0) mips/nlm/hal/iomap.h:#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) mips/nlm/hal/iomap.h:#define XLP_IO_SRIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 4) mips/nlm/hal/iomap.h:#define XLP_IO_REGEX_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 5) mips/nlm/hal/iomap.h:#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) mips/nlm/hal/iomap.h:#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) mips/nlm/hal/iomap.h:#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) mips/nlm/hal/iomap.h:#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) mips/nlm/hal/iomap.h:#define XLP_IO_MMC_OFFSET(node, slot) \ mips/nlm/hal/nlmsaelib.h:#define nlm_read_sec_reg(b, r) nlm_read_reg(b, r) mips/nlm/hal/nlmsaelib.h:#define nlm_write_sec_reg(b, r, v) nlm_write_reg(b, r, v) mips/nlm/hal/nlmsaelib.h:#define nlm_get_sec_regbase(node) \ mips/nlm/hal/nlmsaelib.h:#define nlm_read_rsa_reg(b, r) nlm_read_reg(b, r) mips/nlm/hal/nlmsaelib.h:#define nlm_qidstart_sec(node) nlm_qidstart_kseg(nlm_pcibase_sec(node)) mips/nlm/hal/nlmsaelib.h:#define nlm_qnum_sec(node) nlm_qnum_kseg(nlm_pcibase_sec(node)) mips/nlm/hal/pcibus.h:#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) mips/nlm/hal/pcibus.h:#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) mips/nlm/hal/pcibus.h:#define nlm_get_pcie_regbase(node, inst) \ mips/nlm/hal/pic.h:#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) mips/nlm/hal/pic.h:#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) mips/nlm/hal/pic.h:#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) mips/nlm/hal/poe.h:#define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4) mips/nlm/hal/poe.h:#define nlm_read_poe_reg(b, r) nlm_read_reg(b, r) mips/nlm/hal/poe.h:#define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r) mips/nlm/hal/sgmii.h:#define SGMII_IPG_IFG(block, i) NAE_REG(block, i, 0x02) mips/nlm/hal/sgmii.h:#define SGMII_HLF_DUP(block, i) NAE_REG(block, i, 0x03) mips/nlm/hal/sgmii.h:#define SGMII_TEST(block, i) NAE_REG(block, i, 0x07) mips/nlm/hal/sgmii.h:#define SGMII_MIIM_CONF(block, i) NAE_REG(block, i, 0x08) mips/nlm/hal/sgmii.h:#define SGMII_MIIM_CMD(block, i) NAE_REG(block, i, 0x09) mips/nlm/hal/sgmii.h:#define SGMII_MIIM_ADDR(block, i) NAE_REG(block, i, 0x0a) mips/nlm/hal/sgmii.h:#define SGMII_MIIM_CTRL(block, i) NAE_REG(block, i, 0x0b) mips/nlm/hal/sgmii.h:#define SGMII_MIIM_STAT(block, i) NAE_REG(block, i, 0x0c) mips/nlm/hal/sgmii.h:#define SGMII_MIIM_IND(block, i) NAE_REG(block, i, 0x0d) mips/nlm/hal/sgmii.h:#define SGMII_IO_CTRL(block, i) NAE_REG(block, i, 0x0e) mips/nlm/hal/sgmii.h:#define SGMII_IO_STAT(block, i) NAE_REG(block, i, 0x0f) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TRMAX(block, i) NAE_REG(block, i, 0x25) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TRMGV(block, i) NAE_REG(block, i, 0x26) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RBYT(block, i) NAE_REG(block, i, 0x27) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RPKT(block, i) NAE_REG(block, i, 0x28) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RFCS(block, i) NAE_REG(block, i, 0x29) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RMCA(block, i) NAE_REG(block, i, 0x2a) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RBCA(block, i) NAE_REG(block, i, 0x2b) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RXCF(block, i) NAE_REG(block, i, 0x2c) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RXPF(block, i) NAE_REG(block, i, 0x2d) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RXUO(block, i) NAE_REG(block, i, 0x2e) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RALN(block, i) NAE_REG(block, i, 0x2f) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RFLR(block, i) NAE_REG(block, i, 0x30) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RCDE(block, i) NAE_REG(block, i, 0x31) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RCSE(block, i) NAE_REG(block, i, 0x32) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RUND(block, i) NAE_REG(block, i, 0x33) mips/nlm/hal/sgmii.h:#define SGMII_STATS_ROVR(block, i) NAE_REG(block, i, 0x34) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RFRG(block, i) NAE_REG(block, i, 0x35) mips/nlm/hal/sgmii.h:#define SGMII_STATS_RJBR(block, i) NAE_REG(block, i, 0x36) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TBYT(block, i) NAE_REG(block, i, 0x38) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TPKT(block, i) NAE_REG(block, i, 0x39) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TMCA(block, i) NAE_REG(block, i, 0x3a) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TBCA(block, i) NAE_REG(block, i, 0x3b) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TXPF(block, i) NAE_REG(block, i, 0x3c) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TDFR(block, i) NAE_REG(block, i, 0x3d) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TEDF(block, i) NAE_REG(block, i, 0x3e) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TSCL(block, i) NAE_REG(block, i, 0x3f) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TMCL(block, i) NAE_REG(block, i, 0x40) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TLCL(block, i) NAE_REG(block, i, 0x41) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TXCL(block, i) NAE_REG(block, i, 0x42) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TNCL(block, i) NAE_REG(block, i, 0x43) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TJBR(block, i) NAE_REG(block, i, 0x46) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TFCS(block, i) NAE_REG(block, i, 0x47) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TXCF(block, i) NAE_REG(block, i, 0x48) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TOVR(block, i) NAE_REG(block, i, 0x49) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TUND(block, i) NAE_REG(block, i, 0x4a) mips/nlm/hal/sgmii.h:#define SGMII_STATS_TFRG(block, i) NAE_REG(block, i, 0x4b) mips/nlm/hal/sgmii.h:#define SGMII_NETIOR_RXDROP_CNTR(block, i) NAE_REG(block, i, 0x77) mips/nlm/hal/sgmii.h:#define SGMII_NETIOR_PAUSE_QUANTAMULT(block, i) NAE_REG(block, i, 0x78) mips/nlm/hal/sgmii.h:#define SGMII_NETIOR_MAC_CTRL_OPCODE(block, i) NAE_REG(block, i, 0x79) mips/nlm/hal/sgmii.h:#define SGMII_NETIOR_MAC_DA_H(block, i) NAE_REG(block, i, 0x7a) mips/nlm/hal/sgmii.h:#define SGMII_NETIOR_MAC_DA_L(block, i) NAE_REG(block, i, 0x7b) mips/nlm/hal/sgmii.h:#define SGMII_NETIOR_GMAC_STAT(block, i) NAE_REG(block, i, 0x7d) mips/nlm/hal/usb.h:#define nlm_get_usb_hcd_base(node, inst) nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst)) mips/nlm/hal/xaui.h:#define XAUI_REVISION_LVL(block) NAE_REG(block, 4, 0x0b) mips/nlm/hal/xaui.h:#define XAUI_MII_MGMT_CMD(block) NAE_REG(block, 4, 0x10) mips/nlm/hal/xaui.h:#define XAUI_MII_MGMT_FIELD(block) NAE_REG(block, 4, 0x11) mips/nlm/hal/xaui.h:#define XAUI_MII_MGMT_CFG(block) NAE_REG(block, 4, 0x12) mips/nlm/hal/xaui.h:#define XAUI_MIIM_LINK_FALL_VEC(block) NAE_REG(block, 4, 0x13) mips/nlm/hal/xaui.h:#define XAUI_MII_MGMT_IND(block) NAE_REG(block, 4, 0x14) mips/nlm/hal/xaui.h:#define XAUI_STATS_MLR(block) NAE_REG(block, 4, 0x1f) mips/nlm/hal/xaui.h:#define XAUI_STATS_TRMAX(block) NAE_REG(block, 4, 0x25) mips/nlm/hal/xaui.h:#define XAUI_STATS_TRMGV(block) NAE_REG(block, 4, 0x26) mips/nlm/hal/xaui.h:#define XAUI_STATS_RBYT(block) NAE_REG(block, 4, 0x27) mips/nlm/hal/xaui.h:#define XAUI_STATS_RPKT(block) NAE_REG(block, 4, 0x28) mips/nlm/hal/xaui.h:#define XAUI_STATS_RFCS(block) NAE_REG(block, 4, 0x29) mips/nlm/hal/xaui.h:#define XAUI_STATS_RMCA(block) NAE_REG(block, 4, 0x2a) mips/nlm/hal/xaui.h:#define XAUI_STATS_RBCA(block) NAE_REG(block, 4, 0x2b) mips/nlm/hal/xaui.h:#define XAUI_STATS_RXCF(block) NAE_REG(block, 4, 0x2c) mips/nlm/hal/xaui.h:#define XAUI_STATS_RXPF(block) NAE_REG(block, 4, 0x2d) mips/nlm/hal/xaui.h:#define XAUI_STATS_RXUO(block) NAE_REG(block, 4, 0x2e) mips/nlm/hal/xaui.h:#define XAUI_STATS_RALN(block) NAE_REG(block, 4, 0x2f) mips/nlm/hal/xaui.h:#define XAUI_STATS_RFLR(block) NAE_REG(block, 4, 0x30) mips/nlm/hal/xaui.h:#define XAUI_STATS_RCDE(block) NAE_REG(block, 4, 0x31) mips/nlm/hal/xaui.h:#define XAUI_STATS_RCSE(block) NAE_REG(block, 4, 0x32) mips/nlm/hal/xaui.h:#define XAUI_STATS_RUND(block) NAE_REG(block, 4, 0x33) mips/nlm/hal/xaui.h:#define XAUI_STATS_ROVR(block) NAE_REG(block, 4, 0x34) mips/nlm/hal/xaui.h:#define XAUI_STATS_RFRG(block) NAE_REG(block, 4, 0x35) mips/nlm/hal/xaui.h:#define XAUI_STATS_RJBR(block) NAE_REG(block, 4, 0x36) mips/nlm/hal/xaui.h:#define XAUI_STATS_TBYT(block) NAE_REG(block, 4, 0x38) mips/nlm/hal/xaui.h:#define XAUI_STATS_TPKT(block) NAE_REG(block, 4, 0x39) mips/nlm/hal/xaui.h:#define XAUI_STATS_TMCA(block) NAE_REG(block, 4, 0x3a) mips/nlm/hal/xaui.h:#define XAUI_STATS_TBCA(block) NAE_REG(block, 4, 0x3b) mips/nlm/hal/xaui.h:#define XAUI_STATS_TXPF(block) NAE_REG(block, 4, 0x3c) mips/nlm/hal/xaui.h:#define XAUI_STATS_TDFR(block) NAE_REG(block, 4, 0x3d) mips/nlm/hal/xaui.h:#define XAUI_STATS_TEDF(block) NAE_REG(block, 4, 0x3e) mips/nlm/hal/xaui.h:#define XAUI_STATS_TSCL(block) NAE_REG(block, 4, 0x3f) mips/nlm/hal/xaui.h:#define XAUI_STATS_TMCL(block) NAE_REG(block, 4, 0x40) mips/nlm/hal/xaui.h:#define XAUI_STATS_TLCL(block) NAE_REG(block, 4, 0x41) mips/nlm/hal/xaui.h:#define XAUI_STATS_TXCL(block) NAE_REG(block, 4, 0x42) mips/nlm/hal/xaui.h:#define XAUI_STATS_TNCL(block) NAE_REG(block, 4, 0x43) mips/nlm/hal/xaui.h:#define XAUI_STATS_TJBR(block) NAE_REG(block, 4, 0x46) mips/nlm/hal/xaui.h:#define XAUI_STATS_TFCS(block) NAE_REG(block, 4, 0x47) mips/nlm/hal/xaui.h:#define XAUI_STATS_TXCF(block) NAE_REG(block, 4, 0x48) mips/nlm/hal/xaui.h:#define XAUI_STATS_TOVR(block) NAE_REG(block, 4, 0x49) mips/nlm/hal/xaui.h:#define XAUI_STATS_TUND(block) NAE_REG(block, 4, 0x4a) mips/nlm/hal/xaui.h:#define XAUI_STATS_TFRG(block) NAE_REG(block, 4, 0x4b) mips/nlm/hal/xaui.h:#define XAUI_NETIOR_RX_ABORT_DROP_COUNT(block) NAE_REG(block, 4, 0x77) mips/nlm/hal/xaui.h:#define XAUI_NETIOR_MACCTRL_PAUSE_QUANTA(block) NAE_REG(block, 4, 0x78) mips/nlm/hal/xaui.h:#define XAUI_NETIOR_MACCTRL_OPCODE(block) NAE_REG(block, 4, 0x79) mips/nlm/hal/xaui.h:#define XAUI_NETIOR_MAC_DA_H(block) NAE_REG(block, 4, 0x7a) mips/nlm/hal/xaui.h:#define XAUI_NETIOR_MAC_DA_L(block) NAE_REG(block, 4, 0x7b) mips/nlm/hal/xaui.h:#define XAUI_NETIOR_XGMAC_STAT(block) NAE_REG(block, 4, 0x7c) mips/rmi/dev/nlge/if_nlge.h:#define NLGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) mips/rmi/dev/nlge/if_nlge.h:#define NLGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED) mips/rmi/dev/sec/rmilib.h:#define OS_ALLOC_KERNEL(size) kmalloc((size), GFP_KERNEL) mips/rmi/dev/xlr/debug.h:#define dbg_msg(fmt, args...) printf(fmt, ##args) mips/rmi/dev/xlr/debug.h:#define dbg_panic(fmt, args...) panic(fmt, ##args) mips/rmi/msgring.h:#define msgrng_read_config() read_c2_register32(MSGRNG_MSG_CONFIG_REG, 0) mips/rmi/msgring.h:#define msgrng_read_bucksize(b) read_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, b) mips/rmi/msgring.h:#define msgrng_read_cc(r, s) read_c2_register32(r, s) mips/rmi/pic.h:#define PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) && \ mips/rt305x/rt305xreg.h:#define GDMASA(n) (0x00 + 0x10*n) mips/rt305x/rt305xreg.h:#define GDMADA(n) (0x04 + 0x10*n) net/altq/altq_cdnr.c:#define TB_UNSCALE(x) ((x) >> TB_SHIFT) net/altq/altq_classq.h:#define q_is_red_or_rio(q) ((q)->qtype_ == Q_RED || (q)->qtype_ == Q_RIO) net/altq/altq_codel.c:#define codel_time_before_eq(a, b) ((int64_t)(a) - (int64_t)(b) <= 0) net/altq/altq_red.c:#define FV_FSCALE(x) ((x) << FV_FSHIFT) net/altq/if_altq.h:#define ALTQ_NEEDS_CLASSIFY(ifq) ((ifq)->altq_flags & ALTQF_CLASSIFY) net/altq/if_altq.h:#define ALTQ_IS_EMPTY(ifq) ((ifq)->ifq_len == 0) net/bpf.h:#define BPF_T_FLAG(t) ((t) & BPF_T_FLAG_MASK) net/bpf.h:#define BPF_SIZE(code) ((code) & 0x18) net/bpf.h:#define BPF_MODE(code) ((code) & 0xe0) net/bpf.h:#define BPF_SRC(code) ((code) & 0x08) net/bpf.h:#define BPF_RVAL(code) ((code) & 0x18) net/bpf.h:#define BPF_MISCOP(code) ((code) & 0xf8) net/bpf.h:#define BPF_JUMP(code, k, jt, jf) { (u_short)(code), jt, jf, k } net/dlt.h:#define DLT_NETBSD_RAWAF(af) (DLT_CLASS_NETBSD_RAWAF | (af)) net/dlt.h:#define DLT_NETBSD_RAWAF_AF(x) ((x) & 0x0000ffff) net/dlt.h:#define DLT_IS_NETBSD_RAWAF(x) (DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF) net/ethernet.h:#define ETHER_IS_VALID_LEN(foo) \ net/if.h:#define IF_MSGHDRL_IFM_DATA(_l) \ net/if.h:#define IF_MSGHDRL_RTA(_l) \ net/if.h:#define IFA_MSGHDRL_IFAM_DATA(_l) \ net/if.h:#define IFA_MSGHDRL_RTA(_l) \ net/if.h:#define _SIZEOF_ADDR_IFREQ(ifr) \ net/if_arp.h:#define ARPSTAT_DEC(name) ARPSTAT_SUB(name, 1) net/if_clone.c:#define IF_CLONERS_LOCK_ASSERT() mtx_assert(&if_cloners_mtx, MA_OWNED) net/if_dl.h:#define LLINDEX(s) ((s)->sdl_index) net/if_gif.h:#define GIF_WLOCK_ASSERT(sc) rm_assert(&(sc)->gif_lock, RA_WLOCKED) net/if_gre.h:#define GRE_RLOCK_ASSERT(sc) rm_assert(&(sc)->gre_lock, RA_RLOCKED) net/if_ipsec.c:#define IPSEC_RLOCK_ASSERT(sc) rm_assert(&(sc)->lock, RA_RLOCKED) net/if_ipsec.c:#define IPSEC_WLOCK_ASSERT(sc) rm_assert(&(sc)->lock, RA_WLOCKED) net/if_ipsec.c:#define IPSEC_SC_WLOCK_ASSERT() rm_assert(&ipsec_sc_lock, RA_WLOCKED) net/if_lagg.h:#define LAGG_RLOCK_ASSERT(_sc) rm_assert(&(_sc)->sc_mtx, RA_RLOCKED) net/if_lagg.h:#define LAGG_SLOCK_ASSERT(_sc) sx_assert(&(_sc)->sc_sx, SA_SLOCKED) net/if_llatbl.h:#define LLE_DOWNGRADE(lle) rw_downgrade(&(lle)->lle_lock) net/if_llatbl.h:#define LLE_TRY_UPGRADE(lle) rw_try_upgrade(&(lle)->lle_lock) net/if_llatbl.h:#define LLE_IS_VALID(lle) (((lle) != NULL) && ((lle) != (void *)-1)) net/if_llatbl.h:#define LLATBL_HASH(key, mask) \ net/if_me.c:#define ME_RLOCK_ASSERT(sc) rm_assert(&(sc)->me_lock, RA_RLOCKED) net/if_me.c:#define ME_WLOCK_ASSERT(sc) rm_assert(&(sc)->me_lock, RA_WLOCKED) net/if_media.h:#define IFM_ETHER_IS_EXTENDED(x) ((x) & IFM_ETH_XTYPE) net/if_media.h:#define IFM_TYPE_OPTIONS(x) ((x) & IFM_OMASK) net/if_media.h:#define IFM_MAKEMODE(mode) \ net/if_media.h:#define IFM_STATUS_DESC(ifms, bit) \ net/if_spppsubr.c:#define SPPP_LOCK_ASSERT(sp) mtx_assert (&(sp)->mtx, MA_OWNED) net/if_var.h:#define IF_AFDATA_TRYLOCK(ifp) rw_try_wlock(&(ifp)->if_afdata_lock) net/if_var.h:#define IF_AFDATA_RLOCK_ASSERT(ifp) rw_assert(&(ifp)->if_afdata_lock, RA_RLOCKED) net/if_var.h:#define IFNET_RLOCK_NOSLEEP_ASSERT() rw_assert(&ifnet_rwlock, RA_RLOCKED) net/if_vlan.c:#define VLAN_RLOCK_ASSERT() rm_assert(&_VLAN_RM_ID, RA_RLOCKED) net/if_vlan.c:#define VLAN_SLOCK_ASSERT() sx_assert(&_VLAN_SX_ID, SA_SLOCKED) net/if_vlan.c:#define TRUNK_LOCK_ASSERT(trunk) rm_assert(&(trunk)->lock, RA_LOCKED) net/if_vlan_var.h:#define EVL_APPLY_VLID(m, vlid) \ net/if_vlan_var.h:#define EVL_APPLY_PRI(m, pri) \ net/if_vxlan.c:#define VXLAN_SO_LOCK_WASSERT(_vso) \ net/iflib.c:#define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) net/iflib.c:#define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) net/iflib.c:#define TXQ_MAX_DB_CONSUMED(size) (size >> 4) net/iflib.h:#define PVID_OEM(vendor, devid, svid, sdevid, revid, name) {vendor, devid, svid, sdevid, revid, 0, name} net/ifq.h:#define IF_DEQUEUE_ALL(ifq, m) do { \ net/ifq.h:#define IF_POLL(ifq, m) _IF_POLL(ifq, m) net/ifq.h:#define IFQ_POLL(ifq, m) \ net/ifq.h:#define IFQ_DRV_PURGE(ifq) \ net/netmap.h:#define NS_RFRAGS(_slot) ( ((_slot)->flags >> 8) & 0xff) net/netmap_user.h:#define NETMAP_BUF_IDX(ring, buf) \ net/netmap_user.h:#define NETMAP_FD(d) (P2NMD(d)->fd) net/pfkeyv2.h:#define PFKEY_ADDR_PREFIX(ext) \ net/pfkeyv2.h:#define PFKEY_ADDR_PROTO(ext) \ net/pfvar.h:#define HTONL(x) (x) = htonl((__uint32_t)(x)) net/pfvar.h:#define PF_OSFP_PACK(osfp, class, version, subtype) do { \ net/pfvar.h:#define pf_state_counter_from_pfsync(s) \ net/pfvar.h:#define pf_state_counter_ntoh(s,d) do { \ net/ppp_defs.h:#define PPP_ADDRESS(p) (((u_char *)(p))[0]) net/ppp_defs.h:#define PPP_CONTROL(p) (((u_char *)(p))[1]) net/ppp_defs.h:#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) net/radix.h:#define RADIX_NODE_HEAD_LOCK_TRY_UPGRADE(rnh) rw_try_upgrade(&(rnh)->rnh_lock) net/radix.h:#define RADIX_NODE_HEAD_LOCK_ASSERT(rnh) rw_assert(&(rnh)->rnh_lock, RA_LOCKED) net/radix.h:#define RADIX_NODE_HEAD_WLOCK_ASSERT(rnh) rw_assert(&(rnh)->rnh_lock, RA_WLOCKED) net/route_var.h:#define RIB_WLOCK_ASSERT(rh) rw_assert(&(rh)->rib_lock, RA_WLOCKED) net/rtsock.c:#define RTSOCK_LOCK_ASSERT() mtx_assert(&rtsock_mtx, MA_OWNED) net/vnet.h:#define VNET_PCPUSTAT_FETCH(type, name, f) \ net/vnet.h:#define _VNET(b, n) (*_VNET_PTR(b, n)) net80211/ieee80211.h:#define WME_UAPSD_MAXSP(_qosinfo) \ net80211/ieee80211.h:#define WME_UAPSD_AC_ENABLED(_ac, _qosinfo) \ net80211/ieee80211_freebsd.h:#define MESH_RT_ENTRY_LOCK_ASSERT(rt) mtx_assert(&(rt)->rt_lock, MA_OWNED) net80211/ieee80211_tdma.c:#define TDMA_VERSION_VALID(_version) \ netgraph/atm/sscop/ng_sscop_cust.h:#define SIGQ_EMPTY(Q) TAILQ_EMPTY(Q) netgraph/bluetooth/include/ng_bluetooth.h:#define NG_BT_ITEMQ_FIRST(q) STAILQ_FIRST(&(q)->queue) netgraph/bluetooth/include/ng_bluetooth.h:#define NG_BT_ITEMQ_PREPEND(q, i) \ netgraph/bluetooth/include/ng_btsocket_rfcomm.h:#define RFCOMM_CHANNEL(b) (((b) & 0xf8) >> 3) netgraph/bluetooth/include/ng_btsocket_rfcomm.h:#define RFCOMM_DIRECTION(b) (((b) & 0x04) >> 2) netgraph/bluetooth/include/ng_hci.h:#define NG_HCI_BC_FLAG(h) (((h) & 0xc000) >> 14) netgraph/netgraph.h:#define NG_FWD_MSG_HOOK(error, here, item, hook, retaddr) \ netgraph/netgraph.h:#define _NGI_META(i) NULL netgraph/netgraph.h:#define NGI_META(i) NULL netgraph/netgraph.h:#define ng_copy_meta(meta) NULL netgraph/ng_base.c:#define HEAD_IS_WRITER(QP) NGI_QUEUED_WRITER(STAILQ_FIRST(&(QP)->queue)) /* notused */ netgraph/ng_bridge.c:#define LINK_NUM(hook) (*(u_int16_t *)(&(hook)->private)) netgraph/ng_message.h:#define NG_GENERIC_MKPEER_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_CONNECT_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_NAME_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_RMHOOK_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_NODEINFO_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_LINKINFO_INFO(nitype) { \ netgraph/ng_message.h:#define NG_GENERIC_HOOKLIST_INFO(nitype,litype) { \ netgraph/ng_message.h:#define NG_GENERIC_LISTNODES_INFO(niarraytype) { \ netgraph/ng_message.h:#define NG_GENERIC_TYPEINFO_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_TYPELIST_INFO(tiarraytype) { \ netgraph/ng_message.h:#define NG_GENERIC_BANDWIDTH_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_QUEUE_INFO() { \ netgraph/ng_message.h:#define NG_GENERIC_FLOW_MANAGER_INFO() { \ netinet/cc/cc.h:#define CC_DATA(tp) ((tp)->ccv->cc_data) netinet/cc/cc.h:#define CC_LIST_LOCK_DESTROY() rw_destroy(&cc_list_lock) netinet/igmp.h:#define IGMP_QRESV(x) (((x) >> 4) & 0x0f) netinet/igmp.h:#define IGMP_SFLAG(x) (((x) >> 3) & 0x01) netinet/igmp_var.h:#define IGMP_UNLOCK_ASSERT() mtx_assert(&igmp_mtx, MA_NOTOWNED) netinet/in.h:#define IN_CLASSC(i) (((in_addr_t)(i) & 0xe0000000) == 0xc0000000) netinet/in.h:#define IN_BADCLASS(i) (((in_addr_t)(i) & 0xf0000000) == 0xf0000000) netinet/in.h:#define IN_ANY_LOCAL(i) (IN_LINKLOCAL(i) || IN_LOCAL_GROUP(i)) netinet/in_pcb.h:#define INP_TRY_RLOCK(inp) rw_try_rlock(&(inp)->inp_lock) netinet/in_pcb.h:#define INP_INFO_TRY_WLOCK(ipi) rw_try_wlock(&(ipi)->ipi_lock) netinet/in_pcb.h:#define INP_INFO_TRY_UPGRADE(ipi) rw_try_upgrade(&(ipi)->ipi_lock) netinet/in_pcb.h:#define INP_LIST_TRY_RLOCK(ipi) rw_try_rlock(&(ipi)->ipi_list_lock) netinet/in_pcb.h:#define INP_LIST_TRY_WLOCK(ipi) rw_try_wlock(&(ipi)->ipi_list_lock) netinet/in_pcb.h:#define INP_LIST_TRY_UPGRADE(ipi) rw_try_upgrade(&(ipi)->ipi_list_lock) netinet/in_pcb.h:#define INP_LIST_LOCK_ASSERT(ipi) \ netinet/in_pcb.h:#define INP_LIST_RLOCK_ASSERT(ipi) \ netinet/in_pcb.h:#define INP_LIST_UNLOCK_ASSERT(ipi) \ netinet/in_pcb.h:#define INP_GROUP_LOCK_ASSERT(ipg) mtx_assert(&(ipg)->ipg_lock, MA_OWNED) netinet/in_var.h:#define IA_DSTSIN(ia) (&(((struct in_ifaddr *)(ia))->ia_dstaddr)) netinet/in_var.h:#define IN_LNAOF(in, ifa) \ netinet/in_var.h:#define IN_IFADDR_LOCK_ASSERT() rm_assert(&in_ifaddr_lock, RA_LOCKED) netinet/in_var.h:#define IN_IFADDR_RLOCK_ASSERT() rm_assert(&in_ifaddr_lock, RA_RLOCKED) netinet/in_var.h:#define IN_IFADDR_WLOCK_ASSERT() rm_assert(&in_ifaddr_lock, RA_WLOCKED) netinet/in_var.h:#define IN_MULTI_UNLOCK_ASSERT() mtx_assert(&in_multi_mtx, MA_NOTOWNED) netinet/ip.h:#define IPOPT_CLASS(o) ((o)&0x60) netinet/ip.h:#define IPOPT_NUMBER(o) ((o)&0x1f) netinet/ip_mroute.c:#define MROUTER_LOCK_ASSERT() mtx_assert(&mrouter_mtx, MA_OWNED) netinet/ip_mroute.h:#define VIFM_SET(n, m) ((m) |= (1 << (n))) netinet/ip_mroute.h:#define VIFM_CLR(n, m) ((m) &= ~(1 << (n))) netinet/ip_mroute.h:#define VIFM_ISSET(n, m) ((m) & (1 << (n))) netinet/ip_mroute.h:#define VIFM_CLRALL(m) ((m) = 0x00000000) netinet/ip_mroute.h:#define VIFM_COPY(mfrom, mto) ((mto) = (mfrom)) netinet/ip_mroute.h:#define VIFM_SAME(m1, m2) ((m1) == (m2)) netinet/sctp_constants.h:#define IS_SCTP_DATA(a) (((a)->chunk_type == SCTP_DATA) || ((a)->chunk_type == SCTP_IDATA)) netinet/sctp_constants.h:#define SCTP_SSN_GT(a, b) SCTP_UINT16_GT(a, b) netinet/sctp_constants.h:#define SCTP_SSN_GE(a, b) SCTP_UINT16_GE(a, b) netinet/sctp_constants.h:#define sctp_sorwakeup_locked(inp, so) \ netinet/sctp_lock_bsd.h:#define SCTP_STATLOG_LOCK() netinet/sctp_lock_bsd.h:#define SCTP_STATLOG_UNLOCK() netinet/sctp_lock_bsd.h:#define SCTP_MCORE_QDESTROY(cpstr) do { \ netinet/sctp_lock_bsd.h:#define SCTP_MCORE_DESTROY(cpstr) do { \ netinet/sctp_lock_bsd.h:#define SCTP_IPI_ITERATOR_WQ_DESTROY() \ netinet/sctp_lock_bsd.h:#define SCTP_TCB_UNLOCK_IFOWNED(_tcb) do { \ netinet/sctp_lock_bsd.h:#define SCTP_ITERATOR_LOCK_DESTROY() mtx_destroy(&sctp_it_ctl.it_mtx) netinet/sctp_os_bsd.h:#define SCTP_BUF_RECVIF(m) ((m)->m_pkthdr.rcvif) netinet/sctp_os_bsd.h:#define SCTP_DETACH_HEADER_FROM_CHAIN(m) netinet/sctp_os_bsd.h:#define SCTP_RELEASE_HEADER(m) netinet/sctp_os_bsd.h:#define SCTP_IS_IT_LOOPBACK(m) ((m->m_flags & M_PKTHDR) && ((m->m_pkthdr.rcvif == NULL) || (m->m_pkthdr.rcvif->if_type == IFT_LOOP))) netinet/sctp_uio.h:#define PR_SCTP_VALID_POLICY(x) (PR_SCTP_POLICY(x) <= SCTP_PR_SCTP_MAX) netinet/sctp_var.h:#define sctp_is_mobility_feature_off(inp, feature) ((inp->sctp_mobility_features & feature) == 0) netinet/sctp_var.h:#define SCTP_PF_ENABLED(_net) (_net->pf_threshold < _net->failure_threshold) netinet/sctp_var.h:#define SCTP_NET_IS_PF(_net) (_net->pf_threshold < _net->error_count) netinet/tcp_timer.c:#define INP_CPU(inp) (per_cpu_timers ? (!CPU_ABSENT(((inp)->inp_flowid % (mp_maxid+1))) ? \ netinet/tcp_timewait.c:#define TW_LOCK_ASSERT(tw) rw_assert(&(tw), RA_LOCKED) netinet/tcp_timewait.c:#define TW_RLOCK_ASSERT(tw) rw_assert(&(tw), RA_RLOCKED) netinet/tcp_timewait.c:#define TW_WLOCK_ASSERT(tw) rw_assert(&(tw), RA_WLOCKED) netinet/tcp_timewait.c:#define TW_UNLOCK_ASSERT(tw) rw_assert(&(tw), RA_UNLOCKED) netinet/udp_var.h:#define sotoudpcb(so) (intoudpcb(sotoinpcb(so))) netinet6/in6_ifattach.c:#define IFID_LOCAL(in6) (!EUI64_LOCAL(in6)) netinet6/in6_src.c:#define ADDRSEL_LOCK_ASSERT() mtx_assert(&addrsel_lock, MA_OWNED) netinet6/ip6_mroute.h:#define IF_SET(n, p) ((p)->ifs_bits[(n)/NIFBITS] |= (1 << ((n) % NIFBITS))) netinet6/ip6_mroute.h:#define IF_CLR(n, p) ((p)->ifs_bits[(n)/NIFBITS] &= ~(1 << ((n) % NIFBITS))) netinet6/ip6_mroute.h:#define IF_COPY(f, t) bcopy(f, t, sizeof(*(f))) netinet6/ip6_mroute.h:#define IF_ZERO(p) bzero(p, sizeof(*(p))) netinet6/mld6.h:#define MLD_QRESV(x) (((x) >> 4) & 0x0f) netinet6/mld6.h:#define MLD_SFLAG(x) (((x) >> 3) & 0x01) netinet6/mld6_var.h:#define MLD_UNLOCK_ASSERT() mtx_assert(&mld_mtx, MA_NOTOWNED) netipsec/key.c:#define SPTREE_LOCK_DESTROY() rm_destroy(&sptree_lock) netipsec/key.c:#define SPTREE_RLOCK_ASSERT() rm_assert(&sptree_lock, RA_RLOCKED) netipsec/key.c:#define SAHTREE_LOCK_DESTROY() rm_destroy(&sahtree_lock) netipsec/key.c:#define SAHTREE_RLOCK_ASSERT() rm_assert(&sahtree_lock, RA_RLOCKED) netipsec/key.c:#define SAHTREE_WLOCK_ASSERT() rm_assert(&sahtree_lock, RA_WLOCKED) netipsec/key.c:#define REGTREE_LOCK_DESTROY() mtx_destroy(®tree_lock) netipsec/key.c:#define REGTREE_LOCK_ASSERT() mtx_assert(®tree_lock, MA_OWNED) netipsec/key.c:#define ACQ_LOCK_DESTROY() mtx_destroy(&acq_lock) netipsec/key.c:#define ACQ_LOCK_ASSERT() mtx_assert(&acq_lock, MA_OWNED) netipsec/key.c:#define SPACQ_LOCK_DESTROY() mtx_destroy(&spacq_lock) netipsec/key.c:#define SPACQ_LOCK_ASSERT() mtx_assert(&spacq_lock, MA_OWNED) netipsec/key.c:#define XFORMS_LOCK_DESTROY() mtx_destroy(&xforms_lock) netipsec/key.c:#define DBG_IPSEC_INITREF(t, p) do { \ netipsec/key.c:#define DBG_IPSEC_ADDREF(t, p) do { \ netipsec/key.c:#define DBG_IPSEC_DELREF(t, p) do { \ netipsec/key_var.h:#define _ARRAYLEN(p) (sizeof(p)/sizeof(p[0])) netipsec/keydb.h:#define SECASVAR_LOCK_ASSERT(_sav) mtx_assert((_sav)->lock, MA_OWNED) netpfil/ipfw/ip_dn_private.h:#define DN_UH_RLOCK() mtx_lock(&dn_cfg.uh_mtx) netpfil/ipfw/ip_dn_private.h:#define DN_UH_RUNLOCK() mtx_unlock(&dn_cfg.uh_mtx) netpfil/ipfw/ip_dn_private.h:#define DN_UH_WLOCK() mtx_lock(&dn_cfg.uh_mtx) netpfil/ipfw/ip_dn_private.h:#define DN_UH_WUNLOCK() mtx_unlock(&dn_cfg.uh_mtx) netpfil/ipfw/ip_dn_private.h:#define DN_UH_LOCK_ASSERT() mtx_assert(&dn_cfg.uh_mtx, MA_OWNED) netpfil/ipfw/ip_dn_private.h:#define DN_BH_RLOCK() mtx_lock(&dn_cfg.uh_mtx) netpfil/ipfw/ip_dn_private.h:#define DN_BH_RUNLOCK() mtx_unlock(&dn_cfg.uh_mtx) netpfil/ipfw/ip_dn_private.h:#define DN_BH_LOCK_ASSERT() mtx_assert(&dn_cfg.uh_mtx, MA_OWNED) netpfil/ipfw/nat64/nat64lsn.h:#define CHT_UNLOCK_BUCK(_ph, _PX, _buck) \ netpfil/ipfw/nat64/nat64lsn.h:#define CHT_UNLOCK_KEY(_ph, _hsize, _PX, _key) do { \ netpfil/ipfw/nat64/nat64lsn.h:#define CHT_RESIZE(_ph, _hsize, _nph, _nhsize, _PX, _x, _y) do { \ netsmb/smb_conn.h:#define SMBC_ST_LOCK(vcp) smb_sl_lock(&(vcp)->vc_stlock) netsmb/smb_conn.h:#define SMBC_ST_UNLOCK(vcp) smb_sl_unlock(&(vcp)->vc_stlock) netsmb/smb_subr.h:#define SMBPANIC(format, args...) printf("%s: "format, __func__ ,## args) netsmb/smb_tran.h:#define SMB_TRAN_TIMO(vcp) (vcp)->vc_tdesc->tr_timo(vcp) netsmb/smb_tran.h:#define SMB_TRAN_INTR(vcp) (vcp)->vc_tdesc->tr_intr(vcp) nfs/nfs_common.h:#define nfsm_strsiz(s,m) \ nfs/nfs_common.h:#define nfsm_mtouio(p,s) \ nfs/nfs_common.h:#define nfsm_rndup(a) (((a)+3)&(~0x3)) nfs/nfs_common.h:#define nfsm_adv(s) \ nfs/nfsproto.h:#define NFSX_SRVFH(v3) ((v3) ? NFSX_V3FH : NFSX_V2FH) nfs/nfsproto.h:#define NFSX_PREOPATTR(v3) ((v3) ? (7 * NFSX_UNSIGNED) : 0) nfs/nfsproto.h:#define NFSX_POSTOPATTR(v3) ((v3) ? (NFSX_V3FATTR + NFSX_UNSIGNED) : 0) nfs/nfsproto.h:#define NFSX_POSTOPORFATTR(v3) ((v3) ? (NFSX_V3FATTR + NFSX_UNSIGNED) : \ nfs/nfsproto.h:#define NFSX_WCCDATA(v3) ((v3) ? NFSX_V3WCCDATA : 0) nfs/nfsproto.h:#define NFSX_WCCORFATTR(v3) ((v3) ? NFSX_V3WCCDATA : NFSX_V2FATTR) nfs/nfsproto.h:#define NFSX_COOKIEVERF(v3) ((v3) ? NFSX_V3COOKIEVERF : 0) nfs/nfsproto.h:#define NFSX_WRITEVERF(v3) ((v3) ? NFSX_V3WRITEVERF : 0) nfs/nfsproto.h:#define NFSX_READDIR(v3) ((v3) ? (5 * NFSX_UNSIGNED) : \ nfsclient/nfs.h:#define NFS_SIGREP(rep) nfs_sigintr((rep)->r_nmp, (rep), (rep)->r_td) nfsclient/nfsm_subs.h:#define nfsm_uiotom(p, s) \ nfsclient/nfsm_subs.h:#define nfsm_request(v, t, p, c) \ nfsclient/nfsm_subs.h:#define nfsm_mtofh(d, v, v3, f) \ nfsclient/nfsm_subs.h:#define nfsm_postop_attr(v, f) \ nfsclient/nfsm_subs.h:#define nfsm_postop_attr_va(v, f, va) \ nfsserver/nfs.h:#define NFSD_LOCK_DONTCARE() nfsserver/nfs.h:#define NWDELAYHASH(sock, f) \ nfsserver/nfsm_subs.h:#define nfsm_srvstrsiz(s, m) \ nfsserver/nfsm_subs.h:#define nfsm_srvnamesiz(s) \ nfsserver/nfsm_subs.h:#define nfsm_srvpathsiz(s) \ nfsserver/nfsm_subs.h:#define nfsm_srvmtofh(f) \ nfsserver/nfsm_subs.h:#define nfsm_srvsattr(a) \ nfsserver/nfsm_subs.h:#define nfsm_writereply(s) \ nfsserver/nfsm_subs.h:#define nfsm_srvfhtom(f, v3) \ nfsserver/nfsm_subs.h:#define nfsm_srvpostop_fh(f) \ nfsserver/nfsm_subs.h:#define nfsm_srvwcc_data(br, b, ar, a) \ nfsserver/nfsm_subs.h:#define nfsm_srvpostop_attr(r, a) \ nfsserver/nfsm_subs.h:#define nfsm_srvfillattr(a, f) \ ofed/drivers/infiniband/core/cma.c:#define cma_debug_path(priv, pfx, p) \ ofed/drivers/infiniband/core/cma.c:#define cma_debug_gid(priv, g) \ ofed/drivers/infiniband/core/sysfs.c:#define PORT_ATTR(_name, _mode, _show, _store) \ ofed/drivers/infiniband/ulp/sdp/sdp.h:#define SDP_RLOCK_ASSERT(ssk) rw_assert(&(ssk)->lock, RA_RLOCKED) ofed/drivers/infiniband/ulp/sdp/sdp.h:#define SDP_LOCK_ASSERT(ssk) rw_assert(&(ssk)->lock, RA_LOCKED) ofed/drivers/infiniband/ulp/sdp/sdp.h:#define SDPSTATS_COUNTER_ADD(stat, val) ofed/drivers/infiniband/ulp/sdp/sdp_dbg.h:#define __sock_put(sk, msg) sock_ref(sk, msg, __sock_put) ofed/drivers/infiniband/ulp/sdp/sdp_main.c:#define SDP_LIST_WLOCK_ASSERT() rw_assert(&sdp_lock, RW_WLOCKED) ofed/drivers/infiniband/ulp/sdp/sdp_main.c:#define SDP_LIST_RLOCK_ASSERT() rw_assert(&sdp_lock, RW_RLOCKED) ofed/drivers/infiniband/ulp/sdp/sdp_main.c:#define SDP_LIST_LOCK_ASSERT() rw_assert(&sdp_lock, RW_LOCKED) ofed/include/rdma/ib_user_verbs.h:#define IBV_RESP_TO_VERBS_RESP_EX(ex_ptr, ex_type, ibv_type) \ opencrypto/cryptodev.h:#define CRYPTO_ALGO_VALID(x) ((x) >= CRYPTO_ALGORITHM_MIN && \ powerpc/aim/mmu_oea.c:#define VSID_TO_SR(vsid) ((vsid) & 0xf) powerpc/aim/mmu_oea64.c:#define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) powerpc/include/openpicreg.h:#define OPENPIC_PCPU_WHOAMI(cpu) \ powerpc/include/param.h:#define powerpc_ptob(x) ((x) << PAGE_SHIFT) powerpc/include/pmap.h:#define PVO_VSID(pvo) ((pvo)->pvo_vpn >> 16) powerpc/include/pmc_mdep.h:#define PMLCbx_TRIGONCTL(x) ((x) << 28) powerpc/include/pmc_mdep.h:#define PMLCbx_TRIGOFFCTL(x) ((x) << 24) powerpc/include/pmc_mdep.h:#define PMLCbx_PMP(x) ((x) << 13) powerpc/include/pmc_mdep.h:#define PMLCbx_TREHMUL(x) ((x) << 8) powerpc/include/pmc_mdep.h:#define PMLCbx_TRESHOLD(x) ((x) << 0) powerpc/include/pmc_mdep.h:#define PMGC_TBSEL(x) ((x) << 11) powerpc/include/pte.h:#define PTE_PS_DIRECT(ps) (ps<> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK) powerpc/include/pte.h:#define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT) powerpc/include/spr.h:#define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ powerpc/include/spr.h:#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ powerpc/include/spr.h:#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ powerpc/include/spr.h:#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ powerpc/include/trap.h:#define EXC_ALI_RA(dsisr) (dsisr & 0x1f) powerpc/mambo/mambo_disk.c:#define MBODISK_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); powerpc/mambo/mambo_disk.c:#define MBODISK_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); powerpc/mpc85xx/fsl_diu.c:#define DIU_COLORBARn_R(x) ((x & 0xff) << 16) powerpc/mpc85xx/fsl_diu.c:#define DIU_COLORBARn_G(x) ((x & 0xff) << 8) powerpc/mpc85xx/fsl_diu.c:#define DIU_COLORBARn_B(x) ((x & 0xff) << 0) riscv/include/param.h:#define riscv_btop(x) ((unsigned long)(x) >> PAGE_SHIFT) riscv/include/param.h:#define riscv_ptob(x) ((unsigned long)(x) << PAGE_SHIFT) riscv/include/riscv_opcode.h:#define RISCV_OPCODE(r) (r & 0x7f) riscv/include/riscvreg.h:#define csr_swap(csr, val) \ riscv/include/riscvreg.h:#define csr_write(csr, val) \ riscv/include/riscvreg.h:#define csr_read(csr) \ riscv/riscv/timer.c:#define TIMER_MTIMECMP(cpu) (cpu * 8) rpc/auth.h:#define AUTH_NEXTVERF(auth) \ rpc/auth.h:#define authsys_create(c,i1,i2,i3,ip) authunix_create((c),(i1),(i2),(i3),(ip)) rpc/auth.h:#define authsys_create_default() authunix_create_default() rpc/clnt.h:#define IS_UNRECOVERABLE_RPC(s) (((s) == RPC_AUTHERROR) || \ rpc/clnt.h:#define clnt_abort(rh) ((*(rh)->cl_ops->cl_abort)(rh)) rpc/clnt.h:#define clnt_freeres(rh,xres,resp) ((*(rh)->cl_ops->cl_freeres)(rh,xres,resp)) rpc/rpcm_subs.h:#define rpcm_build(a,c,s) \ rpc/rpcm_subs.h:#define rpcm_dissect(a, c, s) \ rpc/rpcm_subs.h:#define rpcm_mtouio(p,s) \ rpc/rpcm_subs.h:#define rpcm_rndup(a) (((a)+3)&(~0x3)) rpc/rpcm_subs.h:#define rpcm_adv(s) \ rpc/rpcm_subs.h:#define RPCMADV(m, s) (m)->m_data += (s) rpc/svc.c:#define version_keepquiet(xp) (SVC_EXT(xp)->xp_flags & SVC_VERSQUIET) rpc/svc.h:#define svc_recv(xprt, msg) \ rpc/svc.h:#define svc_stat(xprt) \ rpc/svc.h:#define svc_reply(xprt, msg) \ rpc/svc.h:#define SVC_FREEARGS(xprt, xargs, argsp) \ rpc/svc.h:#define SVC_AUTH(xprt) \ rpc/xdr.h:#define xdr_getbytes(xdrs, addr, len) \ rpc/xdr.h:#define xdr_putbytes(xdrs, addr, len) \ rpc/xdr.h:#define xdr_inline(xdrs, len) \ rpc/xdr.h:#define xdr_rpcvers(xdrs, versp) xdr_uint32_t(xdrs, versp) rpc/xdr.h:#define xdr_rpcprog(xdrs, progp) xdr_uint32_t(xdrs, progp) rpc/xdr.h:#define xdr_rpcproc(xdrs, procp) xdr_uint32_t(xdrs, procp) rpc/xdr.h:#define xdr_rpcprot(xdrs, protp) xdr_uint32_t(xdrs, protp) rpc/xdr.h:#define xdr_rpcport(xdrs, portp) xdr_uint32_t(xdrs, portp) rpc/xdr.h:#define IXDR_GET_BOOL(buf) ((bool_t)IXDR_GET_LONG(buf)) rpc/xdr.h:#define IXDR_GET_U_LONG(buf) ((u_long)IXDR_GET_LONG(buf)) rpc/xdr.h:#define IXDR_GET_SHORT(buf) ((short)IXDR_GET_LONG(buf)) rpc/xdr.h:#define IXDR_GET_U_SHORT(buf) ((u_short)IXDR_GET_LONG(buf)) rpc/xdr.h:#define IXDR_PUT_BOOL(buf, v) IXDR_PUT_LONG((buf), (v)) rpc/xdr.h:#define IXDR_PUT_U_LONG(buf, v) IXDR_PUT_LONG((buf), (v)) rpc/xdr.h:#define IXDR_PUT_SHORT(buf, v) IXDR_PUT_LONG((buf), (v)) rpc/xdr.h:#define IXDR_PUT_U_SHORT(buf, v) IXDR_PUT_LONG((buf), (v)) security/audit/audit_pipe.c:#define AUDIT_PIPE_SX_XLOCK_ASSERT(ap) sx_assert(&(ap)->ap_sx, SA_XLOCKED) security/mac_test/mac_test.c:#define LABEL_NOTFREE(label) do { \ sparc64/include/asmacros.h:#define ATOMIC_DEC_INT(r1, r2, r3) \ sparc64/include/asmacros.h:#define ATOMIC_INC_INT(r1, r2, r3) \ sparc64/include/asmacros.h:#define ATOMIC_INC_LONG(r1, r2, r3) \ sparc64/include/asmacros.h:#define ATOMIC_CLEAR_INT(r1, r2, r3, bits) \ sparc64/include/asmacros.h:#define ATOMIC_LOAD_INT(r1, val) \ sparc64/include/asmacros.h:#define ATOMIC_SET_INT(r1, r2, r3, bits) \ sparc64/include/asmacros.h:#define ATOMIC_STORE_INT(r1, r2, r3, val) \ sparc64/include/cpufunc.h:#define rdtickcmpr() rd(asr23) sparc64/include/cpufunc.h:#define rdstickcmpr() rd(asr25) sparc64/include/fsr.h:#define FSR_CEXC(b) ((unsigned long)(b) << FSR_CEXC_SHIFT) sparc64/include/fsr.h:#define FSR_GET_CEXC(x) (((x) & FSR_CEXC_MASK) >> FSR_CEXC_SHIFT) sparc64/include/fsr.h:#define FSR_AEXC(b) ((unsigned long)(b) << FSR_AEXC_SHIFT) sparc64/include/fsr.h:#define FSR_GET_AEXC(x) (((x) & FSR_AEXC_MASK) >> FSR_AEXC_SHIFT) sparc64/include/fsr.h:#define FSR_TEM(b) ((unsigned long)(b) << FSR_TEM_SHIFT) sparc64/include/fsr.h:#define FSR_GET_TEM(x) (((x) & FSR_TEM_MASK) >> FSR_TEM_SHIFT) sparc64/include/fsr.h:#define FSR_FTT(x) ((unsigned long)(x) << FSR_FTT_SHIFT) sparc64/include/fsr.h:#define FSR_GET_FTT(x) (((x) & FSR_FTT_MASK) >> FSR_FTT_SHIFT) sparc64/include/fsr.h:#define FSR_GET_VER(x) (((x) >> FSR_VER_SHIFT) & 7) sparc64/include/fsr.h:#define FSR_RD(x) ((unsigned long)(x) << FSR_RD_SHIFT) sparc64/include/fsr.h:#define FSR_GET_RD(x) (((x) & FSR_RD_MASK) >> FSR_RD_SHIFT) sparc64/include/instr.h:#define EIF_SIMM(x, w) IF_EIMM((x), (w)) sparc64/include/instr.h:#define INSFPdq_RN(rn) (((rn) & ~1) | (((rn) & 1) << 5)) sparc64/include/instr.h:#define IFCC_FCC(c) ((c) & 3) sparc64/include/instr.h:#define IFCC_GET_FCC(c) ((c) & 3) sparc64/include/instr.h:#define IFCC_ISFCC(c) (((c) & 4) == 0) sparc64/include/tlb.h:#define MMU_SFSR_GET_FT(sfsr) \ sparc64/include/tlb.h:#define MMU_SFSR_GET_CT(sfsr) \ sparc64/include/tstate.h:#define TSTATE_CWP(x) ((x & TSTATE_CWP_MASK) >> TSTATE_CWP_SHIFT) sparc64/include/tstate.h:#define TSTATE_ASI(x) ((x & TSTATE_ASI_MASK) >> TSTATE_ASI_SHIFT) sparc64/pci/fire.c:#define FIRE_CTRL_BARRIER(sc, offs, len, flags) \ sparc64/pci/ofw_pci.h:#define OFW_PCI_RANGE_CHILD(r) \ sparc64/pci/ofw_pci.h:#define OFW_PCI_RANGE_SIZE(r) \ sparc64/pci/psychoreg.h:#define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) sparc64/pci/schizo.c:#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ sparc64/sbus/sbusreg.h:#define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off)) sparc64/sparc64/elf_machdep.c:#define RELOC_USE_ADDEND(t) ((reloc_target_flags[t] & _RF_A) != 0) sparc64/sparc64/elf_machdep.c:#define RELOC_USE_TLS_DOFF(t) ((reloc_target_flags[t] & _RF_D) != 0) sparc64/sparc64/elf_machdep.c:#define RELOC_USE_TLS_OFF(t) ((reloc_target_flags[t] & _RF_O) != 0) sparc64/sparc64/elf_machdep.c:#define RELOC_USE_TLS_ID(t) ((reloc_target_flags[t] & _RF_I) != 0) sparc64/sparc64/jbusppm.c:#define JBUSPPM_WRITE(sc, reg, off, val) \ sparc64/sparc64/schppm.c:#define SCHPPM_WRITE(sc, reg, off, val) \ sys/agpio.h:#define AGP_MODE_GET_AGP(x) (((x) & 0x00000100U) >> 8) sys/ata.h:#define ATA_ACOUSTIC_CURRENT(x) ((x) & 0x00ff) sys/ata.h:#define ATA_ACOUSTIC_VENDOR(x) (((x) & 0xff00) >> 8) sys/bitset.h:#define BIT_XOR(_s, d, s) do { \ sys/bitset.h:#define BIT_FLS(_s, p) __extension__ ({ \ sys/buf.h:#define BUF_LOCKFREE(bp) \ sys/bufobj.h:#define ASSERT_BO_UNLOCKED(bo) rw_assert(BO_LOCKPTR((bo)), RA_UNLOCKED) sys/callout.h:#define callout_schedule_curcpu(c, on_tick) \ sys/capsicum.h:#define cap_rights_clear(...) \ sys/capsicum.h:#define cap_rights_get(fd, rights) \ sys/cdefs.h:#define __locks_exclusive(...) \ sys/cdefs.h:#define __locks_shared(...) \ sys/cdefs.h:#define __trylocks_exclusive(...) \ sys/cdefs.h:#define __trylocks_shared(...) \ sys/cdefs.h:#define __unlocks(...) __lock_annotate(unlock_function(__VA_ARGS__)) sys/cdefs.h:#define __asserts_exclusive(...) \ sys/cdefs.h:#define __asserts_shared(...) \ sys/cdefs.h:#define __requires_exclusive(...) \ sys/cdefs.h:#define __requires_shared(...) \ sys/cdefs.h:#define __requires_unlocked(...) \ sys/cdefs.h:#define __guarded_by(x) __lock_annotate(guarded_by(x)) sys/cdefs.h:#define __pt_guarded_by(x) __lock_annotate(pt_guarded_by(x)) sys/cpuset.h:#define CPU_AND_ATOMIC(n, p) BIT_AND_ATOMIC(CPU_SETSIZE, n, p) sys/elf_common.h:#define VER_DEF_IDX(x) VER_NDX(x) sys/elf_common.h:#define VER_NEED_IDX(x) VER_NDX(x) sys/fail.h:#define FAIL_POINT_IS_OFF(fp) (__predict_true((fp)->fp_setting == NULL) || \ sys/fail.h:#define KFAIL_POINT_RETURN_VOID(parent, name) \ sys/fail.h:#define KFAIL_POINT_GOTO(parent, name, error_var, label) \ sys/fail.h:#define KFAIL_POINT_SLEEP_CALLBACKS(parent, name, pre_func, pre_arg, \ sys/fail.h:#define KFAIL_POINT_CODE_FLAGS(parent, name, flags, code...) \ sys/fail.h:#define KFAIL_POINT_CODE_COND(parent, name, cond, flags, code...) \ sys/fbio.h:#define FBTYPE_GET_STRIDE(_fb) ((_fb)->fb_size / (_fb)->fb_height) sys/hhook.h:#define HHOOKS_RUN_LOOKUP_IF(hhook_type, hhook_id, ctx_data, hosd) do { \ sys/iconv.h:#define KICONV_CES(name,size) \ sys/imgact_aout.h:#define N_GETFLAG(ex) \ sys/imgact_aout.h:#define N_SETMAGIC_NET(ex,mag,mid,flag) \ sys/imgact_aout.h:#define N_BADMAG(ex) \ sys/imgact_aout.h:#define N_DATADDR(ex) \ sys/imgact_aout.h:#define N_STROFF(ex) (N_SYMOFF(ex) + le32toh((ex).a_syms)) sys/kernel.h:#define TUNABLE_LONG(path, var) \ sys/link_aout.h:#define LD_VERSION_NZLIST_P(v) ((v) >= 8) sys/link_aout.h:#define LD_GOT(x) ((x)->d_un.d_sdt->sdt_got) sys/link_aout.h:#define LD_PLT(x) ((x)->d_un.d_sdt->sdt_plt) sys/link_aout.h:#define LD_REL(x) ((x)->d_un.d_sdt->sdt_rel) sys/link_aout.h:#define LD_SYMBOL(x) ((x)->d_un.d_sdt->sdt_nzlist) sys/link_aout.h:#define LD_HASH(x) ((x)->d_un.d_sdt->sdt_hash) sys/link_aout.h:#define LD_STRINGS(x) ((x)->d_un.d_sdt->sdt_strings) sys/link_aout.h:#define LD_NEED(x) ((x)->d_un.d_sdt->sdt_sods) sys/link_aout.h:#define LD_BUCKETS(x) ((x)->d_un.d_sdt->sdt_buckets) sys/link_aout.h:#define LD_PATHS(x) ((x)->d_un.d_sdt->sdt_paths) sys/link_aout.h:#define LD_GOTSZ(x) ((x)->d_un.d_sdt->sdt_plt - (x)->d_un.d_sdt->sdt_got) sys/link_aout.h:#define LD_RELSZ(x) ((x)->d_un.d_sdt->sdt_hash - (x)->d_un.d_sdt->sdt_rel) sys/link_aout.h:#define LD_HASHSZ(x) ((x)->d_un.d_sdt->sdt_nzlist - (x)->d_un.d_sdt->sdt_hash) sys/link_aout.h:#define LD_STABSZ(x) ((x)->d_un.d_sdt->sdt_strings - (x)->d_un.d_sdt->sdt_nzlist) sys/link_aout.h:#define LD_PLTSZ(x) ((x)->d_un.d_sdt->sdt_plt_sz) sys/link_aout.h:#define LD_STRSZ(x) ((x)->d_un.d_sdt->sdt_str_sz) sys/link_aout.h:#define LD_TEXTSZ(x) ((x)->d_un.d_sdt->sdt_text_sz) sys/link_aout.h:#define HH_BADMAG(hdr) ((hdr).hh_magic != HH_MAGIC) sys/linker_set.h:#define BSS_SET(set, sym) __MAKE_SET(set, sym) sys/linker_set.h:#define ABS_SET(set, sym) __MAKE_SET(set, sym) sys/linker_set.h:#define SET_ENTRY(set, sym) __MAKE_SET(set, sym) sys/linker_set.h:#define SET_ITEM(set, i) \ sys/lock.h:#define LOCK_DELAY_SYSINIT(func) \ sys/lockmgr.h:#define lockmgr_args_rw(lk, flags, ilk, wmesg, prio, timo) \ sys/lockmgr.h:#define lockmgr_rw(lk, flags, ilk) \ sys/mbuf.h:#define MCHTYPE(m, t) m_chtype((m), (t)) sys/module_khelp.h:#define KHELP_DECLARE_MOD(hname, hdata, hhooks, version) \ sys/mount.h:#define MNT_ITRYLOCK(mp) mtx_trylock(&(mp)->mnt_mtx) sys/nlist_aout.h:#define N_AUX(p) ((p)->n_other & 0xf) sys/nlist_aout.h:#define N_BIND(p) (((unsigned int)(p)->n_other >> 4) & 0xf) sys/nlist_aout.h:#define N_OTHER(r, v) (((unsigned int)(r) << 4) | ((v) & 0xf)) sys/osd.h:#define osd_thread_set_reserved(td, slot, rsv, value) \ sys/osd.h:#define osd_thread_del(td, slot) do { \ sys/osd.h:#define osd_thread_call(td, method, data) \ sys/param.h:#define __PAST_END(array, offset) (((__typeof__(*(array)) *)(array))[offset]) sys/pcpu.h:#define _DPCPU_GET(b, n) (*_DPCPU_PTR(b, n)) sys/pcpu.h:#define _DPCPU_SET(b, n, v) (*_DPCPU_PTR(b, n) = v) sys/pcpu.h:#define DPCPU_SUM(n) __extension__ \ sys/pmc.h:#define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) sys/pmc.h:#define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ sys/pmc.h:#define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ sys/pmc.h:#define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) sys/pmc.h:#define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) sys/pmc.h:#define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) sys/pmclog.h:#define PMC_CALLCHAIN_CPUFLAGS_TO_CPU(CF) (((CF) >> 16) & 0xFFFF) sys/pmclog.h:#define PMC_CALLCHAIN_CPUFLAGS_TO_USERMODE(CF) ((CF) & PMC_CC_F_USERSPACE) sys/pmclog.h:#define PMCLOG_HEADER_TO_LENGTH(H) \ sys/pmclog.h:#define PMCLOG_HEADER_TO_TYPE(H) \ sys/pmclog.h:#define PMCLOG_HEADER_CHECK_MAGIC(H) \ sys/proc.h:#define TD_SET_EXITING(td) TD_SET_INHIB((td), TDI_EXITING) sys/proc.h:#define PROC_ITIMLOCK_ASSERT(p, type) mtx_assert(&(p)->p_itimmtx, (type)) sys/proc.h:#define PROC_PROFLOCK_ASSERT(p, type) mtx_assert(&(p)->p_profmtx, (type)) sys/proc.h:#define PGRP_LOCKED(pg) mtx_owned(&(pg)->pg_mtx) sys/proc.h:#define PGRP_LOCK_PGSIGNAL(pg) do { \ sys/proc.h:#define PGRP_UNLOCK_PGSIGNAL(pg) do { \ sys/proc.h:#define SESS_LOCKED(s) mtx_owned(&(s)->s_mtx) sys/proc.h:#define PROC_ASSERT_NOT_HELD(p) do { \ sys/queue.h:#define SLIST_CLASS_HEAD(name, type) \ sys/queue.h:#define SLIST_CLASS_ENTRY(type) \ sys/queue.h:#define SLIST_CONCAT(head1, head2, type, field) do { \ sys/queue.h:#define SLIST_FOREACH_FROM(var, head, field) \ sys/queue.h:#define SLIST_FOREACH_FROM_SAFE(var, head, field, tvar) \ sys/queue.h:#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \ sys/queue.h:#define SLIST_REMOVE_PREVPTR(prevp, elm, field) do { \ sys/queue.h:#define STAILQ_CLASS_HEAD(name, type) \ sys/queue.h:#define STAILQ_CLASS_ENTRY(type) \ sys/queue.h:#define STAILQ_FOREACH_FROM(var, head, field) \ sys/queue.h:#define STAILQ_FOREACH_FROM_SAFE(var, head, field, tvar) \ sys/queue.h:#define LIST_CLASS_HEAD(name, type) \ sys/queue.h:#define LIST_CLASS_ENTRY(type) \ sys/queue.h:#define LIST_FOREACH_FROM(var, head, field) \ sys/queue.h:#define LIST_FOREACH_FROM_SAFE(var, head, field, tvar) \ sys/queue.h:#define TAILQ_CLASS_HEAD(name, type) \ sys/queue.h:#define TAILQ_CLASS_ENTRY(type) \ sys/queue.h:#define TAILQ_FOREACH_FROM_SAFE(var, head, field, tvar) \ sys/queue.h:#define TAILQ_FOREACH_REVERSE_FROM(var, head, headname, field) \ sys/queue.h:#define TAILQ_FOREACH_REVERSE_FROM_SAFE(var, head, headname, field, tvar) \ sys/rmlock.h:#define RM_SYSINIT_FLAGS(name, rm, desc, opts) \ sys/rtprio.h:#define RTP_PRIO_NEED_RR(P) PRI_NEED_RR(P) sys/rwlock.h:#define _rw_write_lock(rw, tid) \ sys/select.h:#define FD_CLR(n, p) ((p)->__fds_bits[(n)/_NFDBITS] &= ~__fdset_mask(n)) sys/select.h:#define FD_COPY(f, t) (void)(*(t) = *(f)) sys/signalvar.h:#define SIGACTION(p, sig) (p->p_sigacts->ps_sigact[_SIG_IDX(sig)]) sys/signalvar.h:#define SIGSETEQ(set1, set2) (__sigseteq(&(set1), &(set2))) sys/signalvar.h:#define SIGSETNEQ(set1, set2) (!__sigseteq(&(set1), &(set2))) sys/signalvar.h:#define SIGSETOLD(set, oset) ((set).__bits[0] = (oset)) sys/signalvar.h:#define SIG_CONTSIGMASK(set) \ sys/signalvar.h:#define SIGIO_TRYLOCK() mtx_trylock(&sigio_lock) sys/signalvar.h:#define SIGIO_LOCKED() mtx_owned(&sigio_lock) sys/signalvar.h:#define SIGIO_ASSERT(type) mtx_assert(&sigio_lock, type) sys/sockbuf.h:#define SOCKBUF_OWNED(_sb) mtx_owned(SOCKBUF_MTX(_sb)) sys/socket.h:#define SF_FLAGS(rh, flags) (((rh) << 16) | (flags)) sys/socketvar.h:#define SOCK_OWNED(so) mtx_owned(&(so)->so_lock) sys/soundcard.h:#define SEQ_DECLAREBUF() SEQ_USE_EXTBUF() sys/soundcard.h:#define PM_LOAD_PATCH(dev, bank, pgm) \ sys/soundcard.h:#define PM_LOAD_PATCHES(dev, bank, pgm) \ sys/soundcard.h:#define SEQ_VOLUME_MODE(dev, mode) { \ sys/soundcard.h:#define SEQ_START_NOTE(dev, chn, note, vol) \ sys/soundcard.h:#define SEQ_STOP_NOTE(dev, chn, note, vol) \ sys/soundcard.h:#define SEQ_KEY_PRESSURE(dev, chn, note, pressure) \ sys/soundcard.h:#define SEQ_CHN_PRESSURE(dev, chn, pressure) \ sys/soundcard.h:#define SEQ_SET_PATCH(dev, chn, patch) \ sys/soundcard.h:#define SEQ_PITCHBEND(dev, voice, value) \ sys/soundcard.h:#define SEQ_BENDER_RANGE(dev, voice, value) \ sys/soundcard.h:#define SEQ_EXPRESSION(dev, voice, value) \ sys/soundcard.h:#define SEQ_MAIN_VOLUME(dev, voice, value) \ sys/soundcard.h:#define SEQ_PANNING(dev, voice, pos) \ sys/soundcard.h:#define SEQ_START_TIMER() _TIMER_EVENT(TMR_START, 0) sys/soundcard.h:#define SEQ_STOP_TIMER() _TIMER_EVENT(TMR_STOP, 0) sys/soundcard.h:#define SEQ_CONTINUE_TIMER() _TIMER_EVENT(TMR_CONTINUE, 0) sys/soundcard.h:#define SEQ_WAIT_TIME(ticks) _TIMER_EVENT(TMR_WAIT_ABS, ticks) sys/soundcard.h:#define SEQ_DELTA_TIME(ticks) _TIMER_EVENT(TMR_WAIT_REL, ticks) sys/soundcard.h:#define SEQ_ECHO_BACK(key) _TIMER_EVENT(TMR_ECHO, key) sys/soundcard.h:#define SEQ_SET_TEMPO(value) _TIMER_EVENT(TMR_TEMPO, value) sys/soundcard.h:#define SEQ_SONGPOS(pos) _TIMER_EVENT(TMR_SPP, pos) sys/soundcard.h:#define SEQ_TIME_SIGNATURE(sig) _TIMER_EVENT(TMR_TIMESIG, sig) sys/soundcard.h:#define SEQ_PLAYAUDIO(devmask) _LOCAL_EVENT(LOCL_STARTAUDIO, devmask) sys/soundcard.h:#define SEQ_MIDIOUT(device, byte) { \ sys/soundcard.h:#define SEQ_WRPATCH(patchx, len) { \ sys/stat.h:#define S_ISWHT(m) (((m) & 0170000) == 0160000) /* whiteout */ sys/stdatomic.h:#define atomic_compare_exchange_strong(object, expected, desired) \ sys/stdatomic.h:#define atomic_compare_exchange_weak(object, expected, desired) \ sys/stdatomic.h:#define atomic_exchange(object, desired) \ sys/stdatomic.h:#define atomic_fetch_add(object, operand) \ sys/stdatomic.h:#define atomic_fetch_and(object, operand) \ sys/stdatomic.h:#define atomic_fetch_sub(object, operand) \ sys/stdatomic.h:#define atomic_fetch_xor(object, operand) \ sys/sx.h:#define sx_slock_sig(sx) sx_slock_sig_((sx), LOCK_FILE, LOCK_LINE) sys/sysctl.h:#define SYSCTL_ADD_BOOL(ctx, parent, nbr, name, access, ptr, val, descr) \ sys/sysctl.h:#define SYSCTL_UMA_MAX(parent, nbr, name, access, ptr, descr) \ sys/sysctl.h:#define SYSCTL_ADD_UMA_MAX(ctx, parent, nbr, name, access, ptr, descr) \ sys/sysctl.h:#define SYSCTL_ADD_UMA_CUR(ctx, parent, nbr, name, access, ptr, descr) \ sys/sysent.h:#define MAKE_SYSENT_COMPAT(syscallname) \ sys/sysent.h:#define SYSCALL_MODULE_HELPER(syscallname) \ sys/sysent.h:#define SYSCALL_MODULE_PRESENT(syscallname) \ sys/syslog.h:#define LOG_PRI(p) ((p) & LOG_PRIMASK) sys/syslog.h:#define LOG_FAC(p) (((p) & LOG_FACMASK) >> 3) sys/syslog.h:#define LOG_MASK(pri) (1 << (pri)) /* mask for one priority */ sys/syslog.h:#define LOG_UPTO(pri) ((1 << ((pri)+1)) - 1) /* all priorities through pri */ sys/taskqueue.h:#define TASKQUEUE_FAST_DEFINE_THREAD(name) \ sys/terminal.h:#define TCOLOR_DARK(c) ((c) & ~0x8) sys/terminal.h:#define TERMINAL_DECLARE_EARLY(name, class, softc) \ sys/time.h:#define timerclear(tvp) ((tvp)->tv_sec = (tvp)->tv_usec = 0) sys/time.h:#define timerisset(tvp) ((tvp)->tv_sec || (tvp)->tv_usec) sys/time.h:#define timeradd(tvp, uvp, vvp) \ sys/tree.h:#define SPLAY_HEAD(name, type) \ sys/tree.h:#define SPLAY_INITIALIZER(root) \ sys/tree.h:#define SPLAY_INIT(root) do { \ sys/tree.h:#define SPLAY_ENTRY(type) \ sys/tree.h:#define SPLAY_PROTOTYPE(name, type, field, cmp) \ sys/tree.h:#define SPLAY_GENERATE(name, type, field, cmp) \ sys/tree.h:#define SPLAY_INSERT(name, x, y) name##_SPLAY_INSERT(x, y) sys/tree.h:#define SPLAY_REMOVE(name, x, y) name##_SPLAY_REMOVE(x, y) sys/tree.h:#define SPLAY_FIND(name, x, y) name##_SPLAY_FIND(x, y) sys/tree.h:#define SPLAY_MAX(name, x) (SPLAY_EMPTY(x) ? NULL \ sys/tree.h:#define SPLAY_FOREACH(x, name, head) \ sys/tree.h:#define RB_FOREACH_REVERSE(x, name, head) \ sys/tree.h:#define RB_FOREACH_REVERSE_SAFE(x, name, head, y) \ sys/tty.h:#define tty_lock_owned(tp) mtx_owned((tp)->t_mtx) sys/ttycom.h:#define UIOCCMD(n) _IO('u', n) /* usr cntl op "n" */ sys/vnode.h:#define VN_KNOTE_LOCKED(vp, b) VN_KNOTE(vp, b, KNF_LISTLOCKED) sys/vnode.h:#define vn_rangelock_unlock_range(vp, cookie, start, end) \ ufs/ffs/fs.h:#define cgsblock(fs, c) (cgstart(fs, c) + (fs)->fs_sblkno) /* super blk */ ufs/ffs/fs.h:#define INOPF(fs) ((fs)->fs_inopb >> (fs)->fs_fragshift) ufs/ffs/softdep.h:#define WK_DATA(wk) ((void *)(wk)) vm/vm_object.h:#define VM_OBJECT_ASSERT_RLOCKED(object) \ vm/vm_page.h:#define PA_LOCKOBJPTR(pa) ((struct lock_object *)PA_LOCKPTR((pa))) x86/include/acpica_machdep.h:#define ACPI_DISABLE_IRQS() disable_intr() x86/include/segments.h:#define LSEL(s,r) (((s)<<3) | SEL_LDT | r) /* a local selector */ x86/include/segments.h:#define USD_SETBASE(sd, b) (sd)->sd_lobase = (b); \ x86/include/segments.h:#define USD_SETLIMIT(sd, l) (sd)->sd_lolimit = (l); \ x86/include/specialreg.h:#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ x86/iommu/intel_dmar.h:#define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj) x86/iommu/intel_dmar.h:#define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED) x86/iommu/intel_reg.h:#define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */ x86/iommu/intel_reg.h:#define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual x86/iommu/intel_reg.h:#define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */ x86/iommu/intel_reg.h:#define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */ x86/iommu/intel_reg.h:#define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */ x86/iommu/intel_reg.h:#define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */ x86/iommu/intel_reg.h:#define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ x86/iommu/intel_reg.h:#define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ x86/iommu/intel_reg.h:#define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ xen/blkif.h:#define BLKIF_RING_PAGES(_entries) \ xen/interface/arch-x86/cpuid.h:#define XEN_CPUID_LEAF(i) (XEN_CPUID_FIRST_LEAF + (i)) xen/interface/arch-x86/xen.h:#define TI_GET_DPL(_ti) ((_ti)->flags & 3) xen/interface/arch-x86/xen.h:#define TI_GET_IF(_ti) ((_ti)->flags & 4) xen/interface/arch-x86/xen.h:#define TI_SET_DPL(_ti,_dpl) ((_ti)->flags |= (_dpl)) xen/interface/arch-x86/xen.h:#define TI_SET_IF(_ti,_if) ((_ti)->flags |= ((!!(_if))<<2)) xen/interface/gcov.h:#define XENCOV_IS_TAG_COUNTER(n) \ xen/interface/gcov.h:#define XENCOV_COUNTER_NUM(n) ((n)-XENCOV_TAG_COUNTER(0)) xen/interface/hvm/pvdrivers.h:#define PVDRIVERS_PRODUCT_LIST(EACH) \ xen/interface/io/fbif.h:#define XENFB_IN_RING_REF(page, idx) \ xen/interface/io/fbif.h:#define XENFB_OUT_RING_REF(page, idx) \ xen/interface/io/kbdif.h:#define XENKBD_IN_RING_REF(page, idx) \ xen/interface/io/kbdif.h:#define XENKBD_OUT_RING_REF(page, idx) \ xen/interface/io/ring.h:#define RING_REQUEST_PROD_OVERFLOW(_r, _prod) \ xen/interface/io/ring.h:#define RING_PUSH_RESPONSES(_r) do { \ xen/interface/io/usbif.h:#define usbif_pipeportnum(pipe) ((pipe) & USBIF_PIPE_PORT_MASK) xen/interface/io/usbif.h:#define usbif_setportnum_pipe(pipe, portnum) ((pipe) | (portnum)) xen/interface/io/usbif.h:#define usbif_pipesubmit(pipe) (!usbif_pipeunlink(pipe)) xen/interface/io/usbif.h:#define usbif_setunlink_pipe(pipe) ((pipe) | USBIF_PIPE_UNLINK) xen/interface/io/usbif.h:#define usbif_pipeout(pipe) (!usbif_pipein(pipe)) xen/interface/io/usbif.h:#define usbif_pipedevice(pipe) \ xen/interface/io/usbif.h:#define usbif_pipeendpoint(pipe) \ xen/interface/io/usbif.h:#define usbif_pipeisoc(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_ISOC) xen/interface/io/usbif.h:#define usbif_pipeint(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_INT) xen/interface/io/usbif.h:#define usbif_pipectrl(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_CTRL) xen/interface/io/usbif.h:#define usbif_pipebulk(pipe) (usbif_pipetype(pipe) == USBIF_PIPE_TYPE_BULK) xen/interface/memory.h:#define XENMEMF_address_bits(x) (x) xen/interface/memory.h:#define XENMEMF_get_address_bits(x) ((x) & 0xffu) xen/interface/memory.h:#define XENMEMF_get_node(x) ((((x) >> 8) - 1) & 0xffu) xen/interface/memory.h:#define XENMEMF_exact_node(n) (XENMEMF_node(n) | XENMEMF_exact_node_request) xen/interface/memory.h:#define XENMEM_SHARING_OP_FIELD_MAKE_GREF(field, val) \ xen/interface/memory.h:#define XENMEM_SHARING_OP_FIELD_IS_GREF(field) \ xen/interface/memory.h:#define XENMEM_SHARING_OP_FIELD_GET_GREF(field) \ xen/interface/trace.h:#define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff) xen/interface/trace.h:#define TRC_HD_INCLUDES_CYCLE_COUNT(x) ( !!( (x) & TRC_HD_CYCLE_FLAG ) ) xen/interface/trace.h:#define TRC_HD_EXTRA(x) (((x)>>TRACE_EXTRA_SHIFT)&TRACE_EXTRA_MAX) xen/interface/trace.h:#define TRC_SCHED_CLASS_EVT(_c, _e) \