commit 85491a57f77ee0e3f416e5518cc3b61f35623fa7 Author: Rafal Jaworowski Date: Sun Aug 3 11:10:33 2008 +0200 booke: Initial SCHED_ULE support. diff --git a/sys/powerpc/booke/pmap.c b/sys/powerpc/booke/pmap.c index ba54275..4ebfe9d 100644 --- a/sys/powerpc/booke/pmap.c +++ b/sys/powerpc/booke/pmap.c @@ -104,10 +104,6 @@ __FBSDID("$FreeBSD: src/sys/powerpc/booke/pmap.c,v 1.2 2008/04/27 21:04:54 marce #define TODO panic("%s: not implemented", __func__); #define memmove(d, s, l) bcopy(s, d, l) -#include "opt_sched.h" -#ifndef SCHED_4BSD -#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." -#endif extern struct mtx sched_lock; /* Kernel physical load address. */ @@ -1851,7 +1847,7 @@ mmu_booke_activate(mmu_t mmu, struct thread *td) KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); - mtx_lock_spin(&sched_lock); + critical_enter(); atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); PCPU_SET(curpmap, pmap); @@ -1863,7 +1859,7 @@ mmu_booke_activate(mmu_t mmu, struct thread *td) mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); __asm __volatile("isync"); - mtx_unlock_spin(&sched_lock); + critical_exit(); CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); diff --git a/sys/powerpc/booke/swtch.S b/sys/powerpc/booke/swtch.S index f7505f3..20ae831 100644 --- a/sys/powerpc/booke/swtch.S +++ b/sys/powerpc/booke/swtch.S @@ -67,6 +67,8 @@ #include #include +#include "opt_sched.h" + /* * void cpu_throw(struct thread *old, struct thread *new) */ @@ -75,37 +77,58 @@ ENTRY(cpu_throw) b cpu_switchin /* - * void cpu_switch(struct thread *old, struct thread *new) + * void cpu_switch(struct thread *old, struct thread *new, struct mutex *mtx);) * * Switch to a new thread saving the current state in the old thread. */ ENTRY(cpu_switch) - lwz %r5, TD_PCB(%r3) /* Get the old thread's PCB ptr */ - + lwz %r6, TD_PCB(%r3) /* Get the old thread's PCB ptr */ mr %r12, %r2 - stmw %r12, PCB_CONTEXT(%r5) /* Save the non-volatile GP regs. + stmw %r12, PCB_CONTEXT(%r6) /* Save the non-volatile GP regs. These can now be used for scratch */ mfcr %r16 /* Save the condition register */ - stw %r16, PCB_CR(%r5) + stw %r16, PCB_CR(%r6) mflr %r16 /* Save the link register */ - stw %r16, PCB_LR(%r5) + stw %r16, PCB_LR(%r6) mfctr %r16 - stw %r16, PCB_BOOKE_CTR(%r5) + stw %r16, PCB_BOOKE_CTR(%r6) mfxer %r16 - stw %r16, PCB_BOOKE_XER(%r5) + stw %r16, PCB_BOOKE_XER(%r6) + + stw %r1, PCB_SP(%r6) /* Save the stack pointer */ - stw %r1, PCB_SP(%r5) /* Save the stack pointer */ +#if defined(SCHED_ULE) && defined(SMP) + /* Update old thread's lock */ + li %r14, TD_LOCK +1: lwarx %r15, %r14, %r3 + stwcx. %r5, %r14, %r3 + bne- 1b +#else + stw %r5, TD_LOCK(%r3) +#endif mr %r14, %r3 /* Copy the old thread ptr... */ mr %r15, %r4 /* and the new thread ptr in scratch */ - bl pmap_deactivate /* Deactivate the current pmap */ cpu_switchin: mr %r3, %r15 /* Get new thread ptr */ bl pmap_activate /* Activate the new address space */ +#if defined(SCHED_ULE) && defined(SMP) + /* + * while (new->td_lock == &blocked_lock) + * ; + */ + lis %r16, blocked_lock@h + ori %r16, %r16, blocked_lock@l +1: + lwz %r17, TD_LOCK(%r15) + cmpw %r16, %r17 + beq 1b +#endif + mfsprg %r7, 0 /* Get the pcpu pointer */ stw %r15, PC_CURTHREAD(%r7) /* Store new current thread */ lwz %r17, TD_PCB(%r15) /* Store new current PCB */ @@ -114,14 +137,14 @@ cpu_switchin: mr %r3, %r17 /* Recover PCB ptr */ lmw %r12, PCB_CONTEXT(%r3) /* Load the non-volatile GP regs */ mr %r2, %r12 - lwz %r5, PCB_CR(%r3) /* Load the condition register */ - mtcr %r5 - lwz %r5, PCB_LR(%r3) /* Load the link register */ - mtlr %r5 - lwz %r5, PCB_BOOKE_CTR(%r3) - mtctr %r5 - lwz %r5, PCB_BOOKE_XER(%r3) - mtxer %r5 + lwz %r6, PCB_CR(%r3) /* Load the condition register */ + mtcr %r6 + lwz %r6, PCB_LR(%r3) /* Load the link register */ + mtlr %r6 + lwz %r6, PCB_BOOKE_CTR(%r3) + mtctr %r6 + lwz %r6, PCB_BOOKE_XER(%r3) + mtxer %r6 lwz %r1, PCB_SP(%r3) /* Load the stack pointer */ isync