~(l(i0`0`1105     &       ] U p @ @  0`0`1105     &       ] U p @ @ / % ibm,powernvibm,p9-openbmcrcs,taloso8IBM UOPWR.A100034-Node0 10T2P9D01 REV 1.01 A1000341 rcs,talosibm,firmware-code@30000000ibm,firmware-heap@30600000ibm,firmware-data@31000000ibm,firmware-stacks@31c10000ibm,firmware-allocs-memory@35f10000ibm,hb-rsv-mem@f0000000ibm,firmware-allocs-memory@200000000000ibm,RINGOVD@201ffcb50000ibm,VERSION@201ffcb80000ibm,HCODE@201ffcb90000ibm,WOFDATA@201ffcc30000ibm,OCC@201ffce90000ibm,secure-crypt-algo-code@201ffcf30000ibm,sbe-ffdc@201ffcf40000ibm,sbe-comm@201ffcf50000ibm,sbe-ffdc@201ffcf60000ibm,sbe-comm@201ffcf70000ibm,hbrt-code-image@201ffcf80000ibm,hbrt-data@201ffd550000ibm,arch-reg-data@201ffd700000ibm,homer-image@201ffd800000ibm,homer-image@201ffdc00000ibm,occ-common-area@201fff800000p0`0`1105     &       ] U p @ @ cpuscpus /YPowerPC,POWER9@85cPowerPC,POWER9  TUVW 8   \]^_^\,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{\okaycpu/PowerPC,POWER9@858PowerPC,POWER9  PQRS 8   XYZ[^X,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Xokaycpu/PowerPC,POWER9@854PowerPC,POWER9  LMNO 8   TUVW^T,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Tokaycpu/PowerPC,POWER9@850PowerPC,POWER9  HIJK 8   PQRS^P,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Pokaycpu/PowerPC,POWER9@84cPowerPC,POWER9  DEFG 8   LMNO^L,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Lokaycpu/PowerPC,POWER9@848PowerPC,POWER9  @ABC 8   HIJK^H,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Hokaycpu/PowerPC,POWER9@844PowerPC,POWER9  <=>? 8   DEFG^D,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Dokaycpu/PowerPC,POWER9@840PowerPC,POWER9  89:; 8   @ABC^@,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{@okaycpu/PowerPC,POWER9@83cPowerPC,POWER9  4567 8   <=>?^<,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{<okaycpu/PowerPC,POWER9@838PowerPC,POWER9  0123 8   89:;^8,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{8okaycpu/PowerPC,POWER9@834PowerPC,POWER9  ,-./ 8    4567^4,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{4okaycpu/PowerPC,POWER9@830PowerPC,POWER9  ()*+ 8    0123^0,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{0okaycpu/PowerPC,POWER9@82cPowerPC,POWER9  $%&' 8    ,-./^,,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{,okaycpu/PowerPC,POWER9@828PowerPC,POWER9   !"# 8    ()*+^(,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{(okaycpu/PowerPC,POWER9@824PowerPC,POWER9   8    $%&'^$,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{$okaycpu/PowerPC,POWER9@820PowerPC,POWER9   8    !"#^ ,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{ okaycpu/PowerPC,POWER9@81cPowerPC,POWER9   8   ^,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/PowerPC,POWER9@818PowerPC,POWER9   8   ^,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/PowerPC,POWER9@814PowerPC,POWER9     8   ^,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/PowerPC,POWER9@810PowerPC,POWER9      8   ^,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/PowerPC,POWER9@80cPowerPC,POWER9   8     ^ ,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{ okaycpu/PowerPC,POWER9@808PowerPC,POWER9   8      ^,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/PowerPC,POWER9@5cPowerPC,POWER9  defg 8   \]^_^\,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{\okaycpu/PowerPC,POWER9@58PowerPC,POWER9  `abc 8   XYZ[^X,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Xokaycpu/PowerPC,POWER9@54PowerPC,POWER9  \]^_ 8   TUVW^T,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Tokaycpu/PowerPC,POWER9@50PowerPC,POWER9  XYZ[ 8   PQRS^P,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Pokaycpu/~PowerPC,POWER9@4cPowerPC,POWER9  TUVW 8   LMNO^L{,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Lokaycpu/}PowerPC,POWER9@48PowerPC,POWER9  PQRS 8   HIJK^H{,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Hokaycpu/zPowerPC,POWER9@44PowerPC,POWER9  LMNO 8   DEFG^Dw,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{Dokaycpu/yPowerPC,POWER9@40PowerPC,POWER9  HIJK 8   @ABC^@w,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{@okaycpu/vPowerPC,POWER9@3cPowerPC,POWER9  DEFG 8   <=>?^<s,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{<okaycpu/uPowerPC,POWER9@38PowerPC,POWER9  @ABC 8   89:;^8s,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{8okaycpu/rPowerPC,POWER9@34PowerPC,POWER9  <=>? 8    4567^4o,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{4okaycpu/qPowerPC,POWER9@30PowerPC,POWER9  89:; 8    0123^0o,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{0okaycpu/nPowerPC,POWER9@2cPowerPC,POWER9  4567 8    ,-./^,k,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{,okaycpu/mPowerPC,POWER9@28PowerPC,POWER9  0123 8    ()*+^(k,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{(okaycpu/jPowerPC,POWER9@24PowerPC,POWER9  ,-./ 8    $%&'^$g,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{$okaycpu/iPowerPC,POWER9@20PowerPC,POWER9  ()*+ 8   !"#^ g,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{ okaycpu/fPowerPC,POWER9@1cPowerPC,POWER9  $%&' 8   ^c,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/ePowerPC,POWER9@18PowerPC,POWER9  !"# 8   ^c,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/bPowerPC,POWER9@14PowerPC,POWER9   8   ^_,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/aPowerPC,POWER9@10PowerPC,POWER9   8   ^_,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/^PowerPC,POWER9@cPowerPC,POWER9   8   ^ [,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{ okaycpu/]PowerPC,POWER9@8PowerPC,POWER9   8    ^[,9FS`s  +5>FN B[@?Ѐhk  8" "  @ "(N{okaycpu/Zbmc/  ibm,ast2500,openbmcsensors/ sensor@1/  ibm,ipmi-sensor{j"sensor@2/  ibm,ipmi-sensor{jsensor@3/& ibm,ipmi-sensor{j^sensor@4/9 ibm,ipmi-sensor{j^sensor@6/ ibm,ipmi-sensor{j^sensor@7/' ibm,ipmi-sensor{j^sensor@8/ ibm,ipmi-sensor{j^sensor@9/( ibm,ipmi-sensor{ j^sensor@a/  ibm,ipmi-sensor{ jsensor@b/ ibm,ipmi-sensor{ j sensor@c/ ibm,ipmi-sensor{ j sensor@d/ ibm,ipmi-sensor{ j sensor@e/ ibm,ipmi-sensor{j sensor@f/ ibm,ipmi-sensor{j sensor@10/! ibm,ipmi-sensor{j sensor@11/# ibm,ipmi-sensor{j sensor@12/% ibm,ipmi-sensor{j sensor@13/* ibm,ipmi-sensor{j sensor@14/, ibm,ipmi-sensor{j sensor@15/. ibm,ipmi-sensor{j sensor@16/0 ibm,ipmi-sensor{j sensor@17/2 ibm,ipmi-sensor{j sensor@18/4 ibm,ipmi-sensor{j sensor@19/6 ibm,ipmi-sensor{j sensor@1a/8 ibm,ipmi-sensor{j sensor@1b/ ibm,ipmi-sensor{jsensor@1c/ ibm,ipmi-sensor{jsensor@1d/ ibm,ipmi-sensor{jsensor@1e/ ibm,ipmi-sensor{jsensor@1f/ ibm,ipmi-sensor{jsensor@20/  ibm,ipmi-sensor{ jsensor@21/" ibm,ipmi-sensor{!jsensor@22/$ ibm,ipmi-sensor{"jsensor@23/) ibm,ipmi-sensor{#jsensor@24/+ ibm,ipmi-sensor{$jsensor@25/- ibm,ipmi-sensor{%jsensor@26// ibm,ipmi-sensor{&jsensor@27/1 ibm,ipmi-sensor{'jsensor@28/3 ibm,ipmi-sensor{(jsensor@29/5 ibm,ipmi-sensor{)jsensor@2a/7 ibm,ipmi-sensor{*jsensor@8b/ ibm,ipmi-sensor{jsensor@8c/ ibm,ipmi-sensor{jsensor@8d/ ibm,ipmi-sensor{jsensor@8e/ ibm,ipmi-sensor{jsensor@8f/ ibm,ipmi-sensor{jsensor@90/  ibm,ipmi-sensor{jsensor@91/  ibm,ipmi-sensor{jsensor@92/ ibm,ipmi-sensor{jsensor@93/ ibm,ipmi-sensor{jsensor@94/ ibm,ipmi-sensor{jsensor@95/ ibm,ipmi-sensor{jsensor@96/ ibm,ipmi-sensor{jsensor@97/ ibm,ipmi-sensor{jchosenl TKP<4ŎvijV^K$h:InMnh`]|gǘ>I5Z3/ ^Z5q# Q|| \^4}N]1O|}ܦ P<^Di@PwX= C7vfs.root.mountfrom=cd9660:/dev/iso9660/16_0_CURRENT_POWERPC64LE_CD@/G6/ibm,opal/flash@0$/ibm,opal/consoles/serial@0ibm,firmware-versions/ talos-v2.6-948-gaef76a11-dirty 2018.02-22790-gc69ca4e729 ecb1dc7 a98d734 v6.6.16-openpower1-pd27c52f 695b1d9-pe45a591 6289e21 9ddc6ba f5dcee9 9b705d0 0.00ibm,hostboot/ reserved-memory/ ibm,HCODE@201ffcb90000/%{    HCODEibm,OCC@201ffce90000/#{    OCCibm,RINGOVD@201ffcb50000/'{   RINGOVDibm,VERSION@201ffcb80000/&{   VERSIONibm,WOFDATA@201ffcc30000/${ &  WOFDATAibm,arch-reg-data@201ffd700000/{ p  ibm,arch-reg-dataibm,hb-rsv-mem@f0000000/{  ibm,hb-rsv-memibm,hbrt-code-image@201ffcf80000/{ ]  ibm,hbrt-code-imageibm,hbrt-data@201ffd550000/{ U  ibm,hbrt-dataibm,homer-image@201ffd800000/{ @  ibm,homer-imageibm,homer-image@201ffdc00000/{ @  ibm,homer-imageibm,occ-common-area@201fff800000/{   ibm,occ-common-areaibm,sbe-comm@201ffcf50000/ {   ibm,sbe-commibm,sbe-comm@201ffcf70000/{   ibm,sbe-commibm,sbe-ffdc@201ffcf40000/!{   ibm,sbe-ffdcibm,sbe-ffdc@201ffcf60000/{   ibm,sbe-ffdcibm,secure-crypt-algo-code@201ffcf30000/"{   ibm,secure-crypt-algo-codeibm,opal/W   ibm,opal-v3   }0 j07` X00 F # 0#  P . psi#0:fsppsi#0:occpsi#0:fsipsi#0:lpchcpsi#0:local_errpsi#0:global_errpsi#0:lpc_serirq_mux0psi#0:lpc_serirq_mux1psi#0:lpc_serirq_mux2psi#0:lpc_serirq_mux3psi#0:i2cpsi#0:diopsi#0:psupsi#8:fsppsi#8:occpsi#8:fsipsi#8:lpchcpsi#8:local_errpsi#8:global_errpsi#8:i2cpsi#8:diopsi#8:psuphb#0000-infphb#0000-errphb#0001-infphb#0001-errphb#0002-infphb#0002-errphb#0003-infphb#0003-errphb#0004-infphb#0004-errphb#0005-infphb#0005-errphb#0030-infphb#0030-errphb#0031-infphb#0031-errphb#0032-infphb#0032-errphb#0033-infphb#0033-err. psi#0:fsppsi#0:occpsi#0:fsipsi#0:lpchcpsi#0:local_errpsi#0:global_errpsi#0:lpc_serirq_mux0psi#0:lpc_serirq_mux1psi#0:lpc_serirq_mux2psi#0:lpc_serirq_mux3psi#0:i2cpsi#0:diopsi#0:psupsi#8:fsppsi#8:occpsi#8:fsipsi#8:lpchcpsi#8:local_errpsi#8:global_errpsi#8:i2cpsi#8:diopsi#8:psuphb#0000-infphb#0000-errphb#0001-infphb#0001-errphb#0002-infphb#0002-errphb#0003-infphb#0003-errphb#0004-infphb#0004-errphb#0005-infphb#0005-errphb#0030-infphb#0030-errphb#0031-infphb#0031-errphb#0032-infphb#0032-errphb#0033-infphb#0033-err  0$5666%666G6X6i6z6666666777$757F7W   # 4 E V g x          " 3 D U f 0&p okayconsoles/ serial@0/ ibm,opal-console-raw {serialdiagnostics/  ibm,opal-prdevent/ ibm,opal-event w bfirmware/ ibm,opal-firmware firmware skiboot-ecb1dc7 W0Uexports/ L0U C1  ?  /    traces/ 0$ 5 6 6 6% 66 6G 6X 6i 6z 6 6 6 6 6 ~6 u6 l7 c7 Z7$ Q75 H7F ?7W 5  +  ! #  4 E  V g x          " 3 w D m U c fflash@0/ ibm,opal-flash W{ B 9partitions/ fixed-partitions partition@0/ PNOR{partition@1e21000/ BOOTKERNEL{` /partition@3544000/ VERSION{T@  /partition@3589000/ IMA_CATALOG{X /partition@3a10000/ BOOTKERNFW{Ofw-features/fw-bcctrl-serialized/ &fw-branch-hints-honored/ fw-count-cache-disabled/ fw-count-cache-flush-bcctr2,0,0/ &fw-l1d-thread-split/ fw-ltptr-serialized/ &inst-l1d-flush-ori30,30,0/ &inst-l1d-flush-trig2/ inst-spec-barrier-ori31,31,0/ inst-thread-reconfig-control-trig0-1/ &needs-count-cache-flush-on-context-switch/ &needs-l1d-flush-msr-hv-1-to-0/ needs-l1d-flush-msr-pr-0-to-1/ needs-pmu-restricted/ &needs-spec-barrier-for-bound-checks/ speculation-policy-favor-security/ tm-suspend-mode/ user-mode-branch-speculation/ &ipmi/ ibm,opal-ipmi  ? leds/X lightpathnvram/  ibm,opal-nvramoppanel/" ibm,opal-oppanelrcs,ipl-observerpower-mgt/a)stop0_litestop0stop1stop2stop4stop5' @x'N P1-_ p p0F00001020t0u0(000000  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abtcRB1  z i X H 7 &   o ^ N = ,  u d T C 2 "  { j Z I 8 (   p ` O > .  vbTHXHpartc/  ibm,opal-rtcsensors/ ibm,opal-sensor core-temp@c00028/otempU({(KTEMPPROCTHRMC02 OChip 0 Core;(+( ibm,opal-sensorcore-temp@c00029/otempU){)KTEMPPROCTHRMC03 OChip 0 Core ;)+) ibm,opal-sensorcore-temp@c0002a/otempU*{*KTEMPPROCTHRMC04 OChip 0 Core;*+* ibm,opal-sensorcore-temp@c0002b/otempU+{+KTEMPPROCTHRMC05 OChip 0 Core;+++ ibm,opal-sensorcore-temp@c0002c/otempU,{,KTEMPPROCTHRMC06 OChip 0 Core;,+, ibm,opal-sensorcore-temp@c0002d/otempU-{-KTEMPPROCTHRMC07 OChip 0 Core;-+- ibm,opal-sensorcore-temp@c0002e/otempU.{.KTEMPPROCTHRMC08 OChip 0 Core ;.+. ibm,opal-sensorcore-temp@c0002f/otempU/{/KTEMPPROCTHRMC09 OChip 0 Core$;/+/ ibm,opal-sensorcore-temp@c00030/otempU0{0KTEMPPROCTHRMC10 OChip 0 Core(;0+0 ibm,opal-sensorcore-temp@c00031/otempU1{1KTEMPPROCTHRMC11 OChip 0 Core,;1+1 ibm,opal-sensorcore-temp@c00032/otempU2{2KTEMPPROCTHRMC12 OChip 0 Core0;2+2 ibm,opal-sensorcore-temp@c00033/otempU3{3KTEMPPROCTHRMC13 OChip 0 Core4;3+3 ibm,opal-sensorcore-temp@c00034/otempU4{4KTEMPPROCTHRMC14 OChip 0 Core8;4+4 ibm,opal-sensorcore-temp@c00035/otempU5{5KTEMPPROCTHRMC15 OChip 0 Core<;5+5 ibm,opal-sensorcore-temp@c00036/otempU6{6KTEMPPROCTHRMC16 OChip 0 Core@;6+6 ibm,opal-sensorcore-temp@c00037/otempU7{7KTEMPPROCTHRMC17 OChip 0 CoreD;7+7 ibm,opal-sensorcore-temp@c00038/otempU8{8KTEMPPROCTHRMC18 OChip 0 CoreH;8+8 ibm,opal-sensorcore-temp@c00039/otempU9{9KTEMPPROCTHRMC19 OChip 0 CoreL;9+9 ibm,opal-sensorcore-temp@c0003a/otempU:{:KTEMPPROCTHRMC20 OChip 0 CoreP;:+: ibm,opal-sensorcore-temp@c0003b/otempU;{;KTEMPPROCTHRMC21 OChip 0 CoreT;;+; ibm,opal-sensorcore-temp@c0003c/otempU<{<KTEMPPROCTHRMC22 OChip 0 CoreX;<+< ibm,opal-sensorcore-temp@c0003d/otempU={=KTEMPPROCTHRMC23 OChip 0 Core\;=+= ibm,opal-sensorcore-temp@c10028/otempU({(KTEMPPROCTHRMC02 OChip 8 Core;(+( ibm,opal-sensorcore-temp@c10029/otempU){)KTEMPPROCTHRMC03 OChip 8 Core ;)+) ibm,opal-sensorcore-temp@c1002a/otempU*{*KTEMPPROCTHRMC04 OChip 8 Core;*+* ibm,opal-sensorcore-temp@c1002b/otempU+{+KTEMPPROCTHRMC05 OChip 8 Core;+++ ibm,opal-sensorcore-temp@c1002c/otempU,{,KTEMPPROCTHRMC06 OChip 8 Core;,+, ibm,opal-sensorcore-temp@c1002d/otempU-{-KTEMPPROCTHRMC07 OChip 8 Core;-+- ibm,opal-sensorcore-temp@c1002e/otempU.{.KTEMPPROCTHRMC08 OChip 8 Core ;.+. ibm,opal-sensorcore-temp@c1002f/otempU/{/KTEMPPROCTHRMC09 OChip 8 Core$;/+/ ibm,opal-sensorcore-temp@c10030/otempU0{0KTEMPPROCTHRMC10 OChip 8 Core(;0+0 ibm,opal-sensorcore-temp@c10031/otempU1{1KTEMPPROCTHRMC11 OChip 8 Core,;1+1 ibm,opal-sensorcore-temp@c10032/otempU2{2KTEMPPROCTHRMC12 OChip 8 Core0;2+2 ibm,opal-sensorcore-temp@c10033/otempU3{3KTEMPPROCTHRMC13 OChip 8 Core4;3+3 ibm,opal-sensorcore-temp@c10034/otempU4{4KTEMPPROCTHRMC14 OChip 8 Core8;4+4 ibm,opal-sensorcore-temp@c10035/otempU5{5KTEMPPROCTHRMC15 OChip 8 Core<;5+5 ibm,opal-sensorcore-temp@c10036/otempU6{6KTEMPPROCTHRMC16 OChip 8 Core@;6+6 ibm,opal-sensorcore-temp@c10037/otempU7{7KTEMPPROCTHRMC17 OChip 8 CoreD;7+7 ibm,opal-sensorcore-temp@c10038/otempU8{8KTEMPPROCTHRMC18 OChip 8 CoreH;8+8 ibm,opal-sensorcore-temp@c10039/otempU9{9KTEMPPROCTHRMC19 OChip 8 CoreL;9+9 ibm,opal-sensorcore-temp@c1003a/otempU:{:KTEMPPROCTHRMC20 OChip 8 CoreP;:+: ibm,opal-sensorcore-temp@c1003b/otempU;{;KTEMPPROCTHRMC21 OChip 8 CoreT;;+; ibm,opal-sensorcore-temp@c1003c/otempU<{<KTEMPPROCTHRMC22 OChip 8 CoreX;<+< ibm,opal-sensorcore-temp@c1003d/otempU={=KTEMPPROCTHRMC23 OChip 8 Core\;=+= ibm,opal-sensormem-temp@c0003e/otempU>{> KTEMPDIMM00OChip 0 DIMM 0 ;>+> ibm,opal-sensormem-temp@c0003f/otempU?{? KTEMPDIMM01OChip 0 DIMM 1 ;?+? ibm,opal-sensormem-temp@c00040/otempU@{@ KTEMPDIMM02OChip 0 DIMM 2 ;@+@ ibm,opal-sensormem-temp@c00041/otempUA{A KTEMPDIMM03OChip 0 DIMM 3 ;A+A ibm,opal-sensormem-temp@c00042/otempUB{B KTEMPDIMM04OChip 0 DIMM 4 ;B+B ibm,opal-sensormem-temp@c00043/otempUC{C KTEMPDIMM05OChip 0 DIMM 5 ;C+C ibm,opal-sensormem-temp@c00044/otempUD{D KTEMPDIMM06OChip 0 DIMM 6 ;D+D ibm,opal-sensormem-temp@c00045/otempUE{E KTEMPDIMM07OChip 0 DIMM 7 ;E+E ibm,opal-sensormem-temp@c00046/otempUF{F KTEMPDIMM08OChip 0 DIMM 8 ;F+F ibm,opal-sensormem-temp@c00047/otempUG{G KTEMPDIMM09OChip 0 DIMM 9 ;G+G ibm,opal-sensormem-temp@c00048/otempUH{H KTEMPDIMM10OChip 0 DIMM 10 ;H+H ibm,opal-sensormem-temp@c00049/otempUI{I KTEMPDIMM11OChip 0 DIMM 11 ;I+I ibm,opal-sensormem-temp@c0004a/otempUJ{J KTEMPDIMM12OChip 0 DIMM 12 ;J+J ibm,opal-sensormem-temp@c0004b/otempUK{K KTEMPDIMM13OChip 0 DIMM 13 ;K+K ibm,opal-sensormem-temp@c0004c/otempUL{L KTEMPDIMM14OChip 0 DIMM 14 ;L+L ibm,opal-sensormem-temp@c0004d/otempUM{M KTEMPDIMM15OChip 0 DIMM 15 ;M+M ibm,opal-sensormem-temp@c1003e/otempU>{> KTEMPDIMM00OChip 8 DIMM 0 ;>+> ibm,opal-sensormem-temp@c1003f/otempU?{? KTEMPDIMM01OChip 8 DIMM 1 ;?+? ibm,opal-sensormem-temp@c10040/otempU@{@ KTEMPDIMM02OChip 8 DIMM 2 ;@+@ ibm,opal-sensormem-temp@c10041/otempUA{A KTEMPDIMM03OChip 8 DIMM 3 ;A+A ibm,opal-sensormem-temp@c10042/otempUB{B KTEMPDIMM04OChip 8 DIMM 4 ;B+B ibm,opal-sensormem-temp@c10043/otempUC{C KTEMPDIMM05OChip 8 DIMM 5 ;C+C ibm,opal-sensormem-temp@c10044/otempUD{D KTEMPDIMM06OChip 8 DIMM 6 ;D+D ibm,opal-sensormem-temp@c10045/otempUE{E KTEMPDIMM07OChip 8 DIMM 7 ;E+E ibm,opal-sensormem-temp@c10046/otempUF{F KTEMPDIMM08OChip 8 DIMM 8 ;F+F ibm,opal-sensormem-temp@c10047/otempUG{G KTEMPDIMM09OChip 8 DIMM 9 ;G+G ibm,opal-sensormem-temp@c10048/otempUH{H KTEMPDIMM10OChip 8 DIMM 10 ;H+H ibm,opal-sensormem-temp@c10049/otempUI{I KTEMPDIMM11OChip 8 DIMM 11 ;I+I ibm,opal-sensormem-temp@c1004a/otempUJ{J KTEMPDIMM12OChip 8 DIMM 12 ;J+J ibm,opal-sensormem-temp@c1004b/otempUK{K KTEMPDIMM13OChip 8 DIMM 13 ;K+K ibm,opal-sensormem-temp@c1004c/otempUL{L KTEMPDIMM14OChip 8 DIMM 14 ;L+L ibm,opal-sensormem-temp@c1004d/otempUM{M KTEMPDIMM15OChip 8 DIMM 15 ;M+M ibm,opal-sensorproc-energy@5c000b0/oenergyU{KPWRPROCOChip 0  ibm,opal-sensorproc-energy@5c000b1/oenergyU{KPWRVDD OChip 0 Vdd ibm,opal-sensorproc-energy@5c000b2/oenergyU{KPWRVDN OChip 0 Vdn ibm,opal-sensorproc-energy@5c1009f/ oenergyU{KPWRPROCOChip 8  ibm,opal-sensorproc-energy@5c100a0/ oenergyU{KPWRVDD OChip 8 Vdd ibm,opal-sensorproc-energy@5c100a1/ oenergyU{KPWRVDN OChip 8 Vdn ibm,opal-sensorproc-in@c00003/oinU{ KVOLTVDDSENSEOChip 0 Vdd Remote Sense;+ ibm,opal-sensorproc-in@c00005/oinU{ KVOLTVDNSENSEOChip 0 Vdn Remote Sense;+ ibm,opal-sensorproc-in@c10003/oinU{ KVOLTVDDSENSEOChip 8 Vdd Remote Sense;+ ibm,opal-sensorproc-in@c10005/oinU{ KVOLTVDNSENSEOChip 8 Vdn Remote Sense;+ ibm,opal-sensorproc-power@c000b0/opowerU{KPWRPROCOChip 0 ;+ ibm,opal-sensorproc-power@c000b1/opowerU{KPWRVDD OChip 0 Vdd;+ ibm,opal-sensorproc-power@c000b2/opowerU{KPWRVDN OChip 0 Vdn;+ ibm,opal-sensorproc-power@c1009f/opowerU{KPWRPROCOChip 8 ;+ ibm,opal-sensorproc-power@c100a0/ opowerU{KPWRVDD OChip 8 Vdd;+ ibm,opal-sensorproc-power@c100a1/ opowerU{KPWRVDN OChip 8 Vdn;+ ibm,opal-sensorproc-temp@c00024/otempU${$ KTEMPNEST OChip 0 Nest;$+$ ibm,opal-sensorproc-temp@c10024/otempU${$ KTEMPNEST OChip 8 Nest;$+$ ibm,opal-sensorvrm-curr@c00000/ocurrU{KCURVDD OChip 0 Vdd;+ ibm,opal-sensorvrm-curr@c00001/ocurrU{KCURVDN OChip 0 Vdn;+ ibm,opal-sensorvrm-curr@c10000/ocurrU{KCURVDD OChip 8 Vdd;+ ibm,opal-sensorvrm-curr@c10001/ocurrU{KCURVDN OChip 8 Vdn;+ ibm,opal-sensorvrm-in@c00002/oinU{KVOLTVDD OChip 0 Vdd;+ ibm,opal-sensorvrm-in@c00004/oinU{KVOLTVDN OChip 0 Vdn;+ ibm,opal-sensorvrm-in@c10002/oinU{KVOLTVDD OChip 8 Vdd;+ ibm,opal-sensorvrm-in@c10004/oinU{KVOLTVDN OChip 8 Vdn;+ ibm,opal-sensorvrm-temp@c00025/otempU%{%KTEMPVDDOChip 0 VRM VDD;%+% ibm,opal-sensorvrm-temp@c10025/otempU%{%KTEMPVDDOChip 8 VRM VDD;%+% ibm,opal-sensoribm,pcie-slots/7 root-complex@0,0/8{ ! ibm,pcie-portibm,pcie-root-port^SLOT3pluggable/9SLOT3root-complex@0,1/:{ ! ibm,pcie-portibm,pcie-root-port^builtin/;root-complex@0,2/<{ ! ibm,pcie-portibm,pcie-root-port^builtin/=root-complex@0,3/>{ ! ibm,pcie-portibm,pcie-root-port^SLOT1pluggable/?SLOT1root-complex@0,4/@{ ! ibm,pcie-portibm,pcie-root-port^switch-up@10b5,8725/A{% down-port@a/B ibm,pcie-port{ GPU0builtin/CGPU0down-port@b/D ibm,pcie-port{ GPU1builtin/EGPU1down-port@c/F ibm,pcie-port{ GPU2builtin/GGPU2root-complex@0,5/H{ ! ibm,pcie-portibm,pcie-root-port^builtin/Iroot-complex@8,0/S{ ! ibm,pcie-portibm,pcie-root-port^SLOT2pluggable/TSLOT2root-complex@8,3/U{ ! ibm,pcie-portibm,pcie-root-port^SLOT1pluggable/VSLOT1root-complex@8,4/W{ ! ibm,pcie-portibm,pcie-root-port^SLOT0pluggable/XSLOT0root-complex@8,5/Y{ ! ibm,pcie-portibm,pcie-root-port^switch-up@10b5,8725/Z{% down-port@4/[ ibm,pcie-port{GPU3builtin/\GPU3down-port@5/] ibm,pcie-port{GPU4builtin/^GPU4down-port@d/_ ibm,pcie-port{ GPU5builtin/`GPU5ibm,secureboot/! ibm,securebootibm,secureboot-v2@b,^,jPܰ]CG]S@L8\g8Iȱk"5g,ymX@ibm,cvc/b   ibm,container-verification-codeibm,cvc-service@40/c ibm,cvc-sha512{@ ibm,cvc-service@50/d ibm,cvc-verify{P imc-counters/ ibm,opal-in-memory-counters capp0@6c8/ ibm,imc-counters PM_CAPP1_256{yoe  bcore-thread-events/ event@0/{ZPCYC{UThe sum of processor cycles across all SMT threads of the core. Example, a 3GHz core with 4 SMT threads will report 12 billion processor cycles. Processor clock may vary dynamicallyevent@8/eZINST{EUThe sum of instructions completed across all SMT threads of the coreevent@10/ZNON_IDLE_INST{YUThe number of completed instructions with runlatch enabled during the measurement periodevent@18/ZNON_IDLE_PCYC{SUThe number of processor cycles with runlatch enabled during the measurement periodevent@40/ZANY_THRD_NON_IDLE_PCYC{@]UThe number of processor cycles when one or more SMT threads is running non-idle instructionsevent@48/ZCORE_ALL_THRD_NON_IDLE_PCYC{HTUThe number of processor cycles when all threads are executing non-idle instructionsevent@80/ZCCYC{UThe number of constant clock ticks used for the measurement interval. The clock frequency is constant at 32MHz and is set at CEC power on timeevent@88/ Z32MHZ_CYC{=UThe number of constant 32 MHZ clock ticks (Time calibration)event@c0/ZTLB_RELOAD_L2{!URadix or HPT reloads found in L2event@c8/Z0THRD_NON_IDLE_PCYC{9UThe number of processor cycles when all threads are idleevent@100/Z1THRD_NON_IDLE_INST{iUThe number of PPC instructions completed when exactly one SMT thread is executing non-idle instructionsevent@108/Z1THRD_NON_IDLE_PCYC{VUThe number of processor cycles when exactly one SMT thread is executing non-idle codeevent@140/Z2THRD_NON_IDLE_INST{@jUThe number of PPC instructions completed when exactly two SMT threads are executing non-idle instructionsevent@148/Z2THRD_NON_IDLE_PCYC{HUThe number of processor cycles when exactly two SMT threads are executing non-idle code. The cycles are only counted for threads that execute non-idle code within an LPARevent@180/Z3THRD_NON_IDLE_INST{kUThe number of PPC instruction completed when exactly three SMT threads are executing non-idle instructionsevent@188/Z3THRD_NON_IDLE_PCYC{UThe number of processor cycles when exactly three SMT threads are executing non-idle code. The cycles are only counted for threads that execute non-idle code within an LPARevent@1c0/Z4THRD_NON_IDLE_INST{kUThe number of PPC instructions completed when exactly four SMT threads are executing non-idle instructionsevent@1c8/Z4THRD_NON_IDLE_PCYC{UThe number of processor cycles when exactly four SMT threads are executing non-idle code. The cycles are only counted for threads that execute non-idle code within an LPARevent@200/ZTLB_RELOAD_L3{!URadix or HPT reloads found in L3event@240/ZTLB_RELOAD_L3_MISS{@%URadix or HPT reloads found beyond L3event@280/ ZTM_PASSED{&UNumber of TM transactions that passedevent@2c0/ZTHREAD_NAP_STATE_SAVE_CCYC{|UThe sum of all constant clock cycles across all SMT threads in Power Saving mode where the thread state is saved (DD2 only)event@2c8/ZL2L3_NODAL_PB_REQ{bUThe number of Power Bus Requests by Level 2 or Level 3 cache using Nodal (neither X-Bus or A-Bus)event@300/} ZSTCX_FIN{.UThe number of STCX instructions that finishedevent@308/| ZSTCX_FAIL{<UThe number of atomic stores (STCX instructions) that failedevent@340/&ZTLBIE{@/UThe number of TLBIE instructions that finishedevent@348/f ZLARX_FIN{HUUThe sum of all atomic loads (LARX instructions) across all SMT threads that finishedevent@388/d ZEXT_INT_OS{RUThe sum of operating system external interrupts across all SMT threads (DD2 only)event@3c0/ZBUS_PUMP_SYSTEM_CORRECT_PRED{8UThe number of times system pump was correctly predictedevent@3c8/ZBUS_PUMP_NON_FABRIC_OP{SUThe number of time the data source was local Level 2 or Level 3 cache (non fabric)event@400/ZBUS_PUMP_GROUP_CORRECT_PRED{7UThe number of times group pump was correctly predictedevent@408/ZBUS_PUMP_CHIP_CORRECT_PRED{6UThe number of times chip pump was correctly predictedevent@440/ZBUS_PUMP_GROUP_TOO_SMALL{@oUThe number of times of incorrectly predicted pump where group pump was needed but a smaller pump was predictedevent@448/ZBUS_PUMP_GROUP_TOO_LARGE{HLUThe number of times group pump was predicted where chip pump was sufficientevent@480/ZBUS_PUMP_SYSTEM_TOO_SMALL{pUThe number of times of incorrectly predicted pump where system pump was needed but a smaller pump was predictedevent@488/ZBUS_PUMP_SYSTEM_TOO_LARGE{MUThe number of times system pump was predicted where node pump was sufficientevent@4c0/ ZEXT_INT_EBB{TUThe sum of external event based branch interrupts across all SMT threads (DD2 only)event@4c8/ ZTM_ABORTS{"UNumber of TM transactions abortedevent@500/ ZEXT_INT_HYP{RUThe sum of hypervisor virtualization interrupts across all SMT threads (DD2 only)event@508/:ZL2L3_GROUP_PB_REQ{\UThe number of times Level 2 or Level 3 cache made a bus request using the group bus (X-Bus)event@540/ZEXT_INT_DOORBELL{@AUThe sum of doorbell interrupts across all SMT threads (DD2 only)event@548/kZMSR_EXT_INT_DIS_CCYC{HdUThe sum of all processor cycles across all SMT threads with external interrupts disabled (MSR EE=0)event@580/zZMSR_TRANSMEM_INST{YUThe number of PPC instructions completed while the core was in transactional memory modeevent@588/yZMSR_TRANSMEM_PCYC{bUThe sum of all processor cycles across all SMT threads in transactional memory mode with MSR TR=1event@5c0/ZTHREAD_NAP_STATE_LOSS_CCYC{UThe sum of all constant clock cycles across all SMT threads in Power Saving mode where the thread state is not saved (DD2 only)event@5c8/;ZL2L3_SYS_PB_REQ{]UThe number of times the Level 2 or Level 3 cache made a request using the system bus (A-Bus)event@600/mZMSR_PRIV_INST{VUThe number of non-idle instructions completed in privileged mode with MSR HV=0 & PR=0event@608/<ZMSR_PRIV_PCYC{GUThe number of processor cycles in privileged mode with MSR HV=0 & PR=0event@640/oZMSR_PROB_INST{@TUThe number of non-idle instructions completed in problem state with MSR HV=0 & PR=1event@648/nZMSR_PROB_PCYC{HDUThe number of processor cycles in problem mode with MSR HV=0 & PR=1event@680/l ZMSR_HV_INST{LUThe number of non-idle instructions in Hypervisor mode with MSR HV=1 & PR=0event@688/h ZMSR_HV_PCYC{GUThe number of processor cycles in Hypervisor mode with MSR HV=1 & PR=0event@6c0/jZMSR_AJUNCT_INST{MUThe number of non-idle instructions completed with MSR HV=1 & PR=1 (adjunct)event@6c8/iZMSR_ADJUNCT_PCYC{>UThe number of processor cycles with MSR HV=1 & PR=1 (adjunct)event@700/rZMSR_TA_LIC_INST{CUThe number of non-idle instructions completed with MSR US=0 & PR=0event@708/qZMSR_TA_LIC_PCYC{JUThe number of processor cycles in Tags Active LIC state (MSR US=0 & PR=0)event@740/sZMSR_TA_SYSTEM_INST{@CUThe number of non-idle instructions completed with MSR US=0 & PR=1event@748/uZMSR_TA_SYS_PCYC{HJUThe number of processor cycles Tags-Active system State (MSR US=0 & PR=1)event@780/wZMSR_TA_USER_INST{CUThe number of non-idle instructions completed with MSR US=1 & PR=1event@788/vZMSR_TA_USER_PCYC{KUThe number of processor cycles in Tags-Active user State (MSR US=1 & PR=1)event@7c0/g ZLWSYNC_PCYC{cUThe number of processor cycles stalled while waiting for a LWSYNC operation to complete (DD2 only)event@7c8/ ZSYNC_PCYC{aUThe number of processor cycles stalled while waiting for a SYNC operation to complete (DD2 only)event@800/UZCS_PCYC{7UThe sum of all processor cycles across all SMT threadsevent@808/IZCS_INST{MUThe sum of all completed PPC instructions across all SMT threads of the coreevent@840/ZCS_CORE_MODE_ST_CCYC{@DUThe number of processor cycles while the core is running in ST modeevent@848/ZCS_CORE_MODE_SMT2_CCYC{HKUThe number of constant clock cycles while the core is running in SMT2 modeevent@880/ZCS_CORE_MODE_SMT4_CCYC{<UCount of constant clock transitions while core mode is SMT4event@888/pZSMT_MODE_SWITCH{IUThe number of SMT mode switches during the measurement period (DD2 only)event@8c0/ ZCS_CORE_PCYC{?UThe number of processor cycles during the measurement intervalevent@8c8/ ZCS_32MHZ_CYC{!UThe number of 32 MHz clock ticksevent@900/^ ZCS_SPURR{ UThe number of SPURR cyclesevent@908/[ZCS_PURR{ EUThe sum of all constant clock PURR increments across all SMT threadsevent@940/ZCS_FLOP{ @6UThe number of all completed floating point operationsevent@948/ ZCS_BRU_CMPL{ H,UThe number of branch instructions completedevent@980/ ZCS_BR_MPRED{ BUThe sum of branch misdirection across all SMT threads of the coreevent@988/ ZCS_BR_TAKEN{ UThe number of branches takenevent@9c0/ZCS_DTLB_MISS_2M{ /UThe number of data TLB misses for 2M page sizeevent@9c8/~ZCS_DTLB_MISS_1G{ /UThe number of data TLB misses for 1G page sizeevent@a00/X ZCS_PPC_DISP{ IUThe sum of PPC instruction dispatches across all SMT threads of the coreevent@a08/ZCS_DISP_HELD_PCYC{ :UThe number of processor cycles the dispatch unit was heldevent@a40/RZCS_LSU_EMPTY_PCYC{ @VUThe sum of processor cycles where the LSU is empty across all SMT threads of the coreevent@a48/ZCS_CORE_ICT_EMPTY_PCYC{ H1UThe number of processor cycles the ICT was emptyevent@a80/ZCS_DATA_TABLEWALK_PCYC{ JUThe sum of table walk processor cycles across all SMT threads of the coreevent@a88/ ZCS_FLUSH{ UThe number of core flushesevent@ac0/ZCS_1PLUS_PPC_CMPL{ IUThe sum of completed PPC instructions across all SMT threads of the coreevent@ac8/ZCS_CMPLU_STALL_PCYC{ lUThe sum of all processor cycles across all SMT threads where no instruction completed and ICT was not emptyevent@b00/OZCS_L1_MISS_IFETCH{ )UThe number of level 1 instruction missesevent@b08/FZCS_IFETCH_DEMAND_PCYC{ XUThe sum of all processor cycles across all SMT threads when a demand ifetch was pendingevent@b40/ZCS_FROM_L2_IFETCH{ @;UThe number of instruction fetches from local level 2 cacheevent@b48/ZCS_FROM_L3_IFETCH{ H?UThe number of instruction fetches from the cores level 3 cacheevent@b80/.ZCS_FROM_ON_CHIP_L2_IFETCH{ QUThe number of instruction fetches from a level 2 cache from the same POWER9 chipevent@b88/4ZCS_FROM_ON_CHIP_L3_IFETCH{ MUThe number of instruction fetches from level 3 cache on the same POWER9 chipevent@bc0/ZCS_FROM_L4_IFETCH{ ;UThe number of instruction fetches from local level 4 cacheevent@bc8/"ZCS_FROM_MEM_IFETCH{ 4UThe number of instruction fetches from local memoryevent@c00/ZCS_FROM_L2_L3_X_IFETCH{ NUThe number of instruction fetches from level 2 or level 3 cache across X-linkevent@c08/ZCS_FROM_L2_L3_A_IFETCH{ HUThe number of instruction fetches from level 2 or level 3 across A-linkevent@c40/ZCS_FROM_L4_MEM_X_IFETCH{ @OUThe number of instruction fetches from a level 4 cache or memory across X-linkevent@c48/ ZCS_FROM_L4_MEM_A_IFETCH{ HMUThe number of instruction fetches from level 4 cache or memory across A-linkevent@c80/@ZCS_MISS_L1_LDATA{ "UThe number of level 1 data missesevent@cc0/ZCS_FROM_L2_LDATA{ 'UThe number of local level 2 data loadsevent@cc8/ZCS_FROM_L3_LDATA{ 6UThe number of data loads from the cores level 3 cacheevent@d00/1ZCS_FROM_ON_CHIP_L2_LDATA{ HUThe number of data loads from a level 2 cache from the same POWER9 chipevent@d08/7ZCS_FROM_ON_CHIP_L3_LDATA{ HUThe number of data loads from a level 3 cache from the same POWER9 chipevent@d40/ZCS_FROM_L4_LDATA{ @:UThe number of level 4 data loads from local level 4 cacheevent@d48/%ZCS_FROM_MEM_LDATA{ H+UThe number of data loads from local memoryevent@d80/ZCS_FROM_L2_L3_X_LDATA{ GUThe number of data loads from a level 2 or level 3 cache across X-linkevent@d88/ZCS_FROM_L2_L3_A_LDATA{ FUThe number of data loads from level 2 or level 3 cache through A-linkevent@dc0/ZCS_FROM_L4_MEM_X_LDATA{ EUThe number of data load from a level 4 cache or memory across X-linkevent@dc8/ZCS_FROM_L4_MEM_A_LDATA{ DUThe number of data loads from level 4 cache or memory across A-linkevent@e00/aZCS_ST_MISS_L1{/UThe number of stores that missed level 1 cacheevent@e08/= ZCS_ST_FIN{.UThe number of all store instructions finishedevent@e40/CZCS_IERAT_MISS{@UThe number of IERAT reloadsevent@e48/LZCS_ITLB_RELOAD{H&UThe number of instruction TLB reloadsevent@e80/ZCS_FROM_L4_MEM_X_IPTEG{_UThe number of instruction PTEG L3 misses that are satisfied by off-chip- but node-local sourceevent@e88/ZCS_FROM_L4_MEM_A_IPTEG{dUThe number of instruction PTEG misses that are satisfied from level 4 cache of memory across A-linkevent@ec0/ZCS_DERAT_MISS{UThe number of DERAT missesevent@ec8/ZCS_DTLB_RELOAD{UThe number of data TLB reloadsevent@f00/ZCS_DTLB_MISS_4K{/UThe number of data TLB misses for 4K page sizeevent@f08/ZCS_DTLB_MISS_64K{0UThe number of data TLB misses for 64K page sizeevent@f40/ZCS_DTLB_MISS_16M{@0UThe number of data TLB misses for 16M page sizeevent@f48/ZCS_DTLB_MISS_16G{H0UThe number of data TLB misses for 16G page sizeevent@f80/ZCS_FROM_L4_MEM_X_DPTEG{^UThe number of instruction PTEG L3 misses that are satisfied by off-chip but node-local sourceevent@f88/ ZCS_FROM_L4_MEM_A_DPTEG{]UThe number of data PTEG misses that are satisfied from level 4 cache of memory across A-linkevent@fc0/+ZCS_FROM_MEM_NON_LOCAL{ZUThe number of all data and instruction cache misses that are satisfied by Off-Chip Memoryevent@fc8/(ZCS_FROM_MEM_LOCAL{MUThe number of data and instruction misses that are satisfied by local memoryevent@1000/W ZCS_PCYC_USER{EUThe sum of all processor cycles across all SMT threads in user stateevent@1008/K ZCS_INST_USER{[UThe sum of all completed PPC instructions across all SMT threads of the core in user stateevent@1040/ZCS_CORE_MODE_ST_CCYC_USER{@VUThe number of processor cycles in the user state while the core is running in ST modeevent@1048/ZCS_CORE_MODE_SMT2_CCYC_USER{HYUThe number of constant clock cycles in user state while the core is running in SMT2 modeevent@1080/ZCS_CORE_MODE_SMT4_CCYC_USER{JUCount of constant clock transitions in user state while core mode is SMT4event@1088/xZSMT_MODE_SWITCH_USER{VUThe number of SMT mode switches during the measurement period in user state(DD2 only)event@10c0/ZCS_CORE_PCYC_USER{MUThe number of processor cycles in user state during the measurement intervalevent@10c8/ZCS_32MHZ_CYC_USER{/UThe number of 32 MHz clock ticks in user spaceevent@1100/`ZCS_SPURR_USER{)UThe number of SPURR cycles in user stateevent@1108/] ZCS_PURR_USER{SUThe sum of all constant clock PURR increments across all SMT threads in user stateevent@1140/ ZCS_FLOP_USER{@DUThe number of all completed floating point operations in user stateevent@1148/ZCS_BRU_CMPL_USER{H:UThe number of branch instructions completed in user spaceevent@1180/ZCS_BR_MPRED_USER{PUThe sum of branch misdirection across all SMT threads of the core in user spaceevent@1188/ZCS_BR_TAKEN_USER{+UThe number of branches taken in user spaceevent@11c0/ZCS_DTLB_MISS_2M_USER{=UThe number of data TLB misses for 2M page size in user stateevent@11c8/ZCS_DTLB_MISS_1G_USER{=UThe number of data TLB misses for 1G page size in user stateevent@1200/ZZCS_PPC_DISP_USER{WUThe sum of PPC instruction dispatches across all SMT threads of the core in user stateevent@1208/ZCS_DISP_HELD_PCYC_USER{HUThe number of processor cycles the dispatch unit was held in user stateevent@1240/TZCS_LSU_EMPTY_PCYC_USER{@dUThe sum of processor cycles where the LSU is empty across all SMT threads of the core in user stateevent@1248/ZCS_CORE_ICT_EMPTY_PCYC_USER{H?UThe number of processor cycles the ICT was empty in user stateevent@1280/ZCS_DATA_TABLEWALK_PCYC_USER{XUThe sum of table walk processor cycles across all SMT threads of the core in user stateevent@1288/ZCS_FLUSH_USER{-UThe number of core flushes in the user stateevent@12c0/ZCS_1PLUS_PPC_CMPL_USER{NUThe user sum of completed PPC instructions across all SMT threads of the coreevent@12c8/ZCS_CMPLU_STALL_PCYC_USER{qUThe user sum of all processor cycles across all SMT threads where no instruction completed and ICT was not emptyevent@1300/QZCS_L1_MISS_IFETCH_USER{7UThe number of level 1 instruction misses in user stateevent@1308/HZCS_IFETCH_DEMAND_PCYC_USER{fUThe sum of all processor cycles across all SMT threads when a demand ifetch was pending in user stateevent@1340/ZCS_FROM_L2_IFETCH_USER{@IUThe number of instruction fetches from local level 2 cache in user stateevent@1348/ZCS_FROM_L3_IFETCH_USER{HMUThe number of instruction fetches from the cores level 3 cache in user stateevent@1380/0ZCS_FROM_ON_CHIP_L2_IFETCH_USER{_UThe number of instruction fetches from a level 2 cache from the same POWER9 chip in user stateevent@1388/6ZCS_FROM_ON_CHIP_L3_IFETCH_USER{[UThe number of instruction fetches from level 3 cache on the same POWER9 chip in user stateevent@13c0/ZCS_FROM_L4_IFETCH_USER{IUThe number of instruction fetches from local level 4 cache in user stateevent@13c8/$ZCS_FROM_MEM_IFETCH_USER{BUThe number of instruction fetches from local memory in user stateevent@1400/ZCS_FROM_L2_L3_X_IFETCH_USER{\UThe number of instruction fetches from level 2 or level 3 cache across X-link in user stateevent@1408/ZCS_FROM_L2_L3_A_IFETCH_USER{VUThe number of instruction fetches from level 2 or level 3 across A-link in user stateevent@1440/ZCS_FROM_L4_MEM_X_IFETCH_USER{@]UThe number of instruction fetches from a level 4 cache or memory across X-link in user stateevent@1448/ZCS_FROM_L4_MEM_A_IFETCH_USER{H[UThe number of instruction fetches from level 4 cache or memory across A-link in user stateevent@1480/BZCS_MISS_L1_LDATA_USER{0UThe number of level 1 data misses in user stateevent@14c0/ZCS_FROM_L2_LDATA_USER{5UThe number of local level 2 data loads in user stateevent@14c8/ZCS_FROM_L3_LDATA_USER{DUThe number of data loads from the cores level 3 cache in user stateevent@1500/3ZCS_FROM_ON_CHIP_L2_LDATA_USER{VUThe number of data loads from a level 2 cache from the same POWER9 chip in user stateevent@1508/9ZCS_FROM_ON_CHIP_L3_LDATA_USER{VUThe number of data loads from a level 3 cache from the same POWER9 chip in user stateevent@1540/ ZCS_FROM_L4_LDATA_USER{@HUThe number of level 4 data loads from local level 4 cache in user stateevent@1548/'ZCS_FROM_MEM_LDATA_USER{H9UThe number of data loads from local memory in user stateevent@1580/ZCS_FROM_L2_L3_X_LDATA_USER{UUThe number of data loads from a level 2 or level 3 cache across X-link in user stateevent@1588/ZCS_FROM_L2_L3_A_LDATA_USER{TUThe number of data loads from level 2 or level 3 cache through A-link in user stateevent@15c0/!ZCS_FROM_L4_MEM_X_LDATA_USER{SUThe number of data load from a level 4 cache or memory across X-link in user stateevent@15c8/ZCS_FROM_L4_MEM_A_LDATA_USER{RUThe number of data loads from level 4 cache or memory across A-link in user stateevent@1600/cZCS_ST_MISS_L1_USER{=UThe number of stores that missed level 1 cache in user stateevent@1608/?ZCS_ST_FIN_USER{<UThe number of all store instructions finished in user stateevent@1640/EZCS_IERAT_MISS_USER{@*UThe number of IERAT reloads in user stateevent@1648/NZCS_ITLB_RELOAD_USER{H4UThe number of instruction TLB reloads in user stateevent@1680/ZCS_FROM_L4_MEM_X_IPTEG_USER{mUThe number of instruction PTEG L3 misses that are satisfied by off-chip- but node-local source in user stateevent@1688/ZCS_FROM_L4_MEM_A_IPTEG_USER{rUThe number of instruction PTEG misses that are satisfied from level 4 cache of memory across A-link in user stateevent@16c0/ZCS_DERAT_MISS_USER{)UThe number of DERAT misses in user stateevent@16c8/ZCS_DTLB_RELOAD_USER{-UThe number of data TLB reloads in user stateevent@1700/ZCS_DTLB_MISS_4K_USER{=UThe number of data TLB misses for 4K page size in user stateevent@1708/ZCS_DTLB_MISS_64K_USER{>UThe number of data TLB misses for 64K page size in user stateevent@1740/ZCS_DTLB_MISS_16M_USER{@>UThe number of data TLB misses for 16M page size in user stateevent@1748/ZCS_DTLB_MISS_16G_USER{H>UThe number of data TLB misses for 16G page size in user stateevent@1780/ZCS_FROM_L4_MEM_X_DPTEG_USER{lUThe number of instruction PTEG L3 misses that are satisfied by off-chip but node-local source in user stateevent@1788/ ZCS_FROM_L4_MEM_A_DPTEG_USER{kUThe number of data PTEG misses that are satisfied from level 4 cache of memory across A-link in user stateevent@17c0/-ZCS_FROM_MEM_NON_LOCAL_USER{hUThe number of all data and instruction cache misses that are satisfied by Off-Chip Memory in user stateevent@17c8/*ZCS_FROM_MEM_LOCAL_USER{[UThe number of data and instruction misses that are satisfied by local memory in user stateevent@1800/VZCS_PCYC_KERNEL{GUThe sum of all processor cycles across all SMT threads in kernel stateevent@1808/JZCS_INST_KERNEL{]UThe sum of all completed PPC instructions across all SMT threads of the core in kernel stateevent@1840/ZCS_CORE_MODE_ST_CCYC_KERNEL{@RUThe number of processor cycles in the kernel while the core is running in ST modeevent@1848/ZCS_CORE_MODE_SMT2_CCYC_KERNEL{HYUThe number of constant clock cycles in the kernel while the core is running in SMT2 modeevent@1880/ZCS_CORE_MODE_SMT4_CCYC_KERNEL{LUCount of constant clock transitions in kernel state while core mode is SMT4event@1888/tZSMT_MODE_SWITCH_KERNEL{XUThe number of SMT mode switches during the measurement period in kernel state(DD2 only)event@18c0/ZCS_CORE_PCYC_KERNEL{OUThe number of processor cycles in kernel state during the measurement intervalevent@18c8/ZCS_32MHZ_CYC_KERNEL{/UThe number of 32 MHz clock ticks in the kernelevent@1900/_ZCS_SPURR_KERNEL{+UThe number of SPURR cycles in kernel stateevent@1908/\ZCS_PURR_KERNEL{UUThe sum of all constant clock PURR increments across all SMT threads in kernel stateevent@1940/ZCS_FLOP_KERNEL{@FUThe number of all completed floating point operations in kernel stateevent@1948/ZCS_BRU_CMPL_KERNEL{H:UThe number of branch instructions completed in the kernelevent@1980/ZCS_BR_MPRED_KERNEL{PUThe sum of branch misdirection across all SMT threads of the core in the kernelevent@1988/ZCS_BR_TAKEN_KERNEL{'UThe number of branches taken in kernelevent@19c0/ZCS_DTLB_MISS_2M_KERNEL{?UThe number of data TLB misses for 2M page size in kernel stateevent@19c8/ZCS_DTLB_MISS_1G_KERNEL{?UThe number of data TLB misses for 1G page size in kernel stateevent@1a00/YZCS_PPC_DISP_KERNEL{YUThe sum of PPC instruction dispatches across all SMT threads of the core in kernel stateevent@1a08/ZCS_DISP_HELD_PCYC_KERNEL{JUThe number of processor cycles the dispatch unit was held in kernel stateevent@1a40/SZCS_LSU_EMPTY_PCYC_KERNEL{@fUThe sum of processor cycles where the LSU is empty across all SMT threads of the core in kernel stateevent@1a48/ZCS_CORE_ICT_EMPTY_PCYC_KERNEL{HAUThe number of processor cycles the ICT was empty in kernel stateevent@1a80/ZCS_DATA_TABLEWALK_PCYC_KERNEL{ZUThe sum of table walk processor cycles across all SMT threads of the core in kernel stateevent@1a88/ZCS_FLUSH_KERNEL{/UThe number of core flushes in the kernel stateevent@1ac0/ZCS_1PLUS_PPC_CMPL_KERNEL{QUThe kernel sum of completed PPC instructions across all SMT threads of the core event@1ac8/ZCS_CMPLU_STALL_PCYC_KERNEL{sUThe kernel sum of all processor cycles across all SMT threads where no instruction completed and ICT was not emptyevent@1b00/PZCS_L1_MISS_IFETCH_KERNEL{9UThe number of level 1 instruction misses in kernel stateevent@1b08/GZCS_IFETCH_DEMAND_PCYC_KERNEL{hUThe sum of all processor cycles across all SMT threads when a demand ifetch was pending in kernel stateevent@1b40/ZCS_FROM_L2_IFETCH_KERNEL{@KUThe number of instruction fetches from local level 2 cache in kernel stateevent@1b48/ZCS_FROM_L3_IFETCH_KERNEL{HOUThe number of instruction fetches from the cores level 3 cache in kernel stateevent@1b80//!ZCS_FROM_ON_CHIP_L2_IFETCH_KERNEL{aUThe number of instruction fetches from a level 2 cache from the same POWER9 chip in kernel stateevent@1b88/5!ZCS_FROM_ON_CHIP_L3_IFETCH_KERNEL{]UThe number of instruction fetches from level 3 cache on the same POWER9 chip in kernel stateevent@1bc0/ZCS_FROM_L4_IFETCH_KERNEL{KUThe number of instruction fetches from local level 4 cache in kernel stateevent@1bc8/#ZCS_FROM_MEM_IFETCH_KERNEL{DUThe number of instruction fetches from local memory in kernel stateevent@1c00/ZCS_FROM_L2_L3_X_IFETCH_KERNEL{^UThe number of instruction fetches from level 2 or level 3 cache across X-link in kernel stateevent@1c08/ZCS_FROM_L2_L3_A_IFETCH_KERNEL{XUThe number of instruction fetches from level 2 or level 3 across A-link in kernel stateevent@1c40/ZCS_FROM_L4_MEM_X_IFETCH_KERNEL{@_UThe number of instruction fetches from a level 4 cache or memory across X-link in kernel stateevent@1c48/ZCS_FROM_L4_MEM_A_IFETCH_KERNEL{H]UThe number of instruction fetches from level 4 cache or memory across A-link in kernel stateevent@1c80/AZCS_MISS_L1_LDATA_KERNEL{2UThe number of level 1 data misses in kernel stateevent@1cc0/ZCS_FROM_L2_LDATA_KERNEL{7UThe number of local level 2 data loads in kernel stateevent@1cc8/ZCS_FROM_L3_LDATA_KERNEL{FUThe number of data loads from the cores level 3 cache in kernel stateevent@1d00/2 ZCS_FROM_ON_CHIP_L2_LDATA_KERNEL{XUThe number of data loads from a level 2 cache from the same POWER9 chip in kernel stateevent@1d08/8 ZCS_FROM_ON_CHIP_L3_LDATA_KERNEL{XUThe number of data loads from a level 3 cache from the same POWER9 chip in kernel stateevent@1d40/ZCS_FROM_L2_L3_X_LDATA_KERNEL{@WUThe number of data loads from a level 2 or level 3 cache across X-link in kernel stateevent@1d48/ZCS_FROM_L2_L3_A_LDATA_KERNEL{HVUThe number of data loads from level 2 or level 3 cache through A-link in kernel stateevent@1d80/ ZCS_FROM_L4_MEM_X_LDATA_KERNEL{UUThe number of data load from a level 4 cache or memory across X-link in kernel stateevent@1d88/ZCS_FROM_L4_MEM_A_LDATA_KERNEL{TUThe number of data loads from level 4 cache or memory across A-link in kernel stateevent@1dc0/bZCS_ST_MISS_L1_KERNEL{?UThe number of stores that missed level 1 cache in kernel stateevent@1dc8/>ZCS_ST_FIN_KERNEL{>UThe number of all store instructions finished in kernel stateevent@1e00/DZCS_IERAT_MISS_KERNEL{,UThe number of IERAT reloads in kernel stateevent@1e08/MZCS_ITLB_RELOAD_KERNEL{6UThe number of instruction TLB reloads in kernel stateevent@1e40/ZCS_FROM_L4_MEM_X_IPTEG_KERNEL{@oUThe number of instruction PTEG L3 misses that are satisfied by off-chip- but node-local source in kernel stateevent@1e48/ZCS_FROM_L4_MEM_A_IPTEG_KERNEL{HtUThe number of instruction PTEG misses that are satisfied from level 4 cache of memory across A-link in kernel stateevent@1e80/ZCS_DERAT_MISS_KERNEL{+UThe number of DERAT misses in kernel stateevent@1e88/ZCS_DTLB_RELOAD_KERNEL{/UThe number of data TLB reloads in kernel stateevent@1ec0/ZCS_DTLB_MISS_4K_KERNEL{?UThe number of data TLB misses for 4K page size in kernel stateevent@1ec8/ZCS_DTLB_MISS_64K_KERNEL{@UThe number of data TLB misses for 64K page size in kernel stateevent@1f00/ZCS_DTLB_MISS_16M_KERNEL{@UThe number of data TLB misses for 16M page size in kernel stateevent@1f08/ZCS_DTLB_MISS_16G_KERNEL{@UThe number of data TLB misses for 16G page size in kernel stateevent@1f40/ZCS_FROM_L4_MEM_X_DPTEG_KERNEL{@nUThe number of instruction PTEG L3 misses that are satisfied by off-chip but node-local source in kernel stateevent@1f48/ ZCS_FROM_L4_MEM_A_DPTEG_KERNEL{HmUThe number of data PTEG misses that are satisfied from level 4 cache of memory across A-link in kernel stateevent@1f88/)ZCS_FROM_MEM_LOCAL_KERNEL{]UThe number of data and instruction misses that are satisfied by local memory in kernel stateevent@1fc0/,ZCS_FROM_MEM_NON_LOCAL_KERNEL{jUThe number of all data and instruction cache misses that are satisfied by Off-Chip Memory in kernel statecore@18/ ibm,imc-countersCPM_512{ mba0@448/ ibm,imc-counters PM_MBA0_1{Hroe  bmba1@460/ ibm,imc-counters PM_MBA1_1{`roe  bmba4@558/ ibm,imc-counters PM_MBA4_1{Xroe  bmba5@570/ ibm,imc-counters PM_MBA5_1{proe  bmcs01@c8/ ibm,imc-counters PM_MCS01_256{roe  bmcs23@48/ ibm,imc-counters PM_MCS23_256{Hroe  bnest-alink-out-events/ event@0/rZOUT_EVEN_AVLBL_CYC{event@8/sZOUT_EVEN_ANY_RCMD{event@10/tZOUT_EVEN_DATA_COUNT{event@18/uZOUT_EVEN_TOTAL_UTIL{event@20/vZOUT_ODD_AVLBL_CYC{ event@28/wZOUT_ODD_ANY_RCMD{(event@30/xZOUT_ODD_DATA_COUNT{0event@38/yZOUT_ODD_TOTAL_UTIL{8nest-capp-events/ event@0/ZCYC_A{event@8/ZAPC_UOP_SEND_PB_CMD{event@10/ ZAPC_UOP_LCO{event@18/ZAPC_UOP_DATA_XFER{event@20/ZCYC_B{ event@28/ZXPT_MSG_SENT_LE_16{(event@30/ZXPT_MSG_SENT_GT_16_LE_64{0event@38/ ZXPT_MSG_SENT_TSIZE_GT_64_LE_128{8nest-centaur-events/ event@0/ZPORT0_READ_BYTES{event@8/ZPORT0_WRITE_BYTES{event@10/ZPORT0_DRAM_CLK_CYC{event@18/ZPORT1_READ_BYTES{event@20/ZPORT1_WRITE_BYTES{ event@28/ZPORT1_DRAM_CLK_CYC{(nest-mba-events/ event@0/ ZREAD_BYTES{event@8/ ZWRITE_BYTES{event@10/ZCLK_CYC{nest-mcs-events/ event@0/Z64B_RD_DISP_PORT01{UTotal 64 byte reads/writes dispatched for mcs01 on port01. (These are 64Byte request and not get counted in 128byte read request)event@8/Z128B_RD_DISP_PORT01{4UTotal Read 128-byte data blocks for mcs01 on port01event@10/Z128B_WR_DISP_PORT01{5UTotal Write 128-byte data blocks for mcs01 on port01event@18/ZAMO_OP_DISP_PORT01{:UAMO (Atomic Memory Operation) command dispatched in mcs01event@20/Z64B_RD_DISP_PORT23{ {UTotal 64 byte reads dispatched for mcs01 on port23. (These are 64Byte request and not get counted in 128byte read request)event@28/Z128B_RD_DISP_PORT23{(4UTotal Read 128-byte data blocks for mcs01 on port23event@30/Z128B_WR_DISP_PORT23{05UTotal Write 128-byte data blocks for mcs01 on port23nest-nvlink0-events/ event@228/2ZPM_NTL0_CLK_CYC{(event@230/3ZPM_NTL0_TX_DATA_FLIT{0event@238/4ZPM_NTL0_RX_ANY_FLIT{8event@240/5ZPM_NTL0_RX_DATA_FLIT{@event@2e8/:ZPM_ATS_TCE_TRANS_REQ{event@2f0/;ZPM_ATS_TCE_MISS{event@2f8/<ZPM_ATS_NO_TRANS_TCE{event@300/=ZPM_ATS_CACHE_RERUN{event@308/> ZPM_XTS_ATR_DEMAND_CHECKOUT_MISS{event@310/?ZPM_XTS_ATR_DEMAND_CHECKOUT{event@318/@ZPM_XTS_ATSD_TLBI_RCV{event@320/AZPM_XTS_ATSD_SENT{ event@668/6ZPM_NPCQ0_CREQ_BRICK0{hevent@670/7ZPM_NPCQ0_DOWNGRADE_REQ_BRICK0{pevent@678/8ZPM_NPCQ0_CREQ_BRICK1{xevent@680/9ZPM_NPCQ0_DOWNGRADE_REQ_BRICK1{nest-nvlink1-events/ event@248/ ZPM_NTL1_CLK_CYC{Hevent@250/!ZPM_NTL1_TX_DATA_FLIT{Pevent@258/"ZPM_NTL1_RX_ANY_FLIT{Xevent@260/#ZPM_NTL1_RX_DATA_FLIT{`event@2e8/(ZPM_ATS_TCE_TRANS_REQ{event@2f0/)ZPM_ATS_TCE_MISS{event@2f8/*ZPM_ATS_NO_TRANS_TCE{event@300/+ZPM_ATS_CACHE_RERUN{event@308/, ZPM_XTS_ATR_DEMAND_CHECKOUT_MISS{event@310/-ZPM_XTS_ATR_DEMAND_CHECKOUT{event@318/.ZPM_XTS_ATSD_TLBI_RCV{event@320//ZPM_XTS_ATSD_SENT{ event@668/$ZPM_NPCQ0_CREQ_BRICK0{hevent@670/%ZPM_NPCQ0_DOWNGRADE_REQ_BRICK0{pevent@678/&ZPM_NPCQ0_CREQ_BRICK1{xevent@680/'ZPM_NPCQ0_DOWNGRADE_REQ_BRICK1{nest-nvlink2-events/ event@268/ZPM_NTL2_CLK_CYC{hevent@270/ZPM_NTL2_TX_DATA_FLIT{pevent@278/ZPM_NTL2_RX_ANY_FLIT{xevent@280/ZPM_NTL2_RX_DATA_FLIT{event@2e8/ZPM_ATS_TCE_TRANS_REQ{event@2f0/ZPM_ATS_TCE_MISS{event@2f8/ZPM_ATS_NO_TRANS_TCE{event@300/ZPM_ATS_CACHE_RERUN{event@308/ ZPM_XTS_ATR_DEMAND_CHECKOUT_MISS{event@310/ZPM_XTS_ATR_DEMAND_CHECKOUT{event@318/ZPM_XTS_ATSD_TLBI_RCV{event@320/ZPM_XTS_ATSD_SENT{ event@688/ZPM_NPCQ1_CREQ_BRICK0{event@690/ZPM_NPCQ1_DOWNGRADE_REQ_BRICK0{event@698/ZPM_NPCQ1_CREQ_BRICK1{event@6a0/ZPM_NPCQ1_DOWNGRADE_REQ_BRICK1{nest-nvlink3-events/ event@288/ZPM_NTL3_CLK_CYC{event@290/ZPM_NTL3_TX_DATA_FLIT{event@298/ZPM_NTL3_RX_ANY_FLIT{event@2a0/ZPM_NTL3_RX_DATA_FLIT{event@2e8/ZPM_ATS_TCE_TRANS_REQ{event@2f0/ZPM_ATS_TCE_MISS{event@2f8/ZPM_ATS_NO_TRANS_TCE{event@300/ZPM_ATS_CACHE_RERUN{event@308/ ZPM_XTS_ATR_DEMAND_CHECKOUT_MISS{event@310/ ZPM_XTS_ATR_DEMAND_CHECKOUT{event@318/ ZPM_XTS_ATSD_TLBI_RCV{event@320/ ZPM_XTS_ATSD_SENT{ event@688/ZPM_NPCQ1_CREQ_BRICK0{event@690/ZPM_NPCQ1_DOWNGRADE_REQ_BRICK0{event@698/ZPM_NPCQ1_CREQ_BRICK1{event@6a0/ZPM_NPCQ1_DOWNGRADE_REQ_BRICK1{nest-nvlink4-events/ event@2a8/VZPM_NTL4_CLK_CYC{event@2b0/WZPM_NTL4_TX_DATA_FLIT{event@2b8/XZPM_NTL4_RX_ANY_FLIT{event@2c0/YZPM_NTL4_RX_DATA_FLIT{event@2e8/^ZPM_ATS_TCE_TRANS_REQ{event@2f0/_ZPM_ATS_TCE_MISS{event@2f8/`ZPM_ATS_NO_TRANS_TCE{event@300/aZPM_ATS_CACHE_RERUN{event@308/b ZPM_XTS_ATR_DEMAND_CHECKOUT_MISS{event@310/cZPM_XTS_ATR_DEMAND_CHECKOUT{event@318/dZPM_XTS_ATSD_TLBI_RCV{event@320/eZPM_XTS_ATSD_SENT{ event@6a8/ZZPM_NPCQ2_CREQ_BRICK0{event@6b0/[ZPM_NPCQ2_DOWNGRADE_REQ_BRICK0{event@6b8/\ZPM_NPCQ2_CREQ_BRICK1{event@6c0/]ZPM_NPCQ2_DOWNGRADE_REQ_BRICK1{nest-nvlink5-events/ event@2c8/DZPM_NTL5_CLK_CYC{event@2d0/EZPM_NTL5_TX_DATA_FLIT{event@2d8/FZPM_NTL5_RX_ANY_FLIT{event@2e0/GZPM_NTL5_RX_DATA_FLIT{event@2e8/LZPM_ATS_TCE_TRANS_REQ{event@2f0/MZPM_ATS_TCE_MISS{event@2f8/NZPM_ATS_NO_TRANS_TCE{event@300/OZPM_ATS_CACHE_RERUN{event@308/P ZPM_XTS_ATR_DEMAND_CHECKOUT_MISS{event@310/QZPM_XTS_ATR_DEMAND_CHECKOUT{event@318/RZPM_XTS_ATSD_TLBI_RCV{event@320/SZPM_XTS_ATSD_SENT{ event@6a8/HZPM_NPCQ2_CREQ_BRICK0{event@6b0/IZPM_NPCQ2_DOWNGRADE_REQ_BRICK0{event@6b8/JZPM_NPCQ2_CREQ_BRICK1{event@6c0/KZPM_NPCQ2_DOWNGRADE_REQ_BRICK1{nest-nx-events/ event@0/h ZIDLE_CH0{event@8/i ZIDLE_CH2{event@10/j ZIDLE_CH4{event@18/k ZSTALL_IN_CH4{event@20/l ZERAT_LOOKUP{ event@28/m ZERAT_MISS{(event@30/nZERAT_STALLED_CICO_BUFFERS{0event@38/o ZDMA_STALLED{8nest-phb-events/ event@0/ZCYC{event@8/ZDMA_RD_FROM_PCIE{event@10/ZDMA_WR_FROM_PCIE{event@18/ZLD_RESP_FROM_PCIE{nest-powerbus-events/ event@0/ZEVENT_VG_PUMP{0UVg Scope operation (locally mastered) on port nevent@8/ZEVENT_LNS_PUMP{9ULocal Nodal Scope operation (locally mastered) on port nevent@10/ZEVENT_GROUP_PUMP{3UGroup Scope operation (locally mastered) on port nevent@18/ZEVENT_RNS_PUMP{:URemote Nodal Scope operation (locally mastered) on port nevent@20/ZEVENT_RTY_VG_PUMP{ eURetry of a Vg Scope operation (locally mastered) - Retry due to (rty_dropped_rcmd;rty_lpc;rty_other)event@28/ZEVENT_RTY_LNS_PUMP{(lURetry of a Nodal Scope operation (locally mastered) - Retry due to (rty_dropped_rcmd;rty_lpc;rty_other;etc)event@30/ZEVENT_RTY_GROUP_PUMP{0jURetry of a Group Scope operation (locally mastered) - Retry due to (rty_dropped_rcmd; rty_lpc; rty_other)event@38/ZEVENT_RTY_RNS_PUMP{8iURetry of a Remote Nodal Scope op (locally mastered)- Retry due to (rty_dropped_rcmd; rty_lpc; rty_other)event@78/ZCYC{xevent@80/ ZVG_PUMP_P01{event@88/ ZLNS_PUMP_P01{event@90/ZGROUP_PUMP_P01{event@98/ ZRNS_PUMP_P01{event@a0/ZINT_DATA_XFER{9U16x 32B OW Internal Data transfer on a PB horizontal busevent@a8/ZEXT_DATA_XFER{=U16x 32B OW External Data transfer on a PB X/A horizontal busevent@b0/ ZNNS_PUMP{.UNear Nodal Scope operation (locally mastered)event@b8/ZRTY_NNS_PUMP_P01{gURetry of a Near Nodal Scope op (locally mastered)- Retry due to (rty_dropped_rcmd; rty_lpc; rty_other)event@f8/ZCYC2{nest-xlink-out-events/ event@0/ ZOUT_EVEN_CYC{event@8/ZOUT_EVEN_ANY_RCMD{event@10/ZOUT_EVEN_DATA_COUNT{event@18/ZOUT_EVEN_TOTAL_UTIL{event@20/ ZOUT_ODD_CYC{ event@28/ZOUT_ODD_ANY_RCMD{(event@30/ZOUT_ODD_DATA_COUNT{0event@38/ZOUT_ODD_TOTAL_UTIL{8event@c0/ZOUT_EVEN_AVLBL_CYC{event@c8/ZOUT_ODD_AVLBL_CYC{nx@3f8/p ibm,imc-countersPM_NX_256{roe  bphb0@338/ ibm,imc-counters PM_PHB0_1{8roe  bphb1@358/ ibm,imc-counters PM_PHB1_1{Xroe  bphb2@378/ ibm,imc-counters PM_PHB2_1{xroe  bphb3@398/ ibm,imc-counters PM_PHB3_1{roe  bpowerbus0@8/ ibm,imc-countersPM_PB_256{roe  bthread@18/ ibm,imc-countersCPM_512{ trace-events/ event@10200000/Zcycles{ UReference cyclestrace@0/ ibm,imc-counterstrace_{xlink1@158/ ibm,imc-counters PM_XLINK1_4096{Xroe  binterrupt-controller@0/{ ibm,opal-xive-vcIBM,opal-xics  w$PowerPC-Interrupt-Source-Controller binterrupt-controller@6030203180000/@{ ibm,opal-xive-peibm,opal-intcC .ipl-params/ ipl-params/ temptempcoldplatform-dump/sys-params/  01 ylpcm-opb@6030000000000/:  ibm,power9-lpcm-opbsimple-bus{^ lpc-controller@c0012000/= ibm,power9-lpc-controller{ lpc@0/>  ibm,power9-lpcibm,power8-lpc0q(c  P wipmi-bt@ie4/ { ipmi-bt reserved  >serial@i3f8/? { ns16550B   serial reservedopb-arbiter@c0011000/< ibm,power9-lpcm-opb-arbiter{opb-master@c0010000/; ibm,power9-lpcm-opb-master{`memory@0/memory{@^ memory@4000000000/memory{@^ memory@200000000000/ memory{ ^ pciex@600c3c0000000/ ibm,power9-pciexibm,ioda3-phbpciex {2  @  @   !@/^UOPWR.A100034-Node0-Proc00TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww   w  @l[F2     8 8 8 !v b okaypci@0/H=1'n[F6CPU1 Slot2 (16x)%UOPWR.A100034-Node0-CPU1 Slot2 (16x)%UOPWR.A100034-Node0-CPU1 Slot2 (16x){  wpciexPpc +pci@0/H=1'$ CPU1 Slot2 (16x){  wpciexPc    ((((00008888@@@@HHHHPPPPXXXX````hhhhppppxxxx +pci@1/H=1'$  n[F6S000003UOPWR.A100034-Node0-S000003CPU1 Slot2 (16x){  wpciexPpc +mass-storage@0/H=1'M S000003{pci@2/H=1'$ CPU1 Slot2 (16x){  wpciexPpc +mass-storage@0/H=1'M  CPU1 Slot2 (16x){pci@8/H=1'$ CPU1 Slot2 (16x){@  wpciexPpc +pci@9/H=1'$  n[F6S00000aUOPWR.A100034-Node0-S00000aCPU1 Slot2 (16x){H  wpciexPpc +usb-xhci@0/H= 01'!!B S00000a{ pci@a/H=1'$ CPU1 Slot2 (16x){P  wpciexPpc +ethernet@0/H=1'j CPU1 Slot2 (16x){ pciex@600c3c0100000/ ibm,power9-pciexibm,ioda3-phbpciex { 2@@  !@@1^UOPWR.A100034-Node0-Proc00TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww   w  +@@@l[F2     8 8 8!v b okaypci@0/H=1'n[F6CPU1 Slot1 (8x)$UOPWR.A100034-Node0-CPU1 Slot1 (8x)$UOPWR.A100034-Node0-CPU1 Slot1 (8x){  wpciexPpc +multimedia-device@0/H=1' CPU1 Slot1 (8x){pciex@600c3c0200000/ ibm,power9-pciexibm,ioda3-phbpciex { @2 @ !@2^UOPWR.A100034-Node0-Proc00TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww   w  +@l[F2     8 8 8!v b okaypci@0/H=1'n[F6 Builtin SAS UOPWR.A100034-Node0-Builtin SAS UOPWR.A100034-Node0-Builtin SAS{  wpciexPpc +sas@0/H=1'  Builtin SAS{pciex@600c3c0300000/ ibm,power9-pciexibm,ioda3-phbpciex {0`2@@  !@4^UOPWR.A100034-Node0-Proc00TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww   w  +@l[F2     8 8 8 !v b okaypci@0/H=1'n[F6 Builtin USB UOPWR.A100034-Node0-Builtin USB UOPWR.A100034-Node0-Builtin USB{  wpciexPpc +usb-xhci@0/H= 01'LA  Builtin USB{pciex@600c3c0400000/ ibm,power9-pciexibm,ioda3-phbpciex {@À2 @ !@@5^UOPWR.A100034-Node0-Proc00TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww   w  +@@@l[F2     8 8 8!v b okaypci@0/H=1'n[F6Builtin Ethernet%UOPWR.A100034-Node0-Builtin Ethernet%UOPWR.A100034-Node0-Builtin Ethernet{  wpciexPpc +ethernet@0/H=1'W Builtin Ethernet{ethernet@0,1/H=1'W Builtin Ethernet{pciex@600c3c0500000/ ibm,power9-pciexibm,ioda3-phbpciex {Pà2  !@€6^UOPWR.A100034-Node0-Proc00TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww   w  +€@l[F2     8 8 8!v b okaypci@0/H=1'n[F6BMCUOPWR.A100034-Node0-BMCUOPWR.A100034-Node0-BMC{  wpciexPpc +pci@0/H=1'P BMC{  wpciexPc    ((((00008888@@@@HHHHPPPPXXXX````hhhhppppxxxx +vga@0/H=1A'   VqBMC{pciex@620c3c0000000/ ibm,power9-pciexibm,ioda3-phbpciex {  2  @  @   ! @ K^UOPWR.A100034-Node0-Proc10TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww 0  w  +   @l[F2      @  D  F !v b okaypci@0/H='n[F6CPU2 Slot2 (16x)%UOPWR.A100034-Node0-CPU2 Slot2 (16x)%UOPWR.A100034-Node0-CPU2 Slot2 (16x){  wpciexPpc +pciex@620c3c0100000/ ibm,power9-pciexibm,ioda3-phbpciex {  2@@  ! @@ M^UOPWR.A100034-Node0-Proc10TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww 1  w  +  @ @@l[F2      H  L  N!v b okaypci@0/H='n[F6CPU2 Slot3 (8x)$UOPWR.A100034-Node0-CPU2 Slot3 (8x)$UOPWR.A100034-Node0-CPU2 Slot3 (8x){  wpciexPpc +ethernet@0/H='^ CPU2 Slot3 (8x){ethernet@0,1/H='^ CPU2 Slot3 (8x){pciex@620c3c0200000/ ibm,power9-pciexibm,ioda3-phbpciex {  @2 @ ! @ N^UOPWR.A100034-Node0-Proc10TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww 2  w  +   @l[F2      P  T  V!v b okaypci@0/H='UOPWR.A100034-Node0UOPWR.A100034-Node0{  wpciexPpc +pciex@620c3c0300000/ ibm,power9-pciexibm,ioda3-phbpciex { 0 `2@@  !"@ P^UOPWR.A100034-Node0-Proc10TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTwwwwwwwwwwwwwwww 3  w  + ""@l[F2      X  \  ^ !v b okaypci@0/H='n[F6CPU2 Slot1 (16x)%UOPWR.A100034-Node0-CPU2 Slot1 (16x)%UOPWR.A100034-Node0-CPU2 Slot1 (16x){  wpciexPpc +multimedia-device@0,1/H=' CPU2 Slot1 (16x){vga@0/H='f\ CPU2 Slot1 (16x){psi@6030203000000/{ ibm,psiibm,power9-psic       w  ^psi@6230203000000/{# ibm,psiibm,power9-psic       w  ^reserved-memory/ +ibm,HCODE@201ffcb90000/{    HCODEibm,OCC@201ffce90000/{    OCCibm,RINGOVD@201ffcb50000/{   RINGOVDibm,VERSION@201ffcb80000/{   VERSIONibm,WOFDATA@201ffcc30000/{ &  WOFDATAibm,arch-reg-data@201ffd700000/{ p  ibm,arch-reg-dataibm,firmware-allocs-memory@35f10000/{5ibm,firmware-allocs-memory@200000000000/{ ibm,firmware-code@30000000/{0`ibm,firmware-data@31000000/{1ibm,firmware-heap@30600000/{0`ibm,firmware-stacks@31c10000/{10ibm,hb-rsv-mem@f0000000/{  ibm,hb-rsv-memibm,hbrt-code-image@201ffcf80000/{ ]  ibm,hbrt-code-imageibm,hbrt-data@201ffd550000/{ U  ibm,hbrt-dataibm,homer-image@201ffd800000/{ @  ibm,homer-imageibm,homer-image@201ffdc00000/{ @  ibm,homer-imageibm,occ-common-area@201fff800000/{   ibm,occ-common-areaibm,sbe-comm@201ffcf50000/{   ibm,sbe-commibm,sbe-comm@201ffcf70000/{   ibm,sbe-commibm,sbe-ffdc@201ffcf40000/{   ibm,sbe-ffdcibm,sbe-ffdc@201ffcf60000/{   ibm,sbe-ffdcibm,secure-crypt-algo-code@201ffcf30000/{   ibm,secure-crypt-algo-codevas@6019100000000/ ibm,power9-vasibm,vas@{ ^vas@6219100000000/ ibm,power9-vasibm,vas@{!!  ^vpd/@ ibm,opal-v3-vpd RTVINIDRI/O BACKPLANE CE1VZ01FNT2P9D01PNT2P9D01SN CCP000PR HE0002CTHWB3B4B7 PFxPRTOSYSVD01DRMAINBOARDMMT2P9D01 REV 1.01SSA1000341 ETPFxhRTOPFRVD02VNRAPTOR COMP SYS DRSYSTEM MAINBOARDVPT2P9D01 REV 1.01VSA1000341 MBPFxRTVNDRVD01INPFxUOPWR.A100034-Sys0root-node-vpd@a000/AUOPWR.A100034-Sys0VV{ pdDRPROCESSOR MODULEVZ CCAB22CE1FNF120308PN SN PR6"HE0001CTHWxenclosure@1e00/CUOPWR.A100034-Sys0EV{ backplane@800/DUOPWR.A100034-Node0BP{ RTVINIDRI/O BACKPLANE CE1VZ01FNT2P9D01PNT2P9D01SN CCP000PR HE0002CTHWB3B4B7 PFxPRTOSYSVD01DRMAINBOARDMMT2P9D01 REV 1.01SSA1000341 ETPFxhRTOPFRVD02VNRAPTOR COMP SYS DRSYSTEM MAINBOARDVPT2P9D01 REV 1.01VSA1000341 MBPFxRTVNDRVD01INPFxRAPTOR COMP SYSSYSTEM MAINBOARD~T2P9D01 REV 1.01 pA1000341ems-dimm@d000/EUOPWR.A100034-Node0-DIMM0MS{ ^L"@["@16384H# !`  nnnn ((x< , , , , , , , , ,G$2$aHMA82GR7AFR8N-UH TH65Q4938201ADqms-dimm@d001/FUOPWR.A100034-Node0-DIMM1MS{ ^L"@["@16384H# !`  nnnn ((x< , , , , , , , , ,G$02!1HMA82GR7AFR8N-UH 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a!2e,@36ASF2G72PZ-2G3B1 1,BDPAH6RL005Dqms-dimm@d00c/QUOPWR.A100034-Node0-DIMM12MS{  ^L [ 16384H# !`  nnnn ph((x<  a!2e,36ASF2G72PZ-2G3B1 1,BDPAH6RL005Dqms-dimm@d00d/RUOPWR.A100034-Node0-DIMM13MS{  ^L [ 16384H# !`  nnnn ph((x<  a!2e,36ASF2G72PZ-2G3B1 1,BDPAH6RL001Dqms-dimm@d00e/SUOPWR.A100034-Node0-DIMM14MS{ ^L [ 16384H# !`  nnnn ((x< , , , , , , , , ,G$02!1HMA82GR7AFR8N-UH TN71N6770I05Dqms-dimm@d00f/TUOPWR.A100034-Node0-DIMM15MS{ ^L [ 16384H# !`  nnnn ((x< , , , , , , , , ,G$02!1HMA82GR7AFR8N-UH TN71N6770I05Dqprocessor@1000/UUOPWR.A100034-Node0-Proc0PF{ )%RTVRMLVD01PN02CY227SN YA1934492117x~02CY227 pYA1934492117^IBMprocessor@1001/VUOPWR.A100034-Node0-Proc1PF{ )%RTVRMLVD01PN02CY227SN YA1934492124x~02CY227 pYA1934492124^IBMsystem-vpd@1c00/BUOPWR.A100034-Sys0SV{ xscom@603fc00000000/^7 ' ibm,xscomibm,power9-xscom{W9UOPWR.A100034-Node0-Proc0s&o(RTVHDRVD01PTVTOC7HRPFxDRTVTOCPTVINIl)CP00#~VRTNoEVMSC78VSRCxVRMLo4 VWMLPTCRP0 ѭLRP0@ALRP1ϒ@LRP2@!LRP3O@LRP4@LRP5ϛ@qLWP0D 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