Index: powerpc/aim/aim_machdep.c
===================================================================
--- powerpc/aim/aim_machdep.c	(revision 328626)
+++ powerpc/aim/aim_machdep.c	(working copy)
@@ -178,6 +178,27 @@
 	trap_offset = 0;
 	cacheline_warn = 0;
 
+	/* General setup for AIM CPUs */
+	psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
+
+#ifdef __powerpc64__
+	psl_kernset |= PSL_SF;
+	if (mfmsr() & PSL_HV)
+		psl_kernset |= PSL_HV;
+#endif
+	psl_userset = psl_kernset | PSL_PR;
+#ifdef __powerpc64__
+	psl_userset32 = psl_userset & ~PSL_SF;
+#endif
+
+	/* Bits that users aren't allowed to change */
+	psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1);
+	/*
+	 * Mask bits from the SRR1 that aren't really the MSR:
+	 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64)
+	 */
+	psl_userstatic &= ~0x783f0000UL;
+
 	/* Various very early CPU fix ups */
 	switch (mfpvr() >> 16) {
 		/*
Index: powerpc/aim/mp_cpudep.c
===================================================================
--- powerpc/aim/mp_cpudep.c	(revision 328626)
+++ powerpc/aim/mp_cpudep.c	(working copy)
@@ -85,9 +85,13 @@
 		break;
 	case IBMPOWER8:
 	case IBMPOWER8E:
+#ifdef __powerpc64__
 		if (mfmsr() & PSL_HV) {
 			isync();
-			/* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */
+			/*
+			 * Direct interrupts to SRR instead of HSRR and
+			 * reset LPCR otherwise
+			 */
 			mtspr(SPR_LPID, 0);
 			isync();
 
@@ -94,6 +98,7 @@
 			mtspr(SPR_LPCR, LPCR_LPES);
 			isync();
 		}
+#endif
 		break;
 	}
 
@@ -106,7 +111,7 @@
 {
 	register_t msr, sp;
 
-	msr = PSL_KERNSET & ~PSL_EE;
+	msr = psl_kernset & ~PSL_EE;
 	mtmsr(msr);
 
 	pcpup->pc_curthread = pcpup->pc_idlethread;
Index: powerpc/booke/booke_machdep.c
===================================================================
--- powerpc/booke/booke_machdep.c	(revision 328626)
+++ powerpc/booke/booke_machdep.c	(working copy)
@@ -210,6 +210,16 @@
 
 	cpu_features |= PPC_FEATURE_BOOKE;
 
+	psl_kernset = PSL_CE | PSL_ME | PSL_EE;
+#ifdef __powerpc64__
+	psl_kernset |= PSL_CM;
+#endif
+	psl_userset = psl_kernset | PSL_PR;
+#ifdef __powerpc64__
+	psl_userset32 = psl_kernset & ~PSL_CM;
+#endif
+	psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1);
+
 	pmap_mmu_install(MMU_TYPE_BOOKE, BUS_PROBE_GENERIC);
 }
 
Index: powerpc/include/psl.h
===================================================================
--- powerpc/include/psl.h	(revision 328626)
+++ powerpc/include/psl.h	(working copy)
@@ -90,28 +90,13 @@
 #define	PSL_FE_PREC	(PSL_FE0 | PSL_FE1) /* precise */
 #define	PSL_FE_DFLT	PSL_FE_DIS	/* default == none */
 
-#if defined(BOOKE_E500)
-/* Initial kernel MSR, use IS=1 ad DS=1. */
-#define PSL_KERNSET_INIT	(PSL_IS | PSL_DS)
+#ifndef LOCORE
+extern register_t psl_kernset;		/* Default MSR values for kernel */
+extern register_t psl_userset;		/* Default MSR values for userland */
 #ifdef __powerpc64__
-#define PSL_KERNSET		(PSL_CM | PSL_CE | PSL_ME | PSL_EE)
-#else
-#define PSL_KERNSET		(PSL_CE | PSL_ME | PSL_EE)
+extern register_t psl_userset32;	/* Default user MSR values for 32-bit */
 #endif
-#define PSL_SRR1_MASK	0x00000000UL	/* No mask on Book-E */
-#elif defined(BOOKE_PPC4XX)
-#define PSL_KERNSET	(PSL_CE | PSL_ME | PSL_EE | PSL_FP)
-#define PSL_SRR1_MASK	0x00000000UL	/* No mask on Book-E */
-#elif defined(AIM)
-#ifdef __powerpc64__
-#define	PSL_KERNSET	(PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
-#else
-#define	PSL_KERNSET	(PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
+extern register_t psl_userstatic;	/* Bits of SRR1 userland may not set */
 #endif
-#define PSL_SRR1_MASK	0x783f0000UL	/* Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) */
-#endif
 
-#define	PSL_USERSET	(PSL_KERNSET | PSL_PR)
-#define	PSL_USERSTATIC	(~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1) & ~PSL_SRR1_MASK)
-
 #endif	/* _MACHINE_PSL_H_ */
Index: powerpc/powerpc/exec_machdep.c
===================================================================
--- powerpc/powerpc/exec_machdep.c	(revision 328626)
+++ powerpc/powerpc/exec_machdep.c	(working copy)
@@ -454,7 +454,7 @@
 	/*
 	 * Don't let the user set privileged MSR bits
 	 */
-	if ((mcp->mc_srr1 & PSL_USERSTATIC) != (tf->srr1 & PSL_USERSTATIC)) {
+	if ((mcp->mc_srr1 & psl_userstatic) != (tf->srr1 & psl_userstatic)) {
 		return (EINVAL);
 	}
 
@@ -538,16 +538,8 @@
 	tf->srr0 = imgp->entry_addr;
 	#ifdef __powerpc64__
 	tf->fixreg[12] = imgp->entry_addr;
-	#ifdef AIM
-	tf->srr1 = PSL_SF | PSL_USERSET | PSL_FE_DFLT;
-	if (mfmsr() & PSL_HV)
-		tf->srr1 |= PSL_HV;
-	#elif defined(BOOKE)
-	tf->srr1 = PSL_CM | PSL_USERSET | PSL_FE_DFLT;
 	#endif
-	#else
-	tf->srr1 = PSL_USERSET | PSL_FE_DFLT;
-	#endif
+	tf->srr1 = psl_userset | PSL_FE_DFLT;
 	td->td_pcb->pcb_flags = 0;
 }
 
@@ -572,14 +564,7 @@
 	tf->fixreg[8] = (register_t)imgp->ps_strings;	/* NetBSD extension */
 
 	tf->srr0 = imgp->entry_addr;
-	tf->srr1 = PSL_USERSET | PSL_FE_DFLT;
-#ifdef AIM
-	tf->srr1 &= ~PSL_SF;
-	if (mfmsr() & PSL_HV)
-		tf->srr1 |= PSL_HV;
-#elif defined(BOOKE)
-	tf->srr1 &= ~PSL_CM;
-#endif
+	tf->srr1 = psl_userset32 | PSL_FE_DFLT;
 	td->td_pcb->pcb_flags = 0;
 }
 #endif
@@ -990,7 +975,7 @@
 
 	/* Setup to release spin count in fork_exit(). */
 	td->td_md.md_spinlock_count = 1;
-	td->td_md.md_saved_msr = PSL_KERNSET;
+	td->td_md.md_saved_msr = psl_kernset;
 }
 
 void
@@ -1015,9 +1000,10 @@
 	tf->fixreg[3] = (register_t)arg;
 	if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
 		tf->srr0 = (register_t)entry;
-		tf->srr1 = PSL_USERSET | PSL_FE_DFLT;
 		#ifdef __powerpc64__
-		tf->srr1 &= ~PSL_SF;
+		tf->srr1 = psl_userset32 | PSL_FE_DFLT;
+		#else
+		tf->srr1 = psl_userset | PSL_FE_DFLT;
 		#endif
 	} else {
 	    #ifdef __powerpc64__
@@ -1026,14 +1012,10 @@
 		tf->srr0 = entry_desc[0];
 		tf->fixreg[2] = entry_desc[1];
 		tf->fixreg[11] = entry_desc[2];
-		tf->srr1 = PSL_SF | PSL_USERSET | PSL_FE_DFLT;
+		tf->srr1 = psl_userset | PSL_FE_DFLT;
 	    #endif
 	}
 
-	#ifdef __powerpc64__
-	if (mfmsr() & PSL_HV)
-		tf->srr1 |= PSL_HV;
-	#endif
 	td->td_pcb->pcb_flags = 0;
 
 	td->td_retval[0] = (register_t)entry;
Index: powerpc/powerpc/genassym.c
===================================================================
--- powerpc/powerpc/genassym.c	(revision 328626)
+++ powerpc/powerpc/genassym.c	(working copy)
@@ -236,10 +236,6 @@
 ASSYM(PSL_WE, PSL_WE);
 ASSYM(PSL_UBLE, PSL_UBLE);
 
-#if defined(BOOKE_E500)
-ASSYM(PSL_KERNSET_INIT, PSL_KERNSET_INIT);
-#endif
-
 #if defined(AIM) && defined(__powerpc64__)
 ASSYM(PSL_SF, PSL_SF);
 ASSYM(PSL_HV, PSL_HV);
@@ -268,7 +264,4 @@
 ASSYM(PSL_ME, PSL_ME);
 ASSYM(PSL_PR, PSL_PR);
 ASSYM(PSL_PMM, PSL_PMM);
-ASSYM(PSL_KERNSET, PSL_KERNSET);
-ASSYM(PSL_USERSET, PSL_USERSET);
-ASSYM(PSL_USERSTATIC, PSL_USERSTATIC);
 
Index: powerpc/powerpc/machdep.c
===================================================================
--- powerpc/powerpc/machdep.c	(revision 328626)
+++ powerpc/powerpc/machdep.c	(working copy)
@@ -160,6 +160,14 @@
 long		Maxmem = 0;
 long		realmem = 0;
 
+/* Default MSR values set in the AIM/Book-E early startup code */
+register_t	psl_kernset;
+register_t	psl_userset;
+register_t	psl_userstatic;
+#ifdef __powerpc64__
+register_t	psl_userset32;
+#endif
+
 struct kva_md_info kmi;
 
 static void
@@ -380,7 +388,7 @@
 	 * Bring up MMU
 	 */
 	pmap_bootstrap(startkernel, endkernel);
-	mtmsr(PSL_KERNSET & ~PSL_EE);
+	mtmsr(psl_kernset & ~PSL_EE);
 
 	/*
 	 * Initialize params/tunables that are derived from memsize
Index: powerpc/powerpc/vm_machdep.c
===================================================================
--- powerpc/powerpc/vm_machdep.c	(revision 328626)
+++ powerpc/powerpc/vm_machdep.c	(working copy)
@@ -167,7 +167,7 @@
 
 	/* Setup to release spin count in fork_exit(). */
 	td2->td_md.md_spinlock_count = 1;
-	td2->td_md.md_saved_msr = PSL_KERNSET;
+	td2->td_md.md_saved_msr = psl_kernset;
 
 	/*
  	 * Now cpu_switch() can schedule the new process.