Index: powerpc/booke/interrupt.c =================================================================== --- powerpc/booke/interrupt.c (revision 208284) +++ powerpc/booke/interrupt.c (working copy) @@ -134,7 +134,7 @@ { critical_enter(); - PIC_DISPATCH(pic, framep); + PIC_DISPATCH(root_pic, framep); critical_exit(); framep->srr1 &= ~PSL_WE; } Index: powerpc/powerpc/pic_if.m =================================================================== --- powerpc/powerpc/pic_if.m (revision 208284) +++ powerpc/powerpc/pic_if.m (working copy) @@ -60,6 +60,10 @@ u_int cpu; }; +METHOD uint32_t id { + device_t dev; +}; + METHOD void mask { device_t dev; u_int irq; Index: powerpc/powerpc/mp_machdep.c =================================================================== --- powerpc/powerpc/mp_machdep.c (revision 208284) +++ powerpc/powerpc/mp_machdep.c (working copy) @@ -319,7 +319,7 @@ pc, pc->pc_cpuid, ipi); atomic_set_32(&pc->pc_ipimask, (1 << ipi)); - PIC_IPI(pic, pc->pc_cpuid); + PIC_IPI(root_pic, pc->pc_cpuid); CTR1(KTR_SMP, "%s: sent", __func__); } Index: powerpc/powerpc/openpic.c =================================================================== --- powerpc/powerpc/openpic.c (revision 208284) +++ powerpc/powerpc/openpic.c (working copy) @@ -52,6 +52,7 @@ /* * Local routines */ +static int openpic_intr(void *arg); static __inline uint32_t openpic_read(struct openpic_softc *sc, u_int reg) @@ -110,6 +111,29 @@ DELAY(100); } + /* Check if this is a cascaded PIC */ + sc->sc_irq = 0; + sc->sc_intr = NULL; + if (resource_list_find(BUS_GET_RESOURCE_LIST(device_get_parent(dev), + dev), SYS_RES_IRQ, 0) != NULL) { + sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ, + &sc->sc_irq, RF_ACTIVE); + + /* XXX Cascaded PICs pass NULL trapframes! */ + bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE, + openpic_intr, NULL, dev, &sc->sc_icookie); + } + + /* Reset the PIC */ + x = openpic_read(sc, OPENPIC_CONFIG); + x |= OPENPIC_CONFIG_RESET; + openpic_write(sc, OPENPIC_CONFIG, x); + + while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) { + powerpc_sync(); + DELAY(100); + } + x = openpic_read(sc, OPENPIC_FEATURE); switch (x & OPENPIC_FEATURE_VERSION_MASK) { case 1: @@ -185,6 +209,10 @@ powerpc_register_pic(dev, sc->sc_nirq); + /* If this is not a cascaded PIC, it must be the root PIC */ + if (sc->sc_intr == NULL) + root_pic = dev; + return (0); } @@ -212,6 +240,17 @@ openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); } +static int +openpic_intr(void *arg) +{ + device_t dev = (device_t)(arg); + + /* XXX Cascaded PICs do not pass non-NULL trapframes! */ + openpic_dispatch(dev, NULL); + + return (FILTER_HANDLED); +} + void openpic_dispatch(device_t dev, struct trapframe *tf) { Index: powerpc/powerpc/intr_machdep.c =================================================================== --- powerpc/powerpc/intr_machdep.c (revision 208284) +++ powerpc/powerpc/intr_machdep.c (working copy) @@ -85,14 +85,6 @@ #include "pic_if.h" -#ifdef MPC85XX -#define ISA_IRQ_COUNT 16 -#endif - -#ifndef ISA_IRQ_COUNT -#define ISA_IRQ_COUNT 0 -#endif - #define MAX_STRAY_LOG 5 MALLOC_DEFINE(M_INTR, "intr", "interrupt handler data"); @@ -108,20 +100,25 @@ enum intr_polarity pol; }; +struct pic { + device_t pic; + uint32_t pic_id; + int ipi_irq; +}; + static struct mtx intr_table_lock; static struct powerpc_intr *powerpc_intrs[INTR_VECTORS]; +static struct pic piclist[MAX_PICS]; static u_int nvectors; /* Allocated vectors */ +static u_int npics; /* PICs registered */ static u_int stray_count; +device_t root_pic; + #ifdef SMP static void *ipi_cookie; #endif -static u_int ipi_irq; - -device_t pic; -device_t pic8259; - static void intr_init(void *dummy __unused) { @@ -197,21 +194,13 @@ powerpc_map_irq(struct powerpc_intr *i) { -#if ISA_IRQ_COUNT > 0 - if (i->irq < ISA_IRQ_COUNT) { - if (pic8259 == NULL) { - i->pic = pic; - i->intline = 0; - return (ENXIO); - } - i->pic = pic8259; - i->intline = i->irq; - return (0); - } -#endif + i->intline = INTR_INTLINE(i->irq); + i->pic = piclist[INTR_IGN(i->irq)].pic; - i->pic = pic; - i->intline = i->irq - ISA_IRQ_COUNT; + /* Try a best guess if that failed */ + if (i->pic == NULL) + i->pic = root_pic; + return (0); } @@ -242,16 +231,44 @@ void powerpc_register_pic(device_t dev, u_int ipi) { + int i; - pic = dev; - ipi_irq = ipi + ISA_IRQ_COUNT; + mtx_lock(&intr_table_lock); + + for (i = 0; i < npics; i++) { + if (piclist[i].pic_id == PIC_ID(dev)) + break; + } + piclist[i].pic = dev; + piclist[i].pic_id = PIC_ID(dev); + piclist[i].ipi_irq = ipi; + if (i == npics) + npics++; + + mtx_unlock(&intr_table_lock); } -void -powerpc_register_8259(device_t dev) +int +powerpc_ign_lookup(uint32_t pic_id) { + int i; - pic8259 = dev; + mtx_lock(&intr_table_lock); + + for (i = 0; i < npics; i++) { + if (piclist[i].pic_id == pic_id) { + mtx_unlock(&intr_table_lock); + return (i); + } + } + piclist[i].pic = NULL; + piclist[i].pic_id = pic_id; + piclist[i].ipi_irq = 0; + npics++; + + mtx_unlock(&intr_table_lock); + + return (i); } int @@ -259,17 +276,28 @@ { struct powerpc_intr *i; int error, vector; +#ifdef SMP + int n; +#endif - if (pic == NULL) + if (npics == 0) panic("no PIC detected\n"); #ifdef SMP /* Install an IPI handler. */ - error = powerpc_setup_intr("IPI", ipi_irq, powerpc_ipi_handler, - NULL, NULL, INTR_TYPE_MISC | INTR_EXCL | INTR_FAST, &ipi_cookie); - if (error) { - printf("unable to setup IPI handler\n"); - return (error); + + for (n = 0; n < npics; n++) { + if (piclist[n].pic != root_pic) + continue; + + error = powerpc_setup_intr("IPI", + INTR_VEC(piclist[n].pic_id, piclist[n].ipi_irq), + powerpc_ipi_handler, NULL, NULL, + INTR_TYPE_MISC | INTR_EXCL | INTR_FAST, &ipi_cookie); + if (error) { + printf("unable to setup IPI handler\n"); + return (error); + } } #endif @@ -294,7 +322,7 @@ } int -powerpc_setup_intr(const char *name, u_int irq, driver_filter_t filter, +powerpc_setup_intr(const char *name, u_int irq, driver_filter_t filter, driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep) { struct powerpc_intr *i; Index: powerpc/include/intr_machdep.h =================================================================== --- powerpc/include/intr_machdep.h (revision 208284) +++ powerpc/include/intr_machdep.h (working copy) @@ -29,26 +29,32 @@ #define _MACHINE_INTR_MACHDEP_H_ #define INTR_VECTORS 256 +#define MAX_PICS 5 +#define IGN_SHIFT 8 +#define INTR_INTLINE(irq) (irq & ((1 << IGN_SHIFT) - 1)) +#define INTR_IGN(irq) (irq >> IGN_SHIFT) + +#define INTR_VEC(pic_id, irq) ((powerpc_ign_lookup(pic_id) << IGN_SHIFT) | irq) + /* * Default base address for MSI messages on PowerPC */ #define MSI_INTEL_ADDR_BASE 0xfee00000 -extern device_t pic; -extern device_t pic8259; +extern device_t root_pic; struct trapframe; driver_filter_t powerpc_ipi_handler; void powerpc_register_pic(device_t, u_int); -void powerpc_register_8259(device_t); +int powerpc_ign_lookup(uint32_t pic_id); void powerpc_dispatch_intr(u_int, struct trapframe *); int powerpc_enable_intr(void); -int powerpc_setup_intr(const char *, u_int, driver_filter_t, - driver_intr_t, void *, enum intr_type, void **); +int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t, + void *, enum intr_type, void **); int powerpc_teardown_intr(void *); int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity); Index: powerpc/include/openpicvar.h =================================================================== --- powerpc/include/openpicvar.h (revision 208284) +++ powerpc/include/openpicvar.h (working copy) @@ -35,10 +35,13 @@ struct openpic_softc { device_t sc_dev; struct resource *sc_memr; + struct resource *sc_intr; bus_space_tag_t sc_bt; bus_space_handle_t sc_bh; char *sc_version; int sc_rid; + int sc_irq; + void *sc_icookie; u_int sc_ncpu; u_int sc_nirq; int sc_psim; Index: powerpc/include/ocpbus.h =================================================================== --- powerpc/include/ocpbus.h (revision 208284) +++ powerpc/include/ocpbus.h (working copy) @@ -44,4 +44,8 @@ #define OCPBUS_DEVTYPE_I2C 7 #define OCPBUS_DEVTYPE_SEC 8 +/* PIC IDs */ +#define OPIC_ID 0 +#define ATPIC_ID 1 + #endif /* _MACHINE_OCPBUS_H_ */ Index: powerpc/conf/GENERIC =================================================================== --- powerpc/conf/GENERIC (revision 208284) +++ powerpc/conf/GENERIC (working copy) @@ -66,6 +66,7 @@ # Debugging for use in -current options KDB #Enable the kernel debugger +options KDB_TRACE options DDB #Support DDB #options DEADLKRES #Enable the deadlock resolver options INVARIANTS #Enable calls of extra sanity checking Index: powerpc/aim/nexus.c =================================================================== --- powerpc/aim/nexus.c (revision 208284) +++ powerpc/aim/nexus.c (working copy) @@ -208,7 +208,7 @@ sc = device_get_softc(dev); start = 0; - end = INTR_VECTORS - 1; + end = MAX_PICS*INTR_VECTORS - 1; sc->sc_rman.rm_start = start; sc->sc_rman.rm_end = end; Index: powerpc/aim/interrupt.c =================================================================== --- powerpc/aim/interrupt.c (revision 208284) +++ powerpc/aim/interrupt.c (working copy) @@ -81,7 +81,7 @@ switch (framep->exc) { case EXC_EXI: critical_enter(); - PIC_DISPATCH(pic, framep); + PIC_DISPATCH(root_pic, framep); critical_exit(); break; Index: powerpc/ofw/ofw_pcibus.c =================================================================== --- powerpc/ofw/ofw_pcibus.c (revision 208284) +++ powerpc/ofw/ofw_pcibus.c (working copy) @@ -212,13 +212,16 @@ OF_getprop(iparent, "#interrupt-cells", &icells, sizeof(icells)); + if (iparent != 0) + intr[0] = INTR_VEC(iparent, intr[0]); + if (iparent != 0 && icells > 1) { powerpc_config_intr(intr[0], (intr[1] & 1) ? INTR_TRIGGER_LEVEL : INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); } - + resource_list_add(&dinfo->opd_dinfo.resources, SYS_RES_IRQ, 0, intr[0], intr[0], 1); } @@ -293,7 +296,7 @@ ofw_pcibus_assign_interrupt(device_t dev, device_t child) { ofw_pci_intr_t intr; - phandle_t node; + phandle_t node, iparent; int isz; node = ofw_bus_get_node(child); @@ -303,8 +306,8 @@ /* * XXX: Right now we don't have anything sensible to do here, - * since the ofw_imap stuff relies on nodes have a reg - * property. There exists ways around this, so the ePAPR + * since the ofw_imap stuff relies on nodes having a reg + * property. There exist ways around this, so the ePAPR * spec will need to be studied. */ @@ -318,18 +321,30 @@ } /* + * Try to determine the node's interrupt parent so we know which + * PIC to use. + */ + + if (OF_getprop(node, "interrupt-parent", &iparent, sizeof(iparent)) < + sizeof(iparent)) + iparent = -1; + + /* * Any AAPL,interrupts property gets priority and is * fully specified (i.e. does not need routing) */ isz = OF_getprop(node, "AAPL,interrupts", &intr, sizeof(intr)); if (isz == sizeof(intr)) { - return (intr); + return ((iparent == -1) ? intr : INTR_VEC(iparent, intr)); } isz = OF_getprop(node, "interrupts", &intr, sizeof(intr)); - if (isz != sizeof(intr)) { - /* No property; our best guess is the intpin. */ + if (isz == sizeof(intr)) { + if (iparent != -1) + intr = INTR_VEC(iparent, intr); + } else { + /* No property: our best guess is the intpin. */ intr = pci_get_intpin(child); } Index: powerpc/ofw/ofw_pcib_pci.c =================================================================== --- powerpc/ofw/ofw_pcib_pci.c (revision 208284) +++ powerpc/ofw/ofw_pcib_pci.c (working copy) @@ -42,6 +42,8 @@ #include #include +#include + #include "pcib_if.h" static int ofw_pcib_pci_probe(device_t bus); @@ -149,6 +151,7 @@ struct ofw_bus_iinfo *ii; struct ofw_pci_register reg; cell_t pintr, mintr; + phandle_t iparent; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; sc = device_get_softc(bridge); @@ -157,13 +160,13 @@ pintr = intpin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), - maskbuf)) { + &iparent, maskbuf)) { /* * If we've found a mapping, return it and don't map * it again on higher levels - that causes problems * in some cases, and never seems to be required. */ - return (mintr); + return (INTR_VEC(iparent, mintr)); } } else if (intpin >= 1 && intpin <= 4) { /* Index: powerpc/mpc85xx/ocpbus.h =================================================================== --- powerpc/mpc85xx/ocpbus.h (revision 208284) +++ powerpc/mpc85xx/ocpbus.h (working copy) @@ -104,11 +104,9 @@ /* * PIC definitions */ -#define ISA_IRQ_START 0 -#define PIC_IRQ_START (ISA_IRQ_START + 16) -#define ISA_IRQ(n) (ISA_IRQ_START + (n)) -#define PIC_IRQ_EXT(n) (PIC_IRQ_START + (n)) -#define PIC_IRQ_INT(n) (PIC_IRQ_START + 16 + (n)) +#define ISA_IRQ(n) (INTR_VEC(ATPIC_ID, n)) +#define PIC_IRQ_EXT(n) (INTR_VEC(OPIC_ID, (n))) +#define PIC_IRQ_INT(n) (INTR_VEC(OPIC_ID, (16 + (n)))) #endif /* _MACHINE_OCP85XX_H */ Index: powerpc/mpc85xx/atpic.c =================================================================== --- powerpc/mpc85xx/atpic.c (revision 208284) +++ powerpc/mpc85xx/atpic.c (working copy) @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -79,7 +80,10 @@ static void atpic_ipi(device_t, u_int); static void atpic_mask(device_t, u_int); static void atpic_unmask(device_t, u_int); +static uint32_t atpic_id (device_t dev); +static device_t pic8259; + static device_method_t atpic_isa_methods[] = { /* Device interface */ DEVMETHOD(device_identify, atpic_isa_identify), @@ -94,6 +98,7 @@ DEVMETHOD(pic_ipi, atpic_ipi), DEVMETHOD(pic_mask, atpic_mask), DEVMETHOD(pic_unmask, atpic_unmask), + DEVMETHOD(pic_id, atpic_id), { 0, 0 }, }; @@ -219,7 +224,8 @@ atpic_init(sc, ATPIC_SLAVE); atpic_init(sc, ATPIC_MASTER); - powerpc_register_8259(dev); + powerpc_register_pic(dev, 0x10); + pic8259 = dev; return (0); fail: @@ -328,3 +334,11 @@ atpic_write(sc, ATPIC_MASTER, 1, sc->sc_mask[ATPIC_MASTER]); } } + +static uint32_t +atpic_id (device_t dev) +{ + + return (ATPIC_ID); +} + Index: powerpc/mpc85xx/pci_ocp.c =================================================================== --- powerpc/mpc85xx/pci_ocp.c (revision 208284) +++ powerpc/mpc85xx/pci_ocp.c (working copy) @@ -792,7 +792,7 @@ va = sc->sc_iomem_va; break; case SYS_RES_IRQ: - if (start < PIC_IRQ_START) { + if (INTR_IGN(start) == powerpc_ign_lookup(ATPIC_ID)) { device_printf(dev, "%s requested ISA interrupt %lu\n", device_get_nameunit(child), start); } Index: powerpc/mpc85xx/isa.c =================================================================== --- powerpc/mpc85xx/isa.c (revision 208284) +++ powerpc/mpc85xx/isa.c (working copy) @@ -32,12 +32,16 @@ #include #include +#include +#include #include #include #include #include +#include "ocpbus.h" + void isa_init(device_t dev) { @@ -58,7 +62,10 @@ resource_list_find(rl, type, *rid) == NULL) { switch (type) { case SYS_RES_IOPORT: rids = ISA_PNP_NPORT; break; - case SYS_RES_IRQ: rids = ISA_PNP_NIRQ; break; + case SYS_RES_IRQ: + rids = ISA_PNP_NIRQ; + start = ISA_IRQ(start); + break; case SYS_RES_MEMORY: rids = ISA_PNP_NMEM; break; default: rids = 0; break; } Index: powerpc/mpc85xx/opic.c =================================================================== --- powerpc/mpc85xx/opic.c (revision 208284) +++ powerpc/mpc85xx/opic.c (working copy) @@ -49,6 +49,7 @@ * OpenPIC attachment to ocpbus */ static int openpic_ocpbus_probe(device_t); +static uint32_t openpic_ocpbus_id(device_t); static device_method_t openpic_ocpbus_methods[] = { /* Device interface */ @@ -63,6 +64,7 @@ DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_unmask, openpic_unmask), + DEVMETHOD(pic_id, openpic_ocpbus_id), { 0, 0 }, }; @@ -93,3 +95,11 @@ device_set_desc(dev, OPENPIC_DEVSTR); return (BUS_PROBE_DEFAULT); } + +static uint32_t +openpic_ocpbus_id (device_t dev) +{ + return (OPIC_ID); +} + + Index: powerpc/mpc85xx/ocpbus.c =================================================================== --- powerpc/mpc85xx/ocpbus.c (revision 208284) +++ powerpc/mpc85xx/ocpbus.c (working copy) @@ -277,7 +277,7 @@ ccsr_read4(OCP85XX_PORDEVSR), ccsr_read4(OCP85XX_PORDEVSR2)); - for (i = PIC_IRQ_START; i < PIC_IRQ_START + 4; i++) + for (i = INTR_VEC(OPIC_ID, 0); i < INTR_VEC(OPIC_ID, 4); i++) powerpc_config_intr(i, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW); return (bus_generic_attach(dev)); @@ -305,35 +305,35 @@ {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_MEMORY, 0, OCP85XX_QUICC_OFF, OCP85XX_QUICC_SIZE}, - {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(30), 1}, + {OCPBUS_DEVTYPE_QUICC, 0, SYS_RES_IRQ, 0, 30, 1}, {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_MEMORY, 0, OCP85XX_TSEC0_OFF, OCP85XX_TSEC_SIZE}, - {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(13), 1}, - {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 1, PIC_IRQ_INT(14), 1}, - {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 2, PIC_IRQ_INT(18), 1}, + {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 0, 13, 1}, + {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 1, 14, 1}, + {OCPBUS_DEVTYPE_TSEC, 0, SYS_RES_IRQ, 2, 18, 1}, {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_MEMORY, 0, OCP85XX_TSEC1_OFF, OCP85XX_TSEC_SIZE}, - {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(19), 1}, - {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 1, PIC_IRQ_INT(20), 1}, - {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 2, PIC_IRQ_INT(24), 1}, + {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 0, 19, 1}, + {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 1, 20, 1}, + {OCPBUS_DEVTYPE_TSEC, 1, SYS_RES_IRQ, 2, 24, 1}, {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_MEMORY, 0, OCP85XX_TSEC2_OFF, OCP85XX_TSEC_SIZE}, - {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 0, PIC_IRQ_INT(15), 1}, - {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 1, PIC_IRQ_INT(16), 1}, - {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 2, PIC_IRQ_INT(17), 1}, + {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 0, 15, 1}, + {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 1, 16, 1}, + {OCPBUS_DEVTYPE_TSEC, 2, SYS_RES_IRQ, 2, 17, 1}, {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_MEMORY, 0, OCP85XX_TSEC3_OFF, OCP85XX_TSEC_SIZE}, - {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 0, PIC_IRQ_INT(21), 1}, - {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 1, PIC_IRQ_INT(22), 1}, - {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 2, PIC_IRQ_INT(23), 1}, + {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 0, 21, 1}, + {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 1, 22, 1}, + {OCPBUS_DEVTYPE_TSEC, 3, SYS_RES_IRQ, 2, 23, 1}, {OCPBUS_DEVTYPE_UART, 0, SYS_RES_MEMORY, 0, OCP85XX_UART0_OFF, OCP85XX_UART_SIZE}, - {OCPBUS_DEVTYPE_UART, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1}, + {OCPBUS_DEVTYPE_UART, 0, SYS_RES_IRQ, 0, 26, 1}, {OCPBUS_DEVTYPE_UART, 1, SYS_RES_MEMORY, 0, OCP85XX_UART1_OFF, OCP85XX_UART_SIZE}, - {OCPBUS_DEVTYPE_UART, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(26), 1}, + {OCPBUS_DEVTYPE_UART, 1, SYS_RES_IRQ, 0, 26, 1}, {OCPBUS_DEVTYPE_PCIB, 0, SYS_RES_MEMORY, 0, OCP85XX_PCI0_OFF, OCP85XX_PCI_SIZE}, @@ -357,15 +357,15 @@ {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_MEMORY, 0, OCP85XX_I2C0_OFF, OCP85XX_I2C_SIZE}, - {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1}, + {OCPBUS_DEVTYPE_I2C, 0, SYS_RES_IRQ, 0, 27, 1}, {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_MEMORY, 0, OCP85XX_I2C1_OFF, OCP85XX_I2C_SIZE}, - {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_IRQ, 0, PIC_IRQ_INT(27), 1}, + {OCPBUS_DEVTYPE_I2C, 1, SYS_RES_IRQ, 0, 27, 1}, {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_MEMORY, 0, OCP85XX_SEC_OFF, OCP85XX_SEC_SIZE}, - {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 0, PIC_IRQ_INT(29), 1}, - {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 1, PIC_IRQ_INT(42), 1}, + {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 0, 29, 1}, + {OCPBUS_DEVTYPE_SEC, 0, SYS_RES_IRQ, 1, 42, 1}, {0} }; @@ -402,7 +402,7 @@ start = res->sr_offset + CCSRBAR_VA; break; case SYS_RES_IRQ: - start = res->sr_offset; + start = PIC_IRQ_INT(res->sr_offset); break; default: error = EINVAL; Index: powerpc/powermac/cpcht.c =================================================================== --- powerpc/powermac/cpcht.c (revision 208285) +++ powerpc/powermac/cpcht.c (working copy) @@ -595,6 +595,7 @@ static void openpic_cpcht_enable(device_t, u_int irq, u_int vector); static void openpic_cpcht_unmask(device_t, u_int irq); static void openpic_cpcht_eoi(device_t, u_int irq); +static uint32_t openpic_cpcht_id(device_t); static device_method_t openpic_cpcht_methods[] = { /* Device interface */ @@ -609,6 +610,7 @@ DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_unmask, openpic_cpcht_unmask), + DEVMETHOD(pic_id, openpic_cpcht_id), { 0, 0 }, }; @@ -808,3 +810,9 @@ openpic_eoi(dev, irq); } +static uint32_t +openpic_cpcht_id(device_t dev) +{ + return (ofw_bus_get_node(dev)); +} + Index: powerpc/powermac/uninorthpci.c =================================================================== --- powerpc/powermac/uninorthpci.c (revision 208284) +++ powerpc/powermac/uninorthpci.c (working copy) @@ -356,14 +356,15 @@ struct uninorth_softc *sc; struct ofw_pci_register reg; uint32_t pintr, mintr; + phandle_t iparent; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; sc = device_get_softc(bus); pintr = pin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), - maskbuf)) - return (mintr); + &iparent, maskbuf)) + return (INTR_VEC(iparent, mintr)); /* Maybe it's a real interrupt, not an intpin */ if (pin > 4) Index: powerpc/powermac/openpic_macio.c =================================================================== --- powerpc/powermac/openpic_macio.c (revision 208284) +++ powerpc/powermac/openpic_macio.c (working copy) @@ -59,6 +59,7 @@ * MacIO interface */ static int openpic_macio_probe(device_t); +static uint32_t openpic_macio_id(device_t); static device_method_t openpic_macio_methods[] = { /* Device interface */ @@ -73,6 +74,7 @@ DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_unmask, openpic_unmask), + DEVMETHOD(pic_id, openpic_macio_id), { 0, 0 }, }; @@ -96,3 +98,10 @@ device_set_desc(dev, OPENPIC_DEVSTR); return (0); } + +static uint32_t +openpic_macio_id(device_t dev) +{ + return (ofw_bus_get_node(dev)); +} + Index: powerpc/powermac/uninorth.c =================================================================== --- powerpc/powermac/uninorth.c (revision 208284) +++ powerpc/powermac/uninorth.c (working copy) @@ -142,9 +142,9 @@ static void unin_chip_add_intr(phandle_t devnode, struct unin_chip_devinfo *dinfo) { + phandle_t iparent; int *intr; int i, nintr; - phandle_t iparent; int icells; if (dinfo->udi_ninterrupts >= 6) { @@ -174,9 +174,17 @@ for (i = 0; i < nintr; i+=icells) { resource_list_add(&dinfo->udi_resources, SYS_RES_IRQ, - dinfo->udi_ninterrupts, intr[i], intr[i], 1); + dinfo->udi_ninterrupts, INTR_VEC(iparent, intr[i]), + INTR_VEC(iparent, intr[i]), 1); - dinfo->udi_interrupts[dinfo->udi_ninterrupts] = intr[i]; + if (icells > 1) { + powerpc_config_intr(INTR_VEC(iparent, intr[i]), + (intr[i+1] & 1) ? INTR_TRIGGER_LEVEL : + INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); + } + + dinfo->udi_interrupts[dinfo->udi_ninterrupts] = + INTR_VEC(iparent, intr[i]); dinfo->udi_ninterrupts++; } } Index: powerpc/powermac/grackle.c =================================================================== --- powerpc/powermac/grackle.c (revision 208284) +++ powerpc/powermac/grackle.c (working copy) @@ -43,6 +43,7 @@ #include #include +#include #include #include #include @@ -341,13 +342,15 @@ struct grackle_softc *sc; struct ofw_pci_register reg; uint32_t pintr, mintr; + phandle_t iparent; uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; sc = device_get_softc(bus); pintr = pin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, - sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) - return (mintr); + sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), + &iparent, maskbuf)) + return (INTR_VEC(iparent, mintr)); /* Maybe it's a real interrupt, not an intpin */ if (pin > 4) Index: powerpc/powermac/hrowpic.c =================================================================== --- powerpc/powermac/hrowpic.c (revision 208284) +++ powerpc/powermac/hrowpic.c (working copy) @@ -70,6 +70,7 @@ static void hrowpic_ipi(device_t, u_int); static void hrowpic_mask(device_t, u_int); static void hrowpic_unmask(device_t, u_int); +static uint32_t hrowpic_id(device_t dev); static device_method_t hrowpic_methods[] = { /* Device interface */ @@ -80,6 +81,7 @@ DEVMETHOD(pic_dispatch, hrowpic_dispatch), DEVMETHOD(pic_enable, hrowpic_enable), DEVMETHOD(pic_eoi, hrowpic_eoi), + DEVMETHOD(pic_id, hrowpic_id), DEVMETHOD(pic_ipi, hrowpic_ipi), DEVMETHOD(pic_mask, hrowpic_mask), DEVMETHOD(pic_unmask, hrowpic_unmask), @@ -169,6 +171,8 @@ hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_SECONDARY, 0xffffffff); powerpc_register_pic(dev, 64); + root_pic = dev; /* Heathrow systems have only one PIC */ + return (0); } @@ -282,3 +286,10 @@ sc = device_get_softc(dev); hrowpic_toggle_irq(sc, irq, 1); } + +static uint32_t +hrowpic_id(device_t dev) +{ + return (ofw_bus_get_node(dev)); +} + Index: powerpc/powermac/macgpio.c =================================================================== --- powerpc/powermac/macgpio.c (revision 208284) +++ powerpc/powermac/macgpio.c (working copy) @@ -35,15 +35,16 @@ #include #include #include -#include #include -#include #include #include + +#include +#include #include - #include +#include #include #include @@ -148,8 +149,7 @@ { struct macgpio_softc *sc; struct macgpio_devinfo *dinfo; - phandle_t root; - phandle_t child; + phandle_t root, child, iparent; device_t cdev; uint32_t irq; @@ -184,10 +184,13 @@ resource_list_init(&dinfo->mdi_resources); - if (OF_getprop(child,"interrupts",&irq, sizeof(irq)) == + if (OF_getprop(child, "interrupts", &irq, sizeof(irq)) == sizeof(irq)) { + OF_searchprop(child, "interrupt-parent", &iparent, + sizeof(iparent)); resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, - 0, irq, irq, 1); + 0, INTR_VEC(iparent, irq), INTR_VEC(iparent, irq), + 1); } /* Fix messed-up offsets */ Index: powerpc/powermac/macio.c =================================================================== --- powerpc/powermac/macio.c (revision 208284) +++ powerpc/powermac/macio.c (working copy) @@ -37,15 +37,16 @@ #include #include #include -#include #include -#include #include #include + +#include +#include #include - #include +#include #include #include @@ -186,6 +187,7 @@ static void macio_add_intr(phandle_t devnode, struct macio_devinfo *dinfo) { + phandle_t iparent; int *intr; int i, nintr; int icells; @@ -211,11 +213,17 @@ if (intr[0] == -1) return; + if (OF_getprop(devnode, "interrupt-parent", &iparent, sizeof(iparent)) + <= 0) + panic("Interrupt but no interrupt parent!\n"); + for (i = 0; i < nintr; i+=icells) { resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, - dinfo->mdi_ninterrupts, intr[i], intr[i], 1); + dinfo->mdi_ninterrupts, INTR_VEC(iparent, intr[i]), + INTR_VEC(iparent, intr[i]), 1); - dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] = intr[i]; + dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] = + INTR_VEC(iparent, intr[i]); dinfo->mdi_ninterrupts++; } } Index: sparc64/pci/schizo.c =================================================================== --- sparc64/pci/schizo.c (revision 208284) +++ sparc64/pci/schizo.c (working copy) @@ -1077,7 +1077,7 @@ pintr = pin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), - maskbuf)) + NULL, maskbuf)) return (mintr); device_printf(bridge, "could not route pin %d for device %d.%d\n", Index: sparc64/pci/psycho.c =================================================================== --- sparc64/pci/psycho.c (revision 208284) +++ sparc64/pci/psycho.c (working copy) @@ -1046,7 +1046,7 @@ pintr = pin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), - maskbuf)) + NULL, maskbuf)) return (mintr); /* * If this is outside of the range for an intpin, it's likely a full Index: sparc64/pci/ofw_pcib_subr.c =================================================================== --- sparc64/pci/ofw_pcib_subr.c (revision 208284) +++ sparc64/pci/ofw_pcib_subr.c (working copy) @@ -77,7 +77,7 @@ pintr = intpin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), - maskbuf)) { + NULL, maskbuf)) { /* * If we've found a mapping, return it and don't map * it again on higher levels - that causes problems Index: sparc64/pci/fire.c =================================================================== --- sparc64/pci/fire.c (revision 208284) +++ sparc64/pci/fire.c (working copy) @@ -1476,7 +1476,7 @@ pintr = pin; if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), - maskbuf) != 0) + NULL, maskbuf) != 0) return (mintr); device_printf(bridge, "could not route pin %d for device %d.%d\n", Index: sparc64/isa/ofw_isa.c =================================================================== --- sparc64/isa/ofw_isa.c (revision 208284) +++ sparc64/isa/ofw_isa.c (working copy) @@ -113,7 +113,7 @@ * fully specified, so we may not continue to map. */ if (!ofw_bus_lookup_imap(node, ii, ®, sizeof(reg), - &intr, sizeof(intr), &mintr, sizeof(mintr), maskbuf)) { + &intr, sizeof(intr), &mintr, sizeof(mintr), NULL, maskbuf)) { /* Try routing at the parent bridge. */ mintr = PCIB_ROUTE_INTERRUPT(pbridge, bridge, intr); } Index: sparc64/ebus/ebus.c =================================================================== --- sparc64/ebus/ebus.c (revision 208284) +++ sparc64/ebus/ebus.c (working copy) @@ -619,7 +619,7 @@ intr = intrs[i]; rv = ofw_bus_lookup_imap(node, &sc->sc_iinfo, ®, sizeof(reg), &intr, sizeof(intr), &rintr, - sizeof(rintr), maskbuf); + sizeof(rintr), NULL, maskbuf); #ifndef SUN4V if (rv != 0) rintr = INTMAP_VEC(sc->sc_ign, rintr); Index: dev/ofw/ofw_bus_subr.c =================================================================== --- dev/ofw/ofw_bus_subr.c (revision 208284) +++ dev/ofw/ofw_bus_subr.c (working copy) @@ -174,7 +174,7 @@ int ofw_bus_lookup_imap(phandle_t node, struct ofw_bus_iinfo *ii, void *reg, int regsz, void *pintr, int pintrsz, void *mintr, int mintrsz, - void *maskbuf) + phandle_t *iparent, void *maskbuf) { int rv; @@ -188,7 +188,7 @@ panic("ofw_bus_lookup_imap: could not get reg property"); return (ofw_bus_search_intrmap(pintr, pintrsz, reg, ii->opi_addrc, ii->opi_imap, ii->opi_imapsz, ii->opi_imapmsk, maskbuf, mintr, - mintrsz)); + mintrsz, iparent)); } /* @@ -211,7 +211,7 @@ int ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz, void *imap, int imapsz, void *imapmsk, void *maskbuf, void *result, - int rintrsz) + int rintrsz, phandle_t *iparent) { phandle_t parent; uint8_t *ref = maskbuf; @@ -255,6 +255,9 @@ if (bcmp(ref, mptr, physsz + intrsz) == 0) { bcopy(mptr + physsz + intrsz + sizeof(parent), result, rintrsz); + + if (iparent != NULL) + *iparent = parent; return (1); } mptr += tsz; Index: dev/ofw/ofw_bus_subr.h =================================================================== --- dev/ofw/ofw_bus_subr.h (revision 208284) +++ dev/ofw/ofw_bus_subr.h (working copy) @@ -63,8 +63,11 @@ /* Routines for processing firmware interrupt maps */ void ofw_bus_setup_iinfo(phandle_t, struct ofw_bus_iinfo *, int); int ofw_bus_lookup_imap(phandle_t, struct ofw_bus_iinfo *, void *, int, - void *, int, void *, int, void *); + void *, int, void *, int, phandle_t *, void *); int ofw_bus_search_intrmap(void *, int, void *, int, void *, int, void *, - void *, void *, int); + void *, void *, int, phandle_t *); +/* Helper to get node's interrupt parent */ +void ofw_bus_find_iparent(phandle_t); + #endif /* !_DEV_OFW_OFW_BUS_SUBR_H_ */