diff -r 042965c70be1 sys/dev/cxgbe/adapter.h
--- a/sys/dev/cxgbe/adapter.h	Mon Jan 30 20:07:28 2017 -0800
+++ b/sys/dev/cxgbe/adapter.h	Fri Feb 10 12:30:56 2017 -0800
@@ -548,8 +548,6 @@ struct sge_rxq {
 	struct lro_ctrl lro;	/* LRO state */
 	struct t4_lro_ctrl t4_lro;
 #endif
-	int rearm;		/* # of times intr has been rearmed with pending
-				   LRO entries to flush */
 
 	/* stats for common events first */
 
diff -r 042965c70be1 sys/dev/cxgbe/t4_sge.c
--- a/sys/dev/cxgbe/t4_sge.c	Mon Jan 30 20:07:28 2017 -0800
+++ b/sys/dev/cxgbe/t4_sge.c	Fri Feb 10 12:30:56 2017 -0800
@@ -584,6 +584,10 @@ t4_tweak_chip_settings(struct adapter *s
 	    V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
 	t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
 
+	m = V_TSCALE(M_TSCALE);
+	v = V_TSCALE(8);	/* multiply by 10 */
+	t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
+
 	/* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
 	v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
 	t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
@@ -1622,38 +1626,15 @@ service_iq2(struct sge_iq *iq)
 	limit = iq->qsize >> 3;
 	fl_hw_cidx = fl->hw_cidx;	/* stable snapshot */
 	if (iq->flags & IQ_ADJ_CREDIT) {
+		iq->flags &= ~IQ_ADJ_CREDIT;
 		if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
-			if (++rxq->rearm >= 10) {
-				/*
-				 * No activity in a long time.  Flush LRO, tell
-				 * the chip we're all caught up, and rearm with
-				 * normal timer.
-				 */
-				t4_lro_flush_all(&rxq->t4_lro);
-				t4_write_reg(sc, sc->sge_gts_reg,
-				    V_CIDXINC(1) |
-				    V_INGRESSQID((u32)iq->cntxt_id) |
-				    V_SEINTARM(iq->intr_params));
-				iq->flags &= ~IQ_ADJ_CREDIT;
-				rxq->rearm = 0;
-			} else {
-				/*
-				 * No activity but haven't waited long enough.
-				 * Hold back the single credit and rearm intr
-				 * with largest possible timer.
-				 */
-				t4_write_reg(sc, sc->sge_gts_reg,
-				    V_CIDXINC(0) |
-				    V_INGRESSQID((u32)iq->cntxt_id) |
-				    V_SEINTARM(V_QINTR_TIMER_IDX(SGE_NTIMERS - 1)));
-			}
+			t4_lro_flush_all(&rxq->t4_lro);
+			t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
+			    V_INGRESSQID((u32)iq->cntxt_id) |
+			    V_SEINTARM(iq->intr_params));
 			return (0);
 		}
-
-		/* Got new frames, business as usual. */
 		ndescs = 1;
-		iq->flags &= ~IQ_ADJ_CREDIT;
-		rxq->rearm = 0;
 	}
 
 	while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
@@ -1722,10 +1703,10 @@ service_iq2(struct sge_iq *iq)
 		}
 		if (__predict_false(++ndescs == limit)) {
 			t4_write_reg(sc, sc->sge_gts_reg,
-			    V_CIDXINC(ndescs) |
+			    V_CIDXINC(ndescs - 1) |
 			    V_INGRESSQID(iq->cntxt_id) |
 			    V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
-			ndescs = 0;
+			ndescs = 1;
 
 #if 0
 #if defined(INET) || defined(INET6)
@@ -1750,22 +1731,14 @@ service_iq2(struct sge_iq *iq)
 		if (ndescs > 0 && rxq->t4_lro.lro_mbuf_count > 0) {
 			/* hold back one credit and don't flush LRO state */
 			iq->flags |= IQ_ADJ_CREDIT;
-			rxq->rearm = 1;
-			t4_write_reg(sc, sc->sge_gts_reg,
-			    V_CIDXINC(ndescs - 1) |
-			    V_INGRESSQID((u32)iq->cntxt_id) |
-			    V_SEINTARM(V_QINTR_TIMER_IDX(SGE_NTIMERS - 1)));
+			ndescs--;
 		} else {
 			t4_lro_flush_all(&rxq->t4_lro);
-			t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
-			    V_INGRESSQID((u32)iq->cntxt_id) |
-			    V_SEINTARM(iq->intr_params));
 		}
 	}
-#else
+#endif
 	t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
 	    V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
-#endif
 
 	if (iq->flags & IQ_HAS_FL) {
 		int starved;