diff -r af968a390b77 sys/dev/cxgbe/adapter.h
--- a/sys/dev/cxgbe/adapter.h	Sun Jan 29 21:00:28 2017 -0800
+++ b/sys/dev/cxgbe/adapter.h	Mon Jan 30 19:56:44 2017 -0800
@@ -548,6 +548,8 @@ struct sge_rxq {
 	struct lro_ctrl lro;	/* LRO state */
 	struct t4_lro_ctrl t4_lro;
 #endif
+	int rearm;		/* # of times intr has been rearmed with pending
+				   LRO entries to flush */
 
 	/* stats for common events first */
 
diff -r af968a390b77 sys/dev/cxgbe/t4_sge.c
--- a/sys/dev/cxgbe/t4_sge.c	Sun Jan 29 21:00:28 2017 -0800
+++ b/sys/dev/cxgbe/t4_sge.c	Mon Jan 30 19:56:44 2017 -0800
@@ -1622,15 +1622,38 @@ service_iq2(struct sge_iq *iq)
 	limit = iq->qsize >> 3;
 	fl_hw_cidx = fl->hw_cidx;	/* stable snapshot */
 	if (iq->flags & IQ_ADJ_CREDIT) {
-		ndescs++;
-		iq->flags &= ~IQ_ADJ_CREDIT;
 		if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
-			t4_lro_flush_all(&rxq->t4_lro);
-			t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
-			    V_INGRESSQID((u32)iq->cntxt_id) |
-			    V_SEINTARM(iq->intr_params));
+			if (++rxq->rearm >= 10) {
+				/*
+				 * No activity in a long time.  Flush LRO, tell
+				 * the chip we're all caught up, and rearm with
+				 * normal timer.
+				 */
+				t4_lro_flush_all(&rxq->t4_lro);
+				t4_write_reg(sc, sc->sge_gts_reg,
+				    V_CIDXINC(1) |
+				    V_INGRESSQID((u32)iq->cntxt_id) |
+				    V_SEINTARM(iq->intr_params));
+				iq->flags &= ~IQ_ADJ_CREDIT;
+				rxq->rearm = 0;
+			} else {
+				/*
+				 * No activity but haven't waited long enough.
+				 * Hold back the single credit and rearm intr
+				 * with largest possible timer.
+				 */
+				t4_write_reg(sc, sc->sge_gts_reg,
+				    V_CIDXINC(0) |
+				    V_INGRESSQID((u32)iq->cntxt_id) |
+				    V_SEINTARM(V_QINTR_TIMER_IDX(SGE_NTIMERS - 1)));
+			}
 			return (0);
 		}
+
+		/* Got new frames, business as usual. */
+		ndescs = 1;
+		iq->flags &= ~IQ_ADJ_CREDIT;
+		rxq->rearm = 0;
 	}
 
 	while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
@@ -1727,6 +1750,7 @@ service_iq2(struct sge_iq *iq)
 		if (ndescs > 0 && rxq->t4_lro.lro_mbuf_count > 0) {
 			/* hold back one credit and don't flush LRO state */
 			iq->flags |= IQ_ADJ_CREDIT;
+			rxq->rearm = 1;
 			t4_write_reg(sc, sc->sge_gts_reg,
 			    V_CIDXINC(ndescs - 1) |
 			    V_INGRESSQID((u32)iq->cntxt_id) |