Index: sys/amd64/vmm/vmm_instruction_emul.c
===================================================================
--- sys/amd64/vmm/vmm_instruction_emul.c	(revision 254729)
+++ sys/amd64/vmm/vmm_instruction_emul.c	(working copy)
@@ -77,6 +77,10 @@
 		.op_byte = 0x89,
 		.op_type = VIE_OP_TYPE_MOV,
 	},
+	[0x8A] = {
+		.op_byte = 0x8A,
+		.op_type = VIE_OP_TYPE_MOV,
+	},
 	[0x8B] = {
 		.op_byte = 0x8B,
 		.op_type = VIE_OP_TYPE_MOV,
@@ -268,13 +272,18 @@
 			error = memwrite(vm, vcpuid, gpa, val, size, arg);
 		}
 		break;
+	case 0x8A:
 	case 0x8B:
 		/*
 		 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
+		 * 8A/r:	mov r/m8, r8
+		 * REX + 8A/r:	mov r/m8, r8
 		 * 8B/r:	mov r32, r/m32
 		 * REX.W 8B/r:	mov r64, r/m64
 		 */
-		if (vie->rex_w)
+		if (vie->op.op_byte == 0x8A)
+			size = 1;
+		else if (vie->rex_w)
 			size = 8;
 		error = memread(vm, vcpuid, gpa, &val, size, arg);
 		if (error == 0) {
@@ -690,7 +699,6 @@
 				vie->base_register = VM_REG_GUEST_RIP;
 			else
 				vie->base_register = VM_REG_LAST;
-				
 		}
 		break;
 	}
Index: usr.sbin/bhyve/pci_emul.c
===================================================================
--- usr.sbin/bhyve/pci_emul.c	(revision 254729)
+++ usr.sbin/bhyve/pci_emul.c	(working copy)
@@ -245,8 +245,12 @@
 	int tab_index;
 	uint64_t retval = ~0;
 
-	/* support only 4 or 8 byte reads */
-	if (size != 4 && size != 8)
+	/*
+	 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X
+	 * table but we also allow 1 byte access to accomodate reads from
+	 * ddb.
+	 */
+	if (size != 1 && size != 4 && size != 8)
 		return (retval);
 
 	msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
@@ -263,7 +267,9 @@
 		dest = (char *)(pi->pi_msix.table + tab_index);
 		dest += msix_entry_offset;
 
-		if (size == 4)
+		if (size == 1)
+			retval = *((uint8_t *)dest);
+		else if (size == 4)
 			retval = *((uint32_t *)dest);
 		else
 			retval = *((uint64_t *)dest);