Give the undocumented values a name, and try
to fix the DP83815 bug.

Index: if_sis.c
===================================================================
RCS file: /home/ncvs/src/sys/pci/if_sis.c,v
retrieving revision 1.64
diff -u -r1.64 if_sis.c
--- if_sis.c	28 Jan 2003 10:55:38 -0000	1.64
+++ if_sis.c	31 Jan 2003 17:35:48 -0000
@@ -2138,18 +2138,46 @@
 #endif
 
 	/*
-	 * Page 75 of the DP83815 manual recommends the
+	 * Page 75/78 of the DP83815 manual recommends the
 	 * following register settings "for optimum
 	 * performance." Note however that at least three
 	 * of the registers are listed as "reserved" in
 	 * the register map, so who knows what they do.
 	 */
 	if (sc->sis_type == SIS_TYPE_83815) {
-		CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
-		CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
-		CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
-		CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
-		CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
+		int tmp;
+
+		CSR_WRITE_4(sc, NS_PHY_PAGE, NS_PHY_PAGE_VAL);
+		CSR_WRITE_4(sc, NS_PHY_CR, NS_PHY_CR_VAL);
+		CSR_WRITE_4(sc, NS_PHY_TDATA, NS_PHY_TDATA_VAL);
+		CSR_WRITE_4(sc, NS_PHY_DSPCFG, NS_PHY_DSPCFG_VAL1);
+		CSR_WRITE_4(sc, NS_PHY_SDCFG, NS_PHY_SDCFG_VAL);
+
+	       /*
+		* Set up some DSP values to let the dp83815 do the
+		* PHY coefficient checks, so short cables will work with
+		* all chips. The cable attenuation changes. There are
+		* unexplained magic numbers here.
+		* XXX Consult National for the meaning of these numbers
+		*/
+		if (! CSR_READ_4(sc, NS_PHY_STATUS) & NS_PHY_ST_SPEED10) {
+			CSR_WRITE_2(sc, NS_PHY_PAGE, 1);
+			tmp = CSR_READ_4(sc, NS_PHY_DSPCFG);
+			CSR_WRITE_2(sc, NS_PHY_DSPCFG,
+			    (tmp & NS_PHY_PAGE_VAL0)| NS_PHY_PAGE_VAL6);
+			DELAY(100);
+			tmp = CSR_READ_4(sc, NS_PHY_TDATA);
+			if (! (tmp & NS_PHY_PAGE_VAL2) ||
+			   ((tmp >= NS_PHY_PAGE_VAL3) &&
+			    (tmp <= NS_PHY_PAGE_VAL5))) {
+				CSR_WRITE_2(sc, NS_PHY_TDATA,
+				    NS_PHY_PAGE_VAL4);
+				tmp = CSR_READ_4(sc, NS_PHY_DSPCFG);
+				CSR_WRITE_4(sc, NS_PHY_DSPCFG,
+				     (tmp | NS_PHY_PAGE_VAL1));
+			}
+			CSR_WRITE_2(sc, NS_PHY_PAGE, 0);
+		}
 	}
 
 	ifp->if_flags |= IFF_RUNNING;
Index: if_sisreg.h
===================================================================
RCS file: /home/ncvs/src/sys/pci/if_sisreg.h,v
retrieving revision 1.21
diff -u -r1.21 if_sisreg.h
--- if_sisreg.h	29 Jan 2003 21:56:10 -0000	1.21
+++ if_sisreg.h	31 Jan 2003 17:35:48 -0000
@@ -84,14 +84,39 @@
 #define NS_ANLPAR		0x94
 #define NS_ANER			0x98
 #define NS_ANNPTR		0x9C
+#define NS_PHY_STATUS		0xC0
 
+/* Additional NS registers from page 78 */
+#define NS_PHY_PAGE		0xCC
 #define NS_PHY_CR		0xE4
 #define NS_PHY_10BTSCR		0xE8
-#define NS_PHY_PAGE		0xCC
 #define NS_PHY_EXTCFG		0xF0
 #define NS_PHY_DSPCFG		0xF4
-#define NS_PHY_SDCFG		0xF8
 #define NS_PHY_TDATA		0xFC
+#define NS_PHY_SDCFG		0xF8
+
+/* NS PHY_STATUS VALUES */
+#define NS_PHY_ST_VALIDLINK	0x01
+#define NS_PHY_ST_SPEED10	0x02
+#define NS_PHY_ST_FULLDUPLEX	0x04
+#define NS_PHY_ST_LOOPBACK	0x08
+#define NS_PHY_ST_AUTONEGDONE	0x10
+
+/* NS undocumented magic values */
+#define NS_PHY_PAGE_VAL0	0xFFF
+#define NS_PHY_PAGE_VAL1	0x0020
+#define NS_PHY_PAGE_VAL2	0x0080
+#define NS_PHY_PAGE_VAL3	0x00D8
+#define NS_PHY_PAGE_VAL4	0x00E8
+#define NS_PHY_PAGE_VAL5	0x00FF
+#define NS_PHY_PAGE_VAL6	0x1000
+
+#define NS_PHY_PAGE_VAL		0x0001
+#define NS_PHY_CR_VAL		0x189C
+#define NS_PHY_TDATA_VAL	0x0000
+#define NS_PHY_SDCFG_VAL	0x008C
+#define NS_PHY_DSPCFG_VAL1	0x5040
+#define NS_PHY_DSPCFG_VAL2	0x1060
 
 #define NS_CLKRUN_PMESTS	0x00008000
 #define NS_CLKRUN_PMEENB	0x00000100
@@ -474,6 +499,9 @@
  */
 #define CSR_WRITE_4(sc, reg, val)	\
 	bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)
+
+#define CSR_WRITE_2(sc, reg, val)	\
+	bus_space_write_2(sc->sis_btag, sc->sis_bhandle, reg, val)
 
 #define CSR_READ_4(sc, reg)		\
 	bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg)