When reading PHY regs over the i2c bus, the turnaround ACK bit
is read one clock edge too late. This bit is driven low by
slave (as any other input data bits from slave) when the clock
is LOW. The current code did read the bit after the clock was
driven high again.

Found by :	luoqi

--- sys/pci/if_vr.c.orig	Sun Jan  5 18:34:30 2003
+++ sys/pci/if_vr.c	Sun Jan  5 18:48:29 2003
@@ -329,9 +329,9 @@
 	/* Check for ack */
 	SIO_CLR(VR_MIICMD_CLK);
 	DELAY(1);
+	ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
 	SIO_SET(VR_MIICMD_CLK);
 	DELAY(1);
-	ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
 
 	/*
 	 * Now try reading data bits. If the ack failed, we still
--- sys/pci/if_xl.c.orig	Sun Jan  5 18:34:40 2003
+++ sys/pci/if_xl.c	Sun Jan  5 18:49:16 2003
@@ -492,8 +492,8 @@
 
 	/* Check for ack */
 	MII_CLR(XL_MII_CLK);
-	MII_SET(XL_MII_CLK);
 	ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
+	MII_SET(XL_MII_CLK);
 
 	/*
 	 * Now try reading data bits. If the ack failed, we still
--- sys/pci/if_ste.c.orig	Sun Jan  5 18:34:14 2003
+++ sys/pci/if_ste.c	Sun Jan  5 18:49:05 2003
@@ -282,9 +282,9 @@
 	/* Check for ack */
 	MII_CLR(STE_PHYCTL_MCLK);
 	DELAY(1);
+	ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
 	MII_SET(STE_PHYCTL_MCLK);
 	DELAY(1);
-	ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
 
 	/*
 	 * Now try reading data bits. If the ack failed, we still
--- sys/pci/if_wb.c.orig	Sun Jan  5 18:34:34 2003
+++ sys/pci/if_wb.c	Sun Jan  5 18:48:47 2003
@@ -436,9 +436,9 @@
 	/* Check for ack */
 	SIO_CLR(WB_SIO_MII_CLK);
 	DELAY(1);
+	ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
 	SIO_SET(WB_SIO_MII_CLK);
 	DELAY(1);
-	ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
 	SIO_CLR(WB_SIO_MII_CLK);
 	DELAY(1);
 	SIO_SET(WB_SIO_MII_CLK);
--- sys/pci/if_rl.c.orig	Sun Jan  5 18:34:02 2003
+++ sys/pci/if_rl.c	Sun Jan  5 18:47:23 2003
@@ -490,9 +490,9 @@
 	/* Check for ack */
 	MII_CLR(RL_MII_CLK);
 	DELAY(1);
+	ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 	MII_SET(RL_MII_CLK);
 	DELAY(1);
-	ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 
 	/*
 	 * Now try reading data bits. If the ack failed, we still
--- sys/dev/nge/if_nge.c.orig	Tue Jan  7 06:14:14 2003
+++ sys/dev/nge/if_nge.c	Tue Jan  7 06:14:35 2003
@@ -483,9 +483,9 @@
 	/* Check for ack */
 	SIO_CLR(NGE_MEAR_MII_CLK);
 	DELAY(1);
+	ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
 	SIO_SET(NGE_MEAR_MII_CLK);
 	DELAY(1);
-	ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
 
 	/*
 	 * Now try reading data bits. If the ack failed, we still
--- sys/dev/xe/if_xe.c.orig	Tue Jan  7 06:15:18 2003
+++ sys/dev/xe/if_xe.c	Tue Jan  7 06:15:59 2003
@@ -1659,9 +1659,9 @@
   /* Check for ack */
   XE_MII_CLR(XE_MII_CLK);
   DELAY(1);
+  ack = XE_INB(XE_GPR2) & XE_MII_RDD;
   XE_MII_SET(XE_MII_CLK);
   DELAY(1);
-  ack = XE_INB(XE_GPR2) & XE_MII_RDD;
 
   /*
    * Now try reading data bits. If the ack failed, we still