From 54b20a190c2417f9b8acaee37b9f5938ff8d69b8 Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Mon, 28 Nov 2022 12:40:55 -0500 Subject: [PATCH 25/52] mips: Handle TLB exceptions for pages with psind > 1 This is somewhat ugly, but the idea is to reuse the existing handlers and parameterize them for each page size index. The exception-in-kernel-mode handler is untested since we do not yet map large pages into the kernel; they have to be accessed via the direct map. --- sys/mips/include/pte.h | 24 ++++++++++----- sys/mips/mips/exception.S | 61 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 76 insertions(+), 9 deletions(-) diff --git a/sys/mips/include/pte.h b/sys/mips/include/pte.h index 5d2671f55781..d7085645398c 100644 --- a/sys/mips/include/pte.h +++ b/sys/mips/include/pte.h @@ -252,14 +252,22 @@ typedef pt_entry_t *pd_entry_t; #define TLBLO_PTE_TO_IDX(pte) (((pte) & PTE_PS_IDX_MASK) >> 56) #define TLBMASK_IDX_TO_MASK(idx) (((1 << ((idx) << 1)) - 1) << TLBMASK_SHIFT) #define TLBLO_PTE_TO_MASK(pte) TLBMASK_IDX_TO_MASK(TLBLO_PTE_TO_IDX(pte)) -#define TLBMASK_4K_PAGE TLBMASK_IDX_TO_MASK(0) -#define TLBMASK_16K_PAGE TLBMASK_IDX_TO_MASK(1) -#define TLBMASK_64K_PAGE TLBMASK_IDX_TO_MASK(2) -#define TLBMASK_256K_PAGE TLBMASK_IDX_TO_MASK(3) -#define TLBMASK_1M_PAGE TLBMASK_IDX_TO_MASK(4) -#define TLBMASK_4M_PAGE TLBMASK_IDX_TO_MASK(5) -#define TLBMASK_16M_PAGE TLBMASK_IDX_TO_MASK(6) -#define TLBMASK_64M_PAGE TLBMASK_IDX_TO_MASK(7) +#define TLBMASK_IDX_4K 0 +#define TLBMASK_IDX_16K 1 +#define TLBMASK_IDX_64K 2 +#define TLBMASK_IDX_256K 3 +#define TLBMASK_IDX_1M 4 +#define TLBMASK_IDX_4M 5 +#define TLBMASK_IDX_16M 6 +#define TLBMASK_IDX_64M 7 +#define TLBMASK_4K_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_4K) +#define TLBMASK_16K_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_16K) +#define TLBMASK_64K_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_64K) +#define TLBMASK_256K_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_256K) +#define TLBMASK_1M_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_1M) +#define TLBMASK_4M_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_4M) +#define TLBMASK_16M_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_16M) +#define TLBMASK_64M_PAGE TLBMASK_IDX_TO_MASK(TLBMASK_IDX_64M) #else /* ! MIPS64_NEW_PMAP */ #define TLBLO_PTE_TO_IDX(pte) 0 #define TLBLO_PTE_TO_MASK(pte) 0 diff --git a/sys/mips/mips/exception.S b/sys/mips/mips/exception.S index 6ac912a9530b..21df77f448dd 100644 --- a/sys/mips/mips/exception.S +++ b/sys/mips/mips/exception.S @@ -203,12 +203,32 @@ MipsDoTLBMiss: GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE beq k1, zero, not_superpage # ==0 -- not superpage + nop # branch delay slot + sub k1, k1, TLBMASK_IDX_1M + beq k1, zero, miss_super_2m + sub k1, k1, 1 + beq k1, zero, miss_super_8m + sub k1, k1, 1 + beq k1, zero, miss_super_32m + sub k1, k1, 1 + beq k1, zero, miss_super_128m + nop # branch delay slot + PANIC("unknown page size index") + +miss_super_2m: LOAD_SUPERPAGE_TLB(1024 * 1024, TLBMASK_1M_PAGE) +miss_super_8m: + LOAD_SUPERPAGE_TLB(4 * 1024 * 1024, TLBMASK_4M_PAGE) +miss_super_32m: + LOAD_SUPERPAGE_TLB(16 * 1024 * 1024, TLBMASK_16M_PAGE) +miss_super_128m: + LOAD_SUPERPAGE_TLB(64 * 1024 * 1024, TLBMASK_64M_PAGE) #undef LOAD_SUPERPAGE_TLB not_superpage: #endif /* MIPS64_NEW_PMAP */ #endif + PTR_L k1, 0(k0) MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again) PTR_SRL k0, PAGE_SHIFT - PTESHIFT #0b: k0=VPN (aka va>>10) andi k0, k0, PTE2MASK #0c: k0=page tab offset @@ -1007,12 +1027,32 @@ LEAF_NOPROFILE(MipsTLBInvalidException) GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE beq k1, zero, not_spg # ==0 -- not superpage + nop # branch delay slot + sub k1, k1, TLBMASK_IDX_1M + beq k1, zero, invalid_super_2m + sub k1, k1, 1 + beq k1, zero, invalid_super_8m + sub k1, k1, 1 + beq k1, zero, invalid_super_32m + sub k1, k1, 1 + beq k1, zero, invalid_super_128m + nop # branch delay slot + PANIC("unknown page size index") + +invalid_super_2m: LOAD_SUPERPAGE_TLB(1024 * 1024, TLBMASK_1M_PAGE) +invalid_super_8m: + LOAD_SUPERPAGE_TLB(4 * 1024 * 1024, TLBMASK_4M_PAGE) +invalid_super_32m: + LOAD_SUPERPAGE_TLB(16 * 1024 * 1024, TLBMASK_16M_PAGE) +invalid_super_128m: + LOAD_SUPERPAGE_TLB(64 * 1024 * 1024, TLBMASK_64M_PAGE) #undef LOAD_SUPERPAGE_TLB not_spg: #endif /* MIPS64_NEW_PMAP */ #endif + PTR_L k1, 0(k0) MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again) PTR_SRL k0, PAGE_SHIFT - PTESHIFT # k0=VPN andi k0, k0, PTEMASK # k0=page tab offset @@ -1217,12 +1257,31 @@ LEAF_NOPROFILE(MipsTLBMissException) # Check for superpage GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE beq k1, zero, not_kspg # ==0 -- not superpage + nop # branch delay slot + sub k1, k1, TLBMASK_IDX_1M + beq k1, zero, miss_ksuper_2m + sub k1, k1, 1 + beq k1, zero, miss_ksuper_8m + sub k1, k1, 1 + beq k1, zero, miss_ksuper_32m + sub k1, k1, 1 + beq k1, zero, miss_ksuper_128m + nop # branch delay slot + PANIC("unknown page size index") + +miss_ksuper_2m: LOAD_SUPERPAGE_TLB(1024 * 1024, TLBMASK_1M_PAGE) +miss_ksuper_8m: + LOAD_SUPERPAGE_TLB(4 * 1024 * 1024, TLBMASK_4M_PAGE) +miss_ksuper_32m: + LOAD_SUPERPAGE_TLB(16 * 1024 * 1024, TLBMASK_16M_PAGE) +miss_ksuper_128m: + LOAD_SUPERPAGE_TLB(64 * 1024 * 1024, TLBMASK_64M_PAGE) #undef LOAD_SUPERPAGE_TLB not_kspg: #endif /* MIPS64_NEW_PMAP */ - + PTR_L k1, 0(k0) MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again) beq k1, zero, MipsKernGenException # ==0 -- no page table #endif -- 2.41.0