From 5b1fcdb8aa9c1d62442b0e2360f7434f16c6806a Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Wed, 23 Nov 2022 13:05:01 -0500 Subject: [PATCH 23/52] mips: Use a macro to load superpage TLB entries This will make it easier to handle other page sizes. No functional change intended. --- sys/mips/mips/exception.S | 171 ++++++++++++++++---------------------- 1 file changed, 71 insertions(+), 100 deletions(-) diff --git a/sys/mips/mips/exception.S b/sys/mips/mips/exception.S index b7b53edd0cc1..6ac912a9530b 100644 --- a/sys/mips/mips/exception.S +++ b/sys/mips/mips/exception.S @@ -179,45 +179,32 @@ MipsDoTLBMiss: nop #ifdef MIPS64_NEW_PMAP - # Check for superpage - GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE - beq k1, zero, not_superpage # ==0 -- not superpage - PTR_L k1, 0(k0) # k1=pde entry (delay slot) - - # Set the referenced bit in the PDE if valid. - # - # XXX Setting the referenced bit here saves a fault later but it - # may not be safe to do so. Therefore, just take the fault to set - # the reference bit. -# IF_VALID_SET_REFBIT(k1, k0, 0, 1) - - # The PDE is actually a superpage PTE. Store it in the TLB lo0 reg. - CLEAR_PTE_SWBITS(k1) - PTE_MTC0 k1, MIPS_COP_0_TLB_LO0 # lo0 is loaded - COP0_SYNC - - # Compute the PFN for the TLB lo1 register from k1(=PTE for TLB lo0). - GET_ODD_1M_PFN_FROM_EVEN(k1) # k1=Odd PFN in PTE postion - - # Get hard TLB flag bits. - PTR_L k0, 0(k0) # k0=pde entry (again) - GET_HW_TLB_FLAGS(k0) # k0=hw TLB flag bits - or k1, k1, k0 # k1=PTE=PFN | hwflg bits - # Load it into the TLB Lo1 register. - #CLEAR_PTE_SWBITS(k1) # No SW bits to clear - PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded - COP0_SYNC - # Load the TLB PageMask for 1M pages. - dli k0, TLBMASK_1M_PAGE # PageMask for 1M Page - PTE_MTC0 k0, MIPS_COP_0_TLB_PG_MASK # PageMask is loaded - COP0_SYNC +#define LOAD_SUPERPAGE_TLB(size, pagemask) \ + PTR_L k1, 0(k0) ;\ + CLEAR_PTE_SWBITS(k1) ;\ + PTE_MTC0 k1, MIPS_COP_0_TLB_LO0 ;\ + COP0_SYNC ;\ + GET_ODD_PFN_FROM_EVEN(size, k1) ;\ + PTR_L k0, 0(k0) ;\ + GET_HW_TLB_FLAGS(k0) ;\ + or k1, k1, k0 ;\ + CLEAR_PTE_SWBITS(k1) ;\ + PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 ;\ + COP0_SYNC ;\ + dli k0, pagemask ;\ + PTE_MTC0 k0, MIPS_COP_0_TLB_PG_MASK ;\ + COP0_SYNC ;\ + tlbwr ;\ + HAZARD_DELAY ;\ + PTE_MTC0 zero, MIPS_COP_0_TLB_PG_MASK ;\ + COP0_SYNC ;\ + eret - tlbwr # write to tlb - HAZARD_DELAY - PTE_MTC0 zero, MIPS_COP_0_TLB_PG_MASK # zero out PageMask reg - COP0_SYNC - eret # return from exception + GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE + beq k1, zero, not_superpage # ==0 -- not superpage + LOAD_SUPERPAGE_TLB(1024 * 1024, TLBMASK_1M_PAGE) +#undef LOAD_SUPERPAGE_TLB not_superpage: #endif /* MIPS64_NEW_PMAP */ @@ -997,40 +984,31 @@ LEAF_NOPROFILE(MipsTLBInvalidException) nop #ifdef MIPS64_NEW_PMAP - # Check for superpage - GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE - beq k1, zero, not_spg # ==0 -- not superpage - PTR_L k1, 0(k0) # k1=pde entry (delay slot) - - /* Validate page table entry. */ - andi k1, PTE_VR - beqz k1, 3f +#define LOAD_SUPERPAGE_TLB(size, pagemask) \ + PTR_L k1, 0(k0) ;\ + andi k1, PTE_VR ;\ + beqz k1, 3f ;\ + nop ;\ + CLEAR_PTE_SWBITS(k1) ;\ + PTE_MTC0 k1, MIPS_COP_0_TLB_LO0 ;\ + COP0_SYNC ;\ + GET_ODD_PFN_FROM_EVEN(size, k1) ;\ + PTR_L k0, 0(k0) ;\ + GET_HW_TLB_FLAGS(k0) ;\ + or k1, k1, k0 ;\ + CLEAR_PTE_SWBITS(k1) ;\ + PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 ;\ + COP0_SYNC ;\ + dli k0, pagemask ;\ + PTE_MTC0 k0, MIPS_COP_0_TLB_PG_MASK ;\ + COP0_SYNC ;\ + b tlb_insert_entry ;\ nop - # The PDE is actually a superpage PTE. Store it in the TLB lo0 reg. - CLEAR_PTE_SWBITS(k1) - PTE_MTC0 k1, MIPS_COP_0_TLB_LO0 # lo0 is loaded - COP0_SYNC - - # Compute the PFN for the TLB lo1 register from k1(=PTE for TLB lo0). - GET_ODD_1M_PFN_FROM_EVEN(k1) # k1=Odd PFN in PTE postion - - # Get hard TLB flag bits. - PTR_L k0, 0(k0) # k0=pde entry (again) - GET_HW_TLB_FLAGS(k0) # k0=hw TLB flag bits - or k1, k1, k0 # k1=PTE=PFN | hwflg bits - # Load it into the TLB Lo1 register. - # CLEAR_PTE_SWBITS(k1) # No SW bits to clear - PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded - COP0_SYNC - - # Load the TLB PageMask for 1M pages. - dli k0, TLBMASK_1M_PAGE # PageMask for 1M Page - PTE_MTC0 k0, MIPS_COP_0_TLB_PG_MASK # PageMask is loaded - COP0_SYNC - - b tlb_insert_entry - nop + GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE + beq k1, zero, not_spg # ==0 -- not superpage + LOAD_SUPERPAGE_TLB(1024 * 1024, TLBMASK_1M_PAGE) +#undef LOAD_SUPERPAGE_TLB not_spg: #endif /* MIPS64_NEW_PMAP */ @@ -1214,40 +1192,33 @@ LEAF_NOPROFILE(MipsTLBMissException) PTR_L k1, 0(k0) # k1=pde entry #ifdef MIPS64_NEW_PMAP + +#define LOAD_SUPERPAGE_TLB(size, pagemask) \ + PTR_L k1, 0(k0) ;\ + CLEAR_PTE_SWBITS(k1) ;\ + PTE_MTC0 k1, MIPS_COP_0_TLB_LO0 ;\ + COP0_SYNC ;\ + GET_ODD_PFN_FROM_EVEN(size, k1) ;\ + PTR_L k0, 0(k0) ;\ + GET_HW_TLB_FLAGS(k0) ;\ + or k1, k1, k0 ;\ + CLEAR_PTE_SWBITS(k1) ;\ + PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 ;\ + COP0_SYNC ;\ + dli k0, pagemask ;\ + PTE_MTC0 k0, MIPS_COP_0_TLB_PG_MASK ;\ + COP0_SYNC ;\ + tlbwr ;\ + HAZARD_DELAY ;\ + PTE_MTC0 zero, MIPS_COP_0_TLB_PG_MASK ;\ + COP0_SYNC ;\ + eret + # Check for superpage GET_SUPERPAGE_IDX(k1) # k1=superpage index from PTE beq k1, zero, not_kspg # ==0 -- not superpage - PTR_L k1, 0(k0) # k1=pde entry (delay slot) - - # XXX Reference bit emulation - - # The PDE is actually a superpage PTE. Store it in the TLB lo0 reg. - CLEAR_PTE_SWBITS(k1) - PTE_MTC0 k1, MIPS_COP_0_TLB_LO0 # lo0 is loaded - COP0_SYNC - - # Compute the PFN for the TLB lo1 register from k1(=PTE for TLB lo0). - GET_ODD_1M_PFN_FROM_EVEN(k1) # k1=Odd PFN in PTE postion - - # Get hard TLB flag bits. - PTR_L k0, 0(k0) # k0=pde entry (again) - GET_HW_TLB_FLAGS(k0) # k0=hw TLB flag bits - or k1, k1, k0 # k1=PTE=PFN | hwflg bits - # Load it into the TLB Lo1 register. - #CLEAR_PTE_SWBITS(k1) # No SW Bits to clear - PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded - COP0_SYNC - - # Load the TLB PageMask for 1M pages. - dli k0, TLBMASK_1M_PAGE # PageMask for 1M Page - PTE_MTC0 k0, MIPS_COP_0_TLB_PG_MASK # PageMask is loaded - COP0_SYNC - - tlbwr # write to tlb - HAZARD_DELAY - PTE_MTC0 zero, MIPS_COP_0_TLB_PG_MASK # zero out PageMask reg - COP0_SYNC - eret # return from exception + LOAD_SUPERPAGE_TLB(1024 * 1024, TLBMASK_1M_PAGE) +#undef LOAD_SUPERPAGE_TLB not_kspg: #endif /* MIPS64_NEW_PMAP */ -- 2.41.0