Index: packages/hal/powerpc/arch/current/include/basetype.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/arch/current/include/basetype.h,v retrieving revision 1.5 diff -u -r1.5 basetype.h --- basetype.h 2000/08/25 17:33:19 1.5 +++ basetype.h 2001/10/22 21:12:49 @@ -60,6 +60,8 @@ // The PowerPC architecture uses the default definitions of the base types, // so we do not need to define any here. +#define cyg_halatomic cyg_halint32 + //----------------------------------------------------------------------------- #endif // CYGONCE_HAL_BASETYPE_H // End of basetype.h Index: packages/hal/powerpc/arch/current/include/hal_arch.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/arch/current/include/hal_arch.h,v retrieving revision 1.8 diff -u -r1.8 hal_arch.h --- hal_arch.h 2000/10/23 17:11:21 1.8 +++ hal_arch.h 2001/10/22 21:12:49 @@ -339,6 +339,41 @@ #define CYGARC_HAL_SAVE_GP() #define CYGARC_HAL_RESTORE_GP() +#define HAL_READ_BARRIER() asm volatile("isync" : : : "memory") +#define HAL_WRITE_BARRIER() asm volatile("eieio" : : : "memory") + +static inline int +hal_atomic_cas(cyg_atomic* addr, cyg_atomic cmpval, cyg_atomic newval) +{ + cyg_atomic oldval; + + asm volatile ( + "0: lwarx %0,0,%1 ;" + " cmpw %0,%2 ;" + " bne- 1f ;" + " stwcx. %3,0,%1 ;" + " bne- 0b ;" + "1: ;" + : "=&r" (oldval) + : "r" (addr), "r" (cmpval), "r" (newval) + : "memory", "cc" + ); + + return oldval == cmpval; +} + +#define HAL_COMPARE_AND_SWAP_RELEASE(_addr_, _cmp_, _new_) \ + hal_atomic_cas(_addr_, _cmp_, _new_) + +#define HAL_COMPARE_AND_SWAP_ACQUIRE(_addr_, _cmp_, _new_) \ + hal_atomic_cas(_addr_, _cmp_, _new_) + +#define HAL_STORE_RELEASE(_addr_, _val_) \ + CYG_MACRO_START \ + *(_addr_) = (_val_); \ + HAL_WRITE_BARRIER(); \ + CYG_MACRO_END + //----------------------------------------------------------------------------- #endif // CYGONCE_HAL_ARCH_H // End of hal_arch.h