Index: hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc8xx/current/cdl/hal_powerpc_mpc8xx.cdl,v retrieving revision 1.4 diff -u -r1.4 hal_powerpc_mpc8xx.cdl --- hal_powerpc_mpc8xx.cdl 2001/02/13 01:23:33 1.4 +++ hal_powerpc_mpc8xx.cdl 2001/10/16 03:22:58 @@ -110,45 +110,44 @@ cdl_component CYGPKG_HAL_POWERPC_MPC860 { display "PowerPC 860 microprocessor" - default_value 1 implements CYGINT_HAL_POWERPC_VARIANT description " The PowerPC 860 microprocessor. This is an embedded part that in addition to the PowerPC processor core has built in peripherals such as memory controllers, DMA controllers, serial ports and timers/counters." + } - cdl_option CYGHWR_HAL_POWERPC_FPU { - display "Variant FPU support" - calculated 0 - } + cdl_option CYGHWR_HAL_POWERPC_FPU { + display "Variant FPU support" + calculated 0 + } - cdl_option CYGPKG_HAL_POWERPC_MSBFIRST { - display "CPU Variant big-endian" - calculated 1 - } + cdl_option CYGPKG_HAL_POWERPC_MSBFIRST { + display "CPU Variant big-endian" + calculated 1 + } - cdl_component CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE { - display "Enable CPM interrupts" - default_value 1 - description " - This option causes the CPM interrupt arbiter to be attached - at startup, and CPM interrupts are enabled. Enabling CPM - level interrupt arbitration and handling must still be - done by the application code. See intr0.c test for an - example." + cdl_component CYGSEM_HAL_POWERPC_MPC8xx_CPM_ENABLE { + display "Enable CPM interrupts" + default_value 1 + description " + This option causes the CPM interrupt arbiter to be attached + at startup, and CPM interrupts are enabled. Enabling CPM + level interrupt arbitration and handling must still be + done by the application code. See intr0.c test for an + example." - cdl_option CYGHWR_HAL_POWERPC_MPC860_CPM_LVL { - display "CPM interrupt level on the SIU" - flavor data - legal_values 0 to 7 - default_value 7 - description " - This option selects which SIU level the CPM interrupts - should be routed to." - } - } + cdl_option CYGHWR_HAL_POWERPC_MPC8xx_CPM_LVL { + display "CPM interrupt level on the SIU" + flavor data + legal_values 0 to 7 + default_value 4 + description " + This option selects which SIU level the CPM interrupts + should be routed to." + } } define_proc { Index: hal/powerpc/mpc8xx/current/include/var_intr.h =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc8xx/current/include/var_intr.h,v retrieving revision 1.3 diff -u -r1.3 var_intr.h --- var_intr.h 2000/11/17 23:16:44 1.3 +++ var_intr.h 2001/10/16 03:22:58 @@ -87,7 +87,7 @@ #define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0 #define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC8xx // The MPC860 does not generate DSI and ISI: instead it goes to machine // check, so that a software VM system can then call into vectors 0x300 or // 0x400 if the address is truly invalid rather than merely not in the TLB @@ -214,7 +214,7 @@ #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC8xx static __inline__ void cyg_hal_interrupt_mask ( cyg_uint32 vector ) @@ -672,7 +672,7 @@ //-------------------------------------------------------------------------- // Interrupt arbiters -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC8xx externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector, CYG_ADDRWORD data); @@ -683,7 +683,7 @@ externC cyg_uint32 hal_arbitration_isr_cpm (CYG_ADDRWORD vector, CYG_ADDRWORD data); -#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 +#endif // ifdef CYGPKG_HAL_POWERPC_MPC8xx //----------------------------------------------------------------------------- // Symbols used by assembly code Index: hal/powerpc/mpc8xx/current/src/var_intr.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/mpc8xx/current/src/var_intr.c,v retrieving revision 1.5 diff -u -r1.5 var_intr.c --- var_intr.c 2001/06/29 14:45:50 1.5 +++ var_intr.c 2001/10/16 03:22:58 @@ -47,7 +47,7 @@ #include //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC8xx // Since the interrupt sources do not have fixed vectors on the 860 // SIU, some arbitration is required. @@ -167,22 +167,22 @@ return 0; } -#endif // ifdef CYGPKG_HAL_POWERPC_MPC860 +#endif // ifdef CYGPKG_HAL_POWERPC_MPC8xx externC void hal_variant_IRQ_init(void) { -#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE +#ifdef CYGSEM_HAL_POWERPC_MPC8xx_CPM_ENABLE // Attach first-level CPM arbiter to the configured SIU level and // enable CPM interrupts. #define ID_CPM 0xDEAD #define CYGPRI_SIU_LVL (CYGNUM_HAL_INTERRUPT_SIU_LVL0 \ - +CYGHWR_HAL_POWERPC_MPC860_CPM_LVL*2) + +CYGHWR_HAL_POWERPC_MPC8xx_CPM_LVL*2) HAL_INTERRUPT_ATTACH (CYGPRI_SIU_LVL, &hal_arbitration_isr_cpm, ID_CPM, 0); HAL_INTERRUPT_UNMASK (CYGPRI_SIU_LVL); HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_CPM, - CYGHWR_HAL_POWERPC_MPC860_CPM_LVL); + CYGHWR_HAL_POWERPC_MPC8xx_CPM_LVL); HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_CPM); #endif } Index: hal/powerpc/quicc/current/src/quicc_smc1.c =================================================================== RCS file: /cvs/ecos/ecos/packages/hal/powerpc/quicc/current/src/quicc_smc1.c,v retrieving revision 1.15 diff -u -r1.15 quicc_smc1.c --- quicc_smc1.c 2001/02/13 01:23:33 1.15 +++ quicc_smc1.c 2001/10/16 03:22:58 @@ -53,7 +53,7 @@ #include -#ifdef CYGPKG_HAL_POWERPC_MPC860 +#ifdef CYGPKG_HAL_POWERPC_MPC8xx // eCos headers decribing PowerQUICC: #include @@ -508,5 +508,5 @@ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); } -#endif // CYGPKG_HAL_POWERPC_MPC860 +#endif // CYGPKG_HAL_POWERPC_MPC8xx // EOF quicc_smc1.c