--- if_re.c.orig
+++ if_re.c
@@ -1292,8 +1292,10 @@
 	case RL_HWREV_8169S:
 		sc->rl_flags |= RL_FLAG_PHY8169;
 		break;
-	case RL_HWREV_8169_8110SB:
 	case RL_HWREV_8169_8110SC:
+		sc->rl_flags |= 0x10000;
+		/* FALLTHROUGH */
+	case RL_HWREV_8169_8110SB:
 	case RL_HWREV_8169_8110SBL:
 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHY8169;
 		break;
@@ -2498,7 +2500,7 @@
 {
 	struct ifnet		*ifp = sc->rl_ifp;
 	struct mii_data		*mii;
-	u_int32_t		rxcfg = 0;
+	uint32_t		reg, rxcfg = 0;
 	uint16_t		cfg;
 	union {
 		uint32_t align_dummy;
@@ -2534,6 +2536,23 @@
 	} else
 		cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
 	CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
+	if ((sc->rl_flags & 0x10000) != 0) {
+		reg = 0x000FFF00;
+		switch (CSR_READ_4(sc, RL_TXCFG) & 0xFC800000) {
+		case 0x18000000:	/* 8169/8110SCd */
+			reg |= 0x000000FF;
+			/* FALLTHROUGH */
+		case 0x98000000:	/* 8169/8110SCe */
+			if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) == 0)
+				reg |= 0x00900000;
+			CSR_WRITE_4(sc, 0x7C, reg);
+			break;
+		default:
+			break;
+		}
+		/* Disable interrupt mitigation. */
+		CSR_WRITE_2(sc, 0xE2, 0);
+	}
 	/*
 	 * Disable TSO if interface MTU size is greater than MSS
 	 * allowed in controller.