--- //depot/projects/smpng/sys/dev/ipmi/ipmi_pci.c	2006/10/11 18:45:33
+++ //depot/user/jhb/msi/dev/ipmi/ipmi_pci.c	2007/03/14 21:07:13
@@ -220,12 +220,9 @@
 		return (ENXIO);
 	}
 
-	/*
-	 * Bottom bit of bar indicates resouce type.  There should be
-	 * constants in pcireg.h for fields in a BAR.
-	 */
+	/* Check the BAR to determine our resource type. */
 	sc->ipmi_io_rid = PCIR_BAR(0);
-	if (pci_read_config(dev, PCIR_BAR(0), 4) & 0x1)
+	if (PCI_BAR_IO(pci_read_config(dev, PCIR_BAR(0), 4)))
 		type = SYS_RES_IOPORT;
 	else
 		type = SYS_RES_MEMORY;
--- //depot/projects/smpng/sys/dev/pci/pci.c	2007/03/30 00:40:24
+++ //depot/user/jhb/msi/dev/pci/pci.c	2007/03/31 20:47:56
@@ -72,7 +72,7 @@
 #endif
 
 static uint32_t		pci_mapbase(unsigned mapreg);
-static int		pci_maptype(unsigned mapreg);
+static const char	*pci_maptype(unsigned mapreg);
 static int		pci_mapsize(unsigned testval);
 static int		pci_maprange(unsigned mapreg);
 static void		pci_fixancient(pcicfgregs *cfg);
@@ -305,29 +305,24 @@
 static uint32_t
 pci_mapbase(uint32_t mapreg)
 {
-	int mask = 0x03;
-	if ((mapreg & 0x01) == 0)
-		mask = 0x0f;
-	return (mapreg & ~mask);
+
+	if (PCI_BAR_MEM(mapreg))
+		return (mapreg & PCIM_BAR_MEM_BASE);
+	else
+		return (mapreg & PCIM_BAR_IO_BASE);
 }
 
 /* return map type of memory or port map */
 
-static int
+static const char *
 pci_maptype(unsigned mapreg)
 {
-	static uint8_t maptype[0x10] = {
-		PCI_MAPMEM,		PCI_MAPPORT,
-		PCI_MAPMEM,		0,
-		PCI_MAPMEM,		PCI_MAPPORT,
-		0,			0,
-		PCI_MAPMEM|PCI_MAPMEMP,	PCI_MAPPORT,
-		PCI_MAPMEM|PCI_MAPMEMP, 0,
-		PCI_MAPMEM|PCI_MAPMEMP,	PCI_MAPPORT,
-		0,			0,
-	};
 
-	return (maptype[mapreg & 0x0f]);
+	if (PCI_BAR_IO(mapreg))
+		return ("I/O Port");
+	if (mapreg & PCIM_BAR_MEM_PREFETCH)
+		return ("Prefetchable Memory");
+	return ("Memory");
 }
 
 /* return log2 of map size decoded for memory or port map */
@@ -355,19 +350,21 @@
 pci_maprange(unsigned mapreg)
 {
 	int ln2range = 0;
-	switch (mapreg & 0x07) {
-	case 0x00:
-	case 0x01:
-	case 0x05:
+
+	if (PCI_BAR_IO(mapreg))
 		ln2range = 32;
-		break;
-	case 0x02:
-		ln2range = 20;
-		break;
-	case 0x04:
-		ln2range = 64;
-		break;
-	}
+	else
+		switch (mapreg & PCIM_BAR_MEM_TYPE) {
+		case PCIM_BAR_MEM_32:
+			ln2range = 32;
+			break;
+		case PCIM_BAR_MEM_1MB:
+			ln2range = 20;
+			break;
+		case PCIM_BAR_MEM_64:
+			ln2range = 64;
+			break;
+		}
 	return (ln2range);
 }
 
@@ -1972,7 +1975,7 @@
 	testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
 	PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
 
-	if (pci_maptype(map) & PCI_MAPMEM)
+	if (PCI_BAR_MEM(map))
 		type = SYS_RES_MEMORY;
 	else
 		type = SYS_RES_IOPORT;
@@ -1988,8 +1991,7 @@
 	 * areas to the type of memory involved.  Memory must be at least
 	 * 16 bytes in size, while I/O ranges must be at least 4.
 	 */
-	if ((testval & 0x1) == 0x1 &&
-	    (testval & 0x2) != 0)
+	if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
 		return (barlen);
 	if ((type == SYS_RES_MEMORY && ln2size < 4) ||
 	    (type == SYS_RES_IOPORT && ln2size < 2))
@@ -1999,7 +2001,7 @@
 		/* Read the other half of a 64bit map register */
 		base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
 	if (bootverbose) {
-		printf("\tmap[%02x]: type %x, range %2d, base %#jx, size %2d",
+		printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
 		    reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
 		if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
 			printf(", port disabled\n");
@@ -2920,7 +2922,7 @@
 		map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
 	if (pci_mapbase(testval) == 0)
 		goto out;
-	if (pci_maptype(testval) & PCI_MAPMEM) {
+	if (PCI_BAR_MEM(testval)) {
 		if (type != SYS_RES_MEMORY) {
 			if (bootverbose)
 				device_printf(dev,
--- //depot/projects/smpng/sys/dev/pci/pcireg.h	2007/03/07 19:17:11
+++ //depot/user/jhb/msi/dev/pci/pcireg.h	2007/03/31 20:47:56
@@ -118,6 +118,19 @@
 #define	PCIR_BARS	0x10
 #define	PCIR_BAR(x)	(PCIR_BARS + (x) * 4)
 #define	PCI_RID2BAR(rid) (((rid)-PCIR_BARS)/4)
+#define	PCI_BAR_IO(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
+#define	PCI_BAR_MEM(x)		(((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
+#define	PCIM_BAR_SPACE		0x00000001
+#define	PCIM_BAR_MEM_SPACE	0
+#define	PCIM_BAR_IO_SPACE	1
+#define	PCIM_BAR_MEM_TYPE	0x00000006
+#define	PCIM_BAR_MEM_32		0
+#define	PCIM_BAR_MEM_1MB	2	/* Locate below 1MB in PCI <= 2.1 */
+#define	PCIM_BAR_MEM_64		4
+#define	PCIM_BAR_MEM_PREFETCH	0x00000008
+#define	PCIM_BAR_MEM_BASE	0xfffffff0
+#define	PCIM_BAR_IO_RESERVED	0x00000002
+#define	PCIM_BAR_IO_BASE	0xfffffffc
 #define	PCIR_CIS	0x28
 #define	PCIM_CIS_ASI_MASK	0x7
 #define	PCIM_CIS_ASI_TUPLE	0