diff -I '$FreeBSD' -urp msk-patched/if_msk.c /sys/dev/msk/if_msk.c
--- msk-patched/if_msk.c	2009-05-22 11:25:34.000000000 -0400
+++ /sys/dev/msk/if_msk.c	2009-05-22 13:03:15.000000000 -0400
@@ -217,6 +217,8 @@ static struct msk_product {
 	    "Marvell Yukon 88E8056 Gigabit Ethernet" },
 	{ VENDORID_MARVELL, DEVICEID_MRVL_436A,
 	    "Marvell Yukon 88E8058 Gigabit Ethernet" },
+	{ VENDORID_MARVELL, DEVICEID_MRVL_8072,
+	    "Marvell Yukon 88E8072 Gigabit Ethernet" },
 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
 	    "D-Link 550SX Gigabit Ethernet" },
 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
@@ -226,7 +228,7 @@ static struct msk_product {
 static const char *model_name[] = {
 	"Yukon XL",
         "Yukon EC Ultra",
-        "Yukon Unknown",
+        "Yukon Extreme",
         "Yukon EC",
         "Yukon FE",
         "Yukon FE+"
@@ -1127,6 +1129,7 @@ msk_phy_power(struct msk_softc *sc, int 
 			}
 			break;
 		case CHIP_ID_YUKON_EC_U:
+		case CHIP_ID_YUKON_EX:
 		case CHIP_ID_YUKON_FE_P:
 			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
 
@@ -1250,6 +1253,12 @@ mskc_reset(struct msk_softc *sc)
 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
+
+		if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
+			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_CTRL),
+			    GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
+			    GMC_BYP_RETR_ON);
+		}
 	}
 	CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 
@@ -1649,6 +1658,7 @@ mskc_attach(device_t dev)
 		sc->msk_pflags |= MSK_FLAG_JUMBO;
 		break;
 	case CHIP_ID_YUKON_EC_U:
+	case CHIP_ID_YUKON_EX:
 		sc->msk_clock = 125;	/* 125 Mhz */
 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
 		break;
@@ -3550,6 +3560,38 @@ msk_init(void *xsc)
 }
 
 static void
+msk_set_tx_stfwd(struct msk_if_softc *sc_if)
+{
+	struct msk_softc *sc;
+	struct ifnet *ifp;
+
+	ifp = sc_if->msk_ifp;
+	sc = sc_if->msk_softc;
+	if (ifp->if_mtu > ETHERMTU) {
+		if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
+		    sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
+		    sc->msk_hw_id == CHIP_ID_YUKON_FE_P) {
+			/* Enable Store & Forward mode for Tx. */
+			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+			    TX_JUMBO_ENA | TX_STFW_ENA);
+		} else {
+			/*
+			 * Set Tx GMAC FIFO Almost Empty Threshold.
+			 */
+			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
+			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
+			/* Disable Store & Forward mode for Tx. */
+			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+			    TX_JUMBO_ENA | TX_STFW_DIS);
+		}
+	} else {
+		/* Enable Store & Forward mode for Tx. */
+		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+		    TX_JUMBO_DIS | TX_STFW_ENA);
+	}
+}
+
+static void
 msk_init_locked(struct msk_if_softc *sc_if)
 {
 	struct msk_softc *sc;
@@ -3637,7 +3679,8 @@ msk_init_locked(struct msk_if_softc *sc_
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
 	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
-	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P)
+	if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
+	    sc->msk_hw_id == CHIP_ID_YUKON_FE_P)
 		reg |= GMF_RX_OVER_ON;
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
 
@@ -3673,20 +3716,9 @@ msk_init_locked(struct msk_if_softc *sc_
 		    MSK_ECU_LLPP);
 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
 		    MSK_ECU_ULPP);
-		if (ifp->if_mtu > ETHERMTU) {
-			/*
-			 * Set Tx GMAC FIFO Almost Empty Threshold.
-			 */
-			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
-			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
-			/* Disable Store & Forward mode for Tx. */
-			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
-			    TX_JUMBO_ENA | TX_STFW_DIS);
-		} else {
-			/* Enable Store & Forward mode for Tx. */
-			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
-			    TX_JUMBO_DIS | TX_STFW_ENA);
-		}
+
+		/* Configure store-and-forward for Tx. */
+		msk_set_tx_stfwd(sc_if);
 	}
 
  	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
@@ -3717,6 +3749,12 @@ msk_init_locked(struct msk_if_softc *sc_
 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
+	if (sc->msk_hw_id == CHIP_ID_YUKON_EX &&
+	    sc->msk_hw_rev == CHIP_REV_YU_EX_B0) {
+		/* XXX: Copied from Linux driver. */
+		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
+		    F_TX_CHK_AUTO_OFF);
+	}
 	if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
 	    sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
 		/* Fix for Yukon-EC Ultra: set BMU FIFO level */
Only in /sys/dev/msk: if_msk.c.orig
diff -I '$FreeBSD' -urp msk-patched/if_mskreg.h /sys/dev/msk/if_mskreg.h
--- msk-patched/if_mskreg.h	2009-05-22 11:25:34.000000000 -0400
+++ /sys/dev/msk/if_mskreg.h	2009-05-22 12:39:06.000000000 -0400
@@ -141,6 +141,7 @@
 #define DEVICEID_MRVL_4364	0x4364
 #define DEVICEID_MRVL_8070	0x4365
 #define DEVICEID_MRVL_436A	0x436A
+#define	DEVICEID_MRVL_8072	0x436C
 
 /*
  * D-Link gigabit ethernet device ID
@@ -830,6 +831,7 @@
 #define CHIP_ID_YUKON_LP	0xb2 /* Chip ID for YUKON-LP */
 #define CHIP_ID_YUKON_XL	0xb3 /* Chip ID for YUKON-2 XL */
 #define CHIP_ID_YUKON_EC_U	0xb4 /* Chip ID for YUKON-2 EC Ultra */
+#define	CHIP_ID_YUKON_EX	0xb5 /* Chip ID for YUKON-2 Extreme */
 #define CHIP_ID_YUKON_EC	0xb6 /* Chip ID for YUKON-2 EC */
 #define CHIP_ID_YUKON_FE	0xb7 /* Chip ID for YUKON-2 FE */
 #define CHIP_ID_YUKON_FE_P	0xb8 /* Chip ID for YUKON-2 FE+ */
@@ -848,6 +850,9 @@
 
 #define	CHIP_REV_YU_FE_P_A0	0 /* Chip Rev. for Yukon-2 FE+ A0 */
 
+#define	CHIP_REV_YU_EX_A0	1
+#define	CHIP_REV_YU_EX_B0	2
+
 /*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
 #define Y2_STATUS_LNK2_INAC	BIT_7	/* Status Link 2 inactiv (0 = activ) */
 #define Y2_CLK_GAT_LNK2_DIS	BIT_6	/* Disable clock gating Link 2 */
@@ -1033,6 +1038,8 @@
 					/* Bit 10..0: same as for Rx */
 
 /*	Q_F		32 bit	Flag Register */
+#define	F_TX_CHK_AUTO_OFF	BIT_31	/* Tx checksum auto calc off (EX) */
+#define	F_TX_CHK_AUTO_ON	BIT_30	/* Tx checksum auto calc on (EX) */
 #define F_ALM_FULL	BIT_27	/* Rx FIFO: almost full */
 #define F_EMPTY		BIT_27	/* Tx FIFO: empty flag */
 #define F_FIFO_EOF	BIT_26	/* Tag (EOF Flag) bit in FIFO */
@@ -1940,6 +1947,12 @@
 #define SC_STAT_RST_SET	BIT_0	/* Set   Status Unit Reset */
 
 /*	GMAC_CTRL	32 bit	GMAC Control Reg (YUKON only) */
+#define	GMC_BYP_MACSECRX_ON	BIT_13	/* Bypass macsec RX On */
+#define	GMC_BYP_MACSECRX_OFF	BIT_12	/* Bypass macsec RX Off */
+#define	GMC_BYP_MACSECTX_ON	BIT_11	/* Bypass macsec TX On */
+#define	GMC_BYP_MACSECTX_OFF	BIT_10	/* Bypass macsec TX Off */
+#define	GMC_BYP_RETR_ON		BIT_9	/* Bypass retransmit FIFO On */
+#define	GMC_BYP_RETR_OFF	BIT_8	/* Bypass retransmit FIFO Off */
 #define GMC_H_BURST_ON	BIT_7	/* Half Duplex Burst Mode On */
 #define GMC_H_BURST_OFF	BIT_6	/* Half Duplex Burst Mode Off */
 #define GMC_F_LOOPB_ON	BIT_5	/* FIFO Loopback On */
Only in /sys/dev/msk: if_mskreg.h.orig