--- //depot/projects/smpng/sys/dev/pci/pci.c	2006/11/13 22:08:01
+++ //depot/user/jhb/msi/dev/pci/pci.c	2006/11/13 22:15:34
@@ -52,6 +52,10 @@
 #include <sys/rman.h>
 #include <machine/resource.h>
 
+#if defined(__i386__) || defined(__amd64__)
+#include <machine/intr_machdep.h>
+#endif
+
 #include <sys/pciio.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
@@ -442,6 +446,10 @@
 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
 {
 #define REG(n, w)	PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
+#define WREG(n, v, w)	PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
+#if defined(__i386__) || defined(__amd64__)
+	uint64_t addr;
+#endif
 	uint32_t val;
 	int	ptr, nextptr, ptrptr;
 
@@ -482,6 +490,35 @@
 					cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
 			}
 			break;
+#if defined(__i386__) || defined(__amd64__)
+		case PCIY_HT:		/* HyperTransport */
+			/* Determine HT-specific capability type. */
+			val = REG(ptr + PCIR_HT_COMMAND, 2);
+			switch (val & PCIM_HTCMD_CAP_MASK) {
+			case PCIM_HTCAP_MSI_MAPPING:
+				/* Sanity check the mapping window. */
+				addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
+				addr <<= 32;
+				addr = REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
+				if (addr != MSI_INTEL_ADDR_BASE)
+					device_printf(pcib,
+		    "HT Bridge at %d:%d:%d has non-default MSI window 0x%llx\n",
+					    cfg->bus, cfg->slot, cfg->func,
+					    (long long)addr);
+
+				/* DBG */
+				device_printf(pcib,
+			    "Enabling HT MSI window for %d:%d:%d at 0x%llx\n",
+				    cfg->bus, cfg->slot, cfg->func,
+				    (long long)addr);
+
+				/* Enable MSI -> HT mapping. */
+				val |= PCIM_HTCMD_MSI_ENABLE;
+				WREG(ptr + PCIR_HT_COMMAND, val, 2);
+				break;
+			}
+			break;
+#endif
 		case PCIY_MSI:		/* PCI MSI */
 			cfg->msi.msi_location = ptr;
 			cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
@@ -510,7 +547,7 @@
 			break;
 		}
 	}
-/* REG use carry through to next functions */
+/* REG and WREG use carry through to next functions */
 }
 
 /*
@@ -519,7 +556,6 @@
 static uint32_t
 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg)
 {
-#define WREG(n, v, w)	PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
 
 	KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
 
@@ -544,7 +580,6 @@
 	return;
 }
 #endif
-#undef WREG
 
 struct vpd_readstate {
 	device_t	pcib;
@@ -807,6 +842,7 @@
 		cfg->vpd.vpd_ros = NULL;
 	}
 #undef REG
+#undef WREG
 }
 
 int
--- //depot/projects/smpng/sys/dev/pci/pcireg.h	2006/11/13 22:08:01
+++ //depot/user/jhb/msi/dev/pci/pcireg.h	2006/11/13 22:15:34
@@ -431,6 +431,27 @@
 #define PCIXM_STATUS_MAXCRDS	0x1C00	/* Maximum Cumulative Read Size */
 #define PCIXM_STATUS_RCVDSCEM	0x2000	/* Received a Split Comp w/Error msg */
 
+/* HT (HyperTransport) Capability definitions */
+#define	PCIR_HT_COMMAND		0x2
+#define	PCIM_HTCMD_CAP_MASK		0xf800	/* Capability type. */
+#define	PCIM_HTCAP_SLAVE		0x0000	/* 000xx */
+#define	PCIM_HTCAP_HOST			0x2000	/* 001xx */
+#define	PCIM_HTCAP_SWITCH		0x4000	/* 01000 */
+#define	PCIM_HTCAP_INTERRUPT		0x8000	/* 10000 */
+#define	PCIM_HTCAP_REVISION_ID		0x8800	/* 10001 */
+#define	PCIM_HTCAP_UNITID_CLUMPING	0x9000	/* 10010 */
+#define	PCIM_HTCAP_EXT_CONFIG_SPACE	0x9800	/* 10011 */
+#define	PCIM_HTCAP_ADDRESS_MAPPING	0xa000	/* 10100 */
+#define	PCIM_HTCAP_MSI_MAPPING		0xa800	/* 10101 */
+#define	PCIM_HTCAP_DIRECT_ROUTE		0xb000	/* 10110 */
+#define	PCIM_HTCAP_VCSET		0xb800	/* 10111 */
+#define	PCIM_HTCAP_RETRY_MODE		0xc000	/* 11000 */
+
+/* HT MSI Mapping Capability definitions. */
+#define	PCIM_HTCMD_MSI_ENABLE		0x0001
+#define	PCIR_HTMSI_ADDRESS_LO	0x4
+#define	PCIR_HTMSI_ADDRESS_HI	0x8
+
 /* MSI-X definitions */
 #define	PCIR_MSIX_CTRL		0x2
 #define	PCIM_MSIXCTRL_MSIX_ENABLE	0x8000