Index: amd64/amd64/pmap.c
===================================================================
--- amd64/amd64/pmap.c	(revision 210860)
+++ amd64/amd64/pmap.c	(working copy)
@@ -1125,6 +1125,14 @@
 		 eva - sva < 2 * 1024 * 1024) {
 
 		/*
+		 * XXX: Some CPUs fault if we use CLFLUSH on the local
+		 * APIC range.  The local APIC is always uncached, so
+		 * we don't need to flush for that range anyway.
+		 */
+		if (pmap_kextract(sva) == lapic_paddr)
+			return;
+
+		/*
 		 * Otherwise, do per-cache line flush.  Use the mfence
 		 * instruction to insure that previous stores are
 		 * included in the write-back.  The processor
Index: i386/i386/pmap.c
===================================================================
--- i386/i386/pmap.c	(revision 210860)
+++ i386/i386/pmap.c	(working copy)
@@ -103,6 +103,7 @@
  *	and to when physical maps must be made correct.
  */
 
+#include "opt_apic.h"
 #include "opt_cpu.h"
 #include "opt_pmap.h"
 #include "opt_msgbuf.h"
@@ -1173,7 +1174,16 @@
 	else if ((cpu_feature & CPUID_CLFSH) != 0 &&
 		 eva - sva < 2 * 1024 * 1024) {
 
+#ifdef DEV_APIC
 		/*
+		 * XXX: Some CPUs fault if we use CLFLUSH on the local
+		 * APIC range.  The local APIC is always uncached, so
+		 * we don't need to flush for that range anyway.
+		 */
+		if (pmap_kextract(sva) == lapic_paddr)
+			return;
+#endif
+		/*
 		 * Otherwise, do per-cache line flush.  Use the mfence
 		 * instruction to insure that previous stores are
 		 * included in the write-back.  The processor
Index: x86/x86/local_apic.c
===================================================================
--- x86/x86/local_apic.c	(revision 210860)
+++ x86/x86/local_apic.c	(working copy)
@@ -223,8 +223,8 @@
 	/* Map the local APIC and setup the spurious interrupt handler. */
 	KASSERT(trunc_page(addr) == addr,
 	    ("local APIC not aligned on a page boundary"));
+	lapic_paddr = addr;
 	lapic = pmap_mapdev(addr, sizeof(lapic_t));
-	lapic_paddr = addr;
 	setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL,
 	    GSEL_APIC);