--- //depot/user/jake/sparc64/src/sys/sparc64/include/tlb.h	2002/05/28 23:36:57
+++ //depot/user/jake/sparc64/src/sys/sparc64/include/tlb.h	2002/06/07 22:40:48
@@ -85,9 +85,13 @@
 extern int kernel_tlb_slots;
 extern struct tlb_entry *kernel_tlbs;
 
+extern int tlb_slot_count;
+
 void	tlb_context_demap(struct pmap *pm);
 void	tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va);
 void	tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end);
+void	tlb_flush(vm_offset_t start, vm_offset_t end);
+void	tlb_dump(void);
 
 #define	tlb_tte_demap(tp, pm) \
 	tlb_page_demap(TTE_GET_TLB(tp), pm, TTE_GET_VA(tp))
--- //depot/user/jake/sparc64/src/sys/sparc64/include/vmparam.h	2002/05/24 16:45:00
+++ //depot/user/jake/sparc64/src/sys/sparc64/include/vmparam.h	2002/06/07 21:25:38
@@ -159,6 +159,9 @@
 #define	VM_MAX_KERNEL_ADDRESS	(VM_MIN_KERNEL_ADDRESS + KVA_RANGE - PAGE_SIZE)
 #define	KERNBASE		(VM_MIN_KERNEL_ADDRESS)
 
+#define	VM_MIN_PROM_ADDRESS	(0xf0000000)
+#define	VM_MAX_PROM_ADDRESS	(0xffffe000)
+
 /*
  * Initial pagein size of beginning of executable file.
  */
--- //depot/user/jake/sparc64/src/sys/sparc64/sparc64/exception.s	2002/05/24 20:09:50
+++ //depot/user/jake/sparc64/src/sys/sparc64/sparc64/exception.s	2002/06/07 21:25:38
@@ -1817,6 +1817,7 @@
 	.sect	.trap
 	.align	0x8000
 	.globl	tl0_base
+	.globl	tl1_base
 
 tl0_base:
 	tl0_reserved	8				! 0x0-0x7
--- //depot/user/jake/sparc64/src/sys/sparc64/sparc64/machdep.c	2002/06/06 11:53:55
+++ //depot/user/jake/sparc64/src/sys/sparc64/sparc64/machdep.c	2002/06/07 22:40:48
@@ -158,6 +158,8 @@
 	if (child == 0)
 		panic("cpu_startup: no cpu\n");
 	OF_getprop(child, "clock-frequency", &clock, sizeof(clock));
+	OF_getprop(child, "#dtlb-entries", &tlb_slot_count,
+	    sizeof(tlb_slot_count));
 
 	tick_tc.tc_get_timecount = tick_get_timecount;
 	tick_tc.tc_poll_pps = NULL;
--- //depot/user/jake/sparc64/src/sys/sparc64/sparc64/mp_machdep.c	2002/06/06 11:59:12
+++ //depot/user/jake/sparc64/src/sys/sparc64/sparc64/mp_machdep.c	2002/06/07 22:40:48
@@ -332,6 +332,25 @@
 cpu_mp_bootstrap(struct pcpu *pc)
 {
 	volatile struct cpu_start_args *csa;
+	u_long tag;
+	int i;
+
+	/*
+	 * When secondary cpus start up they often have junk in their tlb.
+	 * Sometimes both the lock bit and the valid bit will be set in the
+	 * tlb entries, which can cause our locked mappings to be replaced,
+	 * and other random behvaiour.  The tags always seems to be zero, so
+	 * we flush all mappings with a tag of zero, regardless of the lock
+	 * and/or valid bits.
+	 */
+	for (i = 0; i < tlb_slot_count; i++) {
+		tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
+		if (tag == 0)
+			stxa_sync(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG, 0);
+		tag = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
+		if (tag == 0)
+			stxa_sync(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG, 0);
+	}
 
 	csa = &cpu_start_args;
 	pmap_map_tsb();
--- //depot/user/jake/sparc64/src/sys/sparc64/sparc64/pmap.c	2002/05/28 23:36:57
+++ //depot/user/jake/sparc64/src/sys/sparc64/sparc64/pmap.c	2002/06/07 22:40:48
@@ -359,7 +359,8 @@
 		    "translation: start=%#lx size=%#lx tte=%#lx",
 		    translations[i].om_start, translations[i].om_size,
 		    translations[i].om_tte);
-		if (translations[i].om_start < 0xf0000000)	/* XXX!!! */
+		if (translations[i].om_start < VM_MIN_PROM_ADDRESS ||
+		    translations[i].om_start > VM_MAX_PROM_ADDRESS)
 			continue;
 		for (off = 0; off < translations[i].om_size;
 		    off += PAGE_SIZE) {
@@ -418,8 +419,7 @@
 		    TD_P | TD_W;
 		stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) |
 		    TLB_TAR_CTX(TLB_CTX_KERNEL));
-		stxa(0, ASI_DTLB_DATA_IN_REG, data);
-		membar(Sync);
+		stxa_sync(0, ASI_DTLB_DATA_IN_REG, data);
 	}
 
 	/*
@@ -471,7 +471,7 @@
 
 	mtx_assert(&sched_lock, MA_OWNED);
 	CTR0(KTR_PMAP, "pmap_context_rollover");
-	for (i = 0; i < 64; i++) {
+	for (i = 0; i < tlb_slot_count; i++) {
 		/* XXX - cheetah */
 		data = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG);
 		tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
--- //depot/user/jake/sparc64/src/sys/sparc64/sparc64/tlb.c	2002/05/24 16:45:00
+++ //depot/user/jake/sparc64/src/sys/sparc64/sparc64/tlb.c	2002/06/07 22:40:48
@@ -28,6 +28,7 @@
 
 #include <sys/param.h>
 #include <sys/systm.h>
+#include <sys/ktr.h>
 #include <sys/pcpu.h>
 #include <sys/smp.h>
 
@@ -38,6 +39,8 @@
 #include <machine/smp.h>
 #include <machine/tlb.h>
 
+int tlb_slot_count;
+
 /*
  * Some tlb operations must be atomic, so no interrupt or trap can be allowed
  * while they are in progress. Traps should not happen, but interrupts need to
@@ -138,3 +141,26 @@
 	ipi_wait(cookie);
 	critical_exit();
 }
+
+void
+tlb_dump(void)
+{
+	u_long data;
+	u_long tag;
+	int slot;
+
+	for (slot = 0; slot < tlb_slot_count; slot++) {
+		data = ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG);
+		if ((data & TD_V) != 0) {
+			tag = ldxa(TLB_DAR_SLOT(slot), ASI_DTLB_TAG_READ_REG);
+			TR3("pmap_dump_tlb: dltb slot=%d data=%#lx tag=%#lx",
+			    slot, data, tag);
+		}
+		data = ldxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG);
+		if ((data & TD_V) != 0) {
+			tag = ldxa(TLB_DAR_SLOT(slot), ASI_ITLB_TAG_READ_REG);
+			TR3("pmap_dump_tlb: iltb slot=%d data=%#lx tag=%#lx",
+			    slot, data, tag);
+		}
+	}
+}
--- //depot/user/jake/sparc64/src/sys/sparc64/sparc64/trap.c	2002/06/04 10:15:15
+++ //depot/user/jake/sparc64/src/sys/sparc64/sparc64/trap.c	2002/06/07 22:40:48
@@ -45,6 +45,7 @@
 #include "opt_ktrace.h"
 
 #include <sys/param.h>
+#include <sys/kernel.h>
 #include <sys/bus.h>
 #include <sys/interrupt.h>
 #include <sys/ktr.h>
@@ -55,6 +56,7 @@
 #include <sys/proc.h>
 #include <sys/smp.h>
 #include <sys/syscall.h>
+#include <sys/sysctl.h>
 #include <sys/sysent.h>
 #include <sys/user.h>
 #include <sys/vmmeter.h>
@@ -148,6 +150,8 @@
 };
 
 int debugger_on_signal = 1;
+SYSCTL_INT(_debug, OID_AUTO, debugger_on_signal, CTLFLAG_RW,
+    &debugger_on_signal, 0, "");
 
 void
 trap(struct trapframe *tf)