Index: boot/fdt/dts/pandaboard.dts =================================================================== --- boot/fdt/dts/pandaboard.dts (revision 243980) +++ boot/fdt/dts/pandaboard.dts (working copy) @@ -67,6 +67,8 @@ pl310@48242000 { compatible = "arm,pl310"; reg = < 0x48242000 0x1000 >; + interrupts = < 32 >; + interrupt-parent = < &GIC >; }; mp_tmr@48240200 { compatible = "arm,mpcore-timers"; Index: arm/arm/pl310.c =================================================================== --- arm/arm/pl310.c (revision 243980) +++ arm/arm/pl310.c (working copy) @@ -49,6 +49,8 @@ #include #include +int disabled = 0; + /** * PL310 - L2 Cache Controller register offsets. * @@ -96,9 +98,11 @@ #define PL310_AUX_CTRL_EARLY_BRESP_SHIFT 30 +#if 0 void omap4_l2cache_wbinv_range(vm_paddr_t physaddr, vm_size_t size); void omap4_l2cache_inv_range(vm_paddr_t physaddr, vm_size_t size); void omap4_l2cache_wb_range(vm_paddr_t physaddr, vm_size_t size); +#endif void omap4_l2cache_wbinv_all(void); void omap4_l2cache_inv_all(void); void omap4_l2cache_wb_all(void); @@ -112,6 +116,8 @@ static struct pl310_softc *pl310_softc; + + /** * pl310_read4 - read a 32-bit value from the PL310 registers * pl310_write4 - write a 32-bit value from the PL310 registers @@ -136,6 +142,19 @@ bus_write_4(pl310_softc->sc_mem_res, off, val); } +static int +pl310_filter(void *arg) +{ + printf("INTR == %08x\n", + pl310_read4(PL310_RAW_INTR_STAT)); + printf("COUNTER0 == %d\n", + pl310_read4(PL310_EVENT_COUNTER0_VAL)); + printf("COUNTER1 == %d\n", + pl310_read4(PL310_EVENT_COUNTER1_VAL)); + panic("PL310"); + return (FILTER_HANDLED); +} + static __inline void pl310_wait_background_op(uint32_t off, uint32_t mask) { @@ -157,7 +176,8 @@ static __inline void pl310_cache_sync(void) { - pl310_write4(PL310_CACHE_SYNC, 0); + pl310_write4(0x740, 0xffffffff); + // pl310_write4(PL310_CACHE_SYNC, 0xffffffff); } @@ -165,21 +185,25 @@ pl310_wbinv_all(void) { #if 1 - pl310_write4(PL310_DEBUG_CTRL, 3); + pl310_cache_sync(); + platform_pl310_set_debug(NULL, 3); + printf("PL310_DEBUG_CTRL == %08x\n", pl310_read4(PL310_DEBUG_CTRL)); #endif pl310_write4(PL310_CLEAN_INV_WAY, g_l2cache_way_mask); pl310_wait_background_op(PL310_CLEAN_INV_WAY, g_l2cache_way_mask); pl310_cache_sync(); #if 1 - pl310_write4(PL310_DEBUG_CTRL, 0); + // platform_pl310_set_debug(NULL, 0); + printf("PL310_DEBUG_CTRL == %08x\n", pl310_read4(PL310_DEBUG_CTRL)); #endif } +#if 0 static void pl310_wbinv_range(vm_paddr_t start, vm_size_t size) { - + uint32_t intr = intr_disable(); if (start & g_l2cache_align_mask) { size += start & g_l2cache_align_mask; start &= ~g_l2cache_align_mask; @@ -212,14 +236,15 @@ #if 1 pl310_write4(PL310_DEBUG_CTRL, 0); #endif - pl310_wait_background_op(PL310_CLEAN_INV_LINE_PA, 1); pl310_cache_sync(); + intr_restore(intr); } static void pl310_wb_range(vm_paddr_t start, vm_size_t size) { + uint32_t intr = intr_disable(); if (start & g_l2cache_align_mask) { size += start & g_l2cache_align_mask; @@ -235,13 +260,13 @@ size -= g_l2cache_line_size; } pl310_cache_sync(); - pl310_wait_background_op(PL310_CLEAN_LINE_PA, 1); - + intr_restore(intr); } static void pl310_inv_range(vm_paddr_t start, vm_size_t size) { + uint32_t intr = intr_disable(); if (start & g_l2cache_align_mask) { size += start & g_l2cache_align_mask; @@ -257,9 +282,9 @@ size -= g_l2cache_line_size; } pl310_cache_sync(); - pl310_wait_background_op(PL310_INV_LINE_PA, 1); - + intr_restore(intr); } +#endif static int pl310_probe(device_t dev) @@ -285,9 +310,22 @@ RF_ACTIVE); if (sc->sc_mem_res == NULL) panic("%s: Cannot map registers", device_get_name(dev)); + /* Allocate an IRQ resource */ + rid = 0; + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE | RF_SHAREABLE); + if (sc->sc_irq_res == NULL) { + panic("Cannot allocate IRQ\n"); + } + + /* activate the interrupt */ + bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + pl310_filter, NULL, sc, &sc->sc_irq_h); + + pl310_softc = sc; - platform_init_pl310(sc); + aux_value = pl310_read4(PL310_AUX_CTRL); way_size = (aux_value & PL310_AUX_CTRL_WAY_SIZE_MASK) >> PL310_AUX_CTRL_WAY_SIZE_SHIFT; @@ -306,13 +344,33 @@ /* Enable the L2 cache if disabled */ pl310_write4(PL310_CTRL, ctrl_value & 0x1); } + + pl310_write4(PL310_EVENT_COUNTER_CTRL, 1); + pl310_write4(PL310_EVENT_COUNTER0_CONF, 1 | (1 << 2)); + pl310_write4(PL310_EVENT_COUNTER1_CONF, 1 | (1 << 2)); + pl310_write4(PL310_INTR_MASK, ((1 << 9) -1)); + + uint32_t intr = intr_disable(); + pl310_cache_sync(); pl310_wbinv_all(); - + pl310_cache_sync(); + platform_init_pl310(sc); + intr_restore(intr); + + printf("PL310_CTRL: %d\n", pl310_read4(PL310_CTRL)); + + pl310_write4(PL310_EVENT_COUNTER_CTRL, 3 << 1); + pl310_write4(PL310_INTR_CLEAR, ((1 << 9) -1)); + printf("COUNTER0 == %d\n", + pl310_read4(PL310_EVENT_COUNTER0_VAL)); + printf("COUNTER1 == %d\n", + pl310_read4(PL310_EVENT_COUNTER1_VAL)); + /* Set the l2 functions in the set of cpufuncs */ - cpufuncs.cf_l2cache_wbinv_all = pl310_wbinv_all; - cpufuncs.cf_l2cache_wbinv_range = pl310_wbinv_range; - cpufuncs.cf_l2cache_inv_range = pl310_inv_range; - cpufuncs.cf_l2cache_wb_range = pl310_wb_range; + // cpufuncs.cf_l2cache_wbinv_all = pl310_wbinv_all; + // cpufuncs.cf_l2cache_wbinv_range = pl310_wbinv_range; + // cpufuncs.cf_l2cache_inv_range = pl310_inv_range; + // cpufuncs.cf_l2cache_wb_range = pl310_wb_range; return (0); } @@ -330,4 +388,3 @@ static devclass_t pl310_devclass; DRIVER_MODULE(pl310, simplebus, pl310_driver, pl310_devclass, 0, 0); - Index: arm/include/pl310.h =================================================================== --- arm/include/pl310.h (revision 243980) +++ arm/include/pl310.h (working copy) @@ -31,8 +31,11 @@ #define PL310_H_ struct pl310_softc { struct resource *sc_mem_res; + struct resource *sc_irq_res; + void* sc_irq_h; }; -void platform_init_pl310(struct pl310_softc *sc); +void platform_init_pl310(struct pl310_softc *); +void platform_pl310_set_debug(struct pl310_softc *, uint32_t); #endif /* PL310_H_ */ Index: arm/ti/omap4/omap4_l2cache.c =================================================================== --- arm/ti/omap4/omap4_l2cache.c (revision 243980) +++ arm/ti/omap4/omap4_l2cache.c (working copy) @@ -34,6 +34,11 @@ void platform_init_pl310(struct pl310_softc *softc) { - ti_smc0(1, 0, L2CACHE_ENABLE_L2); + ti_smc0(0, 0, L2CACHE_ENABLE_L2); } +void +platform_pl310_set_debug(struct pl310_softc *softc, uint32_t val) +{ + ti_smc0(val, 0, L2CACHE_WRITE_DEBUG_REG); +}