diff --git a/sys/arm/allwinner/a64/sun50i_a64_acodec.c b/sys/arm/allwinner/a64/sun50i_a64_acodec.c new file mode 100644 index 00000000000..6612a90e3a4 --- /dev/null +++ b/sys/arm/allwinner/a64/sun50i_a64_acodec.c @@ -0,0 +1,494 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * Copyright (c) 2018 Jared McNeill + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include "syscon_if.h" + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" +#include "mixer_if.h" + +#define A64_PR_CFG 0x00 +#define A64_AC_PR_RST (1 << 28) +#define A64_AC_PR_RW (1 << 24) +#define A64_AC_PR_ADDR_MASK (0x1f << 16) +#define A64_AC_PR_ADDR(n) (((n) & 0x1f) << 16) +#define A64_ACDA_PR_WDAT_MASK (0xff << 8) +#define A64_ACDA_PR_WDAT(n) (((n) & 0xff) << 8) +#define A64_ACDA_PR_RDAT(n) ((n) & 0xff) + +#define A64_HP_CTRL 0x00 +#define A64_HPPA_EN (1 << 6) +#define A64_HPVOL_MASK 0x3f +#define A64_HPVOL(n) ((n) & 0x3f) +#define A64_OL_MIX_CTRL 0x01 +#define A64_LMIXMUTE_LDAC (1 << 1) +#define A64_OR_MIX_CTRL 0x02 +#define A64_RMIXMUTE_RDAC (1 << 1) +#define A64_LINEOUT_CTRL0 0x05 +#define A64_LINEOUT_LEFT_EN (1 << 7) +#define A64_LINEOUT_RIGHT_EN (1 << 6) +#define A64_LINEOUT_EN (A64_LINEOUT_LEFT_EN|A64_LINEOUT_RIGHT_EN) +#define A64_LINEOUT_CTRL1 0x06 +#define A64_LINEOUT_VOL __BITS(4,0) +#define A64_MIC1_CTRL 0x07 +#define A64_MIC1G __BITS(6,4) +#define A64_MIC1AMPEN (1 << 3) +#define A64_MIC1BOOST __BITS(2,0) +#define A64_MIC2_CTRL 0x08 +#define A64_MIC2_SEL (1 << 7) +#define A64_MIC2G_MASK (7 << 4) +#define A64_MIC2G(n) (((n) & 7) << 4) +#define A64_MIC2AMPEN (1 << 3) +#define A64_MIC2BOOST_MASK (7 << 0) +#define A64_MIC2BOOST(n) (((n) & 7) << 0) +#define A64_LINEIN_CTRL 0x09 +#define A64_LINEING __BITS(6,4) +#define A64_MIX_DAC_CTRL 0x0a +#define A64_DACAREN (1 << 7) +#define A64_DACALEN (1 << 6) +#define A64_RMIXEN (1 << 5) +#define A64_LMIXEN (1 << 4) +#define A64_RHPPAMUTE (1 << 3) +#define A64_LHPPAMUTE (1 << 2) +#define A64_RHPIS (1 << 1) +#define A64_LHPIS (1 << 0) +#define A64_L_ADCMIX_SRC 0x0b +#define A64_R_ADCMIX_SRC 0x0c +#define A64_ADCMIX_SRC_MIC1 (1 << 6) +#define A64_ADCMIX_SRC_MIC2 (1 << 5) +#define A64_ADCMIX_SRC_LINEIN (1 << 2) +#define A64_ADCMIX_SRC_OMIXER (1 << 1) +#define A64_ADC_CTRL 0x0d +#define A64_ADCREN (1 << 7) +#define A64_ADCLEN (1 << 6) +#define A64_ADCG __BITS(2,0) +#define A64_JACK_MIC_CTRL 0x1d +#define A64_JACKDETEN (1 << 7) +#define A64_INNERRESEN (1 << 6) +#define A64_HMICBIASEN (1 << 5) +#define A64_AUTOPLEN (1 << 1) + +#define A64CODEC_MIXER_DEVS ((1 << SOUND_MIXER_VOLUME) | \ + (1 << SOUND_MIXER_MIC)) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun50i-a64-codec-analog", 1}, + { NULL, 0 } +}; + +struct a64codec_softc { + device_t dev; + struct resource *res; + struct mtx mtx; + u_int regaddr; /* address for the sysctl */ +}; + +#define A64CODEC_LOCK(sc) mtx_lock(&(sc)->mtx) +#define A64CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define A64CODEC_READ(sc, reg) bus_read_4((sc)->res, (reg)) +#define A64CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) + +static int a64codec_probe(device_t dev); +static int a64codec_attach(device_t dev); +static int a64codec_detach(device_t dev); + +static u_int +a64_acodec_pr_read(struct a64codec_softc *sc, u_int addr) +{ + uint32_t val; + + /* Read current value */ + val = A64CODEC_READ(sc, A64_PR_CFG); + + /* De-assert reset */ + val |= A64_AC_PR_RST; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Read mode */ + val &= ~A64_AC_PR_RW; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Set address */ + val &= ~A64_AC_PR_ADDR_MASK; + val |= A64_AC_PR_ADDR(addr); + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Read data */ + val = A64CODEC_READ(sc, A64_PR_CFG); + return A64_ACDA_PR_RDAT(val); +} + +static void +a64_acodec_pr_write(struct a64codec_softc *sc, u_int addr, u_int data) +{ + uint32_t val; + + /* Read current value */ + val = A64CODEC_READ(sc, A64_PR_CFG); + + /* De-assert reset */ + val |= A64_AC_PR_RST; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Set address */ + val &= ~A64_AC_PR_ADDR_MASK; + val |= A64_AC_PR_ADDR(addr); + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Write data */ + val &= ~A64_ACDA_PR_WDAT_MASK; + val |= A64_ACDA_PR_WDAT(data); + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Write mode */ + val |= A64_AC_PR_RW; + A64CODEC_WRITE(sc, A64_PR_CFG, val); + + /* Clear write mode */ + val &= ~A64_AC_PR_RW; + A64CODEC_WRITE(sc, A64_PR_CFG, val); +} + +static void +a64_acodec_pr_set_clear(struct a64codec_softc *sc, u_int addr, u_int set, u_int clr) +{ + u_int old, new; + + old = a64_acodec_pr_read(sc, addr); + new = set | (old & ~clr); + a64_acodec_pr_write(sc, addr, new); +} + +static int +a64codec_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Allwinner A64 Analog Codec"); + return (BUS_PROBE_DEFAULT); +} + +static int +a64codec_attach(device_t dev) +{ + struct a64codec_softc *sc; + int error, rid; + phandle_t node; + regulator_t reg; + + sc = device_get_softc(dev); + sc->dev = dev; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + rid = 0; + sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (!sc->res) { + device_printf(dev, "cannot allocate resource for device\n"); + error = ENXIO; + goto fail; + } + + if (regulator_get_by_ofw_property(dev, 0, "cpvdd-supply", ®) == 0) { + error = regulator_enable(reg); + if (error != 0) { + device_printf(dev, "cannot enable PHY regulator\n"); + goto fail; + } + } + + /* Right & Left Headphone PA enable */ + a64_acodec_pr_set_clear(sc, A64_HP_CTRL, + A64_HPPA_EN, 0); + +#if 0 + /* Jack detect enable */ + a64_acodec_pr_set_clear(sc, A64_JACK_MIC_CTRL, + A64_JACKDETEN | A64_INNERRESEN | A64_AUTOPLEN, 0); +#endif + + /* Microphone BIAS enable */ + a64_acodec_pr_set_clear(sc, A64_JACK_MIC_CTRL, + A64_HMICBIASEN | A64_INNERRESEN, 0); + + /* Unmute DAC to output mixer */ + a64_acodec_pr_set_clear(sc, A64_OL_MIX_CTRL, + A64_LMIXMUTE_LDAC, 0); + a64_acodec_pr_set_clear(sc, A64_OR_MIX_CTRL, + A64_RMIXMUTE_RDAC, 0); + + /* For now we work only with headphones */ + a64_acodec_pr_set_clear(sc, A64_LINEOUT_CTRL0, + 0, A64_LINEOUT_EN); + a64_acodec_pr_set_clear(sc, A64_HP_CTRL, + A64_HPPA_EN, 0); + + u_int val = a64_acodec_pr_read(sc, A64_HP_CTRL); + val &= ~(0x3f); + val |= 0x25; + a64_acodec_pr_write(sc, A64_HP_CTRL, val); + + a64_acodec_pr_set_clear(sc, A64_MIC2_CTRL, + A64_MIC2AMPEN | A64_MIC2_SEL | A64_MIC2G(0x3) | A64_MIC2BOOST(0x4), + A64_MIC2G_MASK | A64_MIC2BOOST_MASK); + + a64_acodec_pr_write(sc, A64_L_ADCMIX_SRC, + A64_ADCMIX_SRC_MIC2); + a64_acodec_pr_write(sc, A64_R_ADCMIX_SRC, + A64_ADCMIX_SRC_MIC2); + + /* Max out MIC2 gain */ + val = a64_acodec_pr_read(sc, A64_MIC2_CTRL); + val &= ~(0x7); + val |= (0x7); + val &= ~(7 << 4); + val |= (7 << 4); + a64_acodec_pr_write(sc, A64_MIC2_CTRL, val); + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + a64codec_detach(dev); + return (error); +} + +static int +a64codec_detach(device_t dev) +{ + struct a64codec_softc *sc; + + sc = device_get_softc(dev); + + if (sc->res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); + mtx_destroy(&sc->mtx); + + return (0); +} + +static int +a64codec_mixer_init(struct snd_mixer *m) +{ + + mix_setdevs(m, A64CODEC_MIXER_DEVS); + + return (0); +} + +static int +a64codec_mixer_uninit(struct snd_mixer *m) +{ + + return (0); +} + +static int +a64codec_mixer_reinit(struct snd_mixer *m) +{ + + return (0); +} + +static int +a64codec_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) +{ + struct a64codec_softc *sc; + struct mtx *mixer_lock; + uint8_t do_unlock; + u_int val; + + sc = device_get_softc(mix_getdevinfo(m)); + mixer_lock = mixer_get_lock(m); + + if (mtx_owned(mixer_lock)) { + do_unlock = 0; + } else { + do_unlock = 1; + mtx_lock(mixer_lock); + } + + right = left; + + A64CODEC_LOCK(sc); + switch(dev) { + case SOUND_MIXER_VOLUME: + val = a64_acodec_pr_read(sc, A64_HP_CTRL); + val &= ~(A64_HPVOL_MASK); + val |= A64_HPVOL(left * 63 / 100); + a64_acodec_pr_write(sc, A64_HP_CTRL, val); + break; + + case SOUND_MIXER_MIC: + val = a64_acodec_pr_read(sc, A64_MIC2_CTRL); + val &= ~(A64_MIC2BOOST_MASK); + val |= A64_MIC2BOOST(left * 7 / 100); + a64_acodec_pr_write(sc, A64_MIC2_CTRL, val); + break; + default: + break; + } + A64CODEC_UNLOCK(sc); + + if (do_unlock) { + mtx_unlock(mixer_lock); + } + + return (left | (right << 8)); +} + +static unsigned +a64codec_mixer_setrecsrc(struct snd_mixer *m, unsigned src) +{ + + return (0); +} + +static kobj_method_t a64codec_mixer_methods[] = { + KOBJMETHOD(mixer_init, a64codec_mixer_init), + KOBJMETHOD(mixer_uninit, a64codec_mixer_uninit), + KOBJMETHOD(mixer_reinit, a64codec_mixer_reinit), + KOBJMETHOD(mixer_set, a64codec_mixer_set), + KOBJMETHOD(mixer_setrecsrc, a64codec_mixer_setrecsrc), + KOBJMETHOD_END +}; + +MIXER_DECLARE(a64codec_mixer); + +static int +a64codec_dai_init(device_t dev, uint32_t format) +{ + + return (0); +} + +static int +a64codec_dai_trigger(device_t dev, int go, int pcm_dir) +{ + struct a64codec_softc *sc = device_get_softc(dev); + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + switch (go) { + case PCMTRIG_START: + if (pcm_dir == PCMDIR_PLAY) { + /* Enable DAC analog l/r channels, HP PA, and output mixer */ + a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL, + A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN | + A64_RHPPAMUTE | A64_LHPPAMUTE, 0); + } + else if (pcm_dir == PCMDIR_REC) { + /* Enable ADC analog l/r channels */ + a64_acodec_pr_set_clear(sc, A64_ADC_CTRL, + A64_ADCREN | A64_ADCLEN, 0); + } + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + if (pcm_dir == PCMDIR_PLAY) { + /* Disable DAC analog l/r channels, HP PA, and output mixer */ + a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL, + 0, A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN | + A64_RHPPAMUTE | A64_LHPPAMUTE); + } + else if (pcm_dir == PCMDIR_REC) { + /* Disable ADC analog l/r channels */ + a64_acodec_pr_set_clear(sc, A64_ADC_CTRL, + 0, A64_ADCREN | A64_ADCLEN); + } + break; + } + + return (0); +} + +static int +a64codec_dai_setup_mixer(device_t dev, device_t pcmdev) +{ + + mixer_init(pcmdev, &a64codec_mixer_class, dev); + + return (0); +} + +static device_method_t a64codec_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, a64codec_probe), + DEVMETHOD(device_attach, a64codec_attach), + DEVMETHOD(device_detach, a64codec_detach), + + DEVMETHOD(audio_dai_init, a64codec_dai_init), + DEVMETHOD(audio_dai_setup_mixer, a64codec_dai_setup_mixer), + DEVMETHOD(audio_dai_trigger, a64codec_dai_trigger), + + DEVMETHOD_END +}; + +static driver_t a64codec_driver = { + "a64codec", + a64codec_methods, + sizeof(struct a64codec_softc), +}; + +static devclass_t a64codec_devclass; + +DRIVER_MODULE(a64codec, simplebus, a64codec_driver, a64codec_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/arm/allwinner/aw_i2s.c b/sys/arm/allwinner/aw_i2s.c new file mode 100644 index 00000000000..797b0e175bc --- /dev/null +++ b/sys/arm/allwinner/aw_i2s.c @@ -0,0 +1,813 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * Copyright (c) 2018 Jared McNeill + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "syscon_if.h" + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" + +#define FIFO_LEVEL 0x40 + +#define DA_CTL 0x00 +#define DA_CTL_BCLK_OUT (1 << 18) /* sun8i */ +#define DA_CLK_LRCK_OUT (1 << 17) /* sun8i */ +#define DA_CTL_SDO_EN (1 << 8) +#define DA_CTL_MS (1 << 5) /* sun4i */ +#define DA_CTL_PCM (1 << 4) /* sun4i */ +#define DA_CTL_MODE_SEL_MASK (3 << 4) /* sun8i */ +#define DA_CTL_MODE_SEL_PCM (0 << 4) /* sun8i */ +#define DA_CTL_MODE_SEL_LJ (1 << 4) /* sun8i */ +#define DA_CTL_MODE_SEL_RJ (2 << 4) /* sun8i */ +#define DA_CTL_TXEN (1 << 2) +#define DA_CTL_RXEN (1 << 1) +#define DA_CTL_GEN (1 << 0) +#define DA_FAT0 0x04 +#define DA_FAT0_LRCK_PERIOD_MASK (0x3ff << 8) /* sun8i */ +#define DA_FAT0_LRCK_PERIOD(n) (((n) & 0x3fff) << 8) /* sun8i */ +#define DA_FAT0_LRCP_MASK (1 << 7) +#define DA_LRCP_NORMAL (0 << 7) +#define DA_LRCP_INVERTED (1 << 7) +#define DA_FAT0_BCP_MASK (1 << 6) +#define DA_BCP_NORMAL (0 << 6) +#define DA_BCP_INVERTED (1 << 6) +#define DA_FAT0_SR __BITS(5,4) +#define DA_FAT0_WSS __BITS(3,2) +#define DA_FAT0_FMT_MASK (3 << 0) +#define DA_FMT_I2S 0 +#define DA_FMT_LJ 1 +#define DA_FMT_RJ 2 +#define DA_FAT1 0x08 +#define DA_ISTA 0x0c +#define DA_ISTA_TXUI_INT (1 << 6) +#define DA_ISTA_TXEI_INT (1 << 4) +#define DA_ISTA_RXAI_INT (1 << 0) +#define DA_RXFIFO 0x10 +#define DA_FCTL 0x14 +#define DA_FCTL_HUB_EN (1 << 31) +#define DA_FCTL_FTX (1 << 25) +#define DA_FCTL_FRX (1 << 24) +#define DA_FCTL_TXTL_MASK (0x7f << 12) +#define DA_FCTL_TXTL(v) (((v) & 0x7f) << 12) +#define DA_FCTL_TXIM (1 << 2) +#define DA_FSTA 0x18 +#define DA_FSTA_TXE_CNT(v) (((v) >> 16) & 0xff) +#define DA_FSTA_RXA_CNT(v) ((v) & 0x3f) +#define DA_INT 0x1c +#define DA_INT_TX_DRQ (1 << 7) +#define DA_INT_TXUI_EN (1 << 6) +#define DA_INT_TXEI_EN (1 << 4) +#define DA_INT_RX_DRQ (1 << 3) +#define DA_INT_RXAI_EN (1 << 0) +#define DA_TXFIFO 0x20 +#define DA_CLKD 0x24 +#define DA_CLKD_MCLKO_EN_SUN8I (1 << 8) +#define DA_CLKD_MCLKO_EN_SUN4I (1 << 7) +#define DA_CLKD_BCLKDIV_SUN8I(n) (((n) & 0xf) << 4) +#define DA_CLKD_BCLKDIV_SUN8I_MASK (0xf << 4) +#define DA_CLKD_BCLKDIV_SUN4I(n) (((n) & 7) << 4) +#define DA_CLKD_BCLKDIV_SUN4I_MASK (7 << 4) +#define DA_CLKD_BCLKDIV_8 3 +#define DA_CLKD_BCLKDIV_16 5 +#define DA_CLKD_MCLKDIV(n) (((n) & 0xff) << 0) +#define DA_CLKD_MCLKDIV_MASK (0xf << 0) +#define DA_CLKD_MCLKDIV_1 0 +#define DA_TXCNT 0x28 +#define DA_RXCNT 0x2c +#define DA_CHCFG 0x30 /* sun8i */ +#define DA_CHCFG_TX_SLOT_HIZ (1 << 9) +#define DA_CHCFG_TXN_STATE (1 << 8) +#define DA_CHCFG_RX_SLOT_NUM_MASK (7 << 4) +#define DA_CHCFG_RX_SLOT_NUM(n) (((n) & 7) << 4) +#define DA_CHCFG_TX_SLOT_NUM_MASK (7 << 0) +#define DA_CHCFG_TX_SLOT_NUM(n) (((n) & 7) << 0) + +#define DA_CHSEL_OFFSET(n) (((n) & 3) << 12) /* sun8i */ +#define DA_CHSEL_OFFSET_MASK (3 << 12) /* sun8i */ +#define DA_CHSEL_EN(n) (((n) & 0xff) << 4) +#define DA_CHSEL_EN_MASK (0xff << 4) +#define DA_CHSEL_SEL(n) (((n) & 7) << 0) +#define DA_CHSEL_SEL_MASK (7 << 0) + +#define AUDIO_BUFFER_SIZE 48000 * 4 + +#define AW_I2S_SAMPLE_RATE 48000 +#define AW_I2S_CLK_RATE 24576000 + +enum sunxi_i2s_type { + SUNXI_I2S_SUN4I, + SUNXI_I2S_SUN8I, +}; + +struct sunxi_i2s_config { + const char *name; + enum sunxi_i2s_type type; + bus_size_t txchsel; + bus_size_t txchmap; + bus_size_t rxchsel; + bus_size_t rxchmap; +}; + +static const struct sunxi_i2s_config sun50i_a64_codec_config = { + .name = "Audio Codec (digital part)", + .type = SUNXI_I2S_SUN4I, + .txchsel = 0x30, + .txchmap = 0x34, + .rxchsel = 0x38, + .rxchmap = 0x3c, +}; + +static const struct sunxi_i2s_config sun8i_h3_config = { + .name = "I2S/PCM controller", + .type = SUNXI_I2S_SUN8I, + .txchsel = 0x34, + .txchmap = 0x44, + .rxchsel = 0x54, + .rxchmap = 0x58, +}; + +static const u_int sun4i_i2s_bclk_divmap[] = { + [0] = 2, + [1] = 4, + [2] = 6, + [3] = 8, + [4] = 12, + [5] = 16, +}; + +static const u_int sun4i_i2s_mclk_divmap[] = { + [0] = 1, + [1] = 2, + [2] = 4, + [3] = 6, + [4] = 8, + [5] = 12, + [6] = 16, + [7] = 24, +}; + +static const u_int sun8i_i2s_divmap[] = { + [1] = 1, + [2] = 2, + [3] = 4, + [4] = 6, + [5] = 8, + [6] = 12, + [7] = 16, + [8] = 24, + [9] = 32, + [10] = 48, + [11] = 64, + [12] = 96, + [13] = 128, + [14] = 176, + [15] = 192, +}; + + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun50i-a64-codec-i2s", (uintptr_t)&sun50i_a64_codec_config }, + { "allwinner,sun8i-h3-i2s", (uintptr_t)&sun8i_h3_config }, + { NULL, 0 } +}; + +static struct resource_spec aw_i2s_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +struct aw_i2s_softc { + device_t dev; + struct resource *res[2]; + struct mtx mtx; + clk_t clk; + struct sunxi_i2s_config *cfg; + void * intrhand; + /* pointers to playback/capture buffers */ + uint32_t play_ptr; + uint32_t rec_ptr; +}; + +#define I2S_LOCK(sc) mtx_lock(&(sc)->mtx) +#define I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) +#define I2S_TYPE(sc) ((sc)->cfg->type) + +static int aw_i2s_probe(device_t dev); +static int aw_i2s_attach(device_t dev); +static int aw_i2s_detach(device_t dev); + +static u_int +sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div) +{ + u_int n; + + for (n = 0; n < divmaplen; n++) + if (divmap[n] == div) + return n; + + return -1; +} + +static uint32_t sc_fmt[] = { + SND_FORMAT(AFMT_S16_LE, 2, 0), + 0 +}; +static struct pcmchan_caps aw_i2s_caps = {AW_I2S_SAMPLE_RATE, AW_I2S_SAMPLE_RATE, sc_fmt, 0}; + + +static int +aw_i2s_init(struct aw_i2s_softc *sc) +{ + uint32_t val; + int error; + + error = clk_enable(sc->clk); + if (error != 0) { + device_printf(sc->dev, "cannot enable mod clock\n"); + return (ENXIO); + } + + /* Reset */ + val = I2S_READ(sc, DA_CTL); + val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); + I2S_WRITE(sc, DA_CTL, val); + + val = I2S_READ(sc, DA_FCTL); + val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); + val &= ~(DA_FCTL_TXTL_MASK); + val |= DA_FCTL_TXTL(FIFO_LEVEL); + I2S_WRITE(sc, DA_FCTL, val); + + I2S_WRITE(sc, DA_TXCNT, 0); + I2S_WRITE(sc, DA_RXCNT, 0); + + /* Enable */ + val = I2S_READ(sc, DA_CTL); + val |= DA_CTL_GEN; + I2S_WRITE(sc, DA_CTL, val); + val |= DA_CTL_SDO_EN; + I2S_WRITE(sc, DA_CTL, val); + + /* Setup channels */ + I2S_WRITE(sc, sc->cfg->txchmap, 0x76543210); + val = I2S_READ(sc, sc->cfg->txchsel); + val &= ~DA_CHSEL_EN_MASK; + val |= DA_CHSEL_EN(3); + val &= ~DA_CHSEL_SEL_MASK; + val |= DA_CHSEL_SEL(1); + I2S_WRITE(sc, sc->cfg->txchsel, val); + I2S_WRITE(sc, sc->cfg->rxchmap, 0x76543210); + val = I2S_READ(sc, sc->cfg->rxchsel); + val &= ~DA_CHSEL_EN_MASK; + val |= DA_CHSEL_EN(3); + val &= ~DA_CHSEL_SEL_MASK; + val |= DA_CHSEL_SEL(1); + I2S_WRITE(sc, sc->cfg->rxchsel, val); + + if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) { + val = I2S_READ(sc, DA_CHCFG); + val &= ~DA_CHCFG_TX_SLOT_NUM_MASK; + val |= DA_CHCFG_TX_SLOT_NUM(1); + val &= ~DA_CHCFG_RX_SLOT_NUM_MASK; + val |= DA_CHCFG_RX_SLOT_NUM(1); + I2S_WRITE(sc, DA_CHCFG, val); + } + + return (0); +} + +static int +aw_i2s_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Rockchip I2S"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_i2s_attach(device_t dev) +{ + struct aw_i2s_softc *sc; + int error; + phandle_t node; + hwreset_t rst; + clk_t clk; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->cfg = (void*)ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + if (bus_alloc_resources(dev, aw_i2s_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk); + if (error != 0) { + device_printf(dev, "cannot get i2s_clk clock\n"); + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "apb", &clk); + if (error != 0) { + device_printf(dev, "cannot get APB clock\n"); + goto fail; + } + + error = clk_enable(clk); + if (error != 0) { + device_printf(dev, "cannot enable APB clock\n"); + goto fail; + } + + if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { + error = hwreset_deassert(rst); + if (error != 0) { + device_printf(dev, "cannot de-assert reset\n"); + goto fail; + } + } + + aw_i2s_init(sc); + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + aw_i2s_detach(dev); + return (error); +} + +static int +aw_i2s_detach(device_t dev) +{ + struct aw_i2s_softc *i2s; + + i2s = device_get_softc(dev); + + if (i2s->clk) + clk_release(i2s->clk); + + if (i2s->intrhand != NULL) + bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); + + bus_release_resources(dev, aw_i2s_spec, i2s->res); + mtx_destroy(&i2s->mtx); + + return (0); +} + +static int +aw_i2s_dai_init(device_t dev, uint32_t format) +{ + struct aw_i2s_softc *sc; + int fmt, pol, clk; + uint32_t ctl, fat0, chsel; + u_int offset; + + sc = device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + ctl = I2S_READ(sc, DA_CTL); + fat0 = I2S_READ(sc, DA_FAT0); + + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + fat0 &= ~DA_FAT0_FMT_MASK; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + fat0 |= DA_FMT_I2S; + break; + case AUDIO_DAI_FORMAT_RJ: + fat0 |= DA_FMT_RJ; + break; + case AUDIO_DAI_FORMAT_LJ: + fat0 |= DA_FMT_LJ; + break; + default: + return EINVAL; + } + ctl &= ~DA_CTL_PCM; + } else { + ctl &= ~DA_CTL_MODE_SEL_MASK; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + ctl |= DA_CTL_MODE_SEL_LJ; + offset = 1; + break; + case AUDIO_DAI_FORMAT_LJ: + ctl |= DA_CTL_MODE_SEL_LJ; + offset = 0; + break; + case AUDIO_DAI_FORMAT_RJ: + ctl |= DA_CTL_MODE_SEL_RJ; + offset = 0; + break; + case AUDIO_DAI_FORMAT_DSPA: + ctl |= DA_CTL_MODE_SEL_PCM; + offset = 1; + break; + case AUDIO_DAI_FORMAT_DSPB: + ctl |= DA_CTL_MODE_SEL_PCM; + offset = 0; + break; + default: + return EINVAL; + } + + chsel = I2S_READ(sc, sc->cfg->txchsel); + chsel &= ~DA_CHSEL_OFFSET_MASK; + chsel |= DA_CHSEL_OFFSET(offset); + I2S_WRITE(sc, sc->cfg->txchsel, chsel); + + chsel = I2S_READ(sc, sc->cfg->rxchsel); + chsel &= ~DA_CHSEL_OFFSET_MASK; + chsel |= DA_CHSEL_OFFSET(offset); + I2S_WRITE(sc, sc->cfg->rxchsel, chsel); + } + + fat0 &= ~(DA_FAT0_LRCP_MASK|DA_FAT0_BCP_MASK); + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) + fat0 |= DA_BCP_INVERTED; + if (AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) + fat0 |= DA_LRCP_INVERTED; + } else { + if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) + fat0 |= DA_BCP_INVERTED; + if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) + fat0 |= DA_LRCP_INVERTED; + + fat0 &= ~DA_FAT0_LRCK_PERIOD_MASK; + fat0 |= DA_FAT0_LRCK_PERIOD(32 - 1); + } + + I2S_WRITE(sc, DA_CTL, ctl); + I2S_WRITE(sc, DA_FAT0, fat0); + + return (0); +} + + +static int +aw_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) +{ + struct aw_i2s_softc *sc; + int ret = 0; + uint32_t val, status; + + sc = device_get_softc(dev); + + I2S_LOCK(sc); + + status = I2S_READ(sc, DA_ISTA); + /* Clear interrupts */ + // device_printf(sc->dev, "status: %08x\n", status); + I2S_WRITE(sc, DA_ISTA, status); + + if (status & DA_ISTA_TXEI_INT) { + uint8_t *samples; + uint32_t count, size, readyptr, written, empty; + + val = I2S_READ(sc, DA_FSTA); + empty = DA_FSTA_TXE_CNT(val); + count = sndbuf_getready(play_buf); + size = sndbuf_getsize(play_buf); + readyptr = sndbuf_getreadyptr(play_buf); + + samples = (uint8_t*)sndbuf_getbuf(play_buf); + written = 0; + if (empty > count / 2) + empty = count / 2; + for (; empty > 0; empty--) { + val = (samples[readyptr++ % size] << 16); + val |= (samples[readyptr++ % size] << 24); + written += 2; + I2S_WRITE(sc, DA_TXFIFO, val); + } + sc->play_ptr += written; + sc->play_ptr %= size; + ret |= AUDIO_DAI_PLAY_INTR; + } + + if (status & DA_ISTA_RXAI_INT) { + uint8_t *samples; + uint32_t count, size, freeptr, recorded, available; + + val = I2S_READ(sc, DA_FSTA); + available = DA_FSTA_RXA_CNT(val); + + count = sndbuf_getfree(rec_buf); + size = sndbuf_getsize(rec_buf); + freeptr = sndbuf_getfreeptr(rec_buf); + samples = (uint8_t*)sndbuf_getbuf(rec_buf); + recorded = 0; + if (available > count / 2) + available = count / 2; + + for (; available > 0; available--) { + val = I2S_READ(sc, DA_RXFIFO); + samples[freeptr++ % size] = (val >> 16) & 0xff; + samples[freeptr++ % size] = (val >> 24) & 0xff; + recorded += 2; + } + sc->rec_ptr += recorded; + sc->rec_ptr %= size; + ret |= AUDIO_DAI_REC_INTR; + } + + I2S_UNLOCK(sc); + + return (ret); +} + +static struct pcmchan_caps * +aw_i2s_dai_get_caps(device_t dev) +{ + return (&aw_i2s_caps); +} + +static int +aw_i2s_dai_trigger(device_t dev, int go, int pcm_dir) +{ + struct aw_i2s_softc *sc = device_get_softc(dev); + uint32_t val; + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + switch (go) { + case PCMTRIG_START: + if (pcm_dir == PCMDIR_PLAY) { + /* Flush FIFO */ + val = I2S_READ(sc, DA_FCTL); + I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); + I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); + + /* Reset TX sample counter */ + I2S_WRITE(sc, DA_TXCNT, 0); + + /* Enable TX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); + + /* Enable TX underrun interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val | DA_INT_TXEI_EN); + } + + if (pcm_dir == PCMDIR_REC) { + /* Flush FIFO */ + val = I2S_READ(sc, DA_FCTL); + I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); + I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); + + /* Reset RX sample counter */ + I2S_WRITE(sc, DA_RXCNT, 0); + + /* Enable RX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); + + /* Enable RX data available interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val | DA_INT_RXAI_EN); + } + + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + I2S_LOCK(sc); + + if (pcm_dir == PCMDIR_PLAY) { + /* Disable TX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); + + /* Enable TX underrun interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val & ~DA_INT_TXEI_EN); + + sc->play_ptr = 0; + } else { + /* Disable RX block */ + val = I2S_READ(sc, DA_CTL); + I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); + + /* Disable RX data available interrupt */ + val = I2S_READ(sc, DA_INT); + I2S_WRITE(sc, DA_INT, val & ~DA_INT_RXAI_EN); + + sc->rec_ptr = 0; + } + + I2S_UNLOCK(sc); + break; + } + + return (0); +} + +static uint32_t +aw_i2s_dai_get_ptr(device_t dev, int pcm_dir) +{ + struct aw_i2s_softc *sc; + uint32_t ptr; + + sc = device_get_softc(dev); + + I2S_LOCK(sc); + if (pcm_dir == PCMDIR_PLAY) + ptr = sc->play_ptr; + else + ptr = sc->rec_ptr; + I2S_UNLOCK(sc); + + return ptr; +} + +static int +aw_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) +{ + struct aw_i2s_softc *sc = device_get_softc(dev); + + if (bus_setup_intr(dev, sc->res[1], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, + &sc->intrhand)) { + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + return (0); +} + +static uint32_t +aw_i2s_dai_set_chanformat(device_t dev, uint32_t format) +{ + + return (0); +} + +static int +aw_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) +{ + struct aw_i2s_softc *sc; + int bclk_val, mclk_val; + uint32_t val; + int error; + + sc = device_get_softc(dev); + + error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN); + if (error != 0) { + device_printf(sc->dev, + "couldn't set mod clock rate to %u Hz: %d\n", AW_I2S_CLK_RATE, error); + return error; + } + error = clk_enable(sc->clk); + if (error != 0) { + device_printf(sc->dev, + "couldn't enable mod clock: %d\n", error); + return error; + } + + const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : AW_I2S_CLK_RATE; + + const u_int bclk_div = bclk_prate / (2 * 32 * AW_I2S_SAMPLE_RATE); + const u_int mclk_div = AW_I2S_CLK_RATE / rate; + + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap, + nitems(sun4i_i2s_bclk_divmap), bclk_div); + mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap, + nitems(sun4i_i2s_mclk_divmap), mclk_div); + } else { + bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, + nitems(sun8i_i2s_divmap), bclk_div); + mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, + nitems(sun8i_i2s_divmap), mclk_div); + } + if (bclk_val == -1 || mclk_val == -1) { + device_printf(sc->dev, "couldn't configure bclk/mclk dividers\n"); + return EIO; + } + + val = I2S_READ(sc, DA_CLKD); + if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { + val |= DA_CLKD_MCLKO_EN_SUN4I; + val &= ~DA_CLKD_BCLKDIV_SUN4I_MASK; + val |= DA_CLKD_BCLKDIV_SUN4I(bclk_val); + } else { + val |= DA_CLKD_MCLKO_EN_SUN8I; + val &= ~DA_CLKD_BCLKDIV_SUN8I_MASK; + val |= DA_CLKD_BCLKDIV_SUN8I(bclk_val); + } + val &= ~DA_CLKD_MCLKDIV_MASK; + val |= DA_CLKD_MCLKDIV(mclk_val); + I2S_WRITE(sc, DA_CLKD, val); + + + return (0); +} + +static uint32_t +aw_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) +{ + + return (speed); +} + +static device_method_t aw_i2s_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_i2s_probe), + DEVMETHOD(device_attach, aw_i2s_attach), + DEVMETHOD(device_detach, aw_i2s_detach), + + DEVMETHOD(audio_dai_init, aw_i2s_dai_init), + DEVMETHOD(audio_dai_setup_intr, aw_i2s_dai_setup_intr), + DEVMETHOD(audio_dai_set_sysclk, aw_i2s_dai_set_sysclk), + DEVMETHOD(audio_dai_set_chanspeed, aw_i2s_dai_set_chanspeed), + DEVMETHOD(audio_dai_set_chanformat, aw_i2s_dai_set_chanformat), + DEVMETHOD(audio_dai_intr, aw_i2s_dai_intr), + DEVMETHOD(audio_dai_get_caps, aw_i2s_dai_get_caps), + DEVMETHOD(audio_dai_trigger, aw_i2s_dai_trigger), + DEVMETHOD(audio_dai_get_ptr, aw_i2s_dai_get_ptr), + + DEVMETHOD_END +}; + +static driver_t aw_i2s_driver = { + "i2s", + aw_i2s_methods, + sizeof(struct aw_i2s_softc), +}; + +static devclass_t aw_i2s_devclass; + +DRIVER_MODULE(aw_i2s, simplebus, aw_i2s_driver, aw_i2s_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/arm/allwinner/aw_nmi.c b/sys/arm/allwinner/aw_nmi.c index 6687d37c632..37d43fa5cd6 100644 --- a/sys/arm/allwinner/aw_nmi.c +++ b/sys/arm/allwinner/aw_nmi.c @@ -55,6 +55,7 @@ __FBSDID("$FreeBSD$"); #define A20_NMI_IRQ_ENABLE_REG 0x8 #define A31_NMI_IRQ_ENABLE_REG 0x34 #define NMI_IRQ_ENABLE (1U << 0) +#define NMI_IRQ_DISABLE (0U << 0) #define R_NMI_IRQ_CTRL_REG 0x0c #define R_NMI_IRQ_PENDING_REG 0x10 @@ -129,7 +130,7 @@ aw_nmi_intr(void *arg) } if (intr_isrc_dispatch(&sc->intr.isrc, curthread->td_intr_frame) != 0) { - SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE); + SC_NMI_WRITE(sc, sc->cfg->enable_reg, NMI_IRQ_DISABLE); device_printf(sc->dev, "Stray interrupt, NMI disabled\n"); } @@ -153,7 +154,7 @@ aw_nmi_disable_intr(device_t dev, struct intr_irqsrc *isrc) sc = device_get_softc(dev); - SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE); + SC_NMI_WRITE(sc, sc->cfg->enable_reg, NMI_IRQ_DISABLE); } static int @@ -296,7 +297,7 @@ aw_nmi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, sc->intr.pol = INTR_POLARITY_CONFORM; sc->intr.tri = INTR_TRIGGER_CONFORM; - SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE); + SC_NMI_WRITE(sc, sc->cfg->enable_reg, NMI_IRQ_DISABLE); } return (0); @@ -367,7 +368,7 @@ aw_nmi_attach(device_t dev) } /* Disable and clear interrupts */ - SC_NMI_WRITE(sc, sc->cfg->enable_reg, !NMI_IRQ_ENABLE); + SC_NMI_WRITE(sc, sc->cfg->enable_reg, NMI_IRQ_DISABLE); SC_NMI_WRITE(sc, sc->cfg->pending_reg, NMI_IRQ_ACK); xref = OF_xref_from_node(ofw_bus_get_node(dev)); diff --git a/sys/arm/allwinner/sun8i_codec.c b/sys/arm/allwinner/sun8i_codec.c new file mode 100644 index 00000000000..2af16f75fd5 --- /dev/null +++ b/sys/arm/allwinner/sun8i_codec.c @@ -0,0 +1,430 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * Copyright (c) 2018 Jared McNeill + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" + +#define SYSCLK_CTL 0x00c +#define AIF1CLK_ENA (1 << 11) +#define AIF1CLK_SRC_MASK (3 << 8) +#define AIF1CLK_SRC_PLL (2 << 8) +#define SYSCLK_ENA (1 << 3) +#define SYSCLK_SRC (1 << 0) + +#define MOD_CLK_ENA 0x010 +#define MOD_RST_CTL 0x014 +#define MOD_AIF1 (1 << 15) +#define MOD_ADC (1 << 3) +#define MOD_DAC (1 << 2) + +#define SYS_SR_CTRL 0x018 +#define AIF1_FS_MASK (0xf << 12) +#define AIF_FS_48KHZ (8 << 12) + +#define AIF1CLK_CTRL 0x040 +#define AIF1_MSTR_MOD (1 << 15) +#define AIF1_BCLK_INV (1 << 14) +#define AIF1_LRCK_INV (1 << 13) +#define AIF1_BCLK_DIV_MASK (0xf << 9) +#define AIF1_BCLK_DIV_16 (6 << 9) +#define AIF1_LRCK_DIV_MASK (7 << 6) +#define AIF1_LRCK_DIV_16 (0 << 6) +#define AIF1_LRCK_DIV_64 (2 << 6) +#define AIF1_WORD_SIZ_MASK (3 << 4) +#define AIF1_WORD_SIZ_16 (1 << 4) +#define AIF1_DATA_FMT_MASK (3 << 2) +#define AIF1_DATA_FMT_I2S (0 << 2) +#define AIF1_DATA_FMT_LJ (1 << 2) +#define AIF1_DATA_FMT_RJ (2 << 2) +#define AIF1_DATA_FMT_DSP (3 << 2) + +#define AIF1_ADCDAT_CTRL 0x044 +#define AIF1_ADC0L_ENA (1 << 15) +#define AIF1_ADC0R_ENA (1 << 14) + +#define AIF1_DACDAT_CTRL 0x048 +#define AIF1_DAC0L_ENA (1 << 15) +#define AIF1_DAC0R_ENA (1 << 14) + +#define AIF1_MXR_SRC 0x04c +#define AIF1L_MXR_SRC_MASK (0xf << 12) +#define AIF1L_MXR_SRC_AIF1 (0x8 << 12) +#define AIF1L_MXR_SRC_ADC (0x2 << 12) +#define AIF1R_MXR_SRC_MASK (0xf << 8) +#define AIF1R_MXR_SRC_AIF1 (0x8 << 8) +#define AIF1R_MXR_SRC_ADC (0x2 << 8) + +#define ADC_DIG_CTRL 0x100 +#define ADC_DIG_CTRL_ENAD (1 << 15) + +#define HMIC_CTRL1 0x110 +/* TODO: check this mask with datasheet */ +#define HMIC_CTRL1_N_MASK (0xf << 8) +#define HMIC_CTRL1_N(n) (((n) & 0xf) << 8) +#define HMIC_CTRL1_JACK_IN_IRQ_EN (1 << 4) +#define HMIC_CTRL1_JACK_OUT_IRQ_EN (1 << 3) +#define HMIC_CTRL1_MIC_DET_IRQ_EN (1 << 0) + +#define HMIC_CTRL2 0x114 +#define HMIC_CTRL2_MDATA_THRES __BITS(12,8) + +#define HMIC_STS 0x118 +#define HMIC_STS_MIC_PRESENT (1 << 6) +#define HMIC_STS_JACK_DET_OIRQ (1 << 4) +#define HMIC_STS_JACK_DET_IIRQ (1 << 3) +#define HMIC_STS_MIC_DET_ST (1 << 0) + +#define DAC_DIG_CTRL 0x120 +#define DAC_DIG_CTRL_ENDA (1 << 15) + +#define DAC_MXR_SRC 0x130 +#define DACL_MXR_SRC_MASK (0xf << 12) +#define DACL_MXR_SRC_AIF1_DAC0L (0x8 << 12) +#define DACR_MXR_SRC_MASK (0xf << 8) +#define DACR_MXR_SRC_AIF1_DAC0R (0x8 << 8) + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun8i-a33-codec", 1}, + { NULL, 0 } +}; + +static struct resource_spec sun8i_codec_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +struct sun8i_codec_softc { + device_t dev; + struct resource *res[2]; + struct mtx mtx; + clk_t clk_gate; + clk_t clk_mod; + void * intrhand; +}; + +#define CODEC_LOCK(sc) mtx_lock(&(sc)->mtx) +#define CODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define CODEC_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define CODEC_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) + +static int sun8i_codec_probe(device_t dev); +static int sun8i_codec_attach(device_t dev); +static int sun8i_codec_detach(device_t dev); + +static int +sun8i_codec_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Allwinner Codec"); + return (BUS_PROBE_DEFAULT); +} + +static int +sun8i_codec_attach(device_t dev) +{ + struct sun8i_codec_softc *sc; + int error; + uint32_t val; + struct gpiobus_pin *pa_pin; + phandle_t node; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + if (bus_alloc_resources(dev, sun8i_codec_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod); + if (error != 0) { + device_printf(dev, "cannot get \"mod\" clock\n"); + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_gate); + if (error != 0) { + device_printf(dev, "cannot get \"bus\" clock\n"); + goto fail; + } + + error = clk_enable(sc->clk_gate); + if (error != 0) { + device_printf(dev, "cannot enable \"bus\" clock\n"); + goto fail; + } + + /* Enable clocks */ + val = CODEC_READ(sc, SYSCLK_CTL); + val |= AIF1CLK_ENA; + val &= ~AIF1CLK_SRC_MASK; + val |= AIF1CLK_SRC_PLL; + val |= SYSCLK_ENA; + val &= ~SYSCLK_SRC; + CODEC_WRITE(sc, SYSCLK_CTL, val); + CODEC_WRITE(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC); + CODEC_WRITE(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC); + + /* Enable digital parts */ + CODEC_WRITE(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA); + CODEC_WRITE(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD); + + /* Set AIF1 to 48 kHz */ + val = CODEC_READ(sc, SYS_SR_CTRL); + val &= ~AIF1_FS_MASK; + val |= AIF_FS_48KHZ; + CODEC_WRITE(sc, SYS_SR_CTRL, val); + + /* Set AIF1 to 16-bit */ + val = CODEC_READ(sc, AIF1CLK_CTRL); + val &= ~AIF1_WORD_SIZ_MASK; + val |= AIF1_WORD_SIZ_16; + CODEC_WRITE(sc, AIF1CLK_CTRL, val); + + /* Enable AIF1 DAC timelot 0 */ + val = CODEC_READ(sc, AIF1_DACDAT_CTRL); + val |= AIF1_DAC0L_ENA; + val |= AIF1_DAC0R_ENA; + CODEC_WRITE(sc, AIF1_DACDAT_CTRL, val); + + /* Enable AIF1 ADC timelot 0 */ + val = CODEC_READ(sc, AIF1_ADCDAT_CTRL); + val |= AIF1_ADC0L_ENA; + val |= AIF1_ADC0R_ENA; + CODEC_WRITE(sc, AIF1_ADCDAT_CTRL, val); + + /* DAC mixer source select */ + val = CODEC_READ(sc, DAC_MXR_SRC); + val &= ~DACL_MXR_SRC_MASK; + val |= DACL_MXR_SRC_AIF1_DAC0L; + val &= ~DACR_MXR_SRC_MASK; + val |= DACR_MXR_SRC_AIF1_DAC0R; + CODEC_WRITE(sc, DAC_MXR_SRC, val); + + /* ADC mixer source select */ + val = CODEC_READ(sc, AIF1_MXR_SRC); + val &= ~AIF1L_MXR_SRC_MASK; + val |= AIF1L_MXR_SRC_ADC; + val &= ~AIF1R_MXR_SRC_MASK; + val |= AIF1R_MXR_SRC_ADC; + CODEC_WRITE(sc, AIF1_MXR_SRC, val); + + /* Enable PA power */ + /* Unmute PA */ + if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios", + &pa_pin) == 0) { + error = gpio_pin_set_active(pa_pin, 1); + if (error != 0) + device_printf(dev, "failed to unmute PA\n"); + } + +#ifdef notyet + /* Enable jack detect */ + val = CODEC_READ(sc, HMIC_CTRL1); + val |= HMIC_CTRL1_N(0xff); + CODEC_WRITE(sc, HMIC_CTRL1, val); + + val = CODEC_READ(sc, HMIC_CTRL2); + val &= ~HMIC_CTRL2_MDATA_THRES; + val |= __SHIFTIN(0x17, HMIC_CTRL2_MDATA_THRES); + CODEC_WRITE(sc, HMIC_CTRL2, val); +#endif + + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + sun8i_codec_detach(dev); + return (error); +} + +static int +sun8i_codec_detach(device_t dev) +{ + struct sun8i_codec_softc *sc; + + sc = device_get_softc(dev); + + if (sc->clk_gate) + clk_release(sc->clk_gate); + + if (sc->clk_mod) + clk_release(sc->clk_mod); + + if (sc->intrhand != NULL) + bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); + + bus_release_resources(dev, sun8i_codec_spec, sc->res); + mtx_destroy(&sc->mtx); + + return (0); +} + +static int +sun8i_codec_dai_init(device_t dev, uint32_t format) +{ + struct sun8i_codec_softc *sc; + int fmt, pol, clk; + uint32_t val; + + sc = device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + val = CODEC_READ(sc, AIF1CLK_CTRL); + + val &= ~AIF1_DATA_FMT_MASK; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + val |= AIF1_DATA_FMT_I2S; + break; + case AUDIO_DAI_FORMAT_RJ: + val |= AIF1_DATA_FMT_RJ; + break; + case AUDIO_DAI_FORMAT_LJ: + val |= AIF1_DATA_FMT_LJ; + break; + case AUDIO_DAI_FORMAT_DSPA: + case AUDIO_DAI_FORMAT_DSPB: + val |= AIF1_DATA_FMT_DSP; + break; + default: + return EINVAL; + } + + val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV); + /* Codec LRCK polarity is inverted (datasheet is wrong) */ + if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) + val |= AIF1_LRCK_INV; + if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) + val |= AIF1_BCLK_INV; + + switch (clk) { + case AUDIO_DAI_CLOCK_CBM_CFM: + val &= ~AIF1_MSTR_MOD; /* codec is master */ + break; + case AUDIO_DAI_CLOCK_CBS_CFS: + val |= AIF1_MSTR_MOD; /* codec is slave */ + break; + default: + return EINVAL; + } + + val &= ~AIF1_LRCK_DIV_MASK; + val |= AIF1_LRCK_DIV_64; + + val &= ~AIF1_BCLK_DIV_MASK; + val |= AIF1_BCLK_DIV_16; + + CODEC_WRITE(sc, AIF1CLK_CTRL, val); + + return (0); +} + +static int +sun8i_codec_dai_trigger(device_t dev, int go, int pcm_dir) +{ + + return (0); +} + +static int +sun8i_codec_dai_setup_mixer(device_t dev, device_t pcmdev) +{ + struct sun8i_codec_softc *sc; + + sc = device_get_softc(dev); + device_printf(sc->dev, "TODO: implement me %s\n", __func__); + + return (0); +} + + +static device_method_t sun8i_codec_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, sun8i_codec_probe), + DEVMETHOD(device_attach, sun8i_codec_attach), + DEVMETHOD(device_detach, sun8i_codec_detach), + + DEVMETHOD(audio_dai_init, sun8i_codec_dai_init), + DEVMETHOD(audio_dai_setup_mixer, sun8i_codec_dai_setup_mixer), + DEVMETHOD(audio_dai_trigger, sun8i_codec_dai_trigger), + + DEVMETHOD_END +}; + +static driver_t sun8i_codec_driver = { + "sun8icodec", + sun8i_codec_methods, + sizeof(struct sun8i_codec_softc), +}; + +static devclass_t sun8i_codec_devclass; + +DRIVER_MODULE(sun8i_codec, simplebus, sun8i_codec_driver, sun8i_codec_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/arm64/conf/GENERIC b/sys/arm64/conf/GENERIC index 5e16c8f4199..91be7b78f70 100644 --- a/sys/arm64/conf/GENERIC +++ b/sys/arm64/conf/GENERIC @@ -237,8 +237,11 @@ device smcphy device smsc # Sound support -device sound -device a10_codec +device sound +device a10_codec +device es8316codec +device rk3328codec +device rt5640codec # DMA controller device a31_dmac diff --git a/sys/arm64/rockchip/clk/rk3328_cru.c b/sys/arm64/rockchip/clk/rk3328_cru.c index 7e53c54fa2b..7fd6c5f37fb 100644 --- a/sys/arm64/rockchip/clk/rk3328_cru.c +++ b/sys/arm64/rockchip/clk/rk3328_cru.c @@ -51,6 +51,11 @@ __FBSDID("$FreeBSD$"); /* GATES */ +#define SCLK_I2S0 41 +#define SCLK_I2S1 42 +#define SCLK_I2S2 43 +#define SCLK_I2S1_OUT 44 +#define SCLK_I2S2_OUT 45 #define SCLK_USB3OTG_REF 96 #define ACLK_USB3OTG 132 #define ACLK_PERI 153 @@ -66,6 +71,10 @@ __FBSDID("$FreeBSD$"); #define PCLK_USB3PHY_OTG 224 #define PCLK_USB3PHY_PIPE 225 #define PCLK_USB3_GRF 226 +#define PCLK_ACODECPHY 235 +#define HCLK_I2S0_8CH 311 +#define HCLK_I2S1_8CH 312 +#define HCLK_I2S2_2CH 313 #define HCLK_SDMMC 317 #define HCLK_SDIO 318 #define HCLK_EMMC 319 @@ -78,6 +87,11 @@ static struct rk_cru_gate rk3328_gates[] = { CRU_GATE(0, "gpll_core", "gpll", 0x200, 2) CRU_GATE(0, "npll_core", "npll", 0x200, 12) + /* CRU_CLKGATE_CON1 */ + CRU_GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 0x204, 3) + CRU_GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 0x204, 6) + CRU_GATE(SCLK_I2S1, "clk_i2s2", "clk_i2s2_mux", 0x204, 10) + /* CRU_CLKGATE_CON4 */ CRU_GATE(0, "gpll_peri", "gpll", 0x210, 0) CRU_GATE(0, "cpll_peri", "cpll", 0x210, 1) @@ -91,6 +105,9 @@ static struct rk_cru_gate rk3328_gates[] = { CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0) /* CRU_CLKGATE_CON15*/ + CRU_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0x23C, 3) + CRU_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0x23C, 4) + CRU_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0x23C, 5) CRU_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0x23C, 10) /* CRU_CLKGATE_CON16 */ @@ -106,6 +123,7 @@ static struct rk_cru_gate rk3328_gates[] = { /* CRU_CLKGATE_CON17 */ CRU_GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", 0x244, 2) + CRU_GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0x244, 5) /* CRU_CLKGATE_CON19 */ CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0) @@ -1077,6 +1095,215 @@ static struct rk_clk_composite_def ref_usb3otg_src = { .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; +/* I2S0 */ +static const char *i2s0_div_parents[] = { "cpll", "gpll" }; +static struct rk_clk_composite_def i2s0_div = { + .clkdef = { + .id = 0, + .name = "clk_i2s0_div", + .parent_names = i2s0_div_parents, + .parent_cnt = nitems(i2s0_div_parents), + }, + /* CRU_CLKSEL_CON6 */ + .muxdiv_offset = 0x118, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON1 */ + .gate_offset = 0x204, + .gate_shift = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *i2s0_frac_parents[] = { "clk_i2s0_div" }; +static struct rk_clk_fract_def i2s0_frac = { + .clkdef = { + .id = 0, + .name = "clk_i2s0_frac", + .parent_names = i2s0_frac_parents, + .parent_cnt = nitems(i2s0_frac_parents), + }, + /* CRU_CLKSEL_CON7 */ + .offset = 0x11c, + + /* CRU_CLKGATE_CON1 */ + .gate_offset = 0x204, + .gate_shift = 2, + + .flags = RK_CLK_FRACT_HAVE_GATE, +}; + +static const char *i2s0_mux_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m" }; +static struct rk_clk_mux_def i2s0_mux = { + .clkdef = { + .id = 0, + .name = "clk_i2s0_mux", + .parent_names = i2s0_mux_parents, + .parent_cnt = nitems(i2s0_mux_parents), + }, + .offset = 0x118, + + .shift = 8, + .width = 2, + + .mux_flags = RK_CLK_MUX_REPARENT, +}; + +/* I2S1 */ +static const char *i2s1_div_parents[] = { "cpll", "gpll" }; +static struct rk_clk_composite_def i2s1_div = { + .clkdef = { + .id = 0, + .name = "clk_i2s1_div", + .parent_names = i2s1_div_parents, + .parent_cnt = nitems(i2s1_div_parents), + }, + /* CRU_CLKSEL_CON8 */ + .muxdiv_offset = 0x120, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON1 */ + .gate_offset = 0x204, + .gate_shift = 4, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *i2s1_frac_parents[] = { "clk_i2s1_div" }; +static struct rk_clk_fract_def i2s1_frac = { + .clkdef = { + .id = 0, + .name = "clk_i2s1_frac", + .parent_names = i2s1_frac_parents, + .parent_cnt = nitems(i2s1_frac_parents), + }, + /* CRU_CLKSEL_CON9 */ + .offset = 0x124, + + /* CRU_CLKGATE_CON1 */ + .gate_offset = 0x204, + .gate_shift = 5, + + .flags = RK_CLK_FRACT_HAVE_GATE, +}; + +static const char *i2s1_mux_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s1", "xin12m" }; +static struct rk_clk_mux_def i2s1_mux = { + .clkdef = { + .id = 0, + .name = "clk_i2s1_mux", + .parent_names = i2s1_mux_parents, + .parent_cnt = nitems(i2s1_mux_parents), + }, + .offset = 0x120, + + .shift = 8, + .width = 2, + .mux_flags = RK_CLK_MUX_REPARENT, +}; + +static struct clk_fixed_def clkin_i2s1 = { + .clkdef = { + .id = 0, + .name = "clkin_i2s1", + .parent_names = NULL, + .parent_cnt = 0 + }, + + .freq = 0, +}; + +/* I2S2 */ +static const char *i2s2_div_parents[] = { "cpll", "gpll" }; +static struct rk_clk_composite_def i2s2_div = { + .clkdef = { + .id = 0, + .name = "clk_i2s2_div", + .parent_names = i2s2_div_parents, + .parent_cnt = nitems(i2s2_div_parents), + }, + /* CRU_CLKSEL_CON10 */ + .muxdiv_offset = 0x128, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON1 */ + .gate_offset = 0x204, + .gate_shift = 8, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *i2s2_frac_parents[] = { "clk_i2s2_div" }; +static struct rk_clk_fract_def i2s2_frac = { + .clkdef = { + .id = 0, + .name = "clk_i2s2_frac", + .parent_names = i2s2_frac_parents, + .parent_cnt = nitems(i2s2_frac_parents), + }, + /* CRU_CLKSEL_CON11 */ + .offset = 0x12c, + + /* CRU_CLKGATE_CON1 */ + .gate_offset = 0x204, + .gate_shift = 9, + + .flags = RK_CLK_FRACT_HAVE_GATE, +}; + +static const char *i2s2_mux_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s2", "xin12m" }; +static struct rk_clk_mux_def i2s2_mux = { + .clkdef = { + .id = 0, + .name = "clk_i2s2_mux", + .parent_names = i2s2_mux_parents, + .parent_cnt = nitems(i2s2_mux_parents), + }, + .offset = 0x128, + + .shift = 8, + .width = 2, + + .mux_flags = RK_CLK_MUX_REPARENT, +}; + +static struct clk_fixed_def clkin_i2s2 = { + .clkdef = { + .id = 0, + .name = "clkin_i2s2", + .parent_names = NULL, + .parent_cnt = 0 + }, + + .freq = 0, +}; + +static struct clk_fixed_def xin12m = { + .clkdef = { + .id = 0, + .name = "xin12m", + .parent_names = NULL, + .parent_cnt = 0 + }, + + .freq = 12000000, +}; + static struct rk_clk rk3328_clks[] = { { .type = RK3328_CLK_PLL, @@ -1175,6 +1402,54 @@ static struct rk_clk rk3328_clks[] = { .type = RK_CLK_COMPOSITE, .clk.composite = &usb3otg_suspend }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2s0_div + }, + { + .type = RK_CLK_FRACT, + .clk.fract = &i2s0_frac + }, + { + .type = RK_CLK_MUX, + .clk.mux = &i2s0_mux + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2s1_div + }, + { + .type = RK_CLK_FRACT, + .clk.fract = &i2s1_frac + }, + { + .type = RK_CLK_MUX, + .clk.mux = &i2s1_mux + }, + { + .type = RK_CLK_FIXED, + .clk.fixed = &clkin_i2s1 + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2s2_div + }, + { + .type = RK_CLK_FRACT, + .clk.fract = &i2s2_frac + }, + { + .type = RK_CLK_MUX, + .clk.mux = &i2s2_mux + }, + { + .type = RK_CLK_FIXED, + .clk.fixed = &clkin_i2s2 + }, + { + .type = RK_CLK_FIXED, + .clk.fixed = &xin12m + }, }; static int diff --git a/sys/arm64/rockchip/clk/rk3399_cru.c b/sys/arm64/rockchip/clk/rk3399_cru.c index e13acc0eaa9..8e61410b1b4 100644 --- a/sys/arm64/rockchip/clk/rk3399_cru.c +++ b/sys/arm64/rockchip/clk/rk3399_cru.c @@ -973,19 +973,19 @@ static struct rk_clk rk3399_clks[] = { 27, 0, 10, 15, 1), /* CRU_CLKSEL_CON28 */ - MUX(0, "clk_i2s0_mux", i2s0_p, 0, + MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT, 28, 8, 2), COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, 28, 0, 7, 7, 1), /* CRU_CLKSEL_CON29 */ - MUX(0, "clk_i2s1_mux", i2s1_p, 0, + MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT, 29, 8, 2), COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0, 29, 0, 7, 7, 1), /* CRU_CLKSEL_CON30 */ - MUX(0, "clk_i2s2_mux", i2s2_p, 0, + MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT, 30, 8, 2), COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0, 30, 0, 7, 7, 1), diff --git a/sys/arm64/rockchip/clk/rk_clk_fract.c b/sys/arm64/rockchip/clk/rk_clk_fract.c index 266e963e88d..ff748b25290 100644 --- a/sys/arm64/rockchip/clk/rk_clk_fract.c +++ b/sys/arm64/rockchip/clk/rk_clk_fract.c @@ -49,21 +49,27 @@ __FBSDID("$FreeBSD$"); #define DEVICE_UNLOCK(_clk) \ CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) +#define RK_CLK_FRACT_MASK_SHIFT 16 + static int rk_clk_fract_init(struct clknode *clk, device_t dev); static int rk_clk_fract_recalc(struct clknode *clk, uint64_t *req); static int rk_clk_fract_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, int flag, int *stop); +static int rk_clk_fract_set_gate(struct clknode *clk, bool enable); struct rk_clk_fract_sc { uint32_t flags; uint32_t offset; uint32_t numerator; uint32_t denominator; + uint32_t gate_offset; + uint32_t gate_shift; }; static clknode_method_t rk_clk_fract_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, rk_clk_fract_init), + CLKNODEMETHOD(clknode_set_gate, rk_clk_fract_set_gate), CLKNODEMETHOD(clknode_recalc_freq, rk_clk_fract_recalc), CLKNODEMETHOD(clknode_set_freq, rk_clk_fract_set_freq), CLKNODEMETHOD_END @@ -150,6 +156,33 @@ rk_clk_fract_init(struct clknode *clk, device_t dev) return(0); } +static int +rk_clk_fract_set_gate(struct clknode *clk, bool enable) +{ + struct rk_clk_fract_sc *sc; + uint32_t val = 0; + + sc = clknode_get_softc(clk); + + if ((sc->flags & RK_CLK_FRACT_HAVE_GATE) == 0) + return (0); + + RD4(clk, sc->gate_offset, &val); + + val = 0; + if (!enable) + val |= 1 << sc->gate_shift; + val |= (1 << sc->gate_shift) << RK_CLK_FRACT_MASK_SHIFT; + DEVICE_LOCK(clk); + WR4(clk, sc->gate_offset, val); + DEVICE_UNLOCK(clk); + + return (0); +} + +static int +rk_clk_fract_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop); static int rk_clk_fract_recalc(struct clknode *clk, uint64_t *freq) { @@ -241,6 +274,8 @@ rk_clk_fract_register(struct clkdom *clkdom, struct rk_clk_fract_def *clkdef) sc = clknode_get_softc(clk); sc->flags = clkdef->flags; sc->offset = clkdef->offset; + sc->gate_offset = clkdef->gate_offset; + sc->gate_shift = clkdef->gate_shift; clknode_register(clkdom, clk); return (0); diff --git a/sys/arm64/rockchip/clk/rk_clk_fract.h b/sys/arm64/rockchip/clk/rk_clk_fract.h index 2fe8f47586e..03fab3fd288 100644 --- a/sys/arm64/rockchip/clk/rk_clk_fract.h +++ b/sys/arm64/rockchip/clk/rk_clk_fract.h @@ -35,9 +35,13 @@ struct rk_clk_fract_def { struct clknode_init_def clkdef; uint32_t offset; + uint32_t gate_offset; + uint32_t gate_shift; uint32_t flags; }; +#define RK_CLK_FRACT_HAVE_GATE 0x0001 + int rk_clk_fract_register(struct clkdom *clkdom, struct rk_clk_fract_def *clkdef); diff --git a/sys/arm64/rockchip/clk/rk_clk_mux.c b/sys/arm64/rockchip/clk/rk_clk_mux.c index 4342b81565f..c2188e0ec13 100644 --- a/sys/arm64/rockchip/clk/rk_clk_mux.c +++ b/sys/arm64/rockchip/clk/rk_clk_mux.c @@ -56,8 +56,17 @@ __FBSDID("$FreeBSD$"); #define DEVICE_UNLOCK(_clk) \ CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else +#define dprintf(format, arg...) +#endif + static int rk_clk_mux_init(struct clknode *clk, device_t dev); static int rk_clk_mux_set_mux(struct clknode *clk, int idx); +static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, + uint64_t *fout, int flags, int *stop); struct rk_clk_mux_sc { uint32_t offset; @@ -70,6 +79,7 @@ static clknode_method_t rk_clk_mux_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, rk_clk_mux_init), CLKNODEMETHOD(clknode_set_mux, rk_clk_mux_set_mux), + CLKNODEMETHOD(clknode_set_freq, rk_clk_mux_set_freq), CLKNODEMETHOD_END }; DEFINE_CLASS_1(rk_clk_mux, rk_clk_mux_class, rk_clk_mux_methods, @@ -118,6 +128,57 @@ rk_clk_mux_set_mux(struct clknode *clk, int idx) return(0); } +static int +rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_mux_sc *sc; + struct clknode *p_clk, *p_best_clk; + const char **p_names; + int p_idx, best_parent; + int rv; + + sc = clknode_get_softc(clk); + + if ((sc->mux_flags & RK_CLK_MUX_REPARENT) == 0) + return (0); + + dprintf("Finding best parent for target freq of %ju\n", *fout); + p_names = clknode_get_parent_names(clk); + for (p_idx = 0; p_idx != clknode_get_parents_num(clk); p_idx++) { + p_clk = clknode_find_by_name(p_names[p_idx]); + dprintf("Testing with parent %s (%d)\n", + clknode_get_name(p_clk), p_idx); + + rv = clknode_set_freq(p_clk, *fout, flags | CLK_SET_DRYRUN, 0); + dprintf("Testing with parent %s (%d) rv=%d\n", + clknode_get_name(p_clk), p_idx, rv); + if (rv == 0) { + best_parent = p_idx; + p_best_clk = p_clk; + *stop = 1; + } + } + + if (!*stop) + return (0); + + if ((flags & CLK_SET_DRYRUN) != 0) + return (0); + + p_idx = clknode_get_parent_idx(clk); + if (p_idx != best_parent) { + dprintf("Switching parent index from %d to %d\n", p_idx, + best_parent); + clknode_set_parent_by_idx(clk, best_parent); + } + + clknode_set_freq(p_best_clk, *fout, flags, 0); + clknode_get_freq(p_best_clk, fout); + + return (0); +} + int rk_clk_mux_register(struct clkdom *clkdom, struct rk_clk_mux_def *clkdef) { diff --git a/sys/arm64/rockchip/clk/rk_clk_mux.h b/sys/arm64/rockchip/clk/rk_clk_mux.h index f44443790b1..7825f8892ac 100644 --- a/sys/arm64/rockchip/clk/rk_clk_mux.h +++ b/sys/arm64/rockchip/clk/rk_clk_mux.h @@ -41,6 +41,7 @@ struct rk_clk_mux_def { }; #define RK_CLK_MUX_MASK 0xFFFF0000 +#define RK_CLK_MUX_REPARENT (1 << 0) int rk_clk_mux_register(struct clkdom *clkdom, struct rk_clk_mux_def *clkdef); diff --git a/sys/arm64/rockchip/rk3328_codec.c b/sys/arm64/rockchip/rk3328_codec.c new file mode 100644 index 00000000000..940b3b8bb9e --- /dev/null +++ b/sys/arm64/rockchip/rk3328_codec.c @@ -0,0 +1,593 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * Copyright (c) 2018 Jared McNeill + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "syscon_if.h" + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" +#include "mixer_if.h" + +#define RKCODEC_MIXER_DEVS (1 << SOUND_MIXER_VOLUME) + +#define GRF_SOC_CON2 0x0408 +#define SOC_CON2_I2S_ACODEC_EN (1 << 14) +#define SOC_CON2_I2S_ACODEC_EN_MASK ((1 << 14) << 16) +#define GRF_SOC_CON10 0x0428 +#define SOC_CON10_GPIOMUT (1 << 1) +#define SOC_CON10_GPIOMUT_MASK ((1 << 1) << 16) +#define SOC_CON10_GPIOMUT_EN (1 << 0) +#define SOC_CON10_GPIOMUT_EN_MASK ((1 << 0) << 16) + +#define CODEC_RESET 0x00 +#define RESET_DIG_CORE_RST (1 << 1) +#define RESET_SYS_RST (1 << 0) +#define CODEC_DAC_INIT_CTRL1 0x0c +#define DAC_INIT_CTRL1_DIRECTION_IN (0 << 5) +#define DAC_INIT_CTRL1_DIRECTION_OUT (1 << 5) +#define DAC_INIT_CTRL1_DAC_I2S_MODE_SLAVE (0 << 4) +#define DAC_INIT_CTRL1_DAC_I2S_MODE_MASTER (1 << 4) +#define DAC_INIT_CTRL1_MODE_MASK (3 << 4) +#define CODEC_DAC_INIT_CTRL2 0x10 +#define DAC_INIT_CTRL2_DAC_VDL_16BITS (0 << 5) +#define DAC_INIT_CTRL2_DAC_VDL_20BITS (1 << 5) +#define DAC_INIT_CTRL2_DAC_VDL_24BITS (2 << 5) +#define DAC_INIT_CTRL2_DAC_VDL_32BITS (3 << 5) +#define DAC_INIT_CTRL2_DAC_VDL_MASK (3 << 5) +#define DAC_INIT_CTRL2_DAC_MODE_RJM (0 << 3) +#define DAC_INIT_CTRL2_DAC_MODE_LJM (1 << 3) +#define DAC_INIT_CTRL2_DAC_MODE_I2S (2 << 3) +#define DAC_INIT_CTRL2_DAC_MODE_PCM (3 << 3) +#define DAC_INIT_CTRL2_DAC_MODE_MASK (3 << 3) +#define CODEC_DAC_INIT_CTRL3 0x14 +#define DAC_INIT_CTRL3_WL_16BITS (0 << 2) +#define DAC_INIT_CTRL3_WL_20BITS (1 << 2) +#define DAC_INIT_CTRL3_WL_24BITS (2 << 2) +#define DAC_INIT_CTRL3_WL_32BITS (3 << 2) +#define DAC_INIT_CTRL3_WL_MASK (3 << 2) +#define DAC_INIT_CTRL3_RST_MASK (1 << 1) +#define DAC_INIT_CTRL3_RST_DIS (1 << 1) +#define DAC_INIT_CTRL3_DAC_BCP_REVERSAL (1 << 0) +#define DAC_INIT_CTRL3_DAC_BCP_NORMAL (0 << 0) +#define DAC_INIT_CTRL3_DAC_BCP_MASK (1 << 0) +#define CODEC_DAC_PRECHARGE_CTRL 0x88 +#define DAC_PRECHARGE_CTRL_DAC_CHARGE_PRECHARGE (1 << 7) +#define DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_I (1 << 0) +#define DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_ALL (0x7f) +#define CODEC_DAC_PWR_CTRL 0x8c +#define DAC_PWR_CTRL_DAC_PWR (1 << 6) +#define DAC_PWR_CTRL_DACL_PATH_REFV (1 << 5) +#define DAC_PWR_CTRL_HPOUTL_ZERO_CROSSING (1 << 4) +#define DAC_PWR_CTRL_DACR_PATH_REFV (1 << 1) +#define DAC_PWR_CTRL_HPOUTR_ZERO_CROSSING (1 << 0) +#define CODEC_DAC_CLK_CTRL 0x90 +#define DAC_CLK_CTRL_DACL_REFV_ON (1 << 7) +#define DAC_CLK_CTRL_DACL_CLK_ON (1 << 6) +#define DAC_CLK_CTRL_DACL_ON (1 << 5) +#define DAC_CLK_CTRL_DACL_INIT_ON (1 << 4) +#define DAC_CLK_CTRL_DACR_REFV_ON (1 << 3) +#define DAC_CLK_CTRL_DACR_CLK_ON (1 << 2) +#define DAC_CLK_CTRL_DACR_ON (1 << 1) +#define DAC_CLK_CTRL_DACR_INIT_ON (1 << 0) +#define CODEC_HPMIX_CTRL 0x94 +#define HPMIX_CTRL_HPMIXL_EN (1 << 6) +#define HPMIX_CTRL_HPMIXL_INIT_EN (1 << 5) +#define HPMIX_CTRL_HPMIXL_INIT2_EN (1 << 4) +#define HPMIX_CTRL_HPMIXR_EN (1 << 2) +#define HPMIX_CTRL_HPMIXR_INIT_EN (1 << 1) +#define HPMIX_CTRL_HPMIXR_INIT2_EN (1 << 0) +#define CODEC_DAC_SELECT 0x98 +#define DAC_SELECT_DACL_SELECT (1 << 4) +#define DAC_SELECT_DACR_SELECT (1 << 0) +#define CODEC_HPOUT_CTRL 0x9c +#define HPOUT_CTRL_HPOUTL_EN (1 << 7) +#define HPOUT_CTRL_HPOUTL_INIT_EN (1 << 6) +#define HPOUT_CTRL_HPOUTL_UNMUTE (1 << 5) +#define HPOUT_CTRL_HPOUTR_EN (1 << 4) +#define HPOUT_CTRL_HPOUTR_INIT_EN (1 << 3) +#define HPOUT_CTRL_HPOUTR_UNMUTE (1 << 2) +#define CODEC_HPOUTL_GAIN_CTRL 0xa0 +#define CODEC_HPOUTR_GAIN_CTRL 0xa4 +#define CODEC_HPOUT_POP_CTRL 0xa8 +#define HPOUT_POP_CTRL_HPOUTR_POP (1 << 5) +#define HPOUT_POP_CTRL_HPOUTR_POP_XCHARGE (1 << 4) +#define HPOUT_POP_CTRL_HPOUTL_POP (1 << 1) +#define HPOUT_POP_CTRL_HPOUTL_POP_XCHARGE (1 << 0) + +#define DEFAULT_RATE (48000 * 256) + +static struct ofw_compat_data compat_data[] = { + { "rockchip,rk3328-codec", 1}, + { NULL, 0 } +}; + +struct rkcodec_softc { + device_t dev; + struct resource *res; + struct mtx mtx; + clk_t mclk; + clk_t pclk; + struct syscon *grf; + u_int regaddr; /* address for the sysctl */ +}; + +#define RKCODEC_LOCK(sc) mtx_lock(&(sc)->mtx) +#define RKCODEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define RKCODEC_READ(sc, reg) bus_read_4((sc)->res, (reg)) +#define RKCODEC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) + +static int rkcodec_probe(device_t dev); +static int rkcodec_attach(device_t dev); +static int rkcodec_detach(device_t dev); + +static void +rkcodec_set_power(struct rkcodec_softc *sc, bool poweron) +{ + uint32_t val; + val = RKCODEC_READ(sc, CODEC_DAC_PRECHARGE_CTRL); + if (poweron) + val |= DAC_PRECHARGE_CTRL_DAC_CHARGE_PRECHARGE; + else + val &= ~(DAC_PRECHARGE_CTRL_DAC_CHARGE_PRECHARGE); + RKCODEC_WRITE(sc, CODEC_DAC_PRECHARGE_CTRL, val); + DELAY(10); + if (poweron) + val |= DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_ALL; + else + val &= ~(DAC_PRECHARGE_CTRL_DAC_CHARGE_CURRENT_ALL); + RKCODEC_WRITE(sc, CODEC_DAC_PRECHARGE_CTRL, val); + +} + +static void +rkcodec_set_mute(struct rkcodec_softc *sc, bool muted) +{ + uint32_t val; + val = SOC_CON10_GPIOMUT_MASK; + if (!muted) + val |= SOC_CON10_GPIOMUT; + SYSCON_WRITE_4(sc->grf, GRF_SOC_CON10, val); +} + +static void +rkcodec_reset(struct rkcodec_softc *sc) +{ + + RKCODEC_WRITE(sc, CODEC_RESET, 0); + DELAY(10); + RKCODEC_WRITE(sc, CODEC_RESET, RESET_DIG_CORE_RST | RESET_SYS_RST); +} + +static int +rkcodec_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Rockchip RK3328 CODEC"); + return (BUS_PROBE_DEFAULT); +} + +static int +rkcodec_attach(device_t dev) +{ + struct rkcodec_softc *sc; + int error, rid; + phandle_t node; + uint32_t val; + + sc = device_get_softc(dev); + sc->dev = dev; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + rid = 0; + sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (!sc->res) { + device_printf(dev, "could not allocate resource for device\n"); + error = ENXIO; + goto fail; + } + + node = ofw_bus_get_node(dev); + if (syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &sc->grf) != 0) { + device_printf(dev, "cannot get rockchip,grf handle\n"); + return (ENXIO); + } + + val = SOC_CON2_I2S_ACODEC_EN_MASK | (SOC_CON2_I2S_ACODEC_EN << 16); + SYSCON_WRITE_4(sc->grf, GRF_SOC_CON2, val); + + val = 0 | (SOC_CON10_GPIOMUT_EN << 16); + SYSCON_WRITE_4(sc->grf, GRF_SOC_CON10, val); + + error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk); + if (error != 0) { + device_printf(dev, "could not get pclk clock\n"); + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "mclk", &sc->mclk); + if (error != 0) { + device_printf(dev, "could not get mclk clock\n"); + goto fail; + } + + error = clk_enable(sc->pclk); + if (error != 0) { + device_printf(sc->dev, "could not enable pclk clock\n"); + goto fail; + } + + error = clk_enable(sc->mclk); + if (error != 0) { + device_printf(sc->dev, "could not enable mclk clock\n"); + goto fail; + } + +#if 0 + error = clk_set_freq(sc->mclk, DEFAULT_RATE, 0); + if (error != 0) { + device_printf(sc->dev, "could not set frequency for mclk clock\n"); + goto fail; + } +#endif + + /* TODO: handle mute-gpios */ + + rkcodec_reset(sc); + rkcodec_set_power(sc, true); + + val = RKCODEC_READ(sc, CODEC_DAC_PWR_CTRL); + val |= DAC_PWR_CTRL_DAC_PWR; + RKCODEC_WRITE(sc, CODEC_DAC_PWR_CTRL, val); + + val |= DAC_PWR_CTRL_DACL_PATH_REFV | + DAC_PWR_CTRL_DACR_PATH_REFV; + RKCODEC_WRITE(sc, CODEC_DAC_PWR_CTRL, val); + + val |= DAC_PWR_CTRL_HPOUTL_ZERO_CROSSING | + DAC_PWR_CTRL_HPOUTR_ZERO_CROSSING; + RKCODEC_WRITE(sc, CODEC_DAC_PWR_CTRL, val); + + val = RKCODEC_READ(sc, CODEC_HPOUT_POP_CTRL); + val |= HPOUT_POP_CTRL_HPOUTR_POP | HPOUT_POP_CTRL_HPOUTL_POP; + val &= ~(HPOUT_POP_CTRL_HPOUTR_POP_XCHARGE | HPOUT_POP_CTRL_HPOUTL_POP_XCHARGE); + RKCODEC_WRITE(sc, CODEC_HPOUT_POP_CTRL, val); + + val = RKCODEC_READ(sc, CODEC_HPMIX_CTRL); + val |= HPMIX_CTRL_HPMIXL_EN | HPMIX_CTRL_HPMIXR_EN; + RKCODEC_WRITE(sc, CODEC_HPMIX_CTRL, val); + + val |= HPMIX_CTRL_HPMIXL_INIT_EN | HPMIX_CTRL_HPMIXR_INIT_EN; + RKCODEC_WRITE(sc, CODEC_HPMIX_CTRL, val); + + val = RKCODEC_READ(sc, CODEC_HPOUT_CTRL); + val |= HPOUT_CTRL_HPOUTL_EN | HPOUT_CTRL_HPOUTR_EN; + RKCODEC_WRITE(sc, CODEC_HPOUT_CTRL, val); + + val |= HPOUT_CTRL_HPOUTL_INIT_EN | HPOUT_CTRL_HPOUTR_INIT_EN; + RKCODEC_WRITE(sc, CODEC_HPOUT_CTRL, val); + + val = RKCODEC_READ(sc, CODEC_DAC_CLK_CTRL); + val |= DAC_CLK_CTRL_DACL_REFV_ON | DAC_CLK_CTRL_DACR_REFV_ON; + RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val); + + val |= DAC_CLK_CTRL_DACL_CLK_ON | DAC_CLK_CTRL_DACR_CLK_ON; + RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val); + + val |= DAC_CLK_CTRL_DACL_ON | DAC_CLK_CTRL_DACR_ON; + RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val); + + val |= DAC_CLK_CTRL_DACL_INIT_ON | DAC_CLK_CTRL_DACR_INIT_ON; + RKCODEC_WRITE(sc, CODEC_DAC_CLK_CTRL, val); + + val = RKCODEC_READ(sc, CODEC_DAC_SELECT); + val |= DAC_SELECT_DACL_SELECT | DAC_SELECT_DACR_SELECT; + RKCODEC_WRITE(sc, CODEC_DAC_SELECT, val); + + val = RKCODEC_READ(sc, CODEC_HPMIX_CTRL); + val |= HPMIX_CTRL_HPMIXL_INIT2_EN | HPMIX_CTRL_HPMIXR_INIT2_EN; + RKCODEC_WRITE(sc, CODEC_HPMIX_CTRL, val); + + val = RKCODEC_READ(sc, CODEC_HPOUT_CTRL); + val |= HPOUT_CTRL_HPOUTL_UNMUTE | HPOUT_CTRL_HPOUTR_UNMUTE; + RKCODEC_WRITE(sc, CODEC_HPOUT_CTRL, val); + + RKCODEC_WRITE(sc, CODEC_HPOUTL_GAIN_CTRL, 0x1f); + RKCODEC_WRITE(sc, CODEC_HPOUTR_GAIN_CTRL, 0x1f); + + rkcodec_set_mute(sc, false); + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + rkcodec_detach(dev); + return (error); +} + +static int +rkcodec_detach(device_t dev) +{ + struct rkcodec_softc *sc; + + sc = device_get_softc(dev); + + if (sc->res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); + mtx_destroy(&sc->mtx); + + return (0); +} + +static int +rkcodec_mixer_init(struct snd_mixer *m) +{ + + mix_setdevs(m, RKCODEC_MIXER_DEVS); + + return (0); +} + +static int +rkcodec_mixer_uninit(struct snd_mixer *m) +{ + + return (0); +} + +static int +rkcodec_mixer_reinit(struct snd_mixer *m) +{ + + return (0); +} + +static int +rkcodec_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) +{ + struct rkcodec_softc *sc; + struct mtx *mixer_lock; + uint8_t do_unlock; + + sc = device_get_softc(mix_getdevinfo(m)); + mixer_lock = mixer_get_lock(m); + + if (mtx_owned(mixer_lock)) { + do_unlock = 0; + } else { + do_unlock = 1; + mtx_lock(mixer_lock); + } + + right = left; + + RKCODEC_LOCK(sc); + switch(dev) { + case SOUND_MIXER_VOLUME: + printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__); + break; + + case SOUND_MIXER_MIC: + printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__); + break; + default: + break; + } + RKCODEC_UNLOCK(sc); + + if (do_unlock) { + mtx_unlock(mixer_lock); + } + + return (left | (right << 8)); +} + +static unsigned +rkcodec_mixer_setrecsrc(struct snd_mixer *m, unsigned src) +{ + + return (0); +} + +static kobj_method_t rkcodec_mixer_methods[] = { + KOBJMETHOD(mixer_init, rkcodec_mixer_init), + KOBJMETHOD(mixer_uninit, rkcodec_mixer_uninit), + KOBJMETHOD(mixer_reinit, rkcodec_mixer_reinit), + KOBJMETHOD(mixer_set, rkcodec_mixer_set), + KOBJMETHOD(mixer_setrecsrc, rkcodec_mixer_setrecsrc), + KOBJMETHOD_END +}; + +MIXER_DECLARE(rkcodec_mixer); + +static int +rkcodec_dai_init(device_t dev, uint32_t format) +{ + struct rkcodec_softc *sc; + int fmt, pol, clk; + uint32_t ctrl1, ctrl2, ctrl3; + + sc = device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + ctrl1 = RKCODEC_READ(sc, CODEC_DAC_INIT_CTRL1); + ctrl2 = RKCODEC_READ(sc, CODEC_DAC_INIT_CTRL2); + ctrl3 = RKCODEC_READ(sc, CODEC_DAC_INIT_CTRL3); + + ctrl3 &= ~(DAC_INIT_CTRL3_DAC_BCP_MASK); + switch (pol) { + case AUDIO_DAI_POLARITY_IB_NF: + ctrl3 |= DAC_INIT_CTRL3_DAC_BCP_REVERSAL; + break; + case AUDIO_DAI_POLARITY_NB_NF: + ctrl3 |= DAC_INIT_CTRL3_DAC_BCP_NORMAL; + break; + default: + return (EINVAL); + } + + ctrl1 &= ~(DAC_INIT_CTRL1_MODE_MASK); + switch (clk) { + case AUDIO_DAI_CLOCK_CBM_CFM: + ctrl1 |= DAC_INIT_CTRL1_DIRECTION_OUT | + DAC_INIT_CTRL1_DAC_I2S_MODE_SLAVE; + break; + case AUDIO_DAI_CLOCK_CBS_CFS: + ctrl1 |= DAC_INIT_CTRL1_DIRECTION_IN | + DAC_INIT_CTRL1_DAC_I2S_MODE_SLAVE; + break; + default: + return (EINVAL); + } + + ctrl2 &= ~(DAC_INIT_CTRL2_DAC_VDL_MASK | DAC_INIT_CTRL2_DAC_MODE_MASK); + ctrl2 |= DAC_INIT_CTRL2_DAC_VDL_16BITS; + ctrl3 &= ~(DAC_INIT_CTRL3_WL_MASK); + ctrl3 |= DAC_INIT_CTRL3_WL_32BITS; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + ctrl2 |= DAC_INIT_CTRL2_DAC_MODE_I2S; + break; + case AUDIO_DAI_FORMAT_LJ: + ctrl2 |= DAC_INIT_CTRL2_DAC_MODE_LJM; + break; + case AUDIO_DAI_FORMAT_RJ: + ctrl2 |= DAC_INIT_CTRL2_DAC_MODE_RJM; + break; + default: + return EINVAL; + } + + ctrl3 &= ~(DAC_INIT_CTRL3_RST_MASK); + ctrl3 |= DAC_INIT_CTRL3_RST_DIS; + + RKCODEC_WRITE(sc, CODEC_DAC_INIT_CTRL1, ctrl1); + RKCODEC_WRITE(sc, CODEC_DAC_INIT_CTRL2, ctrl2); + RKCODEC_WRITE(sc, CODEC_DAC_INIT_CTRL3, ctrl3); + + return (0); +} + +static int +rkcodec_dai_trigger(device_t dev, int go, int pcm_dir) +{ + // struct rkcodec_softc *sc = device_get_softc(dev); + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + switch (go) { + case PCMTRIG_START: + if (pcm_dir == PCMDIR_PLAY) { + printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__); + } + else if (pcm_dir == PCMDIR_REC) { + printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__); + } + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + if (pcm_dir == PCMDIR_PLAY) { + printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__); + } + else if (pcm_dir == PCMDIR_REC) { + printf("[%s] %s:%d\n", __func__, __FILE__, __LINE__); + } + break; + } + + return (0); +} + +static int +rkcodec_dai_setup_mixer(device_t dev, device_t pcmdev) +{ + + mixer_init(pcmdev, &rkcodec_mixer_class, dev); + + return (0); +} + +static device_method_t rkcodec_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rkcodec_probe), + DEVMETHOD(device_attach, rkcodec_attach), + DEVMETHOD(device_detach, rkcodec_detach), + + DEVMETHOD(audio_dai_init, rkcodec_dai_init), + DEVMETHOD(audio_dai_setup_mixer, rkcodec_dai_setup_mixer), + DEVMETHOD(audio_dai_trigger, rkcodec_dai_trigger), + + DEVMETHOD_END +}; + +static driver_t rkcodec_driver = { + "rk3328codec", + rkcodec_methods, + sizeof(struct rkcodec_softc), +}; + +static devclass_t rkcodec_devclass; + +DRIVER_MODULE(rkcodec, simplebus, rkcodec_driver, rkcodec_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/arm64/rockchip/rk_i2s.c b/sys/arm64/rockchip/rk_i2s.c new file mode 100644 index 00000000000..8f53d8581d5 --- /dev/null +++ b/sys/arm64/rockchip/rk_i2s.c @@ -0,0 +1,657 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include "syscon_if.h" + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" + +#define AUDIO_BUFFER_SIZE 48000 * 4 + +#define I2S_TXCR 0x0000 +#define I2S_CSR_2 (0 << 15) +#define I2S_CSR_4 (1 << 15) +#define I2S_CSR_6 (2 << 15) +#define I2S_CSR_8 (3 << 15) +#define I2S_TXCR_IBM_NORMAL (0 << 9) +#define I2S_TXCR_IBM_LJ (1 << 9) +#define I2S_TXCR_IBM_RJ (2 << 9) +#define I2S_TXCR_PBM_NODELAY (0 << 7) +#define I2S_TXCR_PBM_1 (1 << 7) +#define I2S_TXCR_PBM_2 (2 << 7) +#define I2S_TXCR_PBM_3 (3 << 7) +#define I2S_TXCR_TFS_I2S (0 << 5) +#define I2S_TXCR_TFS_PCM (1 << 5) +#define I2S_TXCR_VDW_16 (0xf << 0) +#define I2S_RXCR 0x0004 +#define I2S_RXCR_IBM_NORMAL (0 << 9) +#define I2S_RXCR_IBM_LJ (1 << 9) +#define I2S_RXCR_IBM_RJ (2 << 9) +#define I2S_RXCR_PBM_NODELAY (0 << 7) +#define I2S_RXCR_PBM_1 (1 << 7) +#define I2S_RXCR_PBM_2 (2 << 7) +#define I2S_RXCR_PBM_3 (3 << 7) +#define I2S_RXCR_TFS_I2S (0 << 5) +#define I2S_RXCR_TFS_PCM (1 << 5) +#define I2S_RXCR_VDW_16 (0xf << 0) +#define I2S_CKR 0x0008 +#define I2S_CKR_MSS_MASK (1 << 27) +#define I2S_CKR_MSS_MASTER (0 << 27) +#define I2S_CKR_MSS_SLAVE (1 << 27) +#define I2S_CKR_CKP (1 << 26) +#define I2S_CKR_MDIV(n) (((n) - 1) << 16) +#define I2S_CKR_MDIV_MASK (0xff << 16) +#define I2S_CKR_RSD(n) (((n) - 1) << 8) +#define I2S_CKR_RSD_MASK (0xff << 8) +#define I2S_CKR_TSD(n) (((n) - 1) << 0) +#define I2S_CKR_TSD_MASK (0xff << 0) +#define I2S_TXFIFOLR 0x000c +#define TXFIFO0LR_MASK 0x3f +#define I2S_DMACR 0x0010 +#define I2S_DMACR_RDE_ENABLE (1 << 24) +#define I2S_DMACR_RDL(n) ((n) << 16) +#define I2S_DMACR_TDE_ENABLE (1 << 8) +#define I2S_DMACR_TDL(n) ((n) << 0) +#define I2S_INTCR 0x0014 +#define I2S_INTCR_RFT(n) (((n) - 1) << 20) +#define I2S_INTCR_TFT(n) (((n) - 1) << 4) +#define I2S_INTCR_RXFIE (1 << 16) +#define I2S_INTCR_TXUIC (1 << 2) +#define I2S_INTCR_TXEIE (1 << 0) +#define I2S_INTSR 0x0018 +#define I2S_INTSR_RXFI (1 << 16) +#define I2S_INTSR_TXUI (1 << 1) +#define I2S_INTSR_TXEI (1 << 0) +#define I2S_XFER 0x001c +#define I2S_XFER_RXS_START (1 << 1) +#define I2S_XFER_TXS_START (1 << 0) +#define I2S_CLR 0x0020 +#define I2S_CLR_RXC (1 << 1) +#define I2S_CLR_TXC (1 << 0) +#define I2S_TXDR 0x0024 +#define I2S_RXDR 0x0028 +#define I2S_RXFIFOLR 0x002c +#define RXFIFO0LR_MASK 0x3f + +/* syscon */ +#define GRF_SOC_CON8 0xe220 +#define I2S_IO_DIRECTION_MASK 7 +#define I2S_IO_DIRECTION_SHIFT 11 +#define I2S_IO_8CH_OUT_2CH_IN 0 +#define I2S_IO_6CH_OUT_4CH_IN 4 +#define I2S_IO_4CH_OUT_6CH_IN 6 +#define I2S_IO_2CH_OUT_8CH_IN 7 + +#define DIV_ROUND_CLOSEST(n,d) (((n) + (d) / 2) / (d)) + +#define RK_I2S_SAMPLING_RATE 48000 +#define FIFO_SIZE 32 + +static struct ofw_compat_data compat_data[] = { + { "rockchip,rk3066-i2s", 1 }, + { "rockchip,rk3399-i2s", 1 }, + { NULL, 0 } +}; + +static struct resource_spec rk_i2s_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +struct rk_i2s_softc { + device_t dev; + struct resource *res[2]; + struct mtx mtx; + clk_t clk; + clk_t hclk; + void * intrhand; + struct syscon *grf; + /* pointers to playback/capture buffers */ + uint32_t play_ptr; + uint32_t rec_ptr; +}; + +#define RK_I2S_LOCK(sc) mtx_lock(&(sc)->mtx) +#define RK_I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define RK_I2S_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define RK_I2S_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) + +static int rk_i2s_probe(device_t dev); +static int rk_i2s_attach(device_t dev); +static int rk_i2s_detach(device_t dev); + +static uint32_t sc_fmt[] = { + SND_FORMAT(AFMT_S16_LE, 2, 0), + 0 +}; +static struct pcmchan_caps rk_i2s_caps = {RK_I2S_SAMPLING_RATE, RK_I2S_SAMPLING_RATE, sc_fmt, 0}; + + +static int +rk_i2s_init(struct rk_i2s_softc *sc) +{ + uint32_t val; + int error; + + clk_set_freq(sc->clk, RK_I2S_SAMPLING_RATE * 256, + CLK_SET_ROUND_DOWN); + error = clk_enable(sc->clk); + if (error != 0) { + device_printf(sc->dev, "cannot enable i2s_clk clock\n"); + return (ENXIO); + } + + val = I2S_INTCR_TFT(FIFO_SIZE/2); + val |= I2S_INTCR_RFT(FIFO_SIZE/2); + RK_I2S_WRITE_4(sc, I2S_INTCR, val); + + if (sc->grf) { + val = (I2S_IO_2CH_OUT_8CH_IN << I2S_IO_DIRECTION_SHIFT); + val |= (I2S_IO_DIRECTION_MASK << I2S_IO_DIRECTION_SHIFT) << 16; + SYSCON_WRITE_4(sc->grf, GRF_SOC_CON8, val); + + #if 0 + // HACK: enable IO domain + val = (1 << 1); + val |= (1 << 1) << 16; + SYSCON_WRITE_4(sc->grf, 0xe640, val); + #endif + } + + RK_I2S_WRITE_4(sc, I2S_XFER, 0); + + return (0); +} + +static int +rk_i2s_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Rockchip I2S"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk_i2s_attach(device_t dev) +{ + struct rk_i2s_softc *sc; + int error; + phandle_t node; + + sc = device_get_softc(dev); + sc->dev = dev; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + if (bus_alloc_resources(dev, rk_i2s_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "i2s_hclk", &sc->hclk); + if (error != 0) { + device_printf(dev, "cannot get i2s_hclk clock\n"); + goto fail; + } + + error = clk_get_by_ofw_name(dev, 0, "i2s_clk", &sc->clk); + if (error != 0) { + device_printf(dev, "cannot get i2s_clk clock\n"); + goto fail; + } + + /* Activate the module clock. */ + error = clk_enable(sc->hclk); + if (error != 0) { + device_printf(dev, "cannot enable i2s_hclk clock\n"); + goto fail; + } + + node = ofw_bus_get_node(dev); + if (OF_hasprop(node, "rockchip,grf") && + syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &sc->grf) != 0) { + device_printf(dev, "cannot get grf driver handle\n"); + return (ENXIO); + } + + rk_i2s_init(sc); + + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); + +fail: + rk_i2s_detach(dev); + return (error); +} + +static int +rk_i2s_detach(device_t dev) +{ + struct rk_i2s_softc *i2s; + + i2s = device_get_softc(dev); + + if (i2s->hclk != NULL) + clk_release(i2s->hclk); + if (i2s->clk) + clk_release(i2s->clk); + + if (i2s->intrhand != NULL) + bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); + + bus_release_resources(dev, rk_i2s_spec, i2s->res); + mtx_destroy(&i2s->mtx); + + return (0); +} + +static int +rk_i2s_dai_init(device_t dev, uint32_t format) +{ + uint32_t val, txcr, rxcr; + struct rk_i2s_softc *sc; + int fmt, pol, clk; + + sc = device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + /* Set format */ + val = RK_I2S_READ_4(sc, I2S_CKR); + + val &= ~(I2S_CKR_MSS_MASK); + switch (clk) { + case AUDIO_DAI_CLOCK_CBM_CFM: + val |= I2S_CKR_MSS_MASTER; + break; + case AUDIO_DAI_CLOCK_CBS_CFS: + val |= I2S_CKR_MSS_SLAVE; + break; + default: + return (EINVAL); + } + + switch (pol) { + case AUDIO_DAI_POLARITY_IB_NF: + val |= I2S_CKR_CKP; + break; + case AUDIO_DAI_POLARITY_NB_NF: + val &= ~I2S_CKR_CKP; + break; + default: + return (EINVAL); + } + + RK_I2S_WRITE_4(sc, I2S_CKR, val); + + txcr = I2S_TXCR_VDW_16 | I2S_CSR_2; + rxcr = I2S_RXCR_VDW_16 | I2S_CSR_2; + + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + txcr |= I2S_TXCR_IBM_NORMAL; + rxcr |= I2S_RXCR_IBM_NORMAL; + break; + case AUDIO_DAI_FORMAT_LJ: + txcr |= I2S_TXCR_IBM_LJ; + rxcr |= I2S_RXCR_IBM_LJ; + break; + case AUDIO_DAI_FORMAT_RJ: + txcr |= I2S_TXCR_IBM_RJ; + rxcr |= I2S_RXCR_IBM_RJ; + break; + case AUDIO_DAI_FORMAT_DSPA: + txcr |= I2S_TXCR_TFS_PCM; + rxcr |= I2S_RXCR_TFS_PCM; + txcr |= I2S_TXCR_PBM_1; + rxcr |= I2S_RXCR_PBM_1; + break; + case AUDIO_DAI_FORMAT_DSPB: + txcr |= I2S_TXCR_TFS_PCM; + rxcr |= I2S_RXCR_TFS_PCM; + txcr |= I2S_TXCR_PBM_2; + rxcr |= I2S_RXCR_PBM_2; + break; + default: + return EINVAL; + } + + RK_I2S_WRITE_4(sc, I2S_TXCR, txcr); + RK_I2S_WRITE_4(sc, I2S_RXCR, rxcr); + + RK_I2S_WRITE_4(sc, I2S_XFER, 0); + + return (0); +} + + +static int +rk_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) +{ + struct rk_i2s_softc *sc; + uint32_t status; + uint32_t level; + uint32_t val = 0x00; + int ret = 0; + + sc = device_get_softc(dev); + + RK_I2S_LOCK(sc); + status = RK_I2S_READ_4(sc, I2S_INTSR); + + if (status & I2S_INTSR_TXEI) { + level = RK_I2S_READ_4(sc, I2S_TXFIFOLR) & TXFIFO0LR_MASK; + uint8_t *samples; + uint32_t count, size, readyptr, written; + count = sndbuf_getready(play_buf); + size = sndbuf_getsize(play_buf); + readyptr = sndbuf_getreadyptr(play_buf); + + /* FIXME: check actual count size */ + samples = (uint8_t*)sndbuf_getbuf(play_buf); + written = 0; + for (; level < FIFO_SIZE - 1; level++) { + val = (samples[readyptr++ % size] << 0); + val |= (samples[readyptr++ % size] << 8); + val |= (samples[readyptr++ % size] << 16); + val |= (samples[readyptr++ % size] << 24); + written += 4; + RK_I2S_WRITE_4(sc, I2S_TXDR, val); + } + sc->play_ptr += written; + sc->play_ptr %= size; + ret |= AUDIO_DAI_PLAY_INTR; + } + + if (status & I2S_INTSR_RXFI) { + level = RK_I2S_READ_4(sc, I2S_RXFIFOLR) & RXFIFO0LR_MASK; + uint8_t *samples; + uint32_t count, size, freeptr, recorded; + count = sndbuf_getfree(rec_buf); + size = sndbuf_getsize(rec_buf); + freeptr = sndbuf_getfreeptr(rec_buf); + samples = (uint8_t*)sndbuf_getbuf(rec_buf); + recorded = 0; + if (level > count / 4) + level = count / 4; + + for (; level > 0; level--) { + val = RK_I2S_READ_4(sc, I2S_RXDR); + samples[freeptr++ % size] = val & 0xff; + samples[freeptr++ % size] = (val >> 8) & 0xff; + samples[freeptr++ % size] = (val >> 16) & 0xff; + samples[freeptr++ % size] = (val >> 24) & 0xff; + recorded += 4; + } + sc->rec_ptr += recorded; + sc->rec_ptr %= size; + ret |= AUDIO_DAI_REC_INTR; + } + + RK_I2S_UNLOCK(sc); + + return (ret); +} + +static struct pcmchan_caps * +rk_i2s_dai_get_caps(device_t dev) +{ + return (&rk_i2s_caps); +} + +static int +rk_i2s_dai_trigger(device_t dev, int go, int pcm_dir) +{ + struct rk_i2s_softc *sc = device_get_softc(dev); + uint32_t val; + uint32_t clear_bit; + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + switch (go) { + case PCMTRIG_START: + val = RK_I2S_READ_4(sc, I2S_INTCR); + if (pcm_dir == PCMDIR_PLAY) + val |= I2S_INTCR_TXEIE; + else if (pcm_dir == PCMDIR_REC) + val |= I2S_INTCR_RXFIE; + RK_I2S_WRITE_4(sc, I2S_INTCR, val); + + val = I2S_XFER_TXS_START | I2S_XFER_RXS_START; + RK_I2S_WRITE_4(sc, I2S_XFER, val); + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + val = RK_I2S_READ_4(sc, I2S_INTCR); + if (pcm_dir == PCMDIR_PLAY) + val &= ~I2S_INTCR_TXEIE; + else if (pcm_dir == PCMDIR_REC) + val &= ~I2S_INTCR_RXFIE; + RK_I2S_WRITE_4(sc, I2S_INTCR, val); + + /* + * If there is no other activity going on, stop transfers + */ + if ((val & (I2S_INTCR_TXEIE | I2S_INTCR_RXFIE)) == 0) { + RK_I2S_WRITE_4(sc, I2S_XFER, 0); + + if (pcm_dir == PCMDIR_PLAY) + clear_bit = I2S_CLR_TXC; + else if (pcm_dir == PCMDIR_REC) + clear_bit = I2S_CLR_RXC; + else + return (EINVAL); + + val = RK_I2S_READ_4(sc, I2S_CLR); + val |= clear_bit; + RK_I2S_WRITE_4(sc, I2S_CLR, val); + + while ((RK_I2S_READ_4(sc, I2S_CLR) & clear_bit) != 0) + DELAY(1); + } + + RK_I2S_LOCK(sc); + if (pcm_dir == PCMDIR_PLAY) + sc->play_ptr = 0; + else + sc->rec_ptr = 0; + RK_I2S_UNLOCK(sc); + break; + } + + return (0); +} + +static uint32_t +rk_i2s_dai_get_ptr(device_t dev, int pcm_dir) +{ + struct rk_i2s_softc *sc; + uint32_t ptr; + + sc = device_get_softc(dev); + + RK_I2S_LOCK(sc); + if (pcm_dir == PCMDIR_PLAY) + ptr = sc->play_ptr; + else + ptr = sc->rec_ptr; + RK_I2S_UNLOCK(sc); + + return ptr; +} + +static int +rk_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) +{ + struct rk_i2s_softc *sc = device_get_softc(dev); + + if (bus_setup_intr(dev, sc->res[1], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, + &sc->intrhand)) { + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + return (0); +} + +static uint32_t +rk_i2s_dai_set_chanformat(device_t dev, uint32_t format) +{ + + return (0); +} + +static int +rk_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) +{ + struct rk_i2s_softc *sc; + int error; + + sc = device_get_softc(dev); + error = clk_disable(sc->clk); + if (error != 0) { + device_printf(sc->dev, "could not disable i2s_clk clock\n"); + return (error); + } + + error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN); + if (error != 0) + device_printf(sc->dev, "could not set i2s_clk freq\n"); + + error = clk_enable(sc->clk); + if (error != 0) { + device_printf(sc->dev, "could not enable i2s_clk clock\n"); + return (error); + } + + return (0); +} + +static uint32_t +rk_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) +{ + struct rk_i2s_softc *sc; + int error; + uint32_t val; + uint32_t bus_clock_div, lr_clock_div; + uint64_t bus_clk_freq; + uint64_t clk_freq; + + sc = device_get_softc(dev); + + /* Set format */ + val = RK_I2S_READ_4(sc, I2S_CKR); + + if ((val & I2S_CKR_MSS_SLAVE) == 0) { + error = clk_get_freq(sc->clk, &clk_freq); + if (error != 0) { + device_printf(sc->dev, "failed to get clk frequency: err=%d\n", error); + return (error); + } + bus_clk_freq = 2 * 32 * speed; + bus_clock_div = DIV_ROUND_CLOSEST(clk_freq, bus_clk_freq); + lr_clock_div = bus_clk_freq / speed; + + val &= ~(I2S_CKR_MDIV_MASK | I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK); + val |= I2S_CKR_MDIV(bus_clock_div); + val |= I2S_CKR_RSD(lr_clock_div); + val |= I2S_CKR_TSD(lr_clock_div); + + RK_I2S_WRITE_4(sc, I2S_CKR, val); + } + + return (speed); +} + +static device_method_t rk_i2s_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk_i2s_probe), + DEVMETHOD(device_attach, rk_i2s_attach), + DEVMETHOD(device_detach, rk_i2s_detach), + + DEVMETHOD(audio_dai_init, rk_i2s_dai_init), + DEVMETHOD(audio_dai_setup_intr, rk_i2s_dai_setup_intr), + DEVMETHOD(audio_dai_set_sysclk, rk_i2s_dai_set_sysclk), + DEVMETHOD(audio_dai_set_chanspeed, rk_i2s_dai_set_chanspeed), + DEVMETHOD(audio_dai_set_chanformat, rk_i2s_dai_set_chanformat), + DEVMETHOD(audio_dai_intr, rk_i2s_dai_intr), + DEVMETHOD(audio_dai_get_caps, rk_i2s_dai_get_caps), + DEVMETHOD(audio_dai_trigger, rk_i2s_dai_trigger), + DEVMETHOD(audio_dai_get_ptr, rk_i2s_dai_get_ptr), + + DEVMETHOD_END +}; + +static driver_t rk_i2s_driver = { + "i2s", + rk_i2s_methods, + sizeof(struct rk_i2s_softc), +}; + +static devclass_t rk_i2s_devclass; + +DRIVER_MODULE(rk_i2s, simplebus, rk_i2s_driver, rk_i2s_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/conf/files b/sys/conf/files index da06f0250d3..3360bb6acfb 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -1780,6 +1780,7 @@ dev/iicbus/ds1307.c optional ds1307 dev/iicbus/ds13rtc.c optional ds13rtc | ds133x | ds1374 dev/iicbus/ds1672.c optional ds1672 dev/iicbus/ds3231.c optional ds3231 +dev/iicbus/es8316.c optional es8316codec dev/iicbus/syr827.c optional syr827 ext_resources fdt dev/iicbus/icee.c optional icee dev/iicbus/if_ic.c optional ic @@ -1803,8 +1804,9 @@ dev/iicbus/mux/iic_gpiomux.c optional iic_gpiomux fdt dev/iicbus/mux/ltc430x.c optional ltc430x dev/iicbus/nxprtc.c optional nxprtc | pcf8563 dev/iicbus/ofw_iicbus.c optional fdt iicbus -dev/iicbus/rtc8583.c optional rtc8583 +dev/iicbus/rt5640.c optional rt5640codec dev/iicbus/rtc/rx8803.c optional rx8803 iicbus fdt +dev/iicbus/rtc8583.c optional rtc8583 dev/iicbus/s35390a.c optional s35390a dev/iicbus/sy8106a.c optional sy8106a ext_resources fdt dev/iicbus/gpio/tca6416.c optional tca6416 fdt diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index f17c53a7869..36065e8bfc1 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -28,9 +28,11 @@ cloudabi64_vdso_blob.o optional compat_cloudabi64 \ arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac +arm/allwinner/a64/sun50i_a64_acodec.c optional fdt sound arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt +arm/allwinner/aw_i2s.c optional fdt sound arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ @@ -47,6 +49,7 @@ arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt +arm/allwinner/sun8i_codec.c optional fdt sound # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt @@ -325,6 +328,10 @@ dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt +dev/sound/fdt/audio_dai_if.m optional sound fdt +dev/sound/fdt/audio_soc.c optional sound fdt +dev/sound/fdt/dummy_codec.c optional sound fdt +dev/sound/fdt/simple_amplifier.c optional sound fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 @@ -367,8 +374,10 @@ cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with " # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 +arm64/rockchip/rk3328_codec.c optional fdt rk3328codec soc_rockchip_rk3328 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 +arm64/rockchip/rk_i2s.c optional fdt sound soc_rockchip_rk3328 | fdt sound soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 diff --git a/sys/dev/iicbus/es8316.c b/sys/dev/iicbus/es8316.c new file mode 100644 index 00000000000..18d51c83b60 --- /dev/null +++ b/sys/dev/iicbus/es8316.c @@ -0,0 +1,628 @@ +/*- + * Copyright (c) 2019 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Driver for Realtek es8316 audio codec + */ + +#include "opt_platform.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef FDT +#include +#include +#endif + +#include + +#include +#include +#include + +#include +#include + +#include "iicbus_if.h" +#include "mixer_if.h" +#include "audio_dai_if.h" + +#define MAX_BUFFER 16 + +#define ESCODEC_RESET_REG 0x00 +#define RESET_ALL 0x3f +#define RESET_CSM_ON (1 << 7) +#define ESCODEC_CLKMAN1_REG 0x01 +#define CLKMAN1_MCLK_ON (1 << 6) +#define CLKMAN1_BCLK_ON (1 << 5) +#define CLKMAN1_CLK_CP_ON (1 << 4) +#define CLKMAN1_CLK_ADC_ON (1 << 3) +#define CLKMAN1_CLK_DAC_ON (1 << 2) +#define CLKMAN1_ANACLK_ADC_ON (1 << 1) +#define CLKMAN1_ANACLK_DAC_ON (1 << 0) +#define ESCODEC_ADC_OSR_REG 0x03 +#define ESCODEC_SD_CLK_REG 0x09 +#define SD_CLK_MSC (1 << 7) +#define SD_CLK_BCLK_INV (1 << 5) +#define ESCODEC_SD_ADC_REG 0x0a +#define ESCODEC_SD_DAC_REG 0x0b +#define SD_FMT_LRP (1 << 5) +#define SD_FMT_WL_MASK (7 << 2) +#define SD_FMT_WL_SHIFT 2 +#define SD_FMT_WL_16 3 +#define SD_FMT_MASK (3 << 0) +#define SD_FMT_SHIFT 0 +#define SD_FMT_I2S 0 +#define ESCODEC_VMID_REG 0x0c +#define ESCODEC_PDN_REG 0x0d +#define ESCODEC_LP1_REG 0x0e +#define ESCODEC_LP2_REG 0x0f +#define ESCODEC_HPSEL_REG 0x13 +#define ESCODEC_HPMIXRT_REG 0x14 +#define HPMIXRT_LD2LHPMIX (1 << 7) +#define HPMIXRT_RD2RHPMIX (1 << 3) +#define ESCODEC_HPMIX_REG 0x15 +#define HPMIX_LHPMIX_MUTE (1 << 5) +#define HPMIX_PDN_LHP_MIX (1 << 4) +#define HPMIX_RHPMIX_MUTE (1 << 1) +#define HPMIX_PDN_RHP_MIX (1 << 0) +#define ESCODEC_HPMIXVOL_REG 0x16 +#define HPMIXVOL_LHPMIXVOL_MASK (0xf << 4) +#define HPMIXVOL_LHPMIXVOL(v) (((v) & 0xf) << 4) +#define HPMIXVOL_RHPMIXVOL_MASK (0xf << 0) +#define HPMIXVOL_RHPMIXVOL(v) (((v) & 0xf) << 0) +#define ESCODEC_HPOUTEN_REG 0x17 +#define HPOUTEN_EN_HPL (1 << 6) +#define HPOUTEN_HPL_OUTEN (1 << 5) +#define HPOUTEN_EN_HPR (1 << 2) +#define HPOUTEN_HPR_OUTEN (1 << 1) +#define ESCODEC_HPVOL_REG 0x18 +#define HPVOL_PDN_LICAL (1 << 7) +#define HPVOL_HPLVOL __BITS(5,4) +#define HPVOL_PDN_RICAL (1 << 3) +#define HPVOL_HPRVOL __BITS(1,0) +#define ESCODEC_HPPWR_REG 0x19 +#define HPPWR_PDN_CPHP (1 << 2) +#define ESCODEC_CPPWR_REG 0x1a +#define CPPWR_PDN_CP (1 << 5) +#define CPPWR_CI_HIPWR (1 << 4) +#define ESCODEC_LDOCTL_REG 0x1b +#define LDOCTL_LDOLVL_1_45 (3 << 4) +#define ESCODEC_ADCSEL_REG 0x22 +#define ADCSEL_PDN_AINL (1 << 7) +#define ADCSEL_PDN_MODL (1 << 6) +#define ADCSEL_LINSEL_MASK (3 << 4) +#define ADCSEL_LINSEL_LIN1 (0 << 4) +#define ADCSEL_LINSEL_LIN2 (1 << 4) +#define ESCODEC_ADC_VOLUME 0x27 +#define ADC_VOLUME_ADCVOLUMEL_MAX 0xc0 +#define ESCODEC_DACPWR_REG 0x2f +#define DACPWR_PDN_DAC_L (1 << 4) +#define DACPWR_PDN_DAC_R (1 << 0) +#define ESCODEC_DACCTL1_REG 0x30 +#define DACCTL1_MUTE (1 << 5) +#define ESCODEC_DACVOL_L_REG 0x33 +#define DACVOL_L_DACVOLUME_MASK 0xff +#define DACVOL_L_DACVOLUME_MAX 0xc0 +#define ESCODEC_DACVOL_R_REG 0x34 +#define DACVOL_R_DACVOLUME_MASK 0xff +#define DACVOL_R_DACVOLUME_MAX 0xc0 + +#define ES8316_MIXER_DEVS (SOUND_MASK_VOLUME | SOUND_MASK_MIC) + +#define ADC_SRC_LIN1_RIN1 1 +#define ADC_SRC_LIN2_RIN2 2 + +struct es8316_softc { + device_t dev; + device_t busdev; + struct intr_config_hook + init_hook; + clk_t clk; + int adc_src; +}; + +#ifdef FDT +static struct ofw_compat_data compat_data[] = { + {"everest,es8316", 1}, + {NULL, 0}, +}; +#endif + +static void es8316_init(void *arg); +static int es8316_probe(device_t dev); +static int es8316_attach(device_t dev); +static int es8316_detach(device_t dev); + +static inline int +es8316_read(struct es8316_softc *sc, uint8_t reg, uint8_t *data) +{ + int res; + res = iicdev_readfrom(sc->dev, reg, data, 1, IIC_WAIT); + if (res != 0) + *data = 0xff; + return (res); +} + +static inline int +es8316_write(struct es8316_softc *sc, uint8_t reg, uint8_t val) +{ + + return (iicdev_writeto(sc->dev, reg, &val, 1, IIC_WAIT)); +} + +static void +es8316_init(void *arg) +{ + struct es8316_softc *sc; + + sc = (struct es8316_softc*)arg; + config_intrhook_disestablish(&sc->init_hook); +} + +static int +es8316_mixer_init(struct snd_mixer *m) +{ + mix_setdevs(m, ES8316_MIXER_DEVS); + + return (0); +} + +static int +es8316_mixer_uninit(struct snd_mixer *m) +{ + + return (0); +} + +static int +es8316_mixer_reinit(struct snd_mixer *m) +{ + + return (0); +} + +static int +es8316_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) +{ + struct es8316_softc *sc; + struct mtx *mixer_lock; + int locked; + uint8_t val; + + sc = device_get_softc(mix_getdevinfo(m)); + mixer_lock = mixer_get_lock(m); + locked = mtx_owned(mixer_lock); + + /* + * We need to unlock the mixer lock because iicbus_transfer() + * may sleep. The mixer lock itself is unnecessary here + * because it is meant to serialize hardware access, which + * is taken care of by the I2C layer, so this is safe. + */ + if (locked) + mtx_unlock(mixer_lock); + switch (dev) { + case SOUND_MIXER_VOLUME: + val = DACVOL_L_DACVOLUME_MAX - (left * DACVOL_L_DACVOLUME_MAX / 100); + es8316_write(sc, ESCODEC_DACVOL_L_REG, val); + val = DACVOL_R_DACVOLUME_MAX - (right * DACVOL_R_DACVOLUME_MAX / 100); + es8316_write(sc, ESCODEC_DACVOL_R_REG, val); + return (left | (right << 8)); + case SOUND_MIXER_MIC: + /* + * Force 100% for now. Without boost microphone level declines prety rapidly + * and at 85% it's mostly silence. For demonstration purposes just keep at 100% + * for now. + */ + left = right = 100; + val = ADC_VOLUME_ADCVOLUMEL_MAX - (left * ADC_VOLUME_ADCVOLUMEL_MAX / 100); + es8316_write(sc, ESCODEC_ADC_VOLUME, val); + return (left | (right << 8)); + default: + break; + } + + if (locked) + mtx_lock(mixer_lock); + + return (0); +} + +static u_int32_t +es8316_mixer_setrecsrc(struct snd_mixer *m, u_int32_t src) +{ + + return (0); +} + +static kobj_method_t es8316_mixer_methods[] = { + KOBJMETHOD(mixer_init, es8316_mixer_init), + KOBJMETHOD(mixer_uninit, es8316_mixer_uninit), + KOBJMETHOD(mixer_reinit, es8316_mixer_reinit), + KOBJMETHOD(mixer_set, es8316_mixer_set), + KOBJMETHOD(mixer_setrecsrc, es8316_mixer_setrecsrc), + KOBJMETHOD_END +}; + +MIXER_DECLARE(es8316_mixer); + +static int +es8316_set_rec_src(struct es8316_softc *sc, int lin) +{ + uint8_t val; + + es8316_read(sc, ESCODEC_ADCSEL_REG, &val); + val &= ~(ADCSEL_LINSEL_MASK); + if (lin == ADC_SRC_LIN1_RIN1) + val |= ADCSEL_LINSEL_LIN1; + else if (lin == ADC_SRC_LIN2_RIN2) + val |= ADCSEL_LINSEL_LIN2; + else + return (EINVAL); + + sc->adc_src = lin; + es8316_write(sc, ESCODEC_ADCSEL_REG, val); + + return (0); +} + +static int +es8316_sysctl_audio_src(SYSCTL_HANDLER_ARGS) +{ + struct es8316_softc *sc = arg1; + int val; + int err; + + val = sc->adc_src; + err = sysctl_handle_int(oidp, &val, 0, req); + if (err || !req->newptr) /* error || read request */ + return (err); + + return es8316_set_rec_src(sc, val); +} + +static int +es8316_probe(device_t dev) +{ + +#ifdef FDT + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { + device_set_desc(dev, "Everest Semi ES8316 CODEC"); + return (BUS_PROBE_DEFAULT); + } +#endif + return (ENXIO); +} + +static int +es8316_attach(device_t dev) +{ + struct es8316_softc *sc; + int error; + phandle_t node; + uint8_t val; + struct sysctl_ctx_list *ctx; + struct sysctl_oid *tree_node; + struct sysctl_oid_list *tree; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->busdev = device_get_parent(sc->dev); + + error = clk_get_by_ofw_name(dev, 0, "mclk", &sc->clk); + if (error != 0) { + device_printf(dev, "cannot get mclk clock\n"); + return (ENXIO); + } + + clk_enable(sc->clk); + + /* + * Wait until i2c is ready to set up the chip + */ + sc->init_hook.ich_func = es8316_init; + sc->init_hook.ich_arg = sc; + if (config_intrhook_establish(&sc->init_hook) != 0) + return (ENOMEM); + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + es8316_write(sc, ESCODEC_RESET_REG, RESET_ALL); + DELAY(5); + es8316_write(sc, ESCODEC_RESET_REG, RESET_CSM_ON); + DELAY(30); + + es8316_write(sc, ESCODEC_VMID_REG, 0xff); + es8316_write(sc, ESCODEC_ADC_OSR_REG, 0x32); + + es8316_read(sc, ESCODEC_SD_ADC_REG, &val); + val &= ~SD_FMT_WL_MASK; + val |= (SD_FMT_WL_16 << SD_FMT_WL_SHIFT); + es8316_write(sc, ESCODEC_SD_ADC_REG, val); + + es8316_read(sc, ESCODEC_SD_DAC_REG, &val); + val &= ~SD_FMT_WL_MASK; + val |= (SD_FMT_WL_16 << SD_FMT_WL_SHIFT); + es8316_write(sc, ESCODEC_SD_DAC_REG, val); + + /* Power up */ + es8316_write(sc, ESCODEC_PDN_REG, 0); + + /* Route DAC signal to HP mixer */ + val = HPMIXRT_LD2LHPMIX | HPMIXRT_RD2RHPMIX; + es8316_write(sc, ESCODEC_HPMIXRT_REG, val); + + /* Power up DAC */ + es8316_write(sc, ESCODEC_DACPWR_REG, 0); + + /* Power up HP mixer and unmute */ + es8316_write(sc, ESCODEC_HPMIX_REG, (1 << 3) | (1<<7)); + + /* Power up HP output driver */ + es8316_read(sc, ESCODEC_HPPWR_REG, &val); + val &= ~HPPWR_PDN_CPHP; + es8316_write(sc, ESCODEC_HPPWR_REG, val); + + /* Power up HP charge pump circuits */ + es8316_read(sc, ESCODEC_CPPWR_REG, &val); + val &= ~CPPWR_PDN_CP; + val |= CPPWR_CI_HIPWR; + es8316_write(sc, ESCODEC_CPPWR_REG, val); + + /* Power up CP negative regulator */ + es8316_write(sc, ESCODEC_LDOCTL_REG, LDOCTL_LDOLVL_1_45); + + /* Enable low power mode */ + es8316_write(sc, ESCODEC_LP1_REG, 0x3f); + es8316_write(sc, ESCODEC_LP2_REG, 0x1f); + + /* Set LIN1/RIN1 as inputs for HP mixer */ + es8316_write(sc, ESCODEC_HPSEL_REG, 0); + + /* Set LIN2/RIN2 as inputs for ADC and power up ADC/PGA */ + es8316_read(sc, ESCODEC_ADCSEL_REG, &val); + val &= ~(ADCSEL_PDN_AINL | ADCSEL_PDN_MODL); + es8316_write(sc, ESCODEC_ADCSEL_REG, val); + + es8316_set_rec_src(sc, ADC_SRC_LIN2_RIN2); + + /* Power up HP output driver calibration */ + es8316_read(sc, ESCODEC_HPVOL_REG, &val); + val &= ~HPVOL_PDN_LICAL; + val &= ~HPVOL_PDN_RICAL; + es8316_write(sc, ESCODEC_HPVOL_REG, val); + + /* Set headphone mixer to 0dB */ + es8316_write(sc, ESCODEC_HPMIXVOL_REG, 0xbb); + + /* Set charge pump headphone to 0dB */ + es8316_write(sc, ESCODEC_HPVOL_REG, 0x00); + + /* Set DAC to 0dB */ + es8316_write(sc, ESCODEC_DACVOL_L_REG, 0); + es8316_write(sc, ESCODEC_DACVOL_R_REG, 0); + + /* Enable HP output */ + val = HPOUTEN_EN_HPL | HPOUTEN_EN_HPR | + HPOUTEN_HPL_OUTEN | HPOUTEN_HPR_OUTEN; + es8316_write(sc, ESCODEC_HPOUTEN_REG, val); + + /* + * Add system sysctl tree/handlers. + */ + ctx = device_get_sysctl_ctx(sc->dev); + tree_node = device_get_sysctl_tree(sc->dev); + tree = SYSCTL_CHILDREN(tree_node); + SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "recsrc", + CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, sizeof(*sc), + es8316_sysctl_audio_src, "IU", "ADC source, " + "1 - LIN1/RIN1, 2 - LIN2/RIN2"); + + return (0); +} + +static int +es8316_detach(device_t dev) +{ + + return (0); +} + +static int +es8316_dai_init(device_t dev, uint32_t format) +{ + struct es8316_softc* sc; + uint8_t sd_clk, sd_fmt, val; + int fmt, pol, clk; + + sc = (struct es8316_softc*)device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + if (fmt != AUDIO_DAI_FORMAT_I2S) + return EINVAL; + + if (clk != AUDIO_DAI_CLOCK_CBS_CFS) + return EINVAL; + + switch (pol) { + case AUDIO_DAI_POLARITY_NB_NF: + sd_clk = 0; + sd_fmt = 0; + break; + case AUDIO_DAI_POLARITY_NB_IF: + sd_clk = 0; + sd_fmt = SD_FMT_LRP; + break; + case AUDIO_DAI_POLARITY_IB_NF: + sd_clk = SD_CLK_BCLK_INV; + sd_fmt = 0; + break; + case AUDIO_DAI_POLARITY_IB_IF: + sd_clk = SD_CLK_BCLK_INV; + sd_fmt = SD_FMT_LRP; + break; + } + + es8316_read(sc, ESCODEC_SD_CLK_REG, &val); + val &= ~(SD_CLK_MSC|SD_CLK_BCLK_INV); + val |= sd_clk; + es8316_write(sc, ESCODEC_SD_CLK_REG, val); + + es8316_read(sc, ESCODEC_SD_ADC_REG, &val); + val &= ~SD_FMT_MASK; + val |= (SD_FMT_I2S << SD_FMT_SHIFT); + val &= ~SD_FMT_LRP; + val |= sd_fmt; + es8316_write(sc, ESCODEC_SD_ADC_REG, val); + + es8316_read(sc, ESCODEC_SD_DAC_REG, &val); + val &= ~SD_FMT_MASK; + val |= (SD_FMT_I2S << SD_FMT_SHIFT); + val &= ~SD_FMT_LRP; + val |= sd_fmt; + es8316_write(sc, ESCODEC_SD_DAC_REG, val); + + es8316_read(sc, ESCODEC_CLKMAN1_REG, &val); + val |= CLKMAN1_MCLK_ON; + val |= CLKMAN1_BCLK_ON; + val |= CLKMAN1_CLK_CP_ON; + val |= CLKMAN1_CLK_DAC_ON; + val |= CLKMAN1_ANACLK_DAC_ON; + val |= CLKMAN1_CLK_ADC_ON; + val |= CLKMAN1_ANACLK_ADC_ON; + es8316_write(sc, ESCODEC_CLKMAN1_REG, val); + + return (0); +} + +static int +es8316_dai_setup_mixer(device_t dev, device_t pcmdev) +{ + + mixer_init(pcmdev, &es8316_mixer_class, dev); + + return (0); +} + +static int +es8316_dai_trigger(device_t dev, int go, int pcm_dir) +{ + struct es8316_softc *sc; + sc = device_get_softc(dev); + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + /* TODO: may be move amps/clocks enable/disable here */ + switch (go) { + case PCMTRIG_START: + if (pcm_dir == PCMDIR_PLAY) { + } + else if (pcm_dir == PCMDIR_REC) { + } + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + if (pcm_dir == PCMDIR_PLAY) { + } + else if (pcm_dir == PCMDIR_REC) { + } + break; + } + + return (0); +} + +static int +es8316_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) +{ + struct es8316_softc *sc; + int error; + + sc = device_get_softc(dev); + + error = clk_disable(sc->clk); + if (error != 0) { + device_printf(sc->dev, "could not disable mclk clock\n"); + return (error); + } + + error = clk_set_freq(sc->clk, rate, CLK_SET_ROUND_DOWN); + if (error != 0) + device_printf(sc->dev, "could not set mclk freq\n"); + + error = clk_enable(sc->clk); + if (error != 0) { + device_printf(sc->dev, "could not enable mclk clock\n"); + return (error); + } + + return (0); +} + +static device_method_t es8316_methods[] = { + /* device_if methods */ + DEVMETHOD(device_probe, es8316_probe), + DEVMETHOD(device_attach, es8316_attach), + DEVMETHOD(device_detach, es8316_detach), + + DEVMETHOD(audio_dai_init, es8316_dai_init), + DEVMETHOD(audio_dai_setup_mixer, es8316_dai_setup_mixer), + DEVMETHOD(audio_dai_trigger, es8316_dai_trigger), + DEVMETHOD(audio_dai_set_sysclk, es8316_dai_set_sysclk), + + DEVMETHOD_END, +}; + +static driver_t es8316_driver = { + "es8316codec", + es8316_methods, + sizeof(struct es8316_softc), +}; +static devclass_t es8316_devclass; + +DRIVER_MODULE(es8316codec, iicbus, es8316_driver, es8316_devclass, NULL, NULL); +MODULE_VERSION(es8316codec, 1); +MODULE_DEPEND(es8316codec, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); +IICBUS_FDT_PNP_INFO(compat_data); diff --git a/sys/dev/iicbus/rt5640.c b/sys/dev/iicbus/rt5640.c new file mode 100644 index 00000000000..71222063c08 --- /dev/null +++ b/sys/dev/iicbus/rt5640.c @@ -0,0 +1,798 @@ +/*- + * Copyright (c) 2019 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Driver for Realtek rt5640 audio codec + */ + +#include "opt_platform.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef FDT +#include +#include +#endif + +#include + +#include +#include +#include + +#include +#include + +#include "iicbus_if.h" +#include "mixer_if.h" +#include "audio_dai_if.h" + +#define RT5640_RESET 0x00 +#define RT5640_HP_VOL 0x02 +#define MAX_HPO_VOLUME (0x27) +#define HP_VOL_MU_HPO_L (1 << 15) +#define HP_VOL_MU_HPOVOLL_IN (1 << 14) +#define HP_VOL_MU_HPO_R (1 << 7) +#define HP_VOL_MU_HPOVOLR_IN (1 << 6) +#define HP_VOL_VOLUME(l, r) ((l) << 8 | (r)) +#define HP_VOL_VOLUME_MASK HP_VOL_VOLUME(0x3f, 0x3f) +#define RT5640_IN1_IN2 0x0d +#define IN1_IN2_EN_IN1_DF (1 << 7) +#define RT5640_DAC1_DIG_VOL 0x19 +#define MAX_DIG_VOLUME 0xAF +#define DAC1_DIG_VOL(l, r) (((l) << 8) | (r)) +#define DAC1_DIG_VOL_MASK DAC1_DIG_VOL(0xff, 0xff) +#define DAC1_DIG_VOL_R(v) ((v) & 0xff) +#define DAC1_DIG_VOL_L(v) (((v) >> 8) & 0xff) +#define RT5640_ADC_DIG_VOL 0x1C +#define ADC_DIG_VOL_MU_ADC_VOL_L (1 << 15) +#define ADC_DIG_VOL_AD_GAIN_L(v) ((v) << 8) +#define ADC_DIG_VOL_AD_GAIN_L_MASK (0x7f << 8) +#define ADC_DIG_VOL_MU_ADC_VOL_R (1 << 7) +#define ADC_DIG_VOL_AD_GAIN_R(v) ((v) << 0) +#define ADC_DIG_VOL_AD_GAIN_R_MASK (0x7f << 0) +#define RT5640_STO_ADC_MIXER 0x27 +#define STO_ADC_MIXER_MU_STEREO_ADCL1 (1 << 14) +#define STO_ADC_MIXER_SEL_STEREO_ADC1 (1 << 12) +#define STO_ADC_MIXER_MU_STEREO_ADCR1 (1 << 6) +#define RT5640_AD_DA_MIXER 0x29 +#define AD_DA_MIXER_MU_IF1_DAC_L (1 << 14) +#define AD_DA_MIXER_MU_IF1_DAC_R (1 << 6) +#define RT5640_STO_DAC_MIXER 0x2a +#define STO_DAC_MIXER_MU_STEREO_DACL1 (1 << 14) +#define STO_DAC_MIXER_MU_STEREO_DACR1 (1 << 6) +#define RT5640_DIG_MIXER 0x2c +#define DIG_MIXER_MU_DACL1_TO_DACL (1 << 15) +#define DIG_MIXER_MU_DACR1_TO_DACR (1 << 11) +#define RT5640_DSP_PATH2 0x2e +#define RT5640_REC_L2_MIXER 0x3c +#define L2_MIXER_MU_BST1_RECMIXL (1 << 1) +#define RT5640_REC_R2_MIXER 0x3e +#define R2_MIXER_MU_BST1_RECMIXR (1 << 1) +#define RT5640_HPO_MIXER 0x45 +#define HPO_MIXER_MU_HPOVOL_HPOMIX (1 << 13) +#define RT5640_OUT_L3_MIXER 0x4f +#define OUT_L3_MIXER_MU_DACL1_OUTMIXL (1 << 0) +#define RT5640_OUT_R3_MIXER 0x52 +#define OUT_R3_MIXER_MU_DACR1_OUTMIXR (1 << 0) +#define RT5640_LOUT_MIXER 0x53 +#define RT5640_PWR_DIG1 0x61 +#define PWR_DIG1_EN_I2S1 (1 << 15) +#define PWR_DIG1_POWER_DAC_L_1 (1 << 12) +#define PWR_DIG1_POWER_DAC_R_1 (1 << 11) +#define PWR_DIG1_POWER_ADC_L (1 << 2) +#define PWR_DIG1_POWER_ADC_R (1 << 1) +#define RT5640_PWR_DIG2 0x62 +#define PWR_DIG2_POW_ADC_STEREO_FILTER (1 << 15) +#define RT5640_PWR_ANLG1 0x63 +#define PWR_ANLG1_EN_FASTB1 (1 << 14) +#define PWR_ANLG1_POW_MAIN_BIAS (1 << 13) +#define PWR_ANLG1_EN_L_HP (1 << 7) +#define PWR_ANLG1_EN_R_HP (1 << 6) +#define PWR_ANLG1_EN_AMP_HP (1 << 5) +#define PWR_ANLG1_EN_FASTB2 (1 << 3) +#define RT5640_PWR_ANLG2 0x64 +#define PWR_ANLG2_POW_BST1 (1 << 15) +#define PWR_ANLG2_POW_MICBIAS1 (1 << 11) +#define PWR_ANLG2_POW_PLL (1 << 9) +#define RT5640_PWR_MIXER 0x65 +#define PWR_MIXER_POW_OUTMIXL (1 << 15) +#define PWR_MIXER_POW_OUTMIXR (1 << 14) +#define PWR_MIXER_POW_RECMIXL (1 << 11) +#define PWR_MIXER_POW_RECMIXR (1 << 10) +#define RT5640_PWR_VOL 0x66 +#define PWR_VOL_POW_HPOVOLL (1 << 11) +#define PWR_VOL_POW_HPOVOLR (1 << 10) +#define RT5640_PR_INDEX 0x6a +#define RT5640_PR_DATA 0x6c +#define RT5640_I2S1_SDP 0x70 +#define I2S1_SDP_SEL_I2S1_MS_SLAVE (1 << 15) +#define I2S1_SDP_INV_I2S1_BCLK (1 << 7) +#define I2S1_SDP_SEL_I2S1_LEN_MASK (3 << 2) +#define I2S1_SDP_SEL_I2S1_FORMAT_MASK (3 << 0) +#define I2S1_SDP_SEL_I2S1_FORMAT_I2S (0 << 0) +#define I2S1_SDP_SEL_I2S1_FORMAT_I2S_LJ (1 << 0) +#define I2S1_SDP_SEL_I2S1_FORMAT_PCM_A (2 << 0) +#define I2S1_SDP_SEL_I2S1_FORMAT_PCM_B (3 << 0) +#define RT5640_ADDA_CLK1 0x73 +#define ADDA_CLK1_SEL_I2S_PRE_DIV1_1 (0 << 12) +#define ADDA_CLK1_SEL_I2S_PRE_DIV2_1 (0 << 8) +#define ADDA_CLK1_SEL_I2S_PRE_DIV2_2 (1 << 8) +#define ADDA_CLK1_SEL_DAC_OCR_128 (0 << 2) +#define ADDA_CLK1_SEL_DAC_OCR_64 (1 << 2) +#define ADDA_CLK1_SEL_DAC_OCR_32 (2 << 2) +#define ADDA_CLK1_SEL_DAC_OCR_16 (3 << 2) +#define ADDA_CLK1_SEL_ADC_OCR_128 (0 << 0) +#define ADDA_CLK1_SEL_ADC_OCR_64 (1 << 0) +#define ADDA_CLK1_SEL_ADC_OCR_32 (2 << 0) +#define ADDA_CLK1_SEL_ADC_OCR_16 (3 << 0) +#define RT5640_GLB_CLK 0x80 +#define RT5640_DEPOP_M1 0x8e +#define DEPOP_M1_POW_PUMP_HP (1 << 3) +#define DEPOP_M1_EN_SOFTGEN_HP (1 << 2) +#define DEPOP_M1_POW_CAPLESS (1 << 0) +#define DEPOP_M1_POWER_MASK (0xf) +#define RT5640_DEPOP_M2 0x8f +#define DEPOP_M2_HP_MODE_1 (0 << 13) +#define DEPOP_M2_HP_MODE_2 (1 << 13) +#define DEPOP_M2_HP_MODE_MASK (1 << 13) +#define DEPOP_M2_EN_DEPOP_MODE1 (1 << 6) +#define RT5640_CHARGE_PUMP 0x91 +#define CHARGE_PUMP_MODE_MASK (3 << 8) +#define CHARGE_PUMP_MODE_LOW (0 << 8) +#define CHARGE_PUMP_MODE_MIDDLE (1 << 8) +#define CHARGE_PUMP_MODE_HIGH (2 << 8) +#define RT5640_GCTRL1 0xfa +#define GCTRL1_EN_IN1_SE (1 << 9) +#define GCTRL1_EN_IN2_SE (1 << 8) +#define GCTRL1_DIGITAL_GATE_CTRL (1 << 0) +#define RT5640_VENDOR_ID2 0xff + +#define MAX_BUFFER 16 + +#define RT5640_MIXER_DEVS ((1 << SOUND_MIXER_VOLUME) | \ + (1 << SOUND_MIXER_PHONEOUT)) + +struct rt5640_softc { + device_t dev; + device_t busdev; + struct intr_config_hook + init_hook; + clk_t clk; +}; + +#ifdef FDT +static struct ofw_compat_data compat_data[] = { + {"realtek,rt5640", 1}, + {NULL, 0}, +}; +#endif + +static void rt5640_init(void *arg); +static int rt5640_probe(device_t dev); +static int rt5640_attach(device_t dev); +static int rt5640_detach(device_t dev); + +static int rt5640_writeto(device_t slavedev, uint8_t regaddr, + void *buffer, uint16_t buflen, int waithow); + +static int +rt5640_writeto(device_t slavedev, uint8_t regaddr, void *buffer, + uint16_t buflen, int waithow) +{ + struct iic_msg msgs; + uint8_t slaveaddr; + uint8_t newbuf[MAX_BUFFER]; + + if (buflen > MAX_BUFFER - 1) + return (EINVAL); + + slaveaddr = iicbus_get_addr(slavedev); + + newbuf[0] = regaddr; + memcpy(newbuf + 1, buffer, buflen); + msgs.slave = slaveaddr; + msgs.flags = IIC_M_WR; + msgs.len = 1 + buflen; + msgs.buf = newbuf; + + return (iicbus_transfer_excl(slavedev, &msgs, 1, waithow)); +} + +static inline int +rt5640_read2(struct rt5640_softc *sc, uint8_t reg, uint16_t *data) +{ + int res; + res = iicdev_readfrom(sc->dev, reg, data, 2, IIC_WAIT); + if (res == 0) + *data = be16toh(*data); + return (res); +} + +static inline int +rt5640_write2(struct rt5640_softc *sc, uint8_t reg, uint16_t val) +{ + val = htobe16(val); + + return (rt5640_writeto(sc->dev, reg, &val, 2, IIC_WAIT)); +} + +static inline int +rt5640_pr_read2(struct rt5640_softc *sc, uint8_t reg, uint16_t *data) +{ + int res; + res = rt5640_write2(sc, RT5640_PR_INDEX, reg); + if (res != 0) + return (res); + res = rt5640_read2(sc, RT5640_PR_DATA, data); + return res; +} + +static inline int +rt5640_pr_write2(struct rt5640_softc *sc, uint8_t reg, uint16_t val) +{ + int res; + res = rt5640_write2(sc, RT5640_PR_INDEX, reg); + if (res != 0) + return (res); + res = rt5640_write2(sc, RT5640_PR_DATA, val); + return res; +} + +static void +rt5640_powerup(struct rt5640_softc *sc) +{ + uint16_t reg; + + rt5640_pr_read2(sc, 0x24, ®); + reg &= ~0x0700; + reg |= 0x0200; + rt5640_pr_write2(sc, 0x24, reg); + + rt5640_read2(sc, RT5640_DEPOP_M2, ®); + reg |= DEPOP_M2_HP_MODE_2; + rt5640_write2(sc, RT5640_DEPOP_M2, reg); + + rt5640_read2(sc, RT5640_DEPOP_M1, ®); + reg &= ~(DEPOP_M1_POWER_MASK); + reg |= DEPOP_M1_POW_CAPLESS | DEPOP_M1_POW_PUMP_HP; + rt5640_write2(sc, RT5640_DEPOP_M1, reg); + + rt5640_pr_write2(sc, 0x77, 0x9f00); + + /* VREF1/VREF2 are slow */ + rt5640_read2(sc, RT5640_PWR_ANLG1, ®); + reg &= ~(PWR_ANLG1_EN_FASTB1 | PWR_ANLG1_EN_FASTB2); + rt5640_write2(sc, RT5640_PWR_ANLG1, reg); + + /* Improve HP Amp driving */ + reg |= PWR_ANLG1_EN_AMP_HP; + rt5640_write2(sc, RT5640_PWR_ANLG1, reg); + + pause("pwrup", hz/100); + + reg |= (PWR_ANLG1_EN_FASTB1 | PWR_ANLG1_EN_FASTB2); + rt5640_write2(sc, RT5640_PWR_ANLG1, reg); + + /* depop */ + rt5640_read2(sc, RT5640_DEPOP_M2, ®); + reg &= ~DEPOP_M2_HP_MODE_MASK; + reg |= DEPOP_M2_HP_MODE_1; + reg |= DEPOP_M2_EN_DEPOP_MODE1; + rt5640_write2(sc, RT5640_DEPOP_M2, reg); + + rt5640_read2(sc, RT5640_CHARGE_PUMP, ®); + reg &= ~CHARGE_PUMP_MODE_MASK; + reg |= CHARGE_PUMP_MODE_HIGH; + rt5640_write2(sc, RT5640_CHARGE_PUMP, reg); + + rt5640_pr_write2(sc, 0x37, 0x1c00); + + rt5640_read2(sc, RT5640_DEPOP_M1, ®); + reg &= ~DEPOP_M1_POW_PUMP_HP; + reg |= DEPOP_M1_EN_SOFTGEN_HP; + rt5640_write2(sc, RT5640_DEPOP_M1, reg); + + rt5640_pr_read2(sc, 0x24, ®); + reg &= ~0x0700; + reg |= 0x0400; + rt5640_pr_write2(sc, 0x24, reg); +} + +static void +rt5640_set_hpo_vol(struct rt5640_softc *sc, unsigned int left, unsigned int right) +{ + uint16_t reg; + unsigned int l, r; + + if (left > 100) + left = 100; + if (right > 100) + right = 100; + + l = MAX_HPO_VOLUME - (left * MAX_HPO_VOLUME / 100); + r = MAX_HPO_VOLUME - (right * MAX_HPO_VOLUME / 100); + + rt5640_read2(sc, RT5640_HP_VOL, ®); + reg &= ~(HP_VOL_VOLUME_MASK); + reg |= HP_VOL_VOLUME(l, r); + rt5640_write2(sc, RT5640_HP_VOL, reg); +} + +static void +rt5640_set_if1_vol(struct rt5640_softc *sc, unsigned int left, unsigned int right) +{ + uint16_t reg; + unsigned int l, r; + + if (left > 100) + left = 100; + if (right > 100) + right = 100; + + l = (left * MAX_DIG_VOLUME / 100); + r = (right * MAX_DIG_VOLUME / 100); + + rt5640_read2(sc, RT5640_DAC1_DIG_VOL, ®); + reg &= ~(DAC1_DIG_VOL_MASK); + reg |= DAC1_DIG_VOL(l, r); + rt5640_write2(sc, RT5640_DAC1_DIG_VOL, reg); +} + +static void +rt5640_setup_microphone(struct rt5640_softc *sc) +{ + uint16_t reg; + + /* Power up MICBIAS1 */ + rt5640_read2(sc, RT5640_PWR_ANLG2, ®); + reg |= PWR_ANLG2_POW_MICBIAS1; + rt5640_write2(sc, RT5640_PWR_ANLG2, reg); + + /* Enable power for ADCL and ADCR */ + rt5640_read2(sc, RT5640_PWR_DIG1, ®); + reg |= (PWR_DIG1_POWER_ADC_L | PWR_DIG1_POWER_ADC_R); + rt5640_write2(sc, RT5640_PWR_DIG1, reg); + + // MX-0D[7] - set differential mode + rt5640_read2(sc, RT5640_IN1_IN2, ®); + reg |= IN1_IN2_EN_IN1_DF; + rt5640_write2(sc, RT5640_IN1_IN2, reg); + + // MX-0D[15:12] - MICBST1 volume + + // MX-64[15] - MICBST1 power + rt5640_read2(sc, RT5640_PWR_ANLG2, ®); + reg |= PWR_ANLG2_POW_BST1; + rt5640_write2(sc, RT5640_PWR_ANLG2, reg); + + // MX-3C[1] - MICBST1 input in RECMIXL + rt5640_read2(sc, RT5640_REC_L2_MIXER, ®); + reg &= ~(L2_MIXER_MU_BST1_RECMIXL); + rt5640_write2(sc, RT5640_REC_L2_MIXER, reg); + + // MX-3E[1] - MICBST1 input in RECMIXR + rt5640_read2(sc, RT5640_REC_R2_MIXER, ®); + reg &= ~(R2_MIXER_MU_BST1_RECMIXR); + rt5640_write2(sc, RT5640_REC_R2_MIXER, reg); + + // MX-65[10/11] - RECMIXL/RECMIXR power + rt5640_read2(sc, RT5640_PWR_MIXER, ®); + reg |= (PWR_MIXER_POW_RECMIXL | PWR_MIXER_POW_RECMIXR); + rt5640_write2(sc, RT5640_PWR_MIXER, reg); + + // internals + rt5640_read2(sc, RT5640_PWR_DIG2, ®); + reg |= PWR_DIG2_POW_ADC_STEREO_FILTER; + rt5640_write2(sc, RT5640_PWR_DIG2, reg); + // MX-27[12] to select ADCR + // MX-27[14] to unmute + // MX-27[6] to unmute + rt5640_read2(sc, RT5640_STO_ADC_MIXER, ®); + reg |= STO_ADC_MIXER_SEL_STEREO_ADC1; + reg &= ~(STO_ADC_MIXER_MU_STEREO_ADCL1 | STO_ADC_MIXER_MU_STEREO_ADCR1); + rt5640_write2(sc, RT5640_STO_ADC_MIXER, reg); + + // MX-1C[15] to unmute + // MX-1C[14:8] - volume + // MX-1C[6:0] - volume + rt5640_read2(sc, RT5640_ADC_DIG_VOL, ®); + reg &= ~(ADC_DIG_VOL_MU_ADC_VOL_L | ADC_DIG_VOL_MU_ADC_VOL_R); + reg &= ~(ADC_DIG_VOL_AD_GAIN_R_MASK | ADC_DIG_VOL_MU_ADC_VOL_R); + reg |= ADC_DIG_VOL_AD_GAIN_L(0x7f); + reg |= ADC_DIG_VOL_AD_GAIN_R(0x7f); + rt5640_write2(sc, RT5640_ADC_DIG_VOL, reg); +} + +static void +rt5640_init(void *arg) +{ + struct rt5640_softc *sc; + uint16_t reg; + + sc = (struct rt5640_softc*)arg; + config_intrhook_disestablish(&sc->init_hook); + + rt5640_read2(sc, RT5640_VENDOR_ID2, ®); + + /* Reset codec */ + rt5640_write2(sc, RT5640_RESET, 0); + + rt5640_pr_write2(sc, 0x3d, 0x3600); + rt5640_pr_write2(sc, 0x12, 0x0aa8); + rt5640_pr_write2(sc, 0x14, 0x0aaa); + rt5640_pr_write2(sc, 0x20, 0x6110); + rt5640_pr_write2(sc, 0x21, 0xe0e0); + rt5640_pr_write2(sc, 0x23, 0x1804); + + rt5640_read2(sc, RT5640_DSP_PATH2, ®); + reg &= ~0xfc00; + reg |= 0x0c00; + rt5640_write2(sc, RT5640_DSP_PATH2, reg); + + rt5640_read2(sc, RT5640_GCTRL1, ®); + reg |= GCTRL1_DIGITAL_GATE_CTRL; + rt5640_write2(sc, RT5640_GCTRL1, reg); + + /* HP L/R amp */ + rt5640_read2(sc, RT5640_PWR_ANLG1, ®); + reg |= (PWR_ANLG1_EN_L_HP | PWR_ANLG1_EN_R_HP); + /* XXX: not clear why we need to enable this for playback */ + reg |= PWR_ANLG1_POW_MAIN_BIAS; + rt5640_write2(sc, RT5640_PWR_ANLG1, reg); + + rt5640_read2(sc, RT5640_HP_VOL, ®); + /* unmute HPO */ + reg &= ~(HP_VOL_MU_HPO_L | HP_VOL_MU_HPO_R); + /* unmute HPOVOL */ + reg &= ~(HP_VOL_MU_HPOVOLL_IN | HP_VOL_MU_HPOVOLR_IN); + rt5640_write2(sc, RT5640_HP_VOL, reg); + + rt5640_read2(sc, RT5640_HPO_MIXER, ®); + reg &= ~(HPO_MIXER_MU_HPOVOL_HPOMIX); + rt5640_write2(sc, RT5640_HPO_MIXER, reg); + + /* Enable power for DAC_R1 and DAC_L1 */ + rt5640_read2(sc, RT5640_PWR_DIG1, ®); + reg |= (PWR_DIG1_POWER_DAC_L_1 | PWR_DIG1_POWER_DAC_R_1); + rt5640_write2(sc, RT5640_PWR_DIG1, reg); + + rt5640_read2(sc, RT5640_AD_DA_MIXER, ®); + reg &= ~(AD_DA_MIXER_MU_IF1_DAC_L | AD_DA_MIXER_MU_IF1_DAC_R); + rt5640_write2(sc, RT5640_AD_DA_MIXER, reg); + + /* I2S1 power */ + rt5640_read2(sc, RT5640_PWR_DIG1, ®); + reg |= PWR_DIG1_EN_I2S1; + rt5640_write2(sc, RT5640_PWR_DIG1, reg); + + /* Unmute DAC L1/R1 Switch */ + rt5640_read2(sc, RT5640_DIG_MIXER, ®); + reg &= ~(DIG_MIXER_MU_DACL1_TO_DACL | DIG_MIXER_MU_DACR1_TO_DACR); + rt5640_write2(sc, RT5640_DIG_MIXER, reg); + + /* Power up HPOVOL L/R */ + rt5640_read2(sc, RT5640_PWR_VOL, ®); + reg |= (PWR_VOL_POW_HPOVOLL | PWR_VOL_POW_HPOVOLR); + rt5640_write2(sc, RT5640_PWR_VOL, reg); + + /* Power up OUT MIX L/R */ + rt5640_read2(sc, RT5640_PWR_MIXER, ®); + reg |= (PWR_MIXER_POW_OUTMIXL | PWR_MIXER_POW_OUTMIXR); + rt5640_write2(sc, RT5640_PWR_MIXER, reg); + + /* Unmute OUT MIX R */ + rt5640_read2(sc, RT5640_OUT_R3_MIXER, ®); + reg &= ~(OUT_R3_MIXER_MU_DACR1_OUTMIXR); + rt5640_write2(sc, RT5640_OUT_R3_MIXER, reg); + + /* Unmute OUT MIX L */ + rt5640_read2(sc, RT5640_OUT_L3_MIXER, ®); + reg &= ~(OUT_L3_MIXER_MU_DACL1_OUTMIXL); + rt5640_write2(sc, RT5640_OUT_L3_MIXER, reg); + + /* Stereo DAC MIX L/R */ + rt5640_read2(sc, RT5640_STO_DAC_MIXER, ®); + reg &= ~(STO_DAC_MIXER_MU_STEREO_DACL1 | STO_DAC_MIXER_MU_STEREO_DACR1); + rt5640_write2(sc, RT5640_STO_DAC_MIXER, reg); + + // PLL1 + rt5640_read2(sc, RT5640_PWR_ANLG2, ®); + reg |= PWR_ANLG2_POW_PLL; + rt5640_write2(sc, RT5640_PWR_ANLG2, reg); + + reg = ADDA_CLK1_SEL_I2S_PRE_DIV1_1 | + ADDA_CLK1_SEL_I2S_PRE_DIV2_2 | + ADDA_CLK1_SEL_DAC_OCR_64 | + ADDA_CLK1_SEL_ADC_OCR_128; + rt5640_write2(sc, RT5640_ADDA_CLK1, reg); + + rt5640_setup_microphone(sc); + + rt5640_powerup(sc); +} + +static int +rt5640_mixer_init(struct snd_mixer *m) +{ + mix_setdevs(m, RT5640_MIXER_DEVS); + + return (0); +} + +static int +rt5640_mixer_uninit(struct snd_mixer *m) +{ + + return (0); +} + +static int +rt5640_mixer_reinit(struct snd_mixer *m) +{ + + return (0); +} + +static int +rt5640_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) +{ + struct rt5640_softc *sc; + struct mtx *mixer_lock; + int locked; + + sc = device_get_softc(mix_getdevinfo(m)); + mixer_lock = mixer_get_lock(m); + locked = mtx_owned(mixer_lock); + + /* + * We need to unlock the mixer lock because iicbus_transfer() + * may sleep. The mixer lock itself is unnecessary here + * because it is meant to serialize hardware access, which + * is taken care of by the I2C layer, so this is safe. + */ + if (locked) + mtx_unlock(mixer_lock); + switch (dev) { + case SOUND_MIXER_VOLUME: + rt5640_set_if1_vol(sc, left, right); + return (left | (right << 8)); + case SOUND_MIXER_PHONEOUT: + rt5640_set_hpo_vol(sc, left, right); + return (left | (right << 8)); + default: + break; + } + + if (locked) + mtx_lock(mixer_lock); + + return (0); +} + +static u_int32_t +rt5640_mixer_setrecsrc(struct snd_mixer *m, u_int32_t src) +{ + + return (0); +} + + +static kobj_method_t rt5640_mixer_methods[] = { + KOBJMETHOD(mixer_init, rt5640_mixer_init), + KOBJMETHOD(mixer_uninit, rt5640_mixer_uninit), + KOBJMETHOD(mixer_reinit, rt5640_mixer_reinit), + KOBJMETHOD(mixer_set, rt5640_mixer_set), + KOBJMETHOD(mixer_setrecsrc, rt5640_mixer_setrecsrc), + KOBJMETHOD_END +}; + +MIXER_DECLARE(rt5640_mixer); + +static int +rt5640_probe(device_t dev) +{ + +#ifdef FDT + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { + device_set_desc(dev, "Realtek RT5640"); + return (BUS_PROBE_DEFAULT); + } +#endif + return (ENXIO); +} + +static int +rt5640_attach(device_t dev) +{ + struct rt5640_softc *sc; + int error; + phandle_t node; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->busdev = device_get_parent(sc->dev); + + error = clk_get_by_ofw_name(dev, 0, "mclk", &sc->clk); + if (error != 0) { + device_printf(dev, "cannot get mclk clock\n"); + return (ENXIO); + } + clk_set_freq(sc->clk, 12288000, 0); + + clk_enable(sc->clk); + + /* + * Wait until i2c is ready to set up the chip + */ + sc->init_hook.ich_func = rt5640_init; + sc->init_hook.ich_arg = sc; + if (config_intrhook_establish(&sc->init_hook) != 0) + return (ENOMEM); + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); +} + +static int +rt5640_detach(device_t dev) +{ + + return (0); +} + +static int +rt5640_dai_init(device_t dev, uint32_t format) +{ + struct rt5640_softc* sc; + int fmt, pol, clk; + uint16_t reg; + + sc = (struct rt5640_softc*)device_get_softc(dev); + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + /* I2S1 setup */ + rt5640_read2(sc, RT5640_I2S1_SDP, ®); + + /* channel mapping */ + reg &= ~(0x7 << 12); + + switch (pol) { + case AUDIO_DAI_POLARITY_IB_NF: + reg |= I2S1_SDP_INV_I2S1_BCLK; + break; + case AUDIO_DAI_POLARITY_NB_NF: + reg &= ~I2S1_SDP_INV_I2S1_BCLK; + break; + default: + return (EINVAL); + } + + switch (clk) { + case AUDIO_DAI_CLOCK_CBM_CFM: + reg &= ~I2S1_SDP_SEL_I2S1_MS_SLAVE; + break; + case AUDIO_DAI_CLOCK_CBS_CFS: + reg |= I2S1_SDP_SEL_I2S1_MS_SLAVE; + break; + default: + return (EINVAL); + } + + /* 16 bit samples */ + reg &= ~I2S1_SDP_SEL_I2S1_LEN_MASK; + /* set format */ + reg &= ~I2S1_SDP_SEL_I2S1_FORMAT_MASK; + switch (fmt) { + case AUDIO_DAI_FORMAT_I2S: + reg |= I2S1_SDP_SEL_I2S1_FORMAT_I2S; + break; + case AUDIO_DAI_FORMAT_LJ: + reg |= I2S1_SDP_SEL_I2S1_FORMAT_I2S_LJ; + break; + case AUDIO_DAI_FORMAT_DSPA: + reg |= I2S1_SDP_SEL_I2S1_FORMAT_PCM_A; + break; + case AUDIO_DAI_FORMAT_DSPB: + reg |= I2S1_SDP_SEL_I2S1_FORMAT_PCM_B; + break; + default: + return EINVAL; + } + + rt5640_write2(sc, RT5640_I2S1_SDP, reg); + + return (0); +} + +static int +rt5640_dai_setup_mixer(device_t dev, device_t pcmdev) +{ + + mixer_init(pcmdev, &rt5640_mixer_class, dev); + + return (0); +} + +static int +rt5640_dai_trigger(device_t dev, int go, int pcm_dir) +{ + + switch (go) { + case PCMTRIG_START: + /* TODO: power up amps */ + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + /* TODO: power down amps */ + break; + } + + return (0); +} + +static device_method_t rt5640_methods[] = { + /* device_if methods */ + DEVMETHOD(device_probe, rt5640_probe), + DEVMETHOD(device_attach, rt5640_attach), + DEVMETHOD(device_detach, rt5640_detach), + + DEVMETHOD(audio_dai_init, rt5640_dai_init), + DEVMETHOD(audio_dai_setup_mixer, rt5640_dai_setup_mixer), + DEVMETHOD(audio_dai_trigger, rt5640_dai_trigger), + + DEVMETHOD_END, +}; + +static driver_t rt5640_driver = { + "rt5640codec", + rt5640_methods, + sizeof(struct rt5640_softc), +}; +static devclass_t rt5640_devclass; + +DRIVER_MODULE(rt5640codec, iicbus, rt5640_driver, rt5640_devclass, NULL, NULL); +MODULE_VERSION(rt5640codec, 1); +MODULE_DEPEND(rt5640codec, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); +IICBUS_FDT_PNP_INFO(compat_data); diff --git a/sys/dev/sound/fdt/audio_dai.h b/sys/dev/sound/fdt/audio_dai.h new file mode 100644 index 00000000000..f82fe9c7b83 --- /dev/null +++ b/sys/dev/sound/fdt/audio_dai.h @@ -0,0 +1,72 @@ +/*- + * Copyright (c) 2019 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __DAI_H__ +#define __DAI_H__ + +#define AUDIO_DAI_FORMAT_I2S 0 +#define AUDIO_DAI_FORMAT_RJ 1 +#define AUDIO_DAI_FORMAT_LJ 2 +#define AUDIO_DAI_FORMAT_DSPA 3 +#define AUDIO_DAI_FORMAT_DSPB 4 +#define AUDIO_DAI_FORMAT_AC97 5 +#define AUDIO_DAI_FORMAT_PDM 6 + +/* + * Polarity: Normal/Inverted BCLK/Frame + */ +#define AUDIO_DAI_POLARITY_NB_NF 0 +#define AUDIO_DAI_POLARITY_NB_IF 1 +#define AUDIO_DAI_POLARITY_IB_NF 2 +#define AUDIO_DAI_POLARITY_IB_IF 3 +#define AUDIO_DAI_POLARITY_INVERTED_FRAME(n) ((n) & 0x01) +#define AUDIO_DAI_POLARITY_INVERTED_BCLK(n) ((n) & 0x2) + +#define AUDIO_DAI_CLOCK_CBM_CFM 0 +#define AUDIO_DAI_CLOCK_CBS_CFM 1 +#define AUDIO_DAI_CLOCK_CBM_CFS 2 +#define AUDIO_DAI_CLOCK_CBS_CFS 3 + +#define AUDIO_DAI_CLOCK_IN 0 +#define AUDIO_DAI_CLOCK_OUT 1 + +#define AUDIO_DAI_JACK_HP 0 +#define AUDIO_DAI_JACK_MIC 1 + +/* + * Signal to audio_soc that chn_intr required + * for either recording or playback + */ +#define AUDIO_DAI_REC_INTR (1 << 1) +#define AUDIO_DAI_PLAY_INTR (1 << 0) + +#define AUDIO_DAI_FORMAT(fmt, pol, clk) (((fmt) << 16) | ((pol) << 8) | (clk)) +#define AUDIO_DAI_FORMAT_FORMAT(format) (((format) >> 16) & 0xff) +#define AUDIO_DAI_FORMAT_POLARITY(format) (((format) >> 8) & 0xff) +#define AUDIO_DAI_FORMAT_CLOCK(format) (((format) >> 0) & 0xff) + + +#endif /* __DAI_H__ */ diff --git a/sys/dev/sound/fdt/audio_dai_if.m b/sys/dev/sound/fdt/audio_dai_if.m new file mode 100644 index 00000000000..dc3ebbba548 --- /dev/null +++ b/sys/dev/sound/fdt/audio_dai_if.m @@ -0,0 +1,95 @@ +#- +# Copyright (c) 2019 Oleksandr Tymoshenko +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# $FreeBSD$ +# + +CODE { + #include + #include + #include +} + +INTERFACE audio_dai; + +# set DAI format for communications between CPU/codec nodes +METHOD int init { + device_t dev; + uint32_t format; +} + +# Initialize DAI and set up interrrupt handler +METHOD int setup_intr { + device_t dev; + driver_intr_t intr_handler; + void *intr_arg; +} + +# Setup mixers for codec node +METHOD int setup_mixer { + device_t dev; + device_t ausocdev; +} + +# setup clock speed +METHOD int set_sysclk { + device_t dev; + uint32_t rate; + int dai_dir; +} + +METHOD int trigger { + device_t dev; + int go; + int pcm_dir; +} + +METHOD struct pcmchan_caps* get_caps { + device_t dev; +} + +METHOD uint32_t get_ptr { + device_t dev; + int pcm_dir; +} + +# Set PCM channel format +METHOD uint32_t set_chanformat { + device_t dev; + uint32_t format; +} + +# Set PCM channel sampling rate +METHOD uint32_t set_chanspeed { + device_t dev; + uint32_t speed; +} + +# call DAI interrupt handler +# returns 1 if call to chn_intr required, 0 otherwise +METHOD int intr { + device_t dev; + struct snd_dbuf *play_buf; + struct snd_dbuf *rec_buf; +} diff --git a/sys/dev/sound/fdt/audio_soc.c b/sys/dev/sound/fdt/audio_soc.c new file mode 100644 index 00000000000..643aab10c5b --- /dev/null +++ b/sys/dev/sound/fdt/audio_soc.c @@ -0,0 +1,548 @@ +/*- + * Copyright (c) 2019 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_platform.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "audio_dai_if.h" + +#define AUDIO_BUFFER_SIZE 48000 * 4 + +struct audio_soc_aux_node { + SLIST_ENTRY(audio_soc_aux_node) link; + device_t dev; +}; + +struct audio_soc_channel { + struct audio_soc_softc *sc; /* parent device's softc */ + struct pcm_channel *pcm; /* PCM channel */ + struct snd_dbuf *buf; /* PCM buffer */ + int dir; /* direction */ +}; + +struct audio_soc_softc { + /* + * pcm_register assumes that sc is snddev_info, + * so this has to be first structure member for "compatiblity" + */ + struct snddev_info info; + device_t dev; + char *name; + struct intr_config_hook init_hook; + device_t cpu_dev; + device_t codec_dev; + SLIST_HEAD(, audio_soc_aux_node) aux_devs; + unsigned int mclk_fs; + struct audio_soc_channel play_channel; + struct audio_soc_channel rec_channel; + /* + * The format is from the CPU node, for CODEC node clock roles + * need to be reversed. + */ + uint32_t format; + uint32_t link_mclk_fs; +}; + +static struct ofw_compat_data compat_data[] = { + {"simple-audio-card", 1}, + {NULL, 0}, +}; + +static struct { + const char *name; + unsigned int fmt; +} ausoc_dai_formats[] = { + { "i2s", AUDIO_DAI_FORMAT_I2S }, + { "right_j", AUDIO_DAI_FORMAT_RJ }, + { "left_j", AUDIO_DAI_FORMAT_LJ }, + { "dsp_a", AUDIO_DAI_FORMAT_DSPA }, + { "dsp_b", AUDIO_DAI_FORMAT_DSPB }, + { "ac97", AUDIO_DAI_FORMAT_AC97 }, + { "pdm", AUDIO_DAI_FORMAT_PDM }, +}; + +static int audio_soc_probe(device_t dev); +static int audio_soc_attach(device_t dev); +static int audio_soc_detach(device_t dev); + +/* + * Invert master/slave roles for CODEC side of the node + */ +static uint32_t +audio_soc_reverse_clocks(uint32_t format) +{ + int fmt, pol, clk; + + fmt = AUDIO_DAI_FORMAT_FORMAT(format); + pol = AUDIO_DAI_FORMAT_POLARITY(format); + clk = AUDIO_DAI_FORMAT_CLOCK(format); + + switch (clk) { + case AUDIO_DAI_CLOCK_CBM_CFM: + clk = AUDIO_DAI_CLOCK_CBS_CFS; + break; + case AUDIO_DAI_CLOCK_CBS_CFM: + clk = AUDIO_DAI_CLOCK_CBM_CFS; + break; + case AUDIO_DAI_CLOCK_CBM_CFS: + clk = AUDIO_DAI_CLOCK_CBS_CFM; + break; + case AUDIO_DAI_CLOCK_CBS_CFS: + clk = AUDIO_DAI_CLOCK_CBM_CFM; + break; + } + + return AUDIO_DAI_FORMAT(fmt, pol, clk); +} + +static uint32_t +audio_soc_chan_setblocksize(kobj_t obj, void *data, uint32_t blocksz) +{ + + return (blocksz); +} + +static int +audio_soc_chan_setformat(kobj_t obj, void *data, uint32_t format) +{ + + struct audio_soc_softc *sc; + struct audio_soc_channel *ausoc_chan; + + ausoc_chan = data; + sc = ausoc_chan->sc; + + return AUDIO_DAI_SET_CHANFORMAT(sc->cpu_dev, format); +} + +static uint32_t +audio_soc_chan_setspeed(kobj_t obj, void *data, uint32_t speed) +{ + + struct audio_soc_softc *sc; + struct audio_soc_channel *ausoc_chan; + uint32_t rate; + struct audio_soc_aux_node *aux_node; + + ausoc_chan = data; + sc = ausoc_chan->sc; + + if (sc->link_mclk_fs) { + rate = speed * sc->link_mclk_fs; + if (AUDIO_DAI_SET_SYSCLK(sc->cpu_dev, rate, AUDIO_DAI_CLOCK_IN)) + device_printf(sc->dev, "failed to set sysclk for CPU node\n"); + + if (AUDIO_DAI_SET_SYSCLK(sc->codec_dev, rate, AUDIO_DAI_CLOCK_OUT)) + device_printf(sc->dev, "failed to set sysclk for codec node\n"); + + SLIST_FOREACH(aux_node, &sc->aux_devs, link) { + if (AUDIO_DAI_SET_SYSCLK(aux_node->dev, rate, AUDIO_DAI_CLOCK_OUT)) + device_printf(sc->dev, "failed to set sysclk for aux node\n"); + } + } + + /* + * Let CPU node determine speed + */ + speed = AUDIO_DAI_SET_CHANSPEED(sc->cpu_dev, speed); + AUDIO_DAI_SET_CHANSPEED(sc->codec_dev, speed); + SLIST_FOREACH(aux_node, &sc->aux_devs, link) { + AUDIO_DAI_SET_CHANSPEED(aux_node->dev, speed); + } + + return (speed); +} + +static uint32_t +audio_soc_chan_getptr(kobj_t obj, void *data) +{ + struct audio_soc_softc *sc; + struct audio_soc_channel *ausoc_chan; + + ausoc_chan = data; + sc = ausoc_chan->sc; + + return AUDIO_DAI_GET_PTR(sc->cpu_dev, ausoc_chan->dir); +} + +static void * +audio_soc_chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, + struct pcm_channel *c, int dir) +{ + struct audio_soc_softc *sc; + struct audio_soc_channel *ausoc_chan; + void *buffer; + + ausoc_chan = devinfo; + sc = ausoc_chan->sc; + buffer = malloc(AUDIO_BUFFER_SIZE, M_DEVBUF, M_WAITOK | M_ZERO); + + if (sndbuf_setup(b, buffer, AUDIO_BUFFER_SIZE) != 0) { + free(buffer, M_DEVBUF); + return NULL; + } + + ausoc_chan->dir = dir; + ausoc_chan->buf = b; + ausoc_chan->pcm = c; + + return (devinfo); +} + +static int +audio_soc_chan_trigger(kobj_t obj, void *data, int go) +{ + struct audio_soc_softc *sc; + struct audio_soc_channel *ausoc_chan; + struct audio_soc_aux_node *aux_node; + + ausoc_chan = (struct audio_soc_channel *)data; + sc = ausoc_chan->sc; + AUDIO_DAI_TRIGGER(sc->codec_dev, go, ausoc_chan->dir); + SLIST_FOREACH(aux_node, &sc->aux_devs, link) { + AUDIO_DAI_TRIGGER(aux_node->dev, go, ausoc_chan->dir); + } + + return AUDIO_DAI_TRIGGER(sc->cpu_dev, go, ausoc_chan->dir); +} + +static int +audio_soc_chan_free(kobj_t obj, void *data) +{ + + struct audio_soc_softc *sc; + struct audio_soc_channel *ausoc_chan; + void *buffer; + + ausoc_chan = (struct audio_soc_channel *)data; + sc = ausoc_chan->sc; + + buffer = sndbuf_getbuf(ausoc_chan->buf); + if (buffer) + free(buffer, M_DEVBUF); + + return (0); +} + +static struct pcmchan_caps * +audio_soc_chan_getcaps(kobj_t obj, void *data) +{ + struct audio_soc_softc *sc; + struct audio_soc_channel *ausoc_chan; + + ausoc_chan = data; + sc = ausoc_chan->sc; + + return AUDIO_DAI_GET_CAPS(sc->cpu_dev); +} + +static kobj_method_t audio_soc_chan_methods[] = { + KOBJMETHOD(channel_init, audio_soc_chan_init), + KOBJMETHOD(channel_free, audio_soc_chan_free), + KOBJMETHOD(channel_setformat, audio_soc_chan_setformat), + KOBJMETHOD(channel_setspeed, audio_soc_chan_setspeed), + KOBJMETHOD(channel_setblocksize,audio_soc_chan_setblocksize), + KOBJMETHOD(channel_trigger, audio_soc_chan_trigger), + KOBJMETHOD(channel_getptr, audio_soc_chan_getptr), + KOBJMETHOD(channel_getcaps, audio_soc_chan_getcaps), + KOBJMETHOD_END +}; +CHANNEL_DECLARE(audio_soc_chan); + +static void +audio_soc_intr(void *arg) +{ + struct audio_soc_softc *sc; + int channel_intr_required; + + sc = (struct audio_soc_softc *)arg; + channel_intr_required = AUDIO_DAI_INTR(sc->cpu_dev, sc->play_channel.buf, sc->rec_channel.buf); + if (channel_intr_required & AUDIO_DAI_PLAY_INTR) + chn_intr(sc->play_channel.pcm); + if (channel_intr_required & AUDIO_DAI_REC_INTR) + chn_intr(sc->rec_channel.pcm); +} + +static int +audio_soc_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { + device_set_desc(dev, "simple-audio-card"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static void +audio_soc_init(void *arg) +{ + struct audio_soc_softc *sc; + phandle_t node, child; + device_t daidev, auxdev; + uint32_t xref; + uint32_t *aux_devs; + int ncells, i; + struct audio_soc_aux_node *aux_node; + + sc = (struct audio_soc_softc *)arg; + config_intrhook_disestablish(&sc->init_hook); + + node = ofw_bus_get_node(sc->dev); + /* TODO: handle multi-link nodes */ + child = ofw_bus_find_child(node, "simple-audio-card,cpu"); + if (child == 0) { + device_printf(sc->dev, "cpu node is missing\n"); + return; + } + if ((OF_getencprop(child, "sound-dai", &xref, sizeof(xref))) <= 0) { + device_printf(sc->dev, "missing sound-dai property in cpu node\n"); + return; + } + daidev = OF_device_from_xref(xref); + if (daidev == NULL) { + device_printf(sc->dev, "no driver attached to cpu node\n"); + return; + } + sc->cpu_dev = daidev; + + child = ofw_bus_find_child(node, "simple-audio-card,codec"); + if (child == 0) { + device_printf(sc->dev, "codec node is missing\n"); + return; + } + if ((OF_getencprop(child, "sound-dai", &xref, sizeof(xref))) <= 0) { + device_printf(sc->dev, "missing sound-dai property in codec node\n"); + return; + } + daidev = OF_device_from_xref(xref); + if (daidev == NULL) { + device_printf(sc->dev, "no driver attached to codec node\n"); + return; + } + sc->codec_dev = daidev; + + /* Add AUX devices */ + aux_devs = NULL; + ncells = OF_getencprop_alloc_multi(node, "simple-audio-card,aux-devs", sizeof(*aux_devs), + (void **)&aux_devs); + + for (i = 0; i < ncells; i++) { + auxdev = OF_device_from_xref(aux_devs[i]); + if (auxdev == NULL) + device_printf(sc->dev, "warning: no driver attached to aux node\n"); + aux_node = (struct audio_soc_aux_node *)malloc(sizeof(*aux_node), M_DEVBUF, M_NOWAIT); + if (aux_node == NULL) { + device_printf(sc->dev, "failed to allocate aux node struct\n"); + return; + } + aux_node->dev = auxdev; + SLIST_INSERT_HEAD(&sc->aux_devs, aux_node, link); + } + + if (aux_devs) + OF_prop_free(aux_devs); + + if (AUDIO_DAI_INIT(sc->cpu_dev, sc->format)) { + device_printf(sc->dev, "failed to initalize cpu node\n"); + return; + } + + /* Reverse clock roles for CODEC */ + if (AUDIO_DAI_INIT(sc->codec_dev, audio_soc_reverse_clocks(sc->format))) { + device_printf(sc->dev, "failed to initalize codec node\n"); + return; + } + + SLIST_FOREACH(aux_node, &sc->aux_devs, link) { + if (AUDIO_DAI_INIT(aux_node->dev, audio_soc_reverse_clocks(sc->format))) { + device_printf(sc->dev, "failed to initalize aux node\n"); + return; + } + } + + if (pcm_register(sc->dev, sc, 1, 1)) { + device_printf(sc->dev, "failed to register PCM\n"); + return; + } + + pcm_getbuffersize(sc->dev, AUDIO_BUFFER_SIZE, AUDIO_BUFFER_SIZE, + AUDIO_BUFFER_SIZE); + sc->play_channel.sc = sc; + sc->rec_channel.sc = sc; + + pcm_addchan(sc->dev, PCMDIR_PLAY, &audio_soc_chan_class, &sc->play_channel); + pcm_addchan(sc->dev, PCMDIR_REC, &audio_soc_chan_class, &sc->rec_channel); + + pcm_setstatus(sc->dev, "at EXPERIMENT"); + + AUDIO_DAI_SETUP_INTR(sc->cpu_dev, audio_soc_intr, sc); + AUDIO_DAI_SETUP_MIXER(sc->codec_dev, sc->dev); + SLIST_FOREACH(aux_node, &sc->aux_devs, link) { + AUDIO_DAI_SETUP_MIXER(aux_node->dev, sc->dev); + } +} + +static int +audio_soc_attach(device_t dev) +{ + struct audio_soc_softc *sc; + char *name; + phandle_t node, cpu_child; + uint32_t xref; + int i, ret; + char tmp[32]; + unsigned int fmt, pol, clk; + bool frame_master, bitclock_master; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + + ret = OF_getprop_alloc(node, "name", (void **)&name); + if (ret == -1) + name = "SoC audio"; + + sc->name = strdup(name, M_DEVBUF); + device_set_desc(dev, sc->name); + + if (ret != -1) + OF_prop_free(name); + + SLIST_INIT(&sc->aux_devs); + + ret = OF_getprop(node, "simple-audio-card,format", tmp, sizeof(tmp)); + if (ret == 0) { + for (i = 0; i < nitems(ausoc_dai_formats); i++) { + if (strcmp(tmp, ausoc_dai_formats[i].name) == 0) { + fmt = ausoc_dai_formats[i].fmt; + break; + } + } + if (i == nitems(ausoc_dai_formats)) + return (EINVAL); + } else + fmt = AUDIO_DAI_FORMAT_I2S; + + if (OF_getencprop(node, "simple-audio-card,mclk-fs", + &sc->link_mclk_fs, sizeof(sc->link_mclk_fs)) <= 0) + sc->link_mclk_fs = 0; + + /* Unless specified otherwise, CPU node is the master */ + frame_master = bitclock_master = true; + + cpu_child = ofw_bus_find_child(node, "simple-audio-card,cpu"); + + if ((OF_getencprop(node, "simple-audio-card,frame-master", &xref, sizeof(xref))) > 0) + frame_master = cpu_child == OF_node_from_xref(xref); + + if ((OF_getencprop(node, "simple-audio-card,bitclock-master", &xref, sizeof(xref))) > 0) + bitclock_master = cpu_child == OF_node_from_xref(xref); + + if (frame_master) { + clk = bitclock_master ? + AUDIO_DAI_CLOCK_CBM_CFM : AUDIO_DAI_CLOCK_CBS_CFM; + } else { + clk = bitclock_master ? + AUDIO_DAI_CLOCK_CBM_CFS : AUDIO_DAI_CLOCK_CBS_CFS; + } + + bool bitclock_inversion = OF_hasprop(node, "simple-audio-card,bitclock-inversion"); + bool frame_inversion = OF_hasprop(node, "simple-audio-card,frame-inversion"); + if (bitclock_inversion) { + pol = frame_inversion ? + AUDIO_DAI_POLARITY_IB_IF : AUDIO_DAI_POLARITY_IB_NF; + } else { + pol = frame_inversion ? + AUDIO_DAI_POLARITY_NB_IF : AUDIO_DAI_POLARITY_NB_NF; + } + + sc->format = AUDIO_DAI_FORMAT(fmt, pol, clk); + + sc->init_hook.ich_func = audio_soc_init; + sc->init_hook.ich_arg = sc; + if (config_intrhook_establish(&sc->init_hook) != 0) + return (ENOMEM); + + return (0); +} + +static int +audio_soc_detach(device_t dev) +{ + struct audio_soc_softc *sc; + struct audio_soc_aux_node *aux; + + + sc = device_get_softc(dev); + if (sc->name) + free(sc->name, M_DEVBUF); + + while ((aux = SLIST_FIRST(&sc->aux_devs)) != NULL) { + SLIST_REMOVE_HEAD(&sc->aux_devs, link); + free(aux, M_DEVBUF); + } + + return (0); +} + +static device_method_t audio_soc_methods[] = { + /* device_if methods */ + DEVMETHOD(device_probe, audio_soc_probe), + DEVMETHOD(device_attach, audio_soc_attach), + DEVMETHOD(device_detach, audio_soc_detach), + + DEVMETHOD_END, +}; + +static driver_t audio_soc_driver = { + "pcm", + audio_soc_methods, + sizeof(struct audio_soc_softc), +}; +static devclass_t audio_soc_devclass; + +DRIVER_MODULE(audio_soc, simplebus, audio_soc_driver, audio_soc_devclass, NULL, NULL); +MODULE_VERSION(audio_soc, 1); diff --git a/sys/dev/sound/fdt/dummy_codec.c b/sys/dev/sound/fdt/dummy_codec.c new file mode 100644 index 00000000000..6be2491a069 --- /dev/null +++ b/sys/dev/sound/fdt/dummy_codec.c @@ -0,0 +1,127 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" + +static struct ofw_compat_data compat_data[] = { + { "dummy-codec", 1}, + { NULL, 0 } +}; + +struct dummy_codec_softc { + device_t dev; +}; + +static int dummy_codec_probe(device_t dev); +static int dummy_codec_attach(device_t dev); +static int dummy_codec_detach(device_t dev); + +static int +dummy_codec_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Dummy Codec"); + return (BUS_PROBE_DEFAULT); +} + +static int +dummy_codec_attach(device_t dev) +{ + struct dummy_codec_softc *sc; + phandle_t node; + + sc = device_get_softc(dev); + sc->dev = dev; + + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); +} + +static int +dummy_codec_detach(device_t dev) +{ + + return (0); +} + +static int +dummy_codec_dai_init(device_t dev, uint32_t format) +{ + + return (0); +} + +static device_method_t dummy_codec_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, dummy_codec_probe), + DEVMETHOD(device_attach, dummy_codec_attach), + DEVMETHOD(device_detach, dummy_codec_detach), + + DEVMETHOD(audio_dai_init, dummy_codec_dai_init), + + DEVMETHOD_END +}; + +static driver_t dummy_codec_driver = { + "dummycodec", + dummy_codec_methods, + sizeof(struct dummy_codec_softc), +}; + +static devclass_t dummy_codec_devclass; + +DRIVER_MODULE(dummy_codec, simplebus, dummy_codec_driver, dummy_codec_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/dev/sound/fdt/simple_amplifier.c b/sys/dev/sound/fdt/simple_amplifier.c new file mode 100644 index 00000000000..bc9a800e0d0 --- /dev/null +++ b/sys/dev/sound/fdt/simple_amplifier.c @@ -0,0 +1,201 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "opt_snd.h" +#include +#include +#include "audio_dai_if.h" + +static struct ofw_compat_data compat_data[] = { + { "simple-audio-amplifier", 1}, + { NULL, 0} +}; + +struct simple_amp_softc { + device_t dev; + regulator_t supply_vcc; + gpio_pin_t gpio_enable; +}; + +static int simple_amp_probe(device_t dev); +static int simple_amp_attach(device_t dev); +static int simple_amp_detach(device_t dev); + +static int +simple_amp_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Simple Amplifier"); + return (BUS_PROBE_DEFAULT); +} + +static int +simple_amp_attach(device_t dev) +{ + struct simple_amp_softc *sc; + phandle_t node; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + + error = gpio_pin_get_by_ofw_property(dev, node, + "enable-gpios", &sc->gpio_enable); + if (error != 0) { + device_printf(dev, "could not get 'enable-gpios' gpio\n"); + return (ENXIO); + } + + error = regulator_get_by_ofw_property(dev, 0, "VCC-supply", + &sc->supply_vcc); + if (error != 0) + device_printf(dev, "no VCC supply"); + + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (0); +} + +static int +simple_amp_detach(device_t dev) +{ + + return (0); +} + +static int +simple_amp_dai_init(device_t dev, uint32_t format) +{ + + return (0); +} + +static int +simple_amp_dai_trigger(device_t dev, int go, int pcm_dir) +{ + struct simple_amp_softc *sc; + int error; + + if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) + return (EINVAL); + + sc = device_get_softc(dev); + error = 0; + switch (go) { + case PCMTRIG_START: + if (sc->supply_vcc != NULL) { + error = regulator_enable(sc->supply_vcc); + if (error != 0) { + device_printf(sc->dev, + "could not enable 'VCC' regulator\n"); + break; + } + } + + error = gpio_pin_set_active(sc->gpio_enable, 1); + if (error != 0) { + device_printf(sc->dev, + "could not set 'gpio-enable' gpio\n"); + break; + } + + break; + + case PCMTRIG_STOP: + case PCMTRIG_ABORT: + error = gpio_pin_set_active(sc->gpio_enable, 0); + if (error != 0) { + device_printf(sc->dev, + "could not clear 'gpio-enable' gpio\n"); + break; + } + + if (sc->supply_vcc != NULL) { + error = regulator_disable(sc->supply_vcc); + if (error != 0) { + device_printf(sc->dev, + "could not disable 'VCC' regulator\n"); + break; + } + } + + break; + } + + return (error); +} + +static device_method_t simple_amp_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, simple_amp_probe), + DEVMETHOD(device_attach, simple_amp_attach), + DEVMETHOD(device_detach, simple_amp_detach), + + DEVMETHOD(audio_dai_init, simple_amp_dai_init), + DEVMETHOD(audio_dai_trigger, simple_amp_dai_trigger), + + DEVMETHOD_END +}; + +static driver_t simple_amp_driver = { + "simpleamp", + simple_amp_methods, + sizeof(struct simple_amp_softc), +}; + +static devclass_t simple_amp_devclass; + +DRIVER_MODULE(simple_amp, simplebus, simple_amp_driver, simple_amp_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); diff --git a/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts b/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts index ebf3eb222e1..0d2d5625482 100644 --- a/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts +++ b/sys/gnu/dts/arm64/rockchip/rk3328-rock64.dts @@ -103,6 +103,10 @@ }; }; +&analog_sound { + status = "okay"; +} + &codec { mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dts b/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dts index 4b42717800f..de672729d3d 100644 --- a/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dts +++ b/sys/gnu/dts/arm64/rockchip/rk3399-rockpro64.dts @@ -11,6 +11,36 @@ / { model = "Pine64 RockPro64 v2.1"; compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399"; + + /* Audio components */ + es8316-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MIC1", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR", + "Speaker", "Speaker Amplifier OUTL", + "Speaker", "Speaker Amplifier OUTR"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&es8316>; + }; + }; }; &i2c1 {