diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/conf/EA3250 armv6/sys/arm/conf/EA3250 --- head/sys/arm/conf/EA3250 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/conf/EA3250 2012-08-08 12:43:47.899724431 -0700 @@ -0,0 +1,96 @@ +# +# Custom kernel for EA3250 boards. +# +# $FreeBSD$ +# + +ident EA3250 +include "../lpc/std.lpc" +hints "EA3250.hints" + +makeoptions MODULES_OVERRIDE="" + +#makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols +makeoptions WERROR="-Werror" + +options SCHED_4BSD #4BSD scheduler +options INET #InterNETworking +options INET6 #IPv6 communications protocols +options FFS #Berkeley Fast Filesystem +options NFSCL #Network Filesystem Client +options NFSLOCKD #Network Lock Manager +options NFS_ROOT #NFS usable as /, requires NFSCLIENT +options MSDOSFS +options BOOTP +options BOOTP_NFSROOT +options BOOTP_NFSV3 +options BOOTP_WIRED_TO=lpe0 + +#options ROOTDEVNAME=\"ufs:/dev/da0a\" + +options SYSVSHM #SYSV-style shared memory +options SYSVMSG #SYSV-style message queues +options SYSVSEM #SYSV-style semaphores +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions +options MUTEX_NOINLINE +options RWLOCK_NOINLINE +options NO_FFS_SNAPSHOT +options NO_SWAPPING + +# Debugging +options ALT_BREAK_TO_DEBUGGER +options DDB +#options DEADLKRES #Enable the deadlock resolver +options DIAGNOSTIC +#options INVARIANTS #Enable calls of extra sanity checking +#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS +options KDB +options WITNESS #Enable checks to detect deadlocks and cycles +options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed +#options WITNESS_KDB + +# Pseudo devices +device loop +device md +device pty +device random + +# Serial ports +device uart + +# Networking +device ether +device mii +device bpf +device lpe + +# USB +options USB_DEBUG +device usb +device ohci +device umass +device scbus +device pass +device da + +device mmc +device mmcsd +device lpcmmc + +device gpio +device gpioled +device lpcgpio + +device spibus +device lpcspi +device ssd1289 + +device lpcfb + +# DMAC +device dmac + +# Flattened Device Tree +options FDT +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=ea3250.dts diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/conf/EA3250.hints armv6/sys/arm/conf/EA3250.hints --- head/sys/arm/conf/EA3250.hints 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/conf/EA3250.hints 2012-08-08 12:43:47.894724566 -0700 @@ -0,0 +1,2 @@ +hint.ssd1289.0.at="spibus0" +hint.ssd1289.0.cs=26 diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/files.lpc armv6/sys/arm/lpc/files.lpc --- head/sys/arm/lpc/files.lpc 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/files.lpc 2012-08-08 12:43:50.898723788 -0700 @@ -0,0 +1,21 @@ +# $FreeBSD$ +arm/arm/bus_space_generic.c standard +arm/arm/irq_dispatch.S standard +arm/arm/cpufunc_asm_arm9.S standard +arm/arm/cpufunc_asm_armv5.S standard +arm/lpc/lpc_machdep.c standard +arm/lpc/lpc_space.c standard +arm/lpc/lpc_pwr.c standard +arm/lpc/lpc_intc.c standard +arm/lpc/lpc_timer.c standard +arm/lpc/lpc_rtc.c standard +arm/lpc/if_lpe.c optional lpe +arm/lpc/lpc_ohci.c optional ohci +arm/lpc/lpc_mmc.c optional lpcmmc +arm/lpc/lpc_fb.c optional lpcfb +arm/lpc/lpc_gpio.c optional lpcgpio +arm/lpc/lpc_spi.c optional lpcspi +arm/lpc/lpc_dmac.c optional dmac +arm/lpc/ssd1289.c optional ssd1289 +dev/uart/uart_dev_lpc.c optional uart +kern/kern_clocksource.c standard diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/if_lpe.c armv6/sys/arm/lpc/if_lpe.c --- head/sys/arm/lpc/if_lpe.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/if_lpe.c 2012-08-08 12:43:50.899723836 -0700 @@ -0,0 +1,1231 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include "miibus_if.h" + +#define DEBUG +#undef DEBUG + +#ifdef DEBUG +#define debugf(fmt, args...) do { printf("%s(): ", __func__); \ + printf(fmt,##args); } while (0) +#else +#define debugf(fmt, args...) +#endif + +struct lpe_dmamap_arg { + bus_addr_t lpe_dma_busaddr; +}; + +struct lpe_rxdesc { + struct mbuf * lpe_rxdesc_mbuf; + bus_dmamap_t lpe_rxdesc_dmamap; +}; + +struct lpe_txdesc { + int lpe_txdesc_first; + struct mbuf * lpe_txdesc_mbuf; + bus_dmamap_t lpe_txdesc_dmamap; +}; + +struct lpe_chain_data { + bus_dma_tag_t lpe_parent_tag; + bus_dma_tag_t lpe_tx_ring_tag; + bus_dmamap_t lpe_tx_ring_map; + bus_dma_tag_t lpe_tx_status_tag; + bus_dmamap_t lpe_tx_status_map; + bus_dma_tag_t lpe_tx_buf_tag; + bus_dma_tag_t lpe_rx_ring_tag; + bus_dmamap_t lpe_rx_ring_map; + bus_dma_tag_t lpe_rx_status_tag; + bus_dmamap_t lpe_rx_status_map; + bus_dma_tag_t lpe_rx_buf_tag; + struct lpe_rxdesc lpe_rx_desc[LPE_RXDESC_NUM]; + struct lpe_txdesc lpe_tx_desc[LPE_TXDESC_NUM]; + int lpe_tx_prod; + int lpe_tx_last; + int lpe_tx_used; +}; + +struct lpe_ring_data { + struct lpe_hwdesc * lpe_rx_ring; + struct lpe_hwstatus * lpe_rx_status; + bus_addr_t lpe_rx_ring_phys; + bus_addr_t lpe_rx_status_phys; + struct lpe_hwdesc * lpe_tx_ring; + struct lpe_hwstatus * lpe_tx_status; + bus_addr_t lpe_tx_ring_phys; + bus_addr_t lpe_tx_status_phys; +}; + +struct lpe_softc { + struct ifnet * lpe_ifp; + struct mtx lpe_mtx; + phandle_t lpe_ofw; + device_t lpe_dev; + device_t lpe_miibus; + uint8_t lpe_enaddr[6]; + struct resource * lpe_mem_res; + struct resource * lpe_irq_res; + void * lpe_intrhand; + bus_space_tag_t lpe_bst; + bus_space_handle_t lpe_bsh; +#define LPE_FLAG_LINK (1 << 0) + uint32_t lpe_flags; + int lpe_watchdog_timer; + struct callout lpe_tick; + struct lpe_chain_data lpe_cdata; + struct lpe_ring_data lpe_rdata; +}; + +static int lpe_probe(device_t); +static int lpe_attach(device_t); +static int lpe_detach(device_t); +static int lpe_miibus_readreg(device_t, int, int); +static int lpe_miibus_writereg(device_t, int, int, int); +static void lpe_miibus_statchg(device_t); + +static void lpe_reset(struct lpe_softc *); +static void lpe_init(void *); +static void lpe_init_locked(struct lpe_softc *); +static void lpe_start(struct ifnet *); +static void lpe_start_locked(struct ifnet *); +static void lpe_stop(struct lpe_softc *); +static void lpe_stop_locked(struct lpe_softc *); +static int lpe_ioctl(struct ifnet *, u_long, caddr_t); +static void lpe_set_rxmode(struct lpe_softc *); +static void lpe_set_rxfilter(struct lpe_softc *); +static void lpe_intr(void *); +static void lpe_rxintr(struct lpe_softc *); +static void lpe_txintr(struct lpe_softc *); +static void lpe_tick(void *); +static void lpe_watchdog(struct lpe_softc *); +static int lpe_encap(struct lpe_softc *, struct mbuf **); +static int lpe_dma_alloc(struct lpe_softc *); +static int lpe_dma_alloc_rx(struct lpe_softc *); +static int lpe_dma_alloc_tx(struct lpe_softc *); +static int lpe_init_rx(struct lpe_softc *); +static int lpe_init_rxbuf(struct lpe_softc *, int); +static void lpe_discard_rxbuf(struct lpe_softc *, int); +static void lpe_dmamap_cb(void *, bus_dma_segment_t *, int, int); +static int lpe_ifmedia_upd(struct ifnet *); +static void lpe_ifmedia_sts(struct ifnet *, struct ifmediareq *); + +#define lpe_lock(_sc) mtx_lock(&(_sc)->lpe_mtx) +#define lpe_unlock(_sc) mtx_unlock(&(_sc)->lpe_mtx) +#define lpe_lock_assert(sc) mtx_assert(&(_sc)->lpe_mtx, MA_OWNED) + +#define lpe_read_4(_sc, _reg) \ + bus_space_read_4((_sc)->lpe_bst, (_sc)->lpe_bsh, (_reg)) +#define lpe_write_4(_sc, _reg, _val) \ + bus_space_write_4((_sc)->lpe_bst, (_sc)->lpe_bsh, (_reg), (_val)) + +#define LPE_HWDESC_RXERRS (LPE_HWDESC_CRCERROR | LPE_HWDESC_SYMBOLERROR | \ + LPE_HWDESC_LENGTHERROR | LPE_HWDESC_ALIGNERROR | LPE_HWDESC_OVERRUN | \ + LPE_HWDESC_RXNODESCR) + +#define LPE_HWDESC_TXERRS (LPE_HWDESC_EXCDEFER | LPE_HWDESC_EXCCOLL | \ + LPE_HWDESC_LATECOLL | LPE_HWDESC_UNDERRUN | LPE_HWDESC_TXNODESCR) + +static int +lpe_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "lpc,ethernet")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 10/100 Ethernet"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpe_attach(device_t dev) +{ + struct lpe_softc *sc = device_get_softc(dev); + struct ifnet *ifp; + int rid, i; + uint32_t val; + + sc->lpe_dev = dev; + sc->lpe_ofw = ofw_bus_get_node(dev); + + i = OF_getprop(sc->lpe_ofw, "local-mac-address", (void *)&sc->lpe_enaddr, 6); + if (i != 6) { + sc->lpe_enaddr[0] = 0x00; + sc->lpe_enaddr[1] = 0x11; + sc->lpe_enaddr[2] = 0x22; + sc->lpe_enaddr[3] = 0x33; + sc->lpe_enaddr[4] = 0x44; + sc->lpe_enaddr[5] = 0x55; + } + + mtx_init(&sc->lpe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF); + + callout_init_mtx(&sc->lpe_tick, &sc->lpe_mtx, 0); + + rid = 0; + sc->lpe_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->lpe_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + goto fail; + } + + sc->lpe_bst = rman_get_bustag(sc->lpe_mem_res); + sc->lpe_bsh = rman_get_bushandle(sc->lpe_mem_res); + + rid = 0; + sc->lpe_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (!sc->lpe_irq_res) { + device_printf(dev, "cannot allocate interrupt\n"); + goto fail; + } + + sc->lpe_ifp = if_alloc(IFT_ETHER); + if (!sc->lpe_ifp) { + device_printf(dev, "cannot allocated ifnet\n"); + goto fail; + } + + ifp = sc->lpe_ifp; + + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_start = lpe_start; + ifp->if_ioctl = lpe_ioctl; + ifp->if_init = lpe_init; + IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); + ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_READY(&ifp->if_snd); + + ether_ifattach(ifp, sc->lpe_enaddr); + + if (bus_setup_intr(dev, sc->lpe_irq_res, INTR_TYPE_NET, NULL, + lpe_intr, sc, &sc->lpe_intrhand)) { + device_printf(dev, "cannot establish interrupt handler\n"); + ether_ifdetach(ifp); + goto fail; + } + + /* Enable Ethernet clock */ + lpc_pwr_write(dev, LPC_CLKPWR_MACCLK_CTRL, + LPC_CLKPWR_MACCLK_CTRL_REG | + LPC_CLKPWR_MACCLK_CTRL_SLAVE | + LPC_CLKPWR_MACCLK_CTRL_MASTER | + LPC_CLKPWR_MACCLK_CTRL_HDWINF(3)); + + /* Reset chip */ + lpe_reset(sc); + + /* Initialize MII */ + val = lpe_read_4(sc, LPE_COMMAND); + lpe_write_4(sc, LPE_COMMAND, val | LPE_COMMAND_RMII); + + if (mii_attach(dev, &sc->lpe_miibus, ifp, lpe_ifmedia_upd, + lpe_ifmedia_sts, BMSR_DEFCAPMASK, 0x01, + MII_OFFSET_ANY, 0)) { + device_printf(dev, "cannot find PHY\n"); + goto fail; + } + + lpe_dma_alloc(sc); + + return (0); + +fail: + if (sc->lpe_ifp) + if_free(sc->lpe_ifp); + if (sc->lpe_intrhand) + bus_teardown_intr(dev, sc->lpe_irq_res, sc->lpe_intrhand); + if (sc->lpe_irq_res) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lpe_irq_res); + if (sc->lpe_mem_res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lpe_mem_res); + return (ENXIO); +} + +static int +lpe_detach(device_t dev) +{ + struct lpe_softc *sc = device_get_softc(dev); + + lpe_stop(sc); + + if_free(sc->lpe_ifp); + bus_teardown_intr(dev, sc->lpe_irq_res, sc->lpe_intrhand); + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lpe_irq_res); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lpe_mem_res); + + return (0); +} + +static int +lpe_miibus_readreg(device_t dev, int phy, int reg) +{ + struct lpe_softc *sc = device_get_softc(dev); + uint32_t val; + int result; + + lpe_write_4(sc, LPE_MCMD, LPE_MCMD_READ); + lpe_write_4(sc, LPE_MADR, + (reg & LPE_MADR_REGMASK) << LPE_MADR_REGSHIFT | + (phy & LPE_MADR_PHYMASK) << LPE_MADR_PHYSHIFT); + + val = lpe_read_4(sc, LPE_MIND); + + /* Wait until request is completed */ + while (val & LPE_MIND_BUSY) { + val = lpe_read_4(sc, LPE_MIND); + DELAY(10); + } + + if (val & LPE_MIND_INVALID) + return (0); + + lpe_write_4(sc, LPE_MCMD, 0); + result = (lpe_read_4(sc, LPE_MRDD) & LPE_MRDD_DATAMASK); + debugf("phy=%d reg=%d result=0x%04x\n", phy, reg, result); + + return (result); +} + +static int +lpe_miibus_writereg(device_t dev, int phy, int reg, int data) +{ + struct lpe_softc *sc = device_get_softc(dev); + uint32_t val; + + debugf("phy=%d reg=%d data=0x%04x\n", phy, reg, data); + + lpe_write_4(sc, LPE_MCMD, LPE_MCMD_WRITE); + lpe_write_4(sc, LPE_MADR, + (reg & LPE_MADR_REGMASK) << LPE_MADR_REGSHIFT | + (phy & LPE_MADR_PHYMASK) << LPE_MADR_PHYSHIFT); + + lpe_write_4(sc, LPE_MWTD, (data & LPE_MWTD_DATAMASK)); + + val = lpe_read_4(sc, LPE_MIND); + + /* Wait until request is completed */ + while (val & LPE_MIND_BUSY) { + val = lpe_read_4(sc, LPE_MIND); + DELAY(10); + } + + return (0); +} + +static void +lpe_miibus_statchg(device_t dev) +{ + struct lpe_softc *sc = device_get_softc(dev); + struct mii_data *mii = device_get_softc(sc->lpe_miibus); + + lpe_lock(sc); + + if ((mii->mii_media_status & IFM_ACTIVE) && + (mii->mii_media_status & IFM_AVALID)) + sc->lpe_flags |= LPE_FLAG_LINK; + else + sc->lpe_flags &= ~LPE_FLAG_LINK; + + lpe_unlock(sc); +} + +static void +lpe_reset(struct lpe_softc *sc) +{ + uint32_t mac1; + + /* Enter soft reset mode */ + mac1 = lpe_read_4(sc, LPE_MAC1); + lpe_write_4(sc, LPE_MAC1, mac1 | LPE_MAC1_SOFTRESET | LPE_MAC1_RESETTX | + LPE_MAC1_RESETMCSTX | LPE_MAC1_RESETRX | LPE_MAC1_RESETMCSRX); + + /* Reset registers, Tx path and Rx path */ + lpe_write_4(sc, LPE_COMMAND, LPE_COMMAND_REGRESET | + LPE_COMMAND_TXRESET | LPE_COMMAND_RXRESET); + + /* Set station address */ + lpe_write_4(sc, LPE_SA2, sc->lpe_enaddr[1] << 8 | sc->lpe_enaddr[0]); + lpe_write_4(sc, LPE_SA1, sc->lpe_enaddr[3] << 8 | sc->lpe_enaddr[2]); + lpe_write_4(sc, LPE_SA0, sc->lpe_enaddr[5] << 8 | sc->lpe_enaddr[4]); + + /* Leave soft reset mode */ + mac1 = lpe_read_4(sc, LPE_MAC1); + lpe_write_4(sc, LPE_MAC1, mac1 & ~(LPE_MAC1_SOFTRESET | LPE_MAC1_RESETTX | + LPE_MAC1_RESETMCSTX | LPE_MAC1_RESETRX | LPE_MAC1_RESETMCSRX)); +} + +static void +lpe_init(void *arg) +{ + struct lpe_softc *sc = (struct lpe_softc *)arg; + + lpe_lock(sc); + lpe_init_locked(sc); + lpe_unlock(sc); +} + +static void +lpe_init_locked(struct lpe_softc *sc) +{ + struct ifnet *ifp = sc->lpe_ifp; + uint32_t cmd, mac1; + + lpe_lock_assert(sc); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + return; + + /* Enable Tx and Rx */ + cmd = lpe_read_4(sc, LPE_COMMAND); + lpe_write_4(sc, LPE_COMMAND, cmd | LPE_COMMAND_RXENABLE | + LPE_COMMAND_TXENABLE | LPE_COMMAND_PASSRUNTFRAME); + + /* Enable receive */ + mac1 = lpe_read_4(sc, LPE_MAC1); + lpe_write_4(sc, LPE_MAC1, /*mac1 |*/ LPE_MAC1_RXENABLE | LPE_MAC1_PASSALL); + + lpe_write_4(sc, LPE_MAC2, LPE_MAC2_CRCENABLE | LPE_MAC2_PADCRCENABLE | + LPE_MAC2_FULLDUPLEX); + + lpe_write_4(sc, LPE_MCFG, LPE_MCFG_CLKSEL(7)); + + /* Set up Rx filter */ + lpe_set_rxmode(sc); + + /* Enable interrupts */ + lpe_write_4(sc, LPE_INTENABLE, LPE_INT_RXOVERRUN | LPE_INT_RXERROR | + LPE_INT_RXFINISH | LPE_INT_RXDONE | LPE_INT_TXUNDERRUN | + LPE_INT_TXERROR | LPE_INT_TXFINISH | LPE_INT_TXDONE); + + sc->lpe_cdata.lpe_tx_prod = 0; + sc->lpe_cdata.lpe_tx_last = 0; + sc->lpe_cdata.lpe_tx_used = 0; + + lpe_init_rx(sc); + + /* Initialize Rx packet and status descriptor heads */ + lpe_write_4(sc, LPE_RXDESC, sc->lpe_rdata.lpe_rx_ring_phys); + lpe_write_4(sc, LPE_RXSTATUS, sc->lpe_rdata.lpe_rx_status_phys); + lpe_write_4(sc, LPE_RXDESC_NUMBER, LPE_RXDESC_NUM - 1); + lpe_write_4(sc, LPE_RXDESC_CONS, 0); + + /* Initialize Tx packet and status descriptor heads */ + lpe_write_4(sc, LPE_TXDESC, sc->lpe_rdata.lpe_tx_ring_phys); + lpe_write_4(sc, LPE_TXSTATUS, sc->lpe_rdata.lpe_tx_status_phys); + lpe_write_4(sc, LPE_TXDESC_NUMBER, LPE_TXDESC_NUM - 1); + lpe_write_4(sc, LPE_TXDESC_PROD, 0); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + callout_reset(&sc->lpe_tick, hz, lpe_tick, sc); +} + +static void +lpe_start(struct ifnet *ifp) +{ + struct lpe_softc *sc = (struct lpe_softc *)ifp->if_softc; + + lpe_lock(sc); + lpe_start_locked(ifp); + lpe_unlock(sc); +} + +static void +lpe_start_locked(struct ifnet *ifp) +{ + struct lpe_softc *sc = (struct lpe_softc *)ifp->if_softc; + struct mbuf *m_head; + int encap = 0; + + lpe_lock_assert(sc); + + while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { + if (lpe_read_4(sc, LPE_TXDESC_PROD) == + lpe_read_4(sc, LPE_TXDESC_CONS) - 5) + break; + + /* Dequeue first packet */ + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + if (!m_head) + break; + + lpe_encap(sc, &m_head); + + encap++; + } + + /* Submit new descriptor list */ + if (encap) { + lpe_write_4(sc, LPE_TXDESC_PROD, sc->lpe_cdata.lpe_tx_prod); + sc->lpe_watchdog_timer = 5; + } + +} + +static int +lpe_encap(struct lpe_softc *sc, struct mbuf **m_head) +{ + struct lpe_txdesc *txd; + struct lpe_hwdesc *hwd; + bus_dma_segment_t segs[LPE_MAXFRAGS]; + int i, err, nsegs, prod; + + lpe_lock_assert(sc); + M_ASSERTPKTHDR((*m_head)); + + prod = sc->lpe_cdata.lpe_tx_prod; + txd = &sc->lpe_cdata.lpe_tx_desc[prod]; + + debugf("starting with prod=%d\n", prod); + + err = bus_dmamap_load_mbuf_sg(sc->lpe_cdata.lpe_tx_buf_tag, + txd->lpe_txdesc_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); + + if (err) + return (err); + + if (nsegs == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + bus_dmamap_sync(sc->lpe_cdata.lpe_tx_buf_tag, txd->lpe_txdesc_dmamap, + BUS_DMASYNC_PREREAD); + bus_dmamap_sync(sc->lpe_cdata.lpe_tx_ring_tag, sc->lpe_cdata.lpe_tx_ring_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + txd->lpe_txdesc_first = 1; + txd->lpe_txdesc_mbuf = *m_head; + + for (i = 0; i < nsegs; i++) { + hwd = &sc->lpe_rdata.lpe_tx_ring[prod]; + hwd->lhr_data = segs[i].ds_addr; + hwd->lhr_control = segs[i].ds_len - 1; + + if (i == nsegs - 1) { + hwd->lhr_control |= LPE_HWDESC_LASTFLAG; + hwd->lhr_control |= LPE_HWDESC_INTERRUPT; + hwd->lhr_control |= LPE_HWDESC_CRC; + hwd->lhr_control |= LPE_HWDESC_PAD; + } + + LPE_INC(prod, LPE_TXDESC_NUM); + } + + bus_dmamap_sync(sc->lpe_cdata.lpe_tx_ring_tag, sc->lpe_cdata.lpe_tx_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + sc->lpe_cdata.lpe_tx_used += nsegs; + sc->lpe_cdata.lpe_tx_prod = prod; + + return (0); +} + +static void +lpe_stop(struct lpe_softc *sc) +{ + lpe_lock(sc); + lpe_stop_locked(sc); + lpe_unlock(sc); +} + +static void +lpe_stop_locked(struct lpe_softc *sc) +{ + lpe_lock_assert(sc); + + callout_stop(&sc->lpe_tick); + + /* Disable interrupts */ + lpe_write_4(sc, LPE_INTCLEAR, 0xffffffff); + + /* Stop EMAC */ + lpe_write_4(sc, LPE_MAC1, 0); + lpe_write_4(sc, LPE_MAC2, 0); + lpe_write_4(sc, LPE_COMMAND, 0); + + sc->lpe_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + sc->lpe_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; +} + +static int +lpe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct lpe_softc *sc = ifp->if_softc; + struct mii_data *mii = device_get_softc(sc->lpe_miibus); + struct ifreq *ifr = (struct ifreq *)data; + int err = 0; + + switch (cmd) { + case SIOCSIFFLAGS: + lpe_lock(sc); + if (ifp->if_flags & IFF_UP) { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + lpe_set_rxmode(sc); + lpe_set_rxfilter(sc); + } else + lpe_init_locked(sc); + } else + lpe_stop(sc); + lpe_unlock(sc); + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + lpe_lock(sc); + lpe_set_rxfilter(sc); + lpe_unlock(sc); + } + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + err = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); + break; + default: + err = ether_ioctl(ifp, cmd, data); + break; + } + + return (err); +} + +static void lpe_set_rxmode(struct lpe_softc *sc) +{ + struct ifnet *ifp = sc->lpe_ifp; + uint32_t rxfilt; + + rxfilt = LPE_RXFILTER_UNIHASH | LPE_RXFILTER_MULTIHASH | LPE_RXFILTER_PERFECT; + + if (ifp->if_flags & IFF_BROADCAST) + rxfilt |= LPE_RXFILTER_BROADCAST; + + if (ifp->if_flags & IFF_PROMISC) + rxfilt |= LPE_RXFILTER_UNICAST | LPE_RXFILTER_MULTICAST; + + if (ifp->if_flags & IFF_ALLMULTI) + rxfilt |= LPE_RXFILTER_MULTICAST; + + lpe_write_4(sc, LPE_RXFILTER_CTRL, rxfilt); +} + +static void lpe_set_rxfilter(struct lpe_softc *sc) +{ + struct ifnet *ifp = sc->lpe_ifp; + struct ifmultiaddr *ifma; + int index; + uint32_t hashl, hashh; + + hashl = 0; + hashh = 0; + + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + + index = ether_crc32_be(LLADDR((struct sockaddr_dl *) + ifma->ifma_addr), ETHER_ADDR_LEN) >> 23 & 0x3f; + + if (index > 31) + hashh |= (1 << (index - 32)); + else + hashl |= (1 << index); + } + if_maddr_runlock(ifp); + + /* Program new hash filter */ + lpe_write_4(sc, LPE_HASHFILTER_L, hashl); + lpe_write_4(sc, LPE_HASHFILTER_H, hashh); +} + +static void +lpe_intr(void *arg) +{ + struct lpe_softc *sc = (struct lpe_softc *)arg; + uint32_t intstatus; + + debugf("status=0x%08x\n", lpe_read_4(sc, LPE_INTSTATUS)); + + lpe_lock(sc); + + while ((intstatus = lpe_read_4(sc, LPE_INTSTATUS))) { + if (intstatus & LPE_INT_RXDONE) + lpe_rxintr(sc); + + if (intstatus & LPE_INT_TXDONE) + lpe_txintr(sc); + + lpe_write_4(sc, LPE_INTCLEAR, 0xffff); + } + + lpe_unlock(sc); +} + +static void +lpe_rxintr(struct lpe_softc *sc) +{ + struct ifnet *ifp = sc->lpe_ifp; + struct lpe_hwdesc *hwd; + struct lpe_hwstatus *hws; + struct lpe_rxdesc *rxd; + struct mbuf *m; + int prod, cons; + + for (;;) { + prod = lpe_read_4(sc, LPE_RXDESC_PROD); + cons = lpe_read_4(sc, LPE_RXDESC_CONS); + + if (prod == cons) + break; + + rxd = &sc->lpe_cdata.lpe_rx_desc[cons]; + hwd = &sc->lpe_rdata.lpe_rx_ring[cons]; + hws = &sc->lpe_rdata.lpe_rx_status[cons]; + + /* Check received frame for errors */ + if (hws->lhs_info & LPE_HWDESC_RXERRS) { + ifp->if_ierrors++; + lpe_discard_rxbuf(sc, cons); + lpe_init_rxbuf(sc, cons); + goto skip; + } + + m = rxd->lpe_rxdesc_mbuf; + m->m_pkthdr.rcvif = ifp; + m->m_data += 2; + + ifp->if_ipackets++; + + lpe_unlock(sc); + (*ifp->if_input)(ifp, m); + lpe_lock(sc); + + lpe_init_rxbuf(sc, cons); +skip: + LPE_INC(cons, LPE_RXDESC_NUM); + lpe_write_4(sc, LPE_RXDESC_CONS, cons); + } +} + +static void +lpe_txintr(struct lpe_softc *sc) +{ + struct ifnet *ifp = sc->lpe_ifp; + struct lpe_hwdesc *hwd; + struct lpe_hwstatus *hws; + struct lpe_txdesc *txd; + int cons, last; + + for (;;) { + cons = lpe_read_4(sc, LPE_TXDESC_CONS); + last = sc->lpe_cdata.lpe_tx_last; + + if (cons == last) + break; + + txd = &sc->lpe_cdata.lpe_tx_desc[last]; + hwd = &sc->lpe_rdata.lpe_tx_ring[last]; + hws = &sc->lpe_rdata.lpe_tx_status[last]; + + bus_dmamap_sync(sc->lpe_cdata.lpe_tx_buf_tag, + txd->lpe_txdesc_dmamap, BUS_DMASYNC_POSTWRITE); + + ifp->if_collisions += LPE_HWDESC_COLLISIONS(hws->lhs_info); + + if (hws->lhs_info & LPE_HWDESC_TXERRS) + ifp->if_oerrors++; + else + ifp->if_opackets++; + + if (txd->lpe_txdesc_first) { + bus_dmamap_unload(sc->lpe_cdata.lpe_tx_buf_tag, + txd->lpe_txdesc_dmamap); + + m_freem(txd->lpe_txdesc_mbuf); + txd->lpe_txdesc_mbuf = NULL; + txd->lpe_txdesc_first = 0; + } + + sc->lpe_cdata.lpe_tx_used--; + LPE_INC(sc->lpe_cdata.lpe_tx_last, LPE_TXDESC_NUM); + } + + if (!sc->lpe_cdata.lpe_tx_used) + sc->lpe_watchdog_timer = 0; +} + +static void +lpe_tick(void *arg) +{ + struct lpe_softc *sc = (struct lpe_softc *)arg; + struct mii_data *mii = device_get_softc(sc->lpe_miibus); + + lpe_lock_assert(sc); + + mii_tick(mii); + lpe_watchdog(sc); + + callout_reset(&sc->lpe_tick, hz, lpe_tick, sc); +} + +static void +lpe_watchdog(struct lpe_softc *sc) +{ + struct ifnet *ifp = sc->lpe_ifp; + + lpe_lock_assert(sc); + + if (sc->lpe_watchdog_timer == 0 || sc->lpe_watchdog_timer--) + return; + + /* Chip has stopped responding */ + device_printf(sc->lpe_dev, "WARNING: chip hangup, restarting...\n"); + lpe_stop_locked(sc); + lpe_init_locked(sc); + + /* Try to resend packets */ + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + lpe_start_locked(ifp); +} + +static int +lpe_dma_alloc(struct lpe_softc *sc) +{ + int err; + + /* Create parent DMA tag */ + err = bus_dma_tag_create( + bus_get_dma_tag(sc->lpe_dev), + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ + BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lpe_cdata.lpe_parent_tag); + + if (err) { + device_printf(sc->lpe_dev, "cannot create parent DMA tag\n"); + return (err); + } + + err = lpe_dma_alloc_rx(sc); + if (err) + return (err); + + err = lpe_dma_alloc_tx(sc); + if (err) + return (err); + + return (0); +} + +static int +lpe_dma_alloc_rx(struct lpe_softc *sc) +{ + struct lpe_rxdesc *rxd; + struct lpe_dmamap_arg ctx; + int err, i; + + /* Create tag for Rx ring */ + err = bus_dma_tag_create( + sc->lpe_cdata.lpe_parent_tag, + LPE_DESC_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + LPE_RXDESC_SIZE, 1, /* maxsize, nsegments */ + LPE_RXDESC_SIZE, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lpe_cdata.lpe_rx_ring_tag); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Rx ring DMA tag\n"); + goto fail; + } + + /* Create tag for Rx status ring */ + err = bus_dma_tag_create( + sc->lpe_cdata.lpe_parent_tag, + LPE_DESC_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + LPE_RXSTATUS_SIZE, 1, /* maxsize, nsegments */ + LPE_RXSTATUS_SIZE, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lpe_cdata.lpe_rx_status_tag); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Rx status ring DMA tag\n"); + goto fail; + } + + /* Create tag for Rx buffers */ + err = bus_dma_tag_create( + sc->lpe_cdata.lpe_parent_tag, + LPE_DESC_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MCLBYTES * LPE_RXDESC_NUM, /* maxsize */ + LPE_RXDESC_NUM, /* segments */ + MCLBYTES, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lpe_cdata.lpe_rx_buf_tag); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Rx buffers DMA tag\n"); + goto fail; + } + + /* Allocate Rx DMA ring */ + err = bus_dmamem_alloc(sc->lpe_cdata.lpe_rx_ring_tag, + (void **)&sc->lpe_rdata.lpe_rx_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | + BUS_DMA_ZERO, &sc->lpe_cdata.lpe_rx_ring_map); + + err = bus_dmamap_load(sc->lpe_cdata.lpe_rx_ring_tag, + sc->lpe_cdata.lpe_rx_ring_map, sc->lpe_rdata.lpe_rx_ring, + LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0); + + sc->lpe_rdata.lpe_rx_ring_phys = ctx.lpe_dma_busaddr; + + /* Allocate Rx status ring */ + err = bus_dmamem_alloc(sc->lpe_cdata.lpe_rx_status_tag, + (void **)&sc->lpe_rdata.lpe_rx_status, BUS_DMA_WAITOK | BUS_DMA_COHERENT | + BUS_DMA_ZERO, &sc->lpe_cdata.lpe_rx_status_map); + + err = bus_dmamap_load(sc->lpe_cdata.lpe_rx_status_tag, + sc->lpe_cdata.lpe_rx_status_map, sc->lpe_rdata.lpe_rx_status, + LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0); + + sc->lpe_rdata.lpe_rx_status_phys = ctx.lpe_dma_busaddr; + + + /* Create Rx buffers DMA map */ + for (i = 0; i < LPE_RXDESC_NUM; i++) { + rxd = &sc->lpe_cdata.lpe_rx_desc[i]; + rxd->lpe_rxdesc_mbuf = NULL; + rxd->lpe_rxdesc_dmamap = NULL; + + err = bus_dmamap_create(sc->lpe_cdata.lpe_rx_buf_tag, 0, + &rxd->lpe_rxdesc_dmamap); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Rx DMA map\n"); + return (err); + } + } + + return (0); +fail: + return (err); +} + +static int +lpe_dma_alloc_tx(struct lpe_softc *sc) +{ + struct lpe_txdesc *txd; + struct lpe_dmamap_arg ctx; + int err, i; + + /* Create tag for Tx ring */ + err = bus_dma_tag_create( + sc->lpe_cdata.lpe_parent_tag, + LPE_DESC_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + LPE_TXDESC_SIZE, 1, /* maxsize, nsegments */ + LPE_TXDESC_SIZE, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lpe_cdata.lpe_tx_ring_tag); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Tx ring DMA tag\n"); + goto fail; + } + + /* Create tag for Tx status ring */ + err = bus_dma_tag_create( + sc->lpe_cdata.lpe_parent_tag, + LPE_DESC_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + LPE_TXSTATUS_SIZE, 1, /* maxsize, nsegments */ + LPE_TXSTATUS_SIZE, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lpe_cdata.lpe_tx_status_tag); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Tx status ring DMA tag\n"); + goto fail; + } + + /* Create tag for Tx buffers */ + err = bus_dma_tag_create( + sc->lpe_cdata.lpe_parent_tag, + LPE_DESC_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MCLBYTES * LPE_TXDESC_NUM, /* maxsize */ + LPE_TXDESC_NUM, /* segments */ + MCLBYTES, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lpe_cdata.lpe_tx_buf_tag); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Tx buffers DMA tag\n"); + goto fail; + } + + /* Allocate Tx DMA ring */ + err = bus_dmamem_alloc(sc->lpe_cdata.lpe_tx_ring_tag, + (void **)&sc->lpe_rdata.lpe_tx_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | + BUS_DMA_ZERO, &sc->lpe_cdata.lpe_tx_ring_map); + + err = bus_dmamap_load(sc->lpe_cdata.lpe_tx_ring_tag, + sc->lpe_cdata.lpe_tx_ring_map, sc->lpe_rdata.lpe_tx_ring, + LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0); + + sc->lpe_rdata.lpe_tx_ring_phys = ctx.lpe_dma_busaddr; + + /* Allocate Tx status ring */ + err = bus_dmamem_alloc(sc->lpe_cdata.lpe_tx_status_tag, + (void **)&sc->lpe_rdata.lpe_tx_status, BUS_DMA_WAITOK | BUS_DMA_COHERENT | + BUS_DMA_ZERO, &sc->lpe_cdata.lpe_tx_status_map); + + err = bus_dmamap_load(sc->lpe_cdata.lpe_tx_status_tag, + sc->lpe_cdata.lpe_tx_status_map, sc->lpe_rdata.lpe_tx_status, + LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0); + + sc->lpe_rdata.lpe_tx_status_phys = ctx.lpe_dma_busaddr; + + + /* Create Tx buffers DMA map */ + for (i = 0; i < LPE_TXDESC_NUM; i++) { + txd = &sc->lpe_cdata.lpe_tx_desc[i]; + txd->lpe_txdesc_mbuf = NULL; + txd->lpe_txdesc_dmamap = NULL; + txd->lpe_txdesc_first = 0; + + err = bus_dmamap_create(sc->lpe_cdata.lpe_tx_buf_tag, 0, + &txd->lpe_txdesc_dmamap); + + if (err) { + device_printf(sc->lpe_dev, "cannot create Tx DMA map\n"); + return (err); + } + } + + return (0); +fail: + return (err); +} + +static int +lpe_init_rx(struct lpe_softc *sc) +{ + int i, err; + + for (i = 0; i < LPE_RXDESC_NUM; i++) { + err = lpe_init_rxbuf(sc, i); + if (err) + return (err); + } + + return (0); +} + +static int +lpe_init_rxbuf(struct lpe_softc *sc, int n) +{ + struct lpe_rxdesc *rxd; + struct lpe_hwdesc *hwd; + struct lpe_hwstatus *hws; + struct mbuf *m; + bus_dma_segment_t segs[1]; + int nsegs; + + rxd = &sc->lpe_cdata.lpe_rx_desc[n]; + hwd = &sc->lpe_rdata.lpe_rx_ring[n]; + hws = &sc->lpe_rdata.lpe_rx_status[n]; + m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + + if (!m) { + device_printf(sc->lpe_dev, "WARNING: mbufs exhausted!\n"); + return (ENOBUFS); + } + + m->m_len = m->m_pkthdr.len = MCLBYTES; + + bus_dmamap_unload(sc->lpe_cdata.lpe_rx_buf_tag, rxd->lpe_rxdesc_dmamap); + + if (bus_dmamap_load_mbuf_sg(sc->lpe_cdata.lpe_rx_buf_tag, + rxd->lpe_rxdesc_dmamap, m, segs, &nsegs, 0)) { + m_freem(m); + return (ENOBUFS); + } + + bus_dmamap_sync(sc->lpe_cdata.lpe_rx_buf_tag, rxd->lpe_rxdesc_dmamap, + BUS_DMASYNC_PREREAD); + + rxd->lpe_rxdesc_mbuf = m; + hwd->lhr_data = segs[0].ds_addr + 2; + hwd->lhr_control = (segs[0].ds_len - 1) | LPE_HWDESC_INTERRUPT; + + return (0); +} + +static void +lpe_discard_rxbuf(struct lpe_softc *sc, int n) +{ + struct lpe_rxdesc *rxd; + struct lpe_hwdesc *hwd; + + rxd = &sc->lpe_cdata.lpe_rx_desc[n]; + hwd = &sc->lpe_rdata.lpe_rx_ring[n]; + + bus_dmamap_unload(sc->lpe_cdata.lpe_rx_buf_tag, rxd->lpe_rxdesc_dmamap); + + hwd->lhr_data = 0; + hwd->lhr_control = 0; + + if (rxd->lpe_rxdesc_mbuf) { + m_freem(rxd->lpe_rxdesc_mbuf); + rxd->lpe_rxdesc_mbuf = NULL; + } +} + +static void +lpe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct lpe_dmamap_arg *ctx; + + if (error) + return; + + ctx = (struct lpe_dmamap_arg *)arg; + ctx->lpe_dma_busaddr = segs[0].ds_addr; +} + +static int +lpe_ifmedia_upd(struct ifnet *ifp) +{ + return (0); +} + +static void +lpe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct lpe_softc *sc = ifp->if_softc; + struct mii_data *mii = device_get_softc(sc->lpe_miibus); + + lpe_lock(sc); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + lpe_unlock(sc); +} + +static device_method_t lpe_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpe_probe), + DEVMETHOD(device_attach, lpe_attach), + DEVMETHOD(device_detach, lpe_detach), + + /* Bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + + /* MII interface */ + DEVMETHOD(miibus_readreg, lpe_miibus_readreg), + DEVMETHOD(miibus_writereg, lpe_miibus_writereg), + DEVMETHOD(miibus_statchg, lpe_miibus_statchg), + { 0, 0 } +}; + +static driver_t lpe_driver = { + "lpe", + lpe_methods, + sizeof(struct lpe_softc), +}; + +static devclass_t lpe_devclass; + +DRIVER_MODULE(lpe, simplebus, lpe_driver, lpe_devclass, 0, 0); +DRIVER_MODULE(miibus, lpe, miibus_driver, miibus_devclass, 0, 0); +MODULE_DEPEND(lpe, obio, 1, 1, 1); +MODULE_DEPEND(lpe, miibus, 1, 1, 1); +MODULE_DEPEND(lpe, ether, 1, 1, 1); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/if_lpereg.h armv6/sys/arm/lpc/if_lpereg.h --- head/sys/arm/lpc/if_lpereg.h 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/if_lpereg.h 2012-08-08 12:43:50.900723734 -0700 @@ -0,0 +1,206 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM_LPC_IF_LPEREG_H +#define _ARM_LPC_IF_LPEREG_H + +#define LPE_MAC1 0x000 +#define LPE_MAC1_RXENABLE (1 << 0) +#define LPE_MAC1_PASSALL (1 << 1) +#define LPE_MAC1_RXFLOWCTRL (1 << 2) +#define LPE_MAC1_TXFLOWCTRL (1 << 3) +#define LPE_MAC1_LOOPBACK (1 << 4) +#define LPE_MAC1_RESETTX (1 << 8) +#define LPE_MAC1_RESETMCSTX (1 << 9) +#define LPE_MAC1_RESETRX (1 << 10) +#define LPE_MAC1_RESETMCSRX (1 << 11) +#define LPE_MAC1_SIMRESET (1 << 14) +#define LPE_MAC1_SOFTRESET (1 << 15) +#define LPE_MAC2 0x004 +#define LPE_MAC2_FULLDUPLEX (1 << 0) +#define LPE_MAC2_FRAMELENCHECK (1 << 1) +#define LPE_MAC2_HUGEFRAME (1 << 2) +#define LPE_MAC2_DELAYEDCRC (1 << 3) +#define LPE_MAC2_CRCENABLE (1 << 4) +#define LPE_MAC2_PADCRCENABLE (1 << 5) +#define LPE_MAC2_VLANPADENABLE (1 << 6) +#define LPE_MAC2_AUTOPADENABLE (1 << 7) +#define LPE_MAC2_PUREPREAMBLE (1 << 8) +#define LPE_MAC2_LONGPREAMBLE (1 << 9) +#define LPE_MAC2_NOBACKOFF (1 << 12) +#define LPE_MAC2_BACKPRESSURE (1 << 13) +#define LPE_MAC2_EXCESSDEFER (1 << 14) +#define LPE_IPGT 0x008 +#define LPE_IPGR 0x00c +#define LPE_CLRT 0x010 +#define LPE_MAXF 0x014 +#define LPE_SUPP 0x018 +#define LPE_SUPP_SPEED (1 << 8) +#define LPE_TEST 0x01c +#define LPE_MCFG 0x020 +#define LPE_MCFG_SCANINCR (1 << 0) +#define LPE_MCFG_SUPPREAMBLE (1 << 1) +#define LPE_MCFG_CLKSEL(_n) ((_n & 0x7) << 2) +#define LPC_MCFG_RESETMII (1 << 15) +#define LPE_MCMD 0x024 +#define LPE_MCMD_READ (1 << 0) +#define LPE_MCMD_WRITE (0 << 0) +#define LPE_MCMD_SCAN (1 << 1) +#define LPE_MADR 0x028 +#define LPE_MADR_REGMASK 0x1f +#define LPE_MADR_REGSHIFT 0 +#define LPE_MADR_PHYMASK 0x1f +#define LPE_MADR_PHYSHIFT 8 +#define LPE_MWTD 0x02c +#define LPE_MWTD_DATAMASK 0xffff +#define LPE_MRDD 0x030 +#define LPE_MRDD_DATAMASK 0xffff +#define LPE_MIND 0x034 +#define LPE_MIND_BUSY (1 << 0) +#define LPE_MIND_SCANNING (1 << 1) +#define LPE_MIND_INVALID (1 << 2) +#define LPE_MIND_MIIFAIL (1 << 3) +#define LPE_SA0 0x040 +#define LPE_SA1 0x044 +#define LPE_SA2 0x048 +#define LPE_COMMAND 0x100 +#define LPE_COMMAND_RXENABLE (1 << 0) +#define LPE_COMMAND_TXENABLE (1 << 1) +#define LPE_COMMAND_REGRESET (1 << 3) +#define LPE_COMMAND_TXRESET (1 << 4) +#define LPE_COMMAND_RXRESET (1 << 5) +#define LPE_COMMAND_PASSRUNTFRAME (1 << 6) +#define LPE_COMMAND_PASSRXFILTER (1 << 7) +#define LPE_COMMAND_TXFLOWCTL (1 << 8) +#define LPE_COMMAND_RMII (1 << 9) +#define LPE_COMMAND_FULLDUPLEX (1 << 10) +#define LPE_STATUS 0x104 +#define LPE_STATUS_RXACTIVE (1 << 0) +#define LPE_STATUS_TXACTIVE (1 << 1) +#define LPE_RXDESC 0x108 +#define LPE_RXSTATUS 0x10c +#define LPE_RXDESC_NUMBER 0x110 +#define LPE_RXDESC_PROD 0x114 +#define LPE_RXDESC_CONS 0x118 +#define LPE_TXDESC 0x11c +#define LPE_TXSTATUS 0x120 +#define LPE_TXDESC_NUMBER 0x124 +#define LPE_TXDESC_PROD 0x128 +#define LPE_TXDESC_CONS 0x12c +#define LPE_TSV0 0x158 +#define LPE_TSV1 0x15c +#define LPE_RSV 0x160 +#define LPE_FLOWCONTROL_COUNTER 0x170 +#define LPE_FLOWCONTROL_STATUS 0x174 +#define LPE_RXFILTER_CTRL 0x200 +#define LPE_RXFILTER_UNICAST (1 << 0) +#define LPE_RXFILTER_BROADCAST (1 << 1) +#define LPE_RXFILTER_MULTICAST (1 << 2) +#define LPE_RXFILTER_UNIHASH (1 << 3) +#define LPE_RXFILTER_MULTIHASH (1 << 4) +#define LPE_RXFILTER_PERFECT (1 << 5) +#define LPE_RXFILTER_WOL (1 << 12) +#define LPE_RXFILTER_FILTWOL (1 << 13) +#define LPE_RXFILTER_WOL_STATUS 0x204 +#define LPE_RXFILTER_WOL_CLEAR 0x208 +#define LPE_HASHFILTER_L 0x210 +#define LPE_HASHFILTER_H 0x214 +#define LPE_INTSTATUS 0xfe0 +#define LPE_INTENABLE 0xfe4 +#define LPE_INTCLEAR 0xfe8 +#define LPE_INTSET 0xfec +#define LPE_INT_RXOVERRUN (1 << 0) +#define LPE_INT_RXERROR (1 << 1) +#define LPE_INT_RXFINISH (1 << 2) +#define LPE_INT_RXDONE (1 << 3) +#define LPE_INT_TXUNDERRUN (1 << 4) +#define LPE_INT_TXERROR (1 << 5) +#define LPE_INT_TXFINISH (1 << 6) +#define LPE_INT_TXDONE (1 << 7) +#define LPE_INT_SOFTINT (1 << 12) +#define LPE_INTWAKEUPINT (1 << 13) +#define LPE_POWERDOWN 0xff4 + +#define LPE_DESC_ALIGN 8 +#define LPE_TXDESC_NUM 128 +#define LPE_RXDESC_NUM 128 +#define LPE_TXDESC_SIZE (LPE_TXDESC_NUM * sizeof(struct lpe_hwdesc)) +#define LPE_RXDESC_SIZE (LPE_RXDESC_NUM * sizeof(struct lpe_hwdesc)) +#define LPE_TXSTATUS_SIZE (LPE_TXDESC_NUM * sizeof(struct lpe_hwstatus)) +#define LPE_RXSTATUS_SIZE (LPE_RXDESC_NUM * sizeof(struct lpe_hwstatus)) +#define LPE_MAXFRAGS 8 + +struct lpe_hwdesc { + uint32_t lhr_data; + uint32_t lhr_control; +}; + +struct lpe_hwstatus { + uint32_t lhs_info; + uint32_t lhs_crc; +}; + +#define LPE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 + +/* These are valid for both Rx and Tx descriptors */ +#define LPE_HWDESC_SIZE_MASK (1 << 10) +#define LPE_HWDESC_INTERRUPT (1 << 31) + +/* These are valid for Tx descriptors */ +#define LPE_HWDESC_LAST (1 << 30) +#define LPE_HWDESC_CRC (1 << 29) +#define LPE_HWDESC_PAD (1 << 28) +#define LPE_HWDESC_HUGE (1 << 27) +#define LPE_HWDESC_OVERRIDE (1 << 26) + +/* These are valid for Tx status descriptors */ +#define LPE_HWDESC_COLLISIONS(_n) (((_n) >> 21) & 0x7) +#define LPE_HWDESC_DEFER (1 << 25) +#define LPE_HWDESC_EXCDEFER (1 << 26) +#define LPE_HWDESC_EXCCOLL (1 << 27) +#define LPE_HWDESC_LATECOLL (1 << 28) +#define LPE_HWDESC_UNDERRUN (1 << 29) +#define LPE_HWDESC_TXNODESCR (1 << 30) +#define LPE_HWDESC_ERROR (1 << 31) + +/* These are valid for Rx status descriptors */ +#define LPE_HWDESC_CONTROL (1 << 18) +#define LPE_HWDESC_VLAN (1 << 19) +#define LPE_HWDESC_FAILFILTER (1 << 20) +#define LPE_HWDESC_MULTICAST (1 << 21) +#define LPE_HWDESC_BROADCAST (1 << 22) +#define LPE_HWDESC_CRCERROR (1 << 23) +#define LPE_HWDESC_SYMBOLERROR (1 << 24) +#define LPE_HWDESC_LENGTHERROR (1 << 25) +#define LPE_HWDESC_RANGEERROR (1 << 26) +#define LPE_HWDESC_ALIGNERROR (1 << 27) +#define LPE_HWDESC_OVERRUN (1 << 28) +#define LPE_HWDESC_RXNODESCR (1 << 29) +#define LPE_HWDESC_LASTFLAG (1 << 30) +#define LPE_HWDESC_ERROR (1 << 31) + + +#endif /* _ARM_LPC_IF_LPEREG_H */ diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_dmac.c armv6/sys/arm/lpc/lpc_dmac.c --- head/sys/arm/lpc/lpc_dmac.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_dmac.c 2012-08-08 12:43:50.900723734 -0700 @@ -0,0 +1,288 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include + +struct lpc_dmac_channel +{ + struct lpc_dmac_channel_config *ldc_config; + int ldc_flags; +}; + +struct lpc_dmac_softc +{ + device_t ld_dev; + struct mtx ld_mtx; + struct resource * ld_mem_res; + struct resource * ld_irq_res; + bus_space_tag_t ld_bst; + bus_space_handle_t ld_bsh; + void * ld_intrhand; + struct lpc_dmac_channel ld_channels[8]; +}; + +static struct lpc_dmac_softc *lpc_dmac_sc = NULL; + +static int lpc_dmac_probe(device_t); +static int lpc_dmac_attach(device_t); +static void lpc_dmac_intr(void *); + +#define lpc_dmac_read_4(_sc, _reg) \ + bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, _reg) +#define lpc_dmac_write_4(_sc, _reg, _value) \ + bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, _reg, _value) +#define lpc_dmac_read_ch_4(_sc, _n, _reg) \ + bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n))) +#define lpc_dmac_write_ch_4(_sc, _n, _reg, _value) \ + bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n)), _value) + +static int lpc_dmac_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "lpc,dmac")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 General Purpose DMA controller"); + return (BUS_PROBE_DEFAULT); +} + +static int lpc_dmac_attach(device_t dev) +{ + struct lpc_dmac_softc *sc = device_get_softc(dev); + int rid; + + rid = 0; + sc->ld_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->ld_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->ld_bst = rman_get_bustag(sc->ld_mem_res); + sc->ld_bsh = rman_get_bushandle(sc->ld_mem_res); + + rid = 0; + sc->ld_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (!sc->ld_irq_res) { + device_printf(dev, "cannot allocate cmd interrupt\n"); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res); + return (ENXIO); + } + + if (bus_setup_intr(dev, sc->ld_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, lpc_dmac_intr, sc, &sc->ld_intrhand)) + { + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res); + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ld_irq_res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + lpc_dmac_sc = sc; + + lpc_pwr_write(dev, LPC_CLKPWR_DMACLK_CTRL, LPC_CLKPWR_DMACLK_CTRL_EN); + lpc_dmac_write_4(sc, LPC_DMAC_CONFIG, LPC_DMAC_CONFIG_ENABLE); + + lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, 0xff); + lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, 0xff); + + return (0); +} + +static void lpc_dmac_intr(void *arg) +{ + struct lpc_dmac_softc *sc = (struct lpc_dmac_softc *)arg; + struct lpc_dmac_channel *ch; + uint32_t intstat, tcstat, errstat; + int i; + + do { + intstat = lpc_dmac_read_4(sc, LPC_DMAC_INTSTAT); + + for (i = 0; i < LPC_DMAC_CHNUM; i++) { + if ((intstat & (1 << i)) == 0) + continue; + + ch = &sc->ld_channels[i]; + tcstat = lpc_dmac_read_4(sc, LPC_DMAC_INTTCSTAT); + errstat = lpc_dmac_read_4(sc, LPC_DMAC_INTERRSTAT); + + if (tcstat & (1 << i)) { + ch->ldc_config->ldc_success_handler( + ch->ldc_config->ldc_handler_arg); + lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, (1 << i)); + } + + if (errstat & (1 << i)) { + ch->ldc_config->ldc_error_handler( + ch->ldc_config->ldc_handler_arg); + lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, (1 << i)); + } + } + + } while (intstat); +} + +int +lpc_dmac_config_channel(device_t dev, int chno, struct lpc_dmac_channel_config *cfg) +{ + struct lpc_dmac_softc *sc = lpc_dmac_sc; + struct lpc_dmac_channel *ch; + + if (sc == NULL) + return (ENXIO); + + ch = &sc->ld_channels[chno]; + ch->ldc_config = cfg; + + return 0; +} + +int +lpc_dmac_setup_transfer(device_t dev, int chno, bus_addr_t src, bus_addr_t dst, + bus_size_t size, int flags) +{ + struct lpc_dmac_softc *sc = lpc_dmac_sc; + struct lpc_dmac_channel *ch; + uint32_t ctrl, cfg; + + if (sc == NULL) + return (ENXIO); + + ch = &sc->ld_channels[chno]; + + ctrl = LPC_DMAC_CH_CONTROL_I | + (ch->ldc_config->ldc_dst_incr ? LPC_DMAC_CH_CONTROL_DI : 0) | + (ch->ldc_config->ldc_src_incr ? LPC_DMAC_CH_CONTROL_SI : 0) | + LPC_DMAC_CH_CONTROL_DWIDTH(ch->ldc_config->ldc_dst_width) | + LPC_DMAC_CH_CONTROL_SWIDTH(ch->ldc_config->ldc_src_width) | + LPC_DMAC_CH_CONTROL_DBSIZE(ch->ldc_config->ldc_dst_burst) | + LPC_DMAC_CH_CONTROL_SBSIZE(ch->ldc_config->ldc_src_burst) | + size; + + cfg = LPC_DMAC_CH_CONFIG_ITC | LPC_DMAC_CH_CONFIG_IE | + LPC_DMAC_CH_CONFIG_FLOWCNTL(ch->ldc_config->ldc_fcntl) | + LPC_DMAC_CH_CONFIG_DESTP(ch->ldc_config->ldc_dst_periph) | + LPC_DMAC_CH_CONFIG_SRCP(ch->ldc_config->ldc_src_periph) | LPC_DMAC_CH_CONFIG_E; + lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_SRCADDR, src); + lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_DSTADDR, dst); + lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_LLI, 0); + lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONTROL, ctrl); + lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg); + + return 0; +} + +int +lpc_dmac_enable_channel(device_t dev, int chno) +{ + struct lpc_dmac_softc *sc = lpc_dmac_sc; + uint32_t cfg; + + if (sc == NULL) + return (ENXIO); + + cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG); + cfg |= LPC_DMAC_CH_CONFIG_E; + + lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg); + + return 0; +} + +int +lpc_dmac_disable_channel(device_t dev, int chno) +{ + struct lpc_dmac_softc *sc = lpc_dmac_sc; + uint32_t cfg; + + if (sc == NULL) + return (ENXIO); + + cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG); + cfg &= ~LPC_DMAC_CH_CONFIG_E; + + lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg); + + return 0; +} + +int +lpc_dmac_start_burst(device_t dev, int id) +{ + struct lpc_dmac_softc *sc = lpc_dmac_sc; + + lpc_dmac_write_4(sc, LPC_DMAC_SOFTBREQ, (1 << id)); + return (0); +} + +static device_method_t lpc_dmac_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_dmac_probe), + DEVMETHOD(device_attach, lpc_dmac_attach), + + { 0, 0 }, +}; + +static devclass_t lpc_dmac_devclass; + +static driver_t lpc_dmac_driver = { + "dmac", + lpc_dmac_methods, + sizeof(struct lpc_dmac_softc), +}; + +DRIVER_MODULE(dmac, simplebus, lpc_dmac_driver, lpc_dmac_devclass, 0, 0); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_fb.c armv6/sys/arm/lpc/lpc_fb.c --- head/sys/arm/lpc/lpc_fb.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_fb.c 2012-08-08 12:43:50.904723926 -0700 @@ -0,0 +1,466 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + + +struct lpc_fb_dmamap_arg { + bus_addr_t lf_dma_busaddr; +}; + +struct lpc_lcd_config { + int lc_xres; + int lc_yres; + int lc_bpp; + uint32_t lc_pixelclock; + int lc_left_margin; + int lc_right_margin; + int lc_upper_margin; + int lc_lower_margin; + int lc_hsync_len; + int lc_vsync_len; +}; + +struct lpc_fb_softc { + device_t lf_dev; + struct cdev * lf_cdev; + struct mtx lf_mtx; + struct resource * lf_mem_res; + struct resource * lf_irq_res; + bus_space_tag_t lf_bst; + bus_space_handle_t lf_bsh; + void * lf_intrhand; + bus_dma_tag_t lf_dma_tag; + bus_dmamap_t lf_dma_map; + void * lf_buffer; + bus_addr_t lf_buffer_phys; + bus_size_t lf_buffer_size; + struct lpc_lcd_config lf_lcd_config; + int lf_initialized; + int lf_opened; +}; + +extern void ssd1289_configure(void); + +#define lpc_fb_lock(_sc) mtx_lock(&(_sc)->lf_mtx) +#define lpc_fb_unlock(_sc) mtx_unlock(&(_sc)->lf_mtx) +#define lpc_fb_lock_assert(sc) mtx_assert(&(_sc)->lf_mtx, MA_OWNED) + +#define lpc_fb_read_4(_sc, _reg) \ + bus_space_read_4((_sc)->lf_bst, (_sc)->lf_bsh, (_reg)) +#define lpc_fb_write_4(_sc, _reg, _val) \ + bus_space_write_4((_sc)->lf_bst, (_sc)->lf_bsh, (_reg), (_val)) + + + +static int lpc_fb_probe(device_t); +static int lpc_fb_attach(device_t); +static void lpc_fb_intr(void *); +static void lpc_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err); + +static int lpc_fb_fdt_read(phandle_t, const char *, uint32_t *); +static int lpc_fb_read_lcd_config(phandle_t, struct lpc_lcd_config *); + +static int lpc_fb_open(struct cdev *, int, int, struct thread *); +static int lpc_fb_close(struct cdev *, int, int, struct thread *); +static int lpc_fb_ioctl(struct cdev *, u_long, caddr_t, int, struct thread *); +static int lpc_fb_mmap(struct cdev *, vm_ooffset_t, vm_paddr_t *, int, vm_memattr_t *); + +static void lpc_fb_blank(struct lpc_fb_softc *); + +static struct cdevsw lpc_fb_cdevsw = { + .d_open = lpc_fb_open, + .d_close = lpc_fb_close, + .d_ioctl = lpc_fb_ioctl, + .d_mmap = lpc_fb_mmap, + .d_name = "lpcfb", + .d_version = D_VERSION, +}; + +static int +lpc_fb_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "lpc,fb")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 framebuffer device"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_fb_attach(device_t dev) +{ + struct lpc_fb_softc *sc = device_get_softc(dev); + struct lpc_fb_dmamap_arg ctx; + phandle_t node; + int mode, rid, err = 0; + + sc->lf_dev = dev; + mtx_init(&sc->lf_mtx, "lpcfb", "fb", MTX_DEF); + + rid = 0; + sc->lf_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->lf_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->lf_bst = rman_get_bustag(sc->lf_mem_res); + sc->lf_bsh = rman_get_bushandle(sc->lf_mem_res); + + rid = 0; + sc->lf_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (!sc->lf_irq_res) { + device_printf(dev, "cannot allocate interrupt\n"); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lf_mem_res); + return (ENXIO); + } + + if (bus_setup_intr(dev, sc->lf_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, lpc_fb_intr, sc, &sc->lf_intrhand)) + { + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lf_mem_res); + bus_release_resource(dev, SYS_RES_IRQ, 1, sc->lf_irq_res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + node = ofw_bus_get_node(dev); + + err = lpc_fb_read_lcd_config(node, &sc->lf_lcd_config); + if (err) { + device_printf(dev, "cannot read LCD configuration\n"); + goto fail; + } + + sc->lf_buffer_size = sc->lf_lcd_config.lc_xres * + sc->lf_lcd_config.lc_yres * + (sc->lf_lcd_config.lc_bpp == 24 ? 3 : 2); + + device_printf(dev, "%dx%d LCD, %d bits per pixel, %dkHz pixel clock\n", + sc->lf_lcd_config.lc_xres, sc->lf_lcd_config.lc_yres, + sc->lf_lcd_config.lc_bpp, sc->lf_lcd_config.lc_pixelclock / 1000); + + err = bus_dma_tag_create( + bus_get_dma_tag(sc->lf_dev), + 4, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + sc->lf_buffer_size, 1, /* maxsize, nsegments */ + sc->lf_buffer_size, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lf_dma_tag); + + err = bus_dmamem_alloc(sc->lf_dma_tag, (void **)&sc->lf_buffer, + 0, &sc->lf_dma_map); + if (err) { + device_printf(dev, "cannot allocate framebuffer\n"); + goto fail; + } + + err = bus_dmamap_load(sc->lf_dma_tag, sc->lf_dma_map, sc->lf_buffer, + sc->lf_buffer_size, lpc_fb_dmamap_cb, &ctx, BUS_DMA_NOWAIT); + if (err) { + device_printf(dev, "cannot load DMA map\n"); + goto fail; + } + + switch (sc->lf_lcd_config.lc_bpp) { + case 12: + mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_12; + break; + case 15: + mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_15; + break; + case 16: + mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_16; + break; + case 24: + mode = LPC_CLKPWR_LCDCLK_CTRL_MODE_24; + break; + default: + panic("unsupported bpp"); + } + + lpc_pwr_write(sc->lf_dev, LPC_CLKPWR_LCDCLK_CTRL, + LPC_CLKPWR_LCDCLK_CTRL_MODE(mode) | + LPC_CLKPWR_LCDCLK_CTRL_HCLKEN); + + sc->lf_buffer_phys = ctx.lf_dma_busaddr; + sc->lf_cdev = make_dev(&lpc_fb_cdevsw, 0, UID_ROOT, GID_WHEEL, + 0600, "lpcfb"); + + sc->lf_cdev->si_drv1 = sc; + + return (0); +fail: + return (ENXIO); +} + +static void +lpc_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) +{ + struct lpc_fb_dmamap_arg *ctx; + + if (err) + return; + + ctx = (struct lpc_fb_dmamap_arg *)arg; + ctx->lf_dma_busaddr = segs[0].ds_addr; +} + +static void +lpc_fb_intr(void *arg) +{ +} + +static int +lpc_fb_fdt_read(phandle_t node, const char *name, uint32_t *ret) +{ + if (OF_getprop(node, name, ret, sizeof(uint32_t)) <= 0) + return (ENOENT); + + *ret = fdt32_to_cpu(*ret); + return (0); +} + +static int +lpc_fb_read_lcd_config(phandle_t node, struct lpc_lcd_config *cfg) +{ + if (lpc_fb_fdt_read(node, "horizontal-resolution", &cfg->lc_xres)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "vertical-resolution", &cfg->lc_yres)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "bits-per-pixel", &cfg->lc_bpp)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "pixel-clock", &cfg->lc_pixelclock)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "left-margin", &cfg->lc_left_margin)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "right-margin", &cfg->lc_right_margin)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "upper-margin", &cfg->lc_upper_margin)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "lower-margin", &cfg->lc_lower_margin)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "hsync-len", &cfg->lc_hsync_len)) + return (ENXIO); + + if (lpc_fb_fdt_read(node, "vsync-len", &cfg->lc_vsync_len)) + return (ENXIO); + + return (0); +} + +static void +lpc_fb_setup(struct lpc_fb_softc *sc) +{ + struct lpc_lcd_config *cfg = &sc->lf_lcd_config; + uint32_t bpp; + + lpc_fb_write_4(sc, LPC_LCD_TIMH, + LPC_LCD_TIMH_PPL(cfg->lc_xres) | + LPC_LCD_TIMH_HSW(cfg->lc_hsync_len - 1) | + LPC_LCD_TIMH_HFP(cfg->lc_right_margin - 1) | + LPC_LCD_TIMH_HBP(cfg->lc_left_margin - 1)); + + lpc_fb_write_4(sc, LPC_LCD_TIMV, + LPC_LCD_TIMV_LPP(cfg->lc_yres - 1) | + LPC_LCD_TIMV_VSW(cfg->lc_vsync_len - 1) | + LPC_LCD_TIMV_VFP(cfg->lc_lower_margin) | + LPC_LCD_TIMV_VBP(cfg->lc_upper_margin)); + + /* XXX LPC_LCD_POL_PCD_LO */ + lpc_fb_write_4(sc, LPC_LCD_POL, + LPC_LCD_POL_IHS | LPC_LCD_POL_IVS | + LPC_LCD_POL_CPL(cfg->lc_xres - 1) | + LPC_LCD_POL_PCD_LO(4)); + + lpc_fb_write_4(sc, LPC_LCD_UPBASE, sc->lf_buffer_phys); + + switch (cfg->lc_bpp) { + case 1: + bpp = LPC_LCD_CTRL_BPP1; + break; + case 2: + bpp = LPC_LCD_CTRL_BPP2; + break; + case 4: + bpp = LPC_LCD_CTRL_BPP4; + break; + case 8: + bpp = LPC_LCD_CTRL_BPP8; + break; + case 12: + bpp = LPC_LCD_CTRL_BPP12_444; + break; + case 15: + bpp = LPC_LCD_CTRL_BPP16; + break; + case 16: + bpp = LPC_LCD_CTRL_BPP16_565; + break; + case 24: + bpp = LPC_LCD_CTRL_BPP24; + break; + default: + panic("LCD unknown bpp: %d", cfg->lc_bpp); + } + + lpc_fb_write_4(sc, LPC_LCD_CTRL, + LPC_LCD_CTRL_LCDVCOMP(1) | + LPC_LCD_CTRL_LCDPWR | + LPC_LCD_CTRL_BGR | + LPC_LCD_CTRL_LCDTFT | + LPC_LCD_CTRL_LCDBPP(bpp) | + LPC_LCD_CTRL_LCDEN); +} + + +static int +lpc_fb_open(struct cdev *cdev, int oflags, int devtype, struct thread *td) +{ + struct lpc_fb_softc *sc = cdev->si_drv1; + + lpc_fb_lock(sc); + + if (sc->lf_opened) + return (EBUSY); + + sc->lf_opened = 1; + + lpc_fb_unlock(sc); + + if (!sc->lf_initialized) { + ssd1289_configure(); + lpc_fb_setup(sc); + lpc_fb_blank(sc); + sc->lf_initialized = 1; + } + + return (0); +} + +static int +lpc_fb_close(struct cdev *cdev, int fflag, int devtype, struct thread *td) +{ + struct lpc_fb_softc *sc = cdev->si_drv1; + + lpc_fb_lock(sc); + sc->lf_opened = 0; + lpc_fb_unlock(sc); + + return (0); +} + +static int +lpc_fb_ioctl(struct cdev *cdev, u_long cmd, caddr_t data, int x, + struct thread *td) +{ + + return (EINVAL); +} + +static int +lpc_fb_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, + int nprot, vm_memattr_t *memattr) +{ + struct lpc_fb_softc *sc = cdev->si_drv1; + + *paddr = (vm_paddr_t)(sc->lf_buffer_phys + offset); + return (0); +} + +static void +lpc_fb_blank(struct lpc_fb_softc *sc) +{ + memset(sc->lf_buffer, 0xffff, sc->lf_buffer_size); +} + +static device_method_t lpc_fb_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_fb_probe), + DEVMETHOD(device_attach, lpc_fb_attach), + + { 0, 0 } +}; + +static devclass_t lpc_fb_devclass; + +static driver_t lpc_fb_driver = { + "lpcfb", + lpc_fb_methods, + sizeof(struct lpc_fb_softc), +}; + +DRIVER_MODULE(lpcfb, simplebus, lpc_fb_driver, lpc_fb_devclass, 0, 0); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_gpio.c armv6/sys/arm/lpc/lpc_gpio.c --- head/sys/arm/lpc/lpc_gpio.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_gpio.c 2012-08-08 12:43:50.908724568 -0700 @@ -0,0 +1,547 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +/* + * GPIO on LPC32x0 consist of 4 ports: + * - Port0 with 8 input/output pins + * - Port1 with 24 input/output pins + * - Port2 with 13 input/output pins + * - Port3 with: + * - 26 input pins (GPI_00..GPI_09 + GPI_15..GPI_23 + GPI_25 + GPI_27..GPI_28) + * - 24 output pins (GPO_00..GPO_23) + * - 6 input/ouput pins (GPIO_00..GPIO_05) + * + * Pins are mapped to logical pin number as follows: + * [0..9] -> GPI_00..GPI_09 (port 3) + * [10..18] -> GPI_15..GPI_23 (port 3) + * [19] -> GPI_25 (port 3) + * [20..21] -> GPI_27..GPI_28 (port 3) + * [22..45] -> GPO_00..GPO_23 (port 3) + * [46..51] -> GPIO_00..GPIO_05 (port 3) + * [52..64] -> P2.0..P2.12 (port 2) + * [65..88] -> P1.0..P1.23 (port 1) + * [89..96] -> P0.0..P0.7 (port 0) + * + */ + + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "gpio_if.h" + +struct lpc_gpio_softc +{ + device_t lg_dev; + struct resource * lg_res; + bus_space_tag_t lg_bst; + bus_space_handle_t lg_bsh; +}; + +struct lpc_gpio_pinmap +{ + int lp_start_idx; + int lp_pin_count; + int lp_port; + int lp_start_bit; + int lp_flags; +}; + +static const struct lpc_gpio_pinmap lpc_gpio_pins[] = { + { 0, 10, 3, 0, GPIO_PIN_INPUT }, + { 10, 9, 3, 15, GPIO_PIN_INPUT }, + { 19, 1, 3, 25, GPIO_PIN_INPUT }, + { 20, 2, 3, 27, GPIO_PIN_INPUT }, + { 22, 24, 3, 0, GPIO_PIN_OUTPUT }, + /* + * -1 below is to mark special case for Port3 GPIO pins, as they + * have other bits in Port 3 registers as inputs and as outputs + */ + { 46, 6, 3, -1, GPIO_PIN_INPUT | GPIO_PIN_OUTPUT }, + { 52, 13, 2, 0, GPIO_PIN_INPUT | GPIO_PIN_OUTPUT }, + { 65, 24, 1, 0, GPIO_PIN_INPUT | GPIO_PIN_OUTPUT }, + { 89, 8, 0, 0, GPIO_PIN_INPUT | GPIO_PIN_OUTPUT }, + { -1, -1, -1, -1, -1 }, +}; + +#define LPC_GPIO_NPINS \ + (LPC_GPIO_P0_COUNT + LPC_GPIO_P1_COUNT + \ + LPC_GPIO_P2_COUNT + LPC_GPIO_P3_COUNT) + +#define LPC_GPIO_PIN_IDX(_map, _idx) \ + (_idx - _map->lp_start_idx) + +#define LPC_GPIO_PIN_BIT(_map, _idx) \ + (_map->lp_start_bit + LPC_GPIO_PIN_IDX(_map, _idx)) + +static int lpc_gpio_probe(device_t); +static int lpc_gpio_attach(device_t); +static int lpc_gpio_detach(device_t); + +static int lpc_gpio_pin_max(device_t, int *); +static int lpc_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); +static int lpc_gpio_pin_getflags(device_t, uint32_t, uint32_t *); +static int lpc_gpio_pin_setflags(device_t, uint32_t, uint32_t); +static int lpc_gpio_pin_getname(device_t, uint32_t, char *); +static int lpc_gpio_pin_get(device_t, uint32_t, uint32_t *); +static int lpc_gpio_pin_set(device_t, uint32_t, uint32_t); +static int lpc_gpio_pin_toggle(device_t, uint32_t); + +static const struct lpc_gpio_pinmap *lpc_gpio_get_pinmap(int); + +static struct lpc_gpio_softc *lpc_gpio_sc = NULL; + +#define lpc_gpio_read_4(_sc, _reg) \ + bus_space_read_4(_sc->lg_bst, _sc->lg_bsh, _reg) +#define lpc_gpio_write_4(_sc, _reg, _val) \ + bus_space_write_4(_sc->lg_bst, _sc->lg_bsh, _reg, _val) +#define lpc_gpio_get_4(_sc, _test, _reg1, _reg2) \ + lpc_gpio_read_4(_sc, ((_test) ? _reg1 : _reg2)) +#define lpc_gpio_set_4(_sc, _test, _reg1, _reg2, _val) \ + lpc_gpio_write_4(_sc, ((_test) ? _reg1 : _reg2), _val) + +static int +lpc_gpio_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "lpc,gpio")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 GPIO"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_gpio_attach(device_t dev) +{ + struct lpc_gpio_softc *sc = device_get_softc(dev); + int rid; + + sc->lg_dev = dev; + + rid = 0; + sc->lg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->lg_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->lg_bst = rman_get_bustag(sc->lg_res); + sc->lg_bsh = rman_get_bushandle(sc->lg_res); + + lpc_gpio_sc = sc; + + device_add_child(dev, "gpioc", device_get_unit(dev)); + device_add_child(dev, "gpiobus", device_get_unit(dev)); + + return (bus_generic_attach(dev)); +} + +static int +lpc_gpio_detach(device_t dev) +{ + return (EBUSY); +} + +static int +lpc_gpio_pin_max(device_t dev, int *npins) +{ + *npins = LPC_GPIO_NPINS - 1; + return (0); +} + +static int +lpc_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) +{ + const struct lpc_gpio_pinmap *map; + + if (pin > LPC_GPIO_NPINS) + return (ENODEV); + + map = lpc_gpio_get_pinmap(pin); + + *caps = map->lp_flags; + return (0); +} + +static int +lpc_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) +{ + struct lpc_gpio_softc *sc = device_get_softc(dev); + const struct lpc_gpio_pinmap *map; + uint32_t state; + int dir; + + if (pin > LPC_GPIO_NPINS) + return (ENODEV); + + map = lpc_gpio_get_pinmap(pin); + + /* Check whether it's bidirectional pin */ + if ((map->lp_flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) != + (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { + *flags = map->lp_flags; + return (0); + } + + switch (map->lp_port) { + case 0: + state = lpc_gpio_read_4(sc, LPC_GPIO_P0_DIR_STATE); + dir = (state & (1 << LPC_GPIO_PIN_BIT(map, pin))); + break; + case 1: + state = lpc_gpio_read_4(sc, LPC_GPIO_P1_DIR_STATE); + dir = (state & (1 << LPC_GPIO_PIN_BIT(map, pin))); + break; + case 2: + state = lpc_gpio_read_4(sc, LPC_GPIO_P2_DIR_STATE); + dir = (state & (1 << LPC_GPIO_PIN_BIT(map, pin))); + break; + case 3: + state = lpc_gpio_read_4(sc, LPC_GPIO_P2_DIR_STATE); + dir = (state & (1 << (25 + LPC_GPIO_PIN_IDX(map, pin)))); + break; + default: + panic("unknown GPIO port"); + } + + *flags = dir ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; + + return (0); +} + +static int +lpc_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) +{ + struct lpc_gpio_softc *sc = device_get_softc(dev); + const struct lpc_gpio_pinmap *map; + uint32_t dir, state; + + if (pin > LPC_GPIO_NPINS) + return (ENODEV); + + map = lpc_gpio_get_pinmap(pin); + + /* Check whether it's bidirectional pin */ + if ((map->lp_flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) != + (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) + return (ENOTSUP); + + if (flags & GPIO_PIN_INPUT) + dir = 0; + + if (flags & GPIO_PIN_OUTPUT) + dir = 1; + + switch (map->lp_port) { + case 0: + state = (1 << LPC_GPIO_PIN_IDX(map, pin)); + lpc_gpio_set_4(sc, dir, LPC_GPIO_P0_DIR_SET, + LPC_GPIO_P0_DIR_CLR, state); + break; + case 1: + state = (1 << LPC_GPIO_PIN_IDX(map, pin)); + lpc_gpio_set_4(sc, dir, LPC_GPIO_P1_DIR_SET, + LPC_GPIO_P0_DIR_CLR, state); + break; + case 2: + state = (1 << LPC_GPIO_PIN_IDX(map, pin)); + lpc_gpio_set_4(sc, dir, LPC_GPIO_P2_DIR_SET, + LPC_GPIO_P0_DIR_CLR, state); + break; + case 3: + state = (1 << (25 + (pin - map->lp_start_idx))); + lpc_gpio_set_4(sc, dir, LPC_GPIO_P2_DIR_SET, + LPC_GPIO_P0_DIR_CLR, state); + break; + } + + return (0); +} + +static int +lpc_gpio_pin_getname(device_t dev, uint32_t pin, char *name) +{ + const struct lpc_gpio_pinmap *map; + int idx; + + map = lpc_gpio_get_pinmap(pin); + idx = LPC_GPIO_PIN_IDX(map, pin); + + switch (map->lp_port) { + case 0: + case 1: + case 2: + snprintf(name, GPIOMAXNAME - 1, "P%d.%d", map->lp_port, + map->lp_start_bit + LPC_GPIO_PIN_IDX(map, pin)); + break; + case 3: + if (map->lp_start_bit == -1) { + snprintf(name, GPIOMAXNAME - 1, "GPIO_%02d", idx); + break; + } + + snprintf(name, GPIOMAXNAME - 1, "GP%c_%02d", + (map->lp_flags & GPIO_PIN_INPUT) ? 'I' : 'O', + map->lp_start_bit + idx); + break; + } + + return (0); +} + +static int +lpc_gpio_pin_get(device_t dev, uint32_t pin, uint32_t *value) +{ + struct lpc_gpio_softc *sc = device_get_softc(dev); + const struct lpc_gpio_pinmap *map; + uint32_t state, flags; + int dir; + + map = lpc_gpio_get_pinmap(pin); + + if (lpc_gpio_pin_getflags(dev, pin, &flags)) + return (ENXIO); + + if (flags & GPIO_PIN_OUTPUT) + dir = 1; + + if (flags & GPIO_PIN_INPUT) + dir = 0; + + switch (map->lp_port) { + case 0: + state = lpc_gpio_get_4(sc, dir, LPC_GPIO_P0_OUTP_STATE, + LPC_GPIO_P0_INP_STATE); + *value = !!(state & (1 << LPC_GPIO_PIN_BIT(map, pin))); + case 1: + state = lpc_gpio_get_4(sc, dir, LPC_GPIO_P1_OUTP_STATE, + LPC_GPIO_P1_INP_STATE); + *value = !!(state & (1 << LPC_GPIO_PIN_BIT(map, pin))); + case 2: + state = lpc_gpio_read_4(sc, LPC_GPIO_P2_INP_STATE); + *value = !!(state & (1 << LPC_GPIO_PIN_BIT(map, pin))); + case 3: + state = lpc_gpio_get_4(sc, dir, LPC_GPIO_P3_OUTP_STATE, + LPC_GPIO_P3_INP_STATE); + if (map->lp_start_bit == -1) { + if (dir) + *value = !!(state & (1 << (25 + + LPC_GPIO_PIN_IDX(map, pin)))); + else + *value = !!(state & (1 << (10 + + LPC_GPIO_PIN_IDX(map, pin)))); + } + + *value = !!(state & (1 << LPC_GPIO_PIN_BIT(map, pin))); + } + + return (0); +} + +static int +lpc_gpio_pin_set(device_t dev, uint32_t pin, uint32_t value) +{ + struct lpc_gpio_softc *sc = device_get_softc(dev); + const struct lpc_gpio_pinmap *map; + uint32_t state, flags; + + map = lpc_gpio_get_pinmap(pin); + + if (lpc_gpio_pin_getflags(dev, pin, &flags)) + return (ENXIO); + + if ((flags & GPIO_PIN_OUTPUT) == 0) + return (EINVAL); + + state = (1 << LPC_GPIO_PIN_BIT(map, pin)); + + switch (map->lp_port) { + case 0: + lpc_gpio_set_4(sc, value, LPC_GPIO_P0_OUTP_SET, + LPC_GPIO_P0_OUTP_CLR, state); + break; + case 1: + lpc_gpio_set_4(sc, value, LPC_GPIO_P1_OUTP_SET, + LPC_GPIO_P1_OUTP_CLR, state); + break; + case 2: + lpc_gpio_set_4(sc, value, LPC_GPIO_P2_OUTP_SET, + LPC_GPIO_P2_OUTP_CLR, state); + break; + case 3: + if (map->lp_start_bit == -1) + state = (1 << (25 + LPC_GPIO_PIN_IDX(map, pin))); + + lpc_gpio_set_4(sc, value, LPC_GPIO_P3_OUTP_SET, + LPC_GPIO_P3_OUTP_CLR, state); + break; + } + + return (0); +} + +static int +lpc_gpio_pin_toggle(device_t dev, uint32_t pin) +{ + const struct lpc_gpio_pinmap *map; + uint32_t flags; + + map = lpc_gpio_get_pinmap(pin); + + if (lpc_gpio_pin_getflags(dev, pin, &flags)) + return (ENXIO); + + if ((flags & GPIO_PIN_OUTPUT) == 0) + return (EINVAL); + + panic("not implemented yet"); + + return (0); + +} + +static const struct lpc_gpio_pinmap * +lpc_gpio_get_pinmap(int pin) +{ + const struct lpc_gpio_pinmap *map; + + for (map = &lpc_gpio_pins[0]; map->lp_start_idx != -1; map++) { + if (pin >= map->lp_start_idx && + pin < map->lp_start_idx + map->lp_pin_count) + return map; + } + + panic("pin number %d out of range", pin); +} + +int +lpc_gpio_set_flags(device_t dev, int pin, int flags) +{ + if (lpc_gpio_sc == NULL) + return (ENXIO); + + return lpc_gpio_pin_setflags(lpc_gpio_sc->lg_dev, pin, flags); +} + +int +lpc_gpio_set_state(device_t dev, int pin, int state) +{ + if (lpc_gpio_sc == NULL) + return (ENXIO); + + return lpc_gpio_pin_set(lpc_gpio_sc->lg_dev, pin, state); +} + +int +lpc_gpio_get_state(device_t dev, int pin, int *state) +{ + if (lpc_gpio_sc == NULL) + return (ENXIO); + + return lpc_gpio_pin_get(lpc_gpio_sc->lg_dev, pin, state); +} + +void +platform_gpio_init() +{ + /* Preset SPI devices CS pins to one */ + bus_space_write_4(fdtbus_bs_tag, + LPC_GPIO_BASE, LPC_GPIO_P3_OUTP_SET, + 1 << (SSD1289_CS_PIN - LPC_GPIO_GPO_00(0)) | + 1 << (SSD1289_DC_PIN - LPC_GPIO_GPO_00(0)) | + 1 << (ADS7846_CS_PIN - LPC_GPIO_GPO_00(0))); +} + +static device_method_t lpc_gpio_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_gpio_probe), + DEVMETHOD(device_attach, lpc_gpio_attach), + DEVMETHOD(device_detach, lpc_gpio_detach), + + /* GPIO interface */ + DEVMETHOD(gpio_pin_max, lpc_gpio_pin_max), + DEVMETHOD(gpio_pin_getcaps, lpc_gpio_pin_getcaps), + DEVMETHOD(gpio_pin_getflags, lpc_gpio_pin_getflags), + DEVMETHOD(gpio_pin_setflags, lpc_gpio_pin_setflags), + DEVMETHOD(gpio_pin_getname, lpc_gpio_pin_getname), + DEVMETHOD(gpio_pin_set, lpc_gpio_pin_set), + DEVMETHOD(gpio_pin_get, lpc_gpio_pin_get), + DEVMETHOD(gpio_pin_toggle, lpc_gpio_pin_toggle), + + { 0, 0 } +}; + +static devclass_t lpc_gpio_devclass; + +static driver_t lpc_gpio_driver = { + "lpcgpio", + lpc_gpio_methods, + sizeof(struct lpc_gpio_softc), +}; + +extern devclass_t gpiobus_devclass, gpioc_devclass; +extern driver_t gpiobus_driver, gpioc_driver; + +DRIVER_MODULE(lpcgpio, simplebus, lpc_gpio_driver, lpc_gpio_devclass, 0, 0); +DRIVER_MODULE(gpiobus, lpcgpio, gpiobus_driver, gpiobus_devclass, 0, 0); +DRIVER_MODULE(gpioc, lpcgpio, gpioc_driver, gpioc_devclass, 0, 0); +MODULE_VERSION(lpcgpio, 1); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_intc.c armv6/sys/arm/lpc/lpc_intc.c --- head/sys/arm/lpc/lpc_intc.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_intc.c 2012-08-08 12:43:50.908724568 -0700 @@ -0,0 +1,243 @@ +/*- + * Copyright (c) 2010 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +struct lpc_intc_softc { + struct resource * li_res; + bus_space_tag_t li_bst; + bus_space_handle_t li_bsh; +}; + +static int lpc_intc_probe(device_t); +static int lpc_intc_attach(device_t); +static void lpc_intc_eoi(void *); + +static struct lpc_intc_softc *intc_softc = NULL; + +#define intc_read_4(reg) \ + bus_space_read_4(intc_softc->li_bst, intc_softc->li_bsh, reg) +#define intc_write_4(reg, val) \ + bus_space_write_4(intc_softc->li_bst, intc_softc->li_bsh, reg, val) + +static int +lpc_intc_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "lpc,pic")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 Interrupt Controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_intc_attach(device_t dev) +{ + struct lpc_intc_softc *sc = device_get_softc(dev); + int rid = 0; + + if (intc_softc) + return (ENXIO); + + sc->li_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->li_res) { + device_printf(dev, "could not alloc resources\n"); + return (ENXIO); + } + + sc->li_bst = rman_get_bustag(sc->li_res); + sc->li_bsh = rman_get_bushandle(sc->li_res); + intc_softc = sc; + arm_post_filter = lpc_intc_eoi; + + /* Clear interrupt status registers and disable all interrupts */ + intc_write_4(LPC_INTC_MIC_ER, 0); + intc_write_4(LPC_INTC_SIC1_ER, 0); + intc_write_4(LPC_INTC_SIC2_ER, 0); + intc_write_4(LPC_INTC_MIC_RSR, ~0); + intc_write_4(LPC_INTC_SIC1_RSR, ~0); + intc_write_4(LPC_INTC_SIC2_RSR, ~0); + return (0); +} + +static device_method_t lpc_intc_methods[] = { + DEVMETHOD(device_probe, lpc_intc_probe), + DEVMETHOD(device_attach, lpc_intc_attach), + { 0, 0 } +}; + +static driver_t lpc_intc_driver = { + "pic", + lpc_intc_methods, + sizeof(struct lpc_intc_softc), +}; + +static devclass_t lpc_intc_devclass; + +DRIVER_MODULE(pic, simplebus, lpc_intc_driver, lpc_intc_devclass, 0, 0); + +int +arm_get_next_irq(int last) +{ + uint32_t value; + int i; + + /* IRQs 0-31 are mapped to LPC_INTC_MIC_SR */ + value = intc_read_4(LPC_INTC_MIC_SR); + for (i = 0; i < 32; i++) { + if (value & (1 << i)) + return (i); + } + + /* IRQs 32-63 are mapped to LPC_INTC_SIC1_SR */ + value = intc_read_4(LPC_INTC_SIC1_SR); + for (i = 0; i < 32; i++) { + if (value & (1 << i)) + return (i + 32); + } + + /* IRQs 64-95 are mapped to LPC_INTC_SIC2_SR */ + value = intc_read_4(LPC_INTC_SIC2_SR); + for (i = 0; i < 32; i++) { + if (value & (1 << i)) + return (i + 64); + } + + return (-1); +} + +void +arm_mask_irq(uintptr_t nb) +{ + int reg; + uint32_t value; + + /* Make sure that interrupt isn't active already */ + lpc_intc_eoi((void *)nb); + + if (nb > 63) { + nb -= 64; + reg = LPC_INTC_SIC2_ER; + } else if (nb > 31) { + nb -= 32; + reg = LPC_INTC_SIC1_ER; + } else + reg = LPC_INTC_MIC_ER; + + /* Clear bit in ER register */ + value = intc_read_4(reg); + value &= ~(1 << nb); + intc_write_4(reg, value); +} + +void +arm_unmask_irq(uintptr_t nb) +{ + int reg; + uint32_t value; + + if (nb > 63) { + nb -= 64; + reg = LPC_INTC_SIC2_ER; + } else if (nb > 31) { + nb -= 32; + reg = LPC_INTC_SIC1_ER; + } else + reg = LPC_INTC_MIC_ER; + + /* Set bit in ER register */ + value = intc_read_4(reg); + value |= (1 << nb); + intc_write_4(reg, value); +} + +static void +lpc_intc_eoi(void *data) +{ + int reg; + int nb = (int)data; + uint32_t value; + + if (nb > 63) { + nb -= 64; + reg = LPC_INTC_SIC2_RSR; + } else if (nb > 31) { + nb -= 32; + reg = LPC_INTC_SIC1_RSR; + } else + reg = LPC_INTC_MIC_RSR; + + /* Set bit in RSR register */ + value = intc_read_4(reg); + value |= (1 << nb); + intc_write_4(reg, value); + +} + +struct fdt_fixup_entry fdt_fixup_table[] = { + { NULL, NULL } +}; + +static int +fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, + int *pol) +{ + if (!fdt_is_compatible(node, "lpc,pic")) + return (ENXIO); + + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + return (0); +} + +fdt_pic_decode_t fdt_pic_table[] = { + &fdt_pic_decode_ic, + NULL +}; diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_machdep.c armv6/sys/arm/lpc/lpc_machdep.c --- head/sys/arm/lpc/lpc_machdep.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_machdep.c 2012-08-12 18:32:17.635813235 -0700 @@ -0,0 +1,641 @@ +/*- + * Copyright (c) 1994-1998 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 + */ + +#include "opt_ddb.h" +#include "opt_platform.h" + +#include +__FBSDID("$FreeBSD$"); + +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEBUG +#undef DEBUG + +#ifdef DEBUG +#define debugf(fmt, args...) printf(fmt, ##args) +#else +#define debugf(fmt, args...) +#endif + +/* + * This is the number of L2 page tables required for covering max + * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf, + * stacks etc.), uprounded to be divisible by 4. + */ +#define KERNEL_PT_MAX 78 + +/* Define various stack sizes in pages */ +#define IRQ_STACK_SIZE 1 +#define ABT_STACK_SIZE 1 +#define UND_STACK_SIZE 1 + +extern unsigned char kernbase[]; +extern unsigned char _etext[]; +extern unsigned char _edata[]; +extern unsigned char __bss_start[]; +extern unsigned char _end[]; + +#ifdef DDB +extern vm_offset_t ksym_start, ksym_end; +#endif + +extern u_int data_abort_handler_address; +extern u_int prefetch_abort_handler_address; +extern u_int undefined_handler_address; + +extern vm_offset_t pmap_bootstrap_lastaddr; +extern int *end; + +struct pv_addr kernel_pt_table[KERNEL_PT_MAX]; + +/* Physical and virtual addresses for some global pages */ + +vm_paddr_t phys_avail[10]; +vm_paddr_t dump_avail[4]; +vm_offset_t physical_pages; +vm_offset_t pmap_bootstrap_lastaddr; + +const struct pmap_devmap *pmap_devmap_bootstrap_table; +struct pv_addr systempage; +struct pv_addr msgbufpv; +struct pv_addr irqstack; +struct pv_addr undstack; +struct pv_addr abtstack; +struct pv_addr kernelstack; + +static struct mem_region availmem_regions[FDT_MEM_REGIONS]; +static int availmem_regions_sz; + +static void print_kenv(void); +static void print_kernel_section_addr(void); + +static void physmap_init(void); +static int platform_devmap_init(void); + +static char * +kenv_next(char *cp) +{ + + if (cp != NULL) { + while (*cp != 0) + cp++; + cp++; + if (*cp == 0) + cp = NULL; + } + return (cp); +} + +static void +print_kenv(void) +{ + int len; + char *cp; + + debugf("loader passed (static) kenv:\n"); + if (kern_envp == NULL) { + debugf(" no env, null ptr\n"); + return; + } + debugf(" kern_envp = 0x%08x\n", (uint32_t)kern_envp); + + len = 0; + for (cp = kern_envp; cp != NULL; cp = kenv_next(cp)) + debugf(" %x %s\n", (uint32_t)cp, cp); +} + +static void +print_kernel_section_addr(void) +{ + + debugf("kernel image addresses:\n"); + debugf(" kernbase = 0x%08x\n", (uint32_t)kernbase); + debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext); + debugf(" _edata = 0x%08x\n", (uint32_t)_edata); + debugf(" __bss_start = 0x%08x\n", (uint32_t)__bss_start); + debugf(" _end = 0x%08x\n", (uint32_t)_end); +} + +static void +physmap_init(void) +{ + int i, j, cnt; + vm_offset_t phys_kernelend, kernload; + uint32_t s, e, sz; + struct mem_region *mp, *mp1; + + phys_kernelend = KERNPHYSADDR + (virtual_avail - KERNVIRTADDR); + kernload = KERNPHYSADDR; + + /* + * Remove kernel physical address range from avail + * regions list. Page align all regions. + * Non-page aligned memory isn't very interesting to us. + * Also, sort the entries for ascending addresses. + */ + sz = 0; + cnt = availmem_regions_sz; + debugf("processing avail regions:\n"); + for (mp = availmem_regions; mp->mr_size; mp++) { + s = mp->mr_start; + e = mp->mr_start + mp->mr_size; + debugf(" %08x-%08x -> ", s, e); + /* Check whether this region holds all of the kernel. */ + if (s < kernload && e > phys_kernelend) { + availmem_regions[cnt].mr_start = phys_kernelend; + availmem_regions[cnt++].mr_size = e - phys_kernelend; + e = kernload; + } + /* Look whether this regions starts within the kernel. */ + if (s >= kernload && s < phys_kernelend) { + if (e <= phys_kernelend) + goto empty; + s = phys_kernelend; + } + /* Now look whether this region ends within the kernel. */ + if (e > kernload && e <= phys_kernelend) { + if (s >= kernload) { + goto empty; + } + e = kernload; + } + /* Now page align the start and size of the region. */ + s = round_page(s); + e = trunc_page(e); + if (e < s) + e = s; + sz = e - s; + debugf("%08x-%08x = %x\n", s, e, sz); + + /* Check whether some memory is left here. */ + if (sz == 0) { + empty: + printf("skipping\n"); + bcopy(mp + 1, mp, + (cnt - (mp - availmem_regions)) * sizeof(*mp)); + cnt--; + mp--; + continue; + } + + /* Do an insertion sort. */ + for (mp1 = availmem_regions; mp1 < mp; mp1++) + if (s < mp1->mr_start) + break; + if (mp1 < mp) { + bcopy(mp1, mp1 + 1, (char *)mp - (char *)mp1); + mp1->mr_start = s; + mp1->mr_size = sz; + } else { + mp->mr_start = s; + mp->mr_size = sz; + } + } + availmem_regions_sz = cnt; + + /* Fill in phys_avail table, based on availmem_regions */ + debugf("fill in phys_avail:\n"); + for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { + + debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", + availmem_regions[i].mr_start, + availmem_regions[i].mr_start + availmem_regions[i].mr_size, + availmem_regions[i].mr_size); + + phys_avail[j] = availmem_regions[i].mr_start; + phys_avail[j + 1] = availmem_regions[i].mr_start + + availmem_regions[i].mr_size; + } + phys_avail[j] = 0; + phys_avail[j + 1] = 0; +} + +void * +initarm(void *mdp, void *unused __unused) +{ + struct pv_addr kernel_l1pt; + struct pv_addr dpcpu; + vm_offset_t dtbp, freemempos, l2_start, lastaddr; + uint32_t memsize, l2size; + void *kmdp; + u_int l1pagetable; + int i = 0, j = 0; + + kmdp = NULL; + lastaddr = 0; + memsize = 0; + dtbp = (vm_offset_t)NULL; + + set_cpufuncs(); + + /* + * Mask metadata pointer: it is supposed to be on page boundary. If + * the first argument (mdp) doesn't point to a valid address the + * bootloader must have passed us something else than the metadata + * ptr... In this case we want to fall back to some built-in settings. + */ + mdp = (void *)((uint32_t)mdp & ~PAGE_MASK); + + /* Parse metadata and fetch parameters */ + if (mdp != NULL) { + preload_metadata = mdp; + kmdp = preload_search_by_type("elf kernel"); + if (kmdp != NULL) { + boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); + kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *); + dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); + lastaddr = MD_FETCH(kmdp, MODINFOMD_KERNEND, + vm_offset_t); +#ifdef DDB + ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); + ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); +#endif + } + + } else { + /* Fall back to hardcoded metadata. */ + lastaddr = fake_preload_metadata(); + } + +#if defined(FDT_DTB_STATIC) + /* + * In case the device tree blob was not retrieved (from metadata) try + * to use the statically embedded one. + */ + if (dtbp == (vm_offset_t)NULL) + dtbp = (vm_offset_t)&fdt_static_dtb; + +#endif + + if (OF_install(OFW_FDT, 0) == FALSE) + while (1); + + if (OF_init((void *)dtbp) != 0) + while (1); + + /* Grab physical memory regions information from device tree. */ + if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz, + &memsize) != 0) + while(1); + + if (fdt_immr_addr(LPC_DEV_BASE) != 0) + while (1); + + /* Platform-specific initialisation */ + pmap_bootstrap_lastaddr = fdt_immr_va - ARM_NOCACHE_KVA_SIZE; + + pcpu_init(pcpup, 0, sizeof(struct pcpu)); + PCPU_SET(curthread, &thread0); + + /* Calculate number of L2 tables needed for mapping vm_page_array */ + l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page); + l2size = (l2size >> L1_S_SHIFT) + 1; + + /* + * Add one table for end of kernel map, one for stacks, msgbuf and + * L1 and L2 tables map and one for vectors map. + */ + l2size += 3; + + /* Make it divisible by 4 */ + l2size = (l2size + 3) & ~3; + +#define KERNEL_TEXT_BASE (KERNBASE) + freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; + + /* Define a macro to simplify memory allocation */ +#define valloc_pages(var, np) \ + alloc_pages((var).pv_va, (np)); \ + (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR); + +#define alloc_pages(var, np) \ + (var) = freemempos; \ + freemempos += (np * PAGE_SIZE); \ + memset((char *)(var), 0, ((np) * PAGE_SIZE)); + + while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) + freemempos += PAGE_SIZE; + valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); + + for (i = 0; i < l2size; ++i) { + if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { + valloc_pages(kernel_pt_table[i], + L2_TABLE_SIZE / PAGE_SIZE); + j = i; + } else { + kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va + + L2_TABLE_SIZE_REAL * (i - j); + kernel_pt_table[i].pv_pa = + kernel_pt_table[i].pv_va - KERNVIRTADDR + + KERNPHYSADDR; + + } + } + /* + * Allocate a page for the system page mapped to 0x00000000 + * or 0xffff0000. This page will just contain the system vectors + * and can be shared by all processes. + */ + valloc_pages(systempage, 1); + + /* Allocate dynamic per-cpu area. */ + valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); + dpcpu_init((void *)dpcpu.pv_va, 0); + + /* Allocate stacks for all modes */ + valloc_pages(irqstack, IRQ_STACK_SIZE); + valloc_pages(abtstack, ABT_STACK_SIZE); + valloc_pages(undstack, UND_STACK_SIZE); + valloc_pages(kernelstack, KSTACK_PAGES); + + init_param1(); + + valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); + + /* + * Now we start construction of the L1 page table + * We start by mapping the L2 page tables into the L1. + * This means that we can replace L1 mappings later on if necessary + */ + l1pagetable = kernel_l1pt.pv_va; + + /* + * Try to map as much as possible of kernel text and data using + * 1MB section mapping and for the rest of initial kernel address + * space use L2 coarse tables. + * + * Link L2 tables for mapping remainder of kernel (modulo 1MB) + * and kernel structures + */ + l2_start = lastaddr & ~(L1_S_OFFSET); + for (i = 0 ; i < l2size - 1; i++) + pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE, + &kernel_pt_table[i]); + + pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE; + + /* Map kernel code and data */ + pmap_map_chunk(l1pagetable, KERNVIRTADDR, KERNPHYSADDR, + (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + + /* Map L1 directory and allocated L2 page tables */ + pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, + L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); + + pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va, + kernel_pt_table[0].pv_pa, + L2_TABLE_SIZE_REAL * l2size, + VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); + + /* Map allocated DPCPU, stacks and msgbuf */ + pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, + freemempos - dpcpu.pv_va, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + /* Link and map the vector page */ + pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, + &kernel_pt_table[l2size - 1]); + pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, + VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); + + /* Map pmap_devmap[] entries */ + if (platform_devmap_init() != 0) + while (1); + pmap_devmap_bootstrap(l1pagetable, pmap_devmap_bootstrap_table); + + cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | + DOMAIN_CLIENT); + setttb(kernel_l1pt.pv_pa); + cpu_tlb_flushID(); + cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); + + /* + * Only after the SOC registers block is mapped we can perform device + * tree fixups, as they may attempt to read parameters from hardware. + */ + OF_interpret("perform-fixup", 0); + +#if 0 + /* + * Initialize GPIO as early as possible. + */ + if (platform_gpio_init() != 0) + while (1); +#endif + + cninit(); + + physmem = memsize / PAGE_SIZE; + + debugf("initarm: console initialized\n"); + debugf(" arg1 mdp = 0x%08x\n", (uint32_t)mdp); + debugf(" boothowto = 0x%08x\n", boothowto); + printf(" dtbp = 0x%08x\n", (uint32_t)dtbp); + print_kernel_section_addr(); + print_kenv(); + + /* + * Pages were allocated during the secondary bootstrap for the + * stacks for different CPU modes. + * We must now set the r13 registers in the different CPU modes to + * point to these stacks. + * Since the ARM stacks use STMFD etc. we must set r13 to the top end + * of the stack memory. + */ + cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); + set_stackptr(PSR_IRQ32_MODE, + irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); + set_stackptr(PSR_ABT32_MODE, + abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); + set_stackptr(PSR_UND32_MODE, + undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); + + /* + * We must now clean the cache again.... + * Cleaning may be done by reading new data to displace any + * dirty data in the cache. This will have happened in setttb() + * but since we are boot strapping the addresses used for the read + * may have just been remapped and thus the cache could be out + * of sync. A re-clean after the switch will cure this. + * After booting there are no gross relocations of the kernel thus + * this problem will not occur after initarm(). + */ + cpu_idcache_wbinv_all(); + + /* Set stack for exception handlers */ + data_abort_handler_address = (u_int)data_abort_handler; + prefetch_abort_handler_address = (u_int)prefetch_abort_handler; + undefined_handler_address = (u_int)undefinedinstruction_bounce; + undefined_init(); + + init_proc0(kernelstack.pv_va); + + arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); + + dump_avail[0] = 0; + dump_avail[1] = memsize; + dump_avail[2] = 0; + dump_avail[3] = 0; + + pmap_bootstrap(freemempos, pmap_bootstrap_lastaddr, &kernel_l1pt); + msgbufp = (void *)msgbufpv.pv_va; + msgbufinit(msgbufp, msgbufsize); + mutex_init(); + + /* + * Prepare map of physical memory regions available to vm subsystem. + */ + physmap_init(); + + /* + * Set initial values of GPIO output ports + */ + platform_gpio_init(); + + /* Do basic tuning, hz etc */ + init_param2(physmem); + kdb_init(); + return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - + sizeof(struct pcb))); +} + +#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1) +static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { + { 0, 0, 0, 0, 0, } +}; + +/* + * Construct pmap_devmap[] with DT-derived config data. + */ +static int +platform_devmap_init(void) +{ + + /* + * IMMR range. + */ + fdt_devmap[0].pd_va = fdt_immr_va; + fdt_devmap[0].pd_pa = fdt_immr_pa; + fdt_devmap[0].pd_size = fdt_immr_size; + fdt_devmap[0].pd_prot = VM_PROT_READ | VM_PROT_WRITE; + fdt_devmap[0].pd_cache = PTE_NOCACHE; + + pmap_devmap_bootstrap_table = &fdt_devmap[0]; + return (0); +} + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + + return (0); +} + +void +cpu_reset(void) +{ + /* Enable WDT */ + bus_space_write_4(fdtbus_bs_tag, + LPC_CLKPWR_BASE, LPC_CLKPWR_TIMCLK_CTRL, + LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG); + + /* Instant assert of RESETOUT_N with pulse length 1ms */ + bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_PULSE, 13000); + bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_MCTRL, 0x70); + + for (;;); +} diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_mmc.c armv6/sys/arm/lpc/lpc_mmc.c --- head/sys/arm/lpc/lpc_mmc.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_mmc.c 2012-08-08 12:43:50.901723932 -0700 @@ -0,0 +1,777 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#define DEBUG +#undef DEBUG + +#ifdef DEBUG +#define debugf(fmt, args...) do { printf("%s(): ", __func__); \ + printf(fmt,##args); } while (0) +#else +#define debugf(fmt, args...) +#endif + +struct lpc_mmc_dmamap_arg { + bus_addr_t lm_dma_busaddr; +}; + +struct lpc_mmc_softc { + device_t lm_dev; + struct mtx lm_mtx; + struct resource * lm_mem_res; + struct resource * lm_irq_res; + bus_space_tag_t lm_bst; + bus_space_handle_t lm_bsh; + void * lm_intrhand; + struct mmc_host lm_host; + struct mmc_request * lm_req; + struct mmc_data * lm_data; + uint32_t lm_flags; +#define LPC_SD_FLAGS_IGNORECRC (1 << 0) + int lm_xfer_direction; +#define DIRECTION_READ 0 +#define DIRECTION_WRITE 1 + int lm_xfer_done; + int lm_bus_busy; + bus_dma_tag_t lm_dma_tag; + bus_dmamap_t lm_dma_map; + bus_addr_t lm_buffer_phys; + void * lm_buffer; +}; + +#define LPC_SD_MAX_BLOCKSIZE 1024 +/* XXX */ +#define LPC_MMC_DMACH_READ 1 +#define LPC_MMC_DMACH_WRITE 0 + + +static int lpc_mmc_probe(device_t); +static int lpc_mmc_attach(device_t); +static int lpc_mmc_detach(device_t); +static void lpc_mmc_intr(void *); + +static void lpc_mmc_cmd(struct lpc_mmc_softc *, struct mmc_command *); +static void lpc_mmc_setup_xfer(struct lpc_mmc_softc *, struct mmc_data *); + +static int lpc_mmc_update_ios(device_t, device_t); +static int lpc_mmc_request(device_t, device_t, struct mmc_request *); +static int lpc_mmc_get_ro(device_t, device_t); +static int lpc_mmc_acquire_host(device_t, device_t); +static int lpc_mmc_release_host(device_t, device_t); + +static void lpc_mmc_dma_rxfinish(void *); +static void lpc_mmc_dma_rxerror(void *); +static void lpc_mmc_dma_txfinish(void *); +static void lpc_mmc_dma_txerror(void *); + +static void lpc_mmc_dmamap_cb(void *, bus_dma_segment_t *, int, int); + +#define lpc_mmc_lock(_sc) \ + mtx_lock(&_sc->lm_mtx); +#define lpc_mmc_unlock(_sc) \ + mtx_unlock(&_sc->lm_mtx); +#define lpc_mmc_read_4(_sc, _reg) \ + bus_space_read_4(_sc->lm_bst, _sc->lm_bsh, _reg) +#define lpc_mmc_write_4(_sc, _reg, _value) \ + bus_space_write_4(_sc->lm_bst, _sc->lm_bsh, _reg, _value) + +static struct lpc_dmac_channel_config lpc_mmc_dma_rxconf = { + .ldc_fcntl = LPC_DMAC_FLOW_D_P2M, + .ldc_src_periph = LPC_DMAC_SD_ID, + .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4, + .ldc_src_incr = 0, + .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8, + .ldc_dst_periph = LPC_DMAC_SD_ID, + .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4, + .ldc_dst_incr = 1, + .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8, + .ldc_success_handler = lpc_mmc_dma_rxfinish, + .ldc_error_handler = lpc_mmc_dma_rxerror, +}; + +static struct lpc_dmac_channel_config lpc_mmc_dma_txconf = { + .ldc_fcntl = LPC_DMAC_FLOW_P_M2P, + .ldc_src_periph = LPC_DMAC_SD_ID, + .ldc_src_width = LPC_DMAC_CH_CONTROL_WIDTH_4, + .ldc_src_incr = 1, + .ldc_src_burst = LPC_DMAC_CH_CONTROL_BURST_8, + .ldc_dst_periph = LPC_DMAC_SD_ID, + .ldc_dst_width = LPC_DMAC_CH_CONTROL_WIDTH_4, + .ldc_dst_incr = 0, + .ldc_dst_burst = LPC_DMAC_CH_CONTROL_BURST_8, + .ldc_success_handler = lpc_mmc_dma_txfinish, + .ldc_error_handler = lpc_mmc_dma_txerror, +}; + +static int +lpc_mmc_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "lpc,mmc")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 MMC/SD controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_mmc_attach(device_t dev) +{ + struct lpc_mmc_softc *sc = device_get_softc(dev); + struct lpc_mmc_dmamap_arg ctx; + device_t child; + int rid, err; + + sc->lm_dev = dev; + sc->lm_req = NULL; + + mtx_init(&sc->lm_mtx, "lpcmmc", "mmc", MTX_DEF); + + rid = 0; + sc->lm_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->lm_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->lm_bst = rman_get_bustag(sc->lm_mem_res); + sc->lm_bsh = rman_get_bushandle(sc->lm_mem_res); + + debugf("virtual register space: 0x%08lx\n", sc->lm_bsh); + + rid = 0; + sc->lm_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (!sc->lm_irq_res) { + device_printf(dev, "cannot allocate interrupt\n"); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res); + return (ENXIO); + } + + if (bus_setup_intr(dev, sc->lm_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, lpc_mmc_intr, sc, &sc->lm_intrhand)) + { + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res); + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + sc->lm_host.f_min = 312500; + sc->lm_host.f_max = 2500000; + sc->lm_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 | + MMC_OCR_320_330 | MMC_OCR_330_340; +#if 0 + sc->lm_host.caps = MMC_CAP_4_BIT_DATA; +#endif + + lpc_pwr_write(dev, LPC_CLKPWR_MS_CTRL, + LPC_CLKPWR_MS_CTRL_CLOCK_EN | LPC_CLKPWR_MS_CTRL_SD_CLOCK | 1); + lpc_mmc_write_4(sc, LPC_SD_POWER, LPC_SD_POWER_CTRL_ON); + + device_set_ivars(dev, &sc->lm_host); + + child = device_add_child(dev, "mmc", -1); + if (!child) { + device_printf(dev, "attaching MMC bus failed!\n"); + bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res); + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res); + return (ENXIO); + } + + /* Alloc DMA memory */ + err = bus_dma_tag_create( + bus_get_dma_tag(sc->lm_dev), + 4, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + LPC_SD_MAX_BLOCKSIZE, 1, /* maxsize, nsegments */ + LPC_SD_MAX_BLOCKSIZE, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->lm_dma_tag); + + err = bus_dmamem_alloc(sc->lm_dma_tag, (void **)&sc->lm_buffer, + 0, &sc->lm_dma_map); + if (err) { + device_printf(dev, "cannot allocate framebuffer\n"); + goto fail; + } + + err = bus_dmamap_load(sc->lm_dma_tag, sc->lm_dma_map, sc->lm_buffer, + LPC_SD_MAX_BLOCKSIZE, lpc_mmc_dmamap_cb, &ctx, BUS_DMA_NOWAIT); + if (err) { + device_printf(dev, "cannot load DMA map\n"); + goto fail; + } + + sc->lm_buffer_phys = ctx.lm_dma_busaddr; + + lpc_mmc_dma_rxconf.ldc_handler_arg = (void *)sc; + err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_READ, &lpc_mmc_dma_rxconf); + if (err) { + device_printf(dev, "cannot allocate RX DMA channel\n"); + goto fail; + } + + + lpc_mmc_dma_txconf.ldc_handler_arg = (void *)sc; + err = lpc_dmac_config_channel(dev, LPC_MMC_DMACH_WRITE, &lpc_mmc_dma_txconf); + if (err) { + device_printf(dev, "cannot allocate TX DMA channel\n"); + goto fail; + } + + bus_generic_probe(dev); + bus_generic_attach(dev); + + return (0); + +fail: + if (sc->lm_intrhand) + bus_teardown_intr(dev, sc->lm_irq_res, sc->lm_intrhand); + if (sc->lm_irq_res) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lm_irq_res); + if (sc->lm_mem_res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lm_mem_res); + return (err); +} + +static int +lpc_mmc_detach(device_t dev) +{ + return (EBUSY); +} + +static void +lpc_mmc_intr(void *arg) +{ + struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg; + struct mmc_command *cmd; + uint32_t status; + + status = lpc_mmc_read_4(sc, LPC_SD_STATUS); + + debugf("interrupt: 0x%08x\n", status); + + if (status & LPC_SD_STATUS_CMDCRCFAIL) { + cmd = sc->lm_req->cmd; + cmd->error = sc->lm_flags & LPC_SD_FLAGS_IGNORECRC + ? MMC_ERR_NONE : MMC_ERR_BADCRC; + cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0); + sc->lm_req->done(sc->lm_req); + sc->lm_req = NULL; + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDCRCFAIL); + } + + if (status & LPC_SD_STATUS_CMDACTIVE) + { + debugf("command active\n"); + cmd = sc->lm_req->cmd; + cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0); + sc->lm_req->done(sc->lm_req); + sc->lm_req = NULL; + } + + if (status & LPC_SD_STATUS_DATATIMEOUT) { + device_printf(sc->lm_dev, "data timeout\n"); + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATATIMEOUT); + } + + if (status & LPC_SD_STATUS_TXUNDERRUN) { + device_printf(sc->lm_dev, "TX underrun\n"); + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_TXUNDERRUN); + } + + if (status & LPC_SD_STATUS_CMDRESPEND) { + debugf("command response\n"); + cmd = sc->lm_req->cmd; + + if (cmd->flags & MMC_RSP_136) { + cmd->resp[3] = lpc_mmc_read_4(sc, LPC_SD_RESP3); + cmd->resp[2] = lpc_mmc_read_4(sc, LPC_SD_RESP2); + cmd->resp[1] = lpc_mmc_read_4(sc, LPC_SD_RESP1); + } + + cmd->resp[0] = lpc_mmc_read_4(sc, LPC_SD_RESP0); + cmd->error = MMC_ERR_NONE; + + if (cmd->data && (cmd->data->flags & MMC_DATA_WRITE)) + lpc_mmc_setup_xfer(sc, sc->lm_req->cmd->data); + + if (!cmd->data) { + sc->lm_req->done(sc->lm_req); + sc->lm_req = NULL; + } + + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDRESPEND); + } + + if (status & LPC_SD_STATUS_CMDSENT) { + debugf("command sent\n"); + cmd = sc->lm_req->cmd; + cmd->error = MMC_ERR_NONE; + sc->lm_req->done(sc->lm_req); + sc->lm_req = NULL; + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDSENT); + } + + if (status & LPC_SD_STATUS_DATAEND) { + if (sc->lm_xfer_direction == DIRECTION_READ) + lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID); + + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATAEND); + } + + if (status & LPC_SD_STATUS_CMDTIMEOUT) { + device_printf(sc->lm_dev, "command response timeout\n"); + cmd = sc->lm_req->cmd; + cmd->error = MMC_ERR_TIMEOUT; + sc->lm_req->done(sc->lm_req); + sc->lm_req = NULL; + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_CMDTIMEOUT); + return; + } + + if (status & LPC_SD_STATUS_STARTBITERR) { + device_printf(sc->lm_dev, "start bit error\n"); + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_STARTBITERR); + } + + if (status & LPC_SD_STATUS_DATACRCFAIL) { + device_printf(sc->lm_dev, "data CRC error\n"); + debugf("data buffer: %p\n", sc->lm_buffer); + cmd = sc->lm_req->cmd; + cmd->error = MMC_ERR_BADCRC; + sc->lm_req->done(sc->lm_req); + sc->lm_req = NULL; + + if (sc->lm_xfer_direction == DIRECTION_READ) + lpc_dmac_start_burst(sc->lm_dev, LPC_DMAC_SD_ID); + + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATACRCFAIL); + } + + if (status & LPC_SD_STATUS_DATABLOCKEND) { + debugf("data block end\n"); + if (sc->lm_xfer_direction == DIRECTION_READ) + memcpy(sc->lm_data->data, sc->lm_buffer, sc->lm_data->len); + + if (sc->lm_xfer_direction == DIRECTION_WRITE) { + lpc_dmac_disable_channel(sc->lm_dev, LPC_MMC_DMACH_WRITE); + lpc_mmc_write_4(sc, LPC_SD_DATACTRL, 0); + } + + sc->lm_req->done(sc->lm_req); + sc->lm_req = NULL; + lpc_mmc_write_4(sc, LPC_SD_CLEAR, LPC_SD_STATUS_DATABLOCKEND); + } + + debugf("done\n"); +} + +static int +lpc_mmc_request(device_t bus, device_t child, struct mmc_request *req) +{ + struct lpc_mmc_softc *sc = device_get_softc(bus); + + debugf("request: %p\n", req); + + lpc_mmc_lock(sc); + if (sc->lm_req) + return (EBUSY); + + sc->lm_req = req; + + if (req->cmd->data && req->cmd->data->flags & MMC_DATA_WRITE) { + memcpy(sc->lm_buffer, req->cmd->data->data, req->cmd->data->len); + lpc_mmc_cmd(sc, req->cmd); + lpc_mmc_unlock(sc); + return (0); + } + + if (req->cmd->data) + lpc_mmc_setup_xfer(sc, req->cmd->data); + + lpc_mmc_cmd(sc, req->cmd); + lpc_mmc_unlock(sc); + + return (0); +} + +static void +lpc_mmc_cmd(struct lpc_mmc_softc *sc, struct mmc_command *cmd) +{ + uint32_t cmdreg = 0; + + debugf("cmd: %d arg: 0x%08x\n", cmd->opcode, cmd->arg); + + if (lpc_mmc_read_4(sc, LPC_SD_COMMAND) & LPC_SD_COMMAND_ENABLE) { + lpc_mmc_write_4(sc, LPC_SD_COMMAND, 0); + DELAY(1000); + } + + sc->lm_flags &= ~LPC_SD_FLAGS_IGNORECRC; + + if (cmd->flags & MMC_RSP_PRESENT) + cmdreg |= LPC_SD_COMMAND_RESPONSE; + + if (MMC_RSP(cmd->flags) == MMC_RSP_R2) + cmdreg |= LPC_SD_COMMAND_LONGRSP; + + if (MMC_RSP(cmd->flags) == MMC_RSP_R3) + sc->lm_flags |= LPC_SD_FLAGS_IGNORECRC; + + cmdreg |= LPC_SD_COMMAND_ENABLE; + cmdreg |= (cmd->opcode & LPC_SD_COMMAND_CMDINDEXMASK); + + lpc_mmc_write_4(sc, LPC_SD_MASK0, 0xffffffff); + lpc_mmc_write_4(sc, LPC_SD_MASK1, 0xffffffff); + lpc_mmc_write_4(sc, LPC_SD_ARGUMENT, cmd->arg); + lpc_mmc_write_4(sc, LPC_SD_COMMAND, cmdreg); +} + +static void +lpc_mmc_setup_xfer(struct lpc_mmc_softc *sc, struct mmc_data *data) +{ + uint32_t datactrl = 0; + int data_words = data->len / 4; + + sc->lm_data = data; + sc->lm_xfer_done = 0; + + debugf("data: %p, len: %d, %s\n", data, + data->len, (data->flags & MMC_DATA_READ) ? "read" : "write"); + + if (data->flags & MMC_DATA_READ) { + sc->lm_xfer_direction = DIRECTION_READ; + lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_READ, + LPC_SD_BASE + LPC_SD_FIFO, sc->lm_buffer_phys, + data_words, 0); + } + + if (data->flags & MMC_DATA_WRITE) { + sc->lm_xfer_direction = DIRECTION_WRITE; + lpc_dmac_setup_transfer(sc->lm_dev, LPC_MMC_DMACH_WRITE, + sc->lm_buffer_phys, LPC_SD_BASE + LPC_SD_FIFO, + data_words, 0); + } + + datactrl |= (sc->lm_xfer_direction + ? LPC_SD_DATACTRL_WRITE + : LPC_SD_DATACTRL_READ); + + datactrl |= LPC_SD_DATACTRL_DMAENABLE | LPC_SD_DATACTRL_ENABLE; + datactrl |= (ffs(data->len) - 1) << 4; + + debugf("datactrl: 0x%08x\n", datactrl); + + lpc_mmc_write_4(sc, LPC_SD_DATATIMER, 0xFFFF0000); + lpc_mmc_write_4(sc, LPC_SD_DATALENGTH, data->len); + lpc_mmc_write_4(sc, LPC_SD_DATACTRL, datactrl); +} + +static int +lpc_mmc_read_ivar(device_t bus, device_t child, int which, + uintptr_t *result) +{ + struct lpc_mmc_softc *sc = device_get_softc(bus); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + *(int *)result = sc->lm_host.ios.bus_mode; + break; + case MMCBR_IVAR_BUS_WIDTH: + *(int *)result = sc->lm_host.ios.bus_width; + break; + case MMCBR_IVAR_CHIP_SELECT: + *(int *)result = sc->lm_host.ios.chip_select; + break; + case MMCBR_IVAR_CLOCK: + *(int *)result = sc->lm_host.ios.clock; + break; + case MMCBR_IVAR_F_MIN: + *(int *)result = sc->lm_host.f_min; + break; + case MMCBR_IVAR_F_MAX: + *(int *)result = sc->lm_host.f_max; + break; + case MMCBR_IVAR_HOST_OCR: + *(int *)result = sc->lm_host.host_ocr; + break; + case MMCBR_IVAR_MODE: + *(int *)result = sc->lm_host.mode; + break; + case MMCBR_IVAR_OCR: + *(int *)result = sc->lm_host.ocr; + break; + case MMCBR_IVAR_POWER_MODE: + *(int *)result = sc->lm_host.ios.power_mode; + break; + case MMCBR_IVAR_VDD: + *(int *)result = sc->lm_host.ios.vdd; + break; + case MMCBR_IVAR_CAPS: + *(int *)result = sc->lm_host.caps; + break; + case MMCBR_IVAR_MAX_DATA: + *(int *)result = 1; + break; + } + + return (0); +} + +static int +lpc_mmc_write_ivar(device_t bus, device_t child, int which, + uintptr_t value) +{ + struct lpc_mmc_softc *sc = device_get_softc(bus); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + sc->lm_host.ios.bus_mode = value; + break; + case MMCBR_IVAR_BUS_WIDTH: + sc->lm_host.ios.bus_width = value; + break; + case MMCBR_IVAR_CHIP_SELECT: + sc->lm_host.ios.chip_select = value; + break; + case MMCBR_IVAR_CLOCK: + sc->lm_host.ios.clock = value; + break; + case MMCBR_IVAR_MODE: + sc->lm_host.mode = value; + break; + case MMCBR_IVAR_OCR: + sc->lm_host.ocr = value; + break; + case MMCBR_IVAR_POWER_MODE: + sc->lm_host.ios.power_mode = value; + break; + case MMCBR_IVAR_VDD: + sc->lm_host.ios.vdd = value; + break; + /* These are read-only */ + case MMCBR_IVAR_CAPS: + case MMCBR_IVAR_HOST_OCR: + case MMCBR_IVAR_F_MIN: + case MMCBR_IVAR_F_MAX: + case MMCBR_IVAR_MAX_DATA: + return (EINVAL); + } + return (0); +} + +static int +lpc_mmc_update_ios(device_t bus, device_t child) +{ + struct lpc_mmc_softc *sc = device_get_softc(bus); + struct mmc_ios *ios = &sc->lm_host.ios; + uint32_t clkdiv = 0, pwr = 0; + + if (ios->bus_width == bus_width_4) + clkdiv |= LPC_SD_CLOCK_WIDEBUS; + + /* Calculate clock divider */ + clkdiv = (LPC_SD_CLK / (2 * ios->clock)) - 1; + + /* Clock rate should not exceed rate requested in ios */ + if ((LPC_SD_CLK / (2 * (clkdiv + 1))) > ios->clock) + clkdiv++; + + debugf("clock: %dHz, clkdiv: %d\n", ios->clock, clkdiv); + + if (ios->bus_width == bus_width_4) { + debugf("using wide bus mode\n"); + clkdiv |= LPC_SD_CLOCK_WIDEBUS; + } + + lpc_mmc_write_4(sc, LPC_SD_CLOCK, clkdiv | LPC_SD_CLOCK_ENABLE); + + switch (ios->power_mode) { + case power_off: + pwr |= LPC_SD_POWER_CTRL_OFF; + break; + case power_up: + pwr |= LPC_SD_POWER_CTRL_UP; + break; + case power_on: + pwr |= LPC_SD_POWER_CTRL_ON; + break; + } + + if (ios->bus_mode == opendrain) + pwr |= LPC_SD_POWER_OPENDRAIN; + + lpc_mmc_write_4(sc, LPC_SD_POWER, pwr); + + return (0); +} + +static int +lpc_mmc_get_ro(device_t bus, device_t child) +{ + + return (0); +} + +static int +lpc_mmc_acquire_host(device_t bus, device_t child) +{ + struct lpc_mmc_softc *sc = device_get_softc(bus); + int error = 0; + + lpc_mmc_lock(sc); + while (sc->lm_bus_busy) + error = mtx_sleep(sc, &sc->lm_mtx, PZERO, "mmcah", 0); + + sc->lm_bus_busy++; + lpc_mmc_unlock(sc); + return (error); +} + +static int +lpc_mmc_release_host(device_t bus, device_t child) +{ + struct lpc_mmc_softc *sc = device_get_softc(bus); + + lpc_mmc_lock(sc); + sc->lm_bus_busy--; + wakeup(sc); + lpc_mmc_unlock(sc); + return (0); +} + +static void lpc_mmc_dma_rxfinish(void *arg) +{ +} + +static void lpc_mmc_dma_rxerror(void *arg) +{ + struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg; + device_printf(sc->lm_dev, "DMA RX error\n"); +} + +static void lpc_mmc_dma_txfinish(void *arg) +{ +} + +static void lpc_mmc_dma_txerror(void *arg) +{ + struct lpc_mmc_softc *sc = (struct lpc_mmc_softc *)arg; + device_printf(sc->lm_dev, "DMA TX error\n"); +} + +static void +lpc_mmc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) +{ + struct lpc_mmc_dmamap_arg *ctx; + + if (err) + return; + + ctx = (struct lpc_mmc_dmamap_arg *)arg; + ctx->lm_dma_busaddr = segs[0].ds_addr; +} + +static device_method_t lpc_mmc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_mmc_probe), + DEVMETHOD(device_attach, lpc_mmc_attach), + DEVMETHOD(device_detach, lpc_mmc_detach), + + /* Bus interface */ + DEVMETHOD(bus_read_ivar, lpc_mmc_read_ivar), + DEVMETHOD(bus_write_ivar, lpc_mmc_write_ivar), + DEVMETHOD(bus_print_child, bus_generic_print_child), + + /* MMC bridge interface */ + DEVMETHOD(mmcbr_update_ios, lpc_mmc_update_ios), + DEVMETHOD(mmcbr_request, lpc_mmc_request), + DEVMETHOD(mmcbr_get_ro, lpc_mmc_get_ro), + DEVMETHOD(mmcbr_acquire_host, lpc_mmc_acquire_host), + DEVMETHOD(mmcbr_release_host, lpc_mmc_release_host), + + { 0, 0 } +}; + +static devclass_t lpc_mmc_devclass; + +static driver_t lpc_mmc_driver = { + "lpcmmc", + lpc_mmc_methods, + sizeof(struct lpc_mmc_softc), +}; + +DRIVER_MODULE(lpcmmc, simplebus, lpc_mmc_driver, lpc_mmc_devclass, 0, 0); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_ohci.c armv6/sys/arm/lpc/lpc_ohci.c --- head/sys/arm/lpc/lpc_ohci.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_ohci.c 2012-08-08 12:43:50.903723953 -0700 @@ -0,0 +1,354 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#define I2C_START_BIT (1 << 8) +#define I2C_STOP_BIT (1 << 9) +#define I2C_READ 0x01 +#define I2C_WRITE 0x00 +#define DUMMY_BYTE 0x55 + +#define lpc_otg_read_4(_sc, _reg) \ + bus_space_read_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg) +#define lpc_otg_write_4(_sc, _reg, _value) \ + bus_space_write_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg, _value) +#define lpc_otg_wait_write_4(_sc, _wreg, _sreg, _value) \ + do { \ + lpc_otg_write_4(_sc, _wreg, _value); \ + while ((lpc_otg_read_4(_sc, _sreg) & _value) != _value); \ + } while (0); + +static int lpc_ohci_probe(device_t dev); +static int lpc_ohci_attach(device_t dev); +static int lpc_ohci_detach(device_t dev); + +static void lpc_otg_i2c_reset(struct ohci_softc *); + +static int lpc_isp3101_read(struct ohci_softc *, int); +static void lpc_isp3101_write(struct ohci_softc *, int, int); +static void lpc_isp3101_clear(struct ohci_softc *, int, int); +static void lpc_isp3101_configure(device_t dev, struct ohci_softc *); + +static int +lpc_ohci_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "lpc,usb-ohci")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 USB OHCI controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_ohci_attach(device_t dev) +{ + struct ohci_softc *sc = device_get_softc(dev); + int err; + int rid; + int i = 0; + uint32_t usbctrl; + uint32_t otgstatus; + + sc->sc_bus.parent = dev; + sc->sc_bus.devices = sc->sc_devices; + sc->sc_bus.devices_max = OHCI_MAX_DEVICES; + + if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), + &ohci_iterate_hw_softc)) + return (ENOMEM); + + rid = 0; + sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (!sc->sc_io_res) { + device_printf(dev, "cannot map OHCI register space\n"); + goto fail; + } + + sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); + sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); + sc->sc_io_size = rman_get_size(sc->sc_io_res); + + rid = 0; + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); + if (sc->sc_irq_res == NULL) { + device_printf(dev, "cannot allocate interrupt\n"); + goto fail; + } + + sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); + if (!(sc->sc_bus.bdev)) + goto fail; + + device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); + strlcpy(sc->sc_vendor, "NXP", sizeof(sc->sc_vendor)); + + err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, + NULL, (void *)ohci_interrupt, sc, &sc->sc_intr_hdl); + if (err) { + sc->sc_intr_hdl = NULL; + goto fail; + } + + usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL); + usbctrl |= LPC_CLKPWR_USB_CTRL_SLAVE_HCLK | LPC_CLKPWR_USB_CTRL_BUSKEEPER; + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + + /* Enable OTG I2C clock */ + lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL, + LPC_OTG_CLOCK_STATUS, LPC_OTG_CLOCK_CTRL_I2C_EN); + + /* Reset OTG I2C bus */ + lpc_otg_i2c_reset(sc); + + lpc_isp3101_configure(dev, sc); + + /* Configure PLL */ + usbctrl &= ~(LPC_CLKPWR_USB_CTRL_CLK_EN1 | LPC_CLKPWR_USB_CTRL_CLK_EN2); + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + + usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN1; + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + + usbctrl |= LPC_CLKPWR_USB_CTRL_FDBKDIV(192-1); + usbctrl |= LPC_CLKPWR_USB_CTRL_POSTDIV(1); + usbctrl |= LPC_CLKPWR_USB_CTRL_PLL_PDOWN; + + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + do { + usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL); + if (i++ > 100000) { + device_printf(dev, "USB OTG PLL doesn't lock!\n"); + goto fail; + } + } while ((usbctrl & LPC_CLKPWR_USB_CTRL_PLL_LOCK) == 0); + + usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN2; + usbctrl |= LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN; + lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl); + lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL, LPC_OTG_CLOCK_STATUS, + (LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_OTG_EN | + LPC_OTG_CLOCK_CTRL_I2C_EN | LPC_OTG_CLOCK_CTRL_HOST_EN)); + + otgstatus = lpc_otg_read_4(sc, LPC_OTG_STATUS); + lpc_otg_write_4(sc, LPC_OTG_STATUS, otgstatus | + LPC_OTG_STATUS_HOST_EN); + + lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1, + LPC_ISP3101_OTG1_VBUS_DRV); + + err = ohci_init(sc); + if (err) + goto fail; + + err = device_probe_and_attach(sc->sc_bus.bdev); + if (err) + goto fail; + + return (0); + +fail: + if (sc->sc_intr_hdl) + bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); + if (sc->sc_irq_res) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + if (sc->sc_io_res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res); + + return (ENXIO); +} + +static int +lpc_isp3101_read(struct ohci_softc *sc, int reg) +{ + int status; + int i = 0; + + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, + (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT); + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, reg); + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, (LPC_ISP3101_I2C_ADDR << 1) | + I2C_START_BIT | I2C_READ); + lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, I2C_STOP_BIT | DUMMY_BYTE); + + do { + status = lpc_otg_read_4(sc, LPC_OTG_I2C_STATUS); + i++; + } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000); + + lpc_otg_write_4(sc, LPC_OTG_I2C_STATUS, LPC_OTG_I2C_STATUS_TDI); + + return (lpc_otg_read_4(sc, LPC_OTG_I2C_TXRX) & 0xff); +} + +static void +lpc_otg_i2c_reset(struct ohci_softc *sc) +{ + int ctrl; + int i = 0; + + lpc_otg_write_4(sc, LPC_OTG_I2C_CLKHI, 0x3f); + lpc_otg_write_4(sc, LPC_OTG_I2C_CLKLO, 0x3f); + + ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL); + lpc_otg_write_4(sc, LPC_OTG_I2C_CTRL, ctrl | LPC_OTG_I2C_CTRL_SRST); + + do { + ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL); + i++; + } while (ctrl & LPC_OTG_I2C_CTRL_SRST); +} + +static void +lpc_isp3101_write(struct ohci_softc *sc, int reg, int value) +{ + int status; + int i = 0; + + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX, + (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT); + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX, + (reg | I2C_WRITE)); + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX, + (value | I2C_STOP_BIT)); + + do { + status = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl, + LPC_OTG_I2C_STATUS); + i++; + } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000); + + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_STATUS, + LPC_OTG_I2C_STATUS_TDI); +} + +static __inline void +lpc_isp3101_clear(struct ohci_softc *sc, int reg, int value) +{ + lpc_isp3101_write(sc, (reg | LPC_ISP3101_REG_CLEAR_ADDR), value); +} + +static void +lpc_isp3101_configure(device_t dev, struct ohci_softc *sc) +{ + lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_UART_EN); + lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, ~LPC_ISP3101_MC1_SPEED_REG); + lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_SPEED_REG); + lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_2, ~0); + lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_2, + (LPC_ISP3101_MC2_BI_DI | LPC_ISP3101_MC2_PSW_EN + | LPC_ISP3101_MC2_SPD_SUSP_CTRL)); + + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1, ~0); + lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_DAT_SE0); + lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1, + (LPC_ISP3101_OTG1_DM_PULLDOWN | LPC_ISP3101_OTG1_DP_PULLDOWN)); + + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1, + (LPC_ISP3101_OTG1_DM_PULLUP | LPC_ISP3101_OTG1_DP_PULLUP)); + + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_LATCH, ~0); + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_FALLING, ~0); + lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_RISING, ~0); + + device_printf(dev, + "ISP3101 PHY \n", + (lpc_isp3101_read(sc, 0x00) | (lpc_isp3101_read(sc, 0x01) << 8)), + (lpc_isp3101_read(sc, 0x03) | (lpc_isp3101_read(sc, 0x04) << 8)), + (lpc_isp3101_read(sc, 0x14) | (lpc_isp3101_read(sc, 0x15) << 8))); +} + +static int +lpc_ohci_detach(device_t dev) +{ + return (0); +} + + +static device_method_t lpc_ohci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_ohci_probe), + DEVMETHOD(device_attach, lpc_ohci_attach), + DEVMETHOD(device_detach, lpc_ohci_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + + /* Bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + { 0, 0 } +}; + +static driver_t lpc_ohci_driver = { + "ohci", + lpc_ohci_methods, + sizeof(struct ohci_softc), +}; + +static devclass_t lpc_ohci_devclass; + +DRIVER_MODULE(ohci, simplebus, lpc_ohci_driver, lpc_ohci_devclass, 0, 0); +MODULE_DEPEND(ohci, usb, 1, 1, 1); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_pll.c armv6/sys/arm/lpc/lpc_pll.c --- head/sys/arm/lpc/lpc_pll.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_pll.c 2012-08-08 12:43:50.905723899 -0700 @@ -0,0 +1,28 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_pwr.c armv6/sys/arm/lpc/lpc_pwr.c --- head/sys/arm/lpc/lpc_pwr.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_pwr.c 2012-08-08 12:43:50.901723932 -0700 @@ -0,0 +1,126 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +struct lpc_pwr_softc { + device_t dp_dev; + struct resource * dp_mem_res; + bus_space_tag_t dp_bst; + bus_space_handle_t dp_bsh; +}; + +static struct lpc_pwr_softc *lpc_pwr_sc = NULL; + +static int lpc_pwr_probe(device_t); +static int lpc_pwr_attach(device_t); + +#define lpc_pwr_read_4(_sc, _reg) \ + bus_space_read_4((_sc)->dp_bst, (_sc)->dp_bsh, _reg) +#define lpc_pwr_write_4(_sc, _reg, _val) \ + bus_space_write_4((_sc)->dp_bst, (_sc)->dp_bsh, _reg, _val) + +static int +lpc_pwr_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "lpc,pwr")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 Power Controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_pwr_attach(device_t dev) +{ + struct lpc_pwr_softc *sc = device_get_softc(dev); + int rid; + + sc->dp_dev = dev; + + rid = 0; + sc->dp_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->dp_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->dp_bst = rman_get_bustag(sc->dp_mem_res); + sc->dp_bsh = rman_get_bushandle(sc->dp_mem_res); + + lpc_pwr_sc = sc; + + return (0); +} + +uint32_t +lpc_pwr_read(device_t dev, int reg) +{ + return (lpc_pwr_read_4(lpc_pwr_sc, reg)); +} + +void +lpc_pwr_write(device_t dev, int reg, uint32_t value) +{ + lpc_pwr_write_4(lpc_pwr_sc, reg, value); +} + +static device_method_t lpc_pwr_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_pwr_probe), + DEVMETHOD(device_attach, lpc_pwr_attach), + { 0, 0 } +}; + +static devclass_t lpc_pwr_devclass; + +static driver_t lpc_pwr_driver = { + "pwr", + lpc_pwr_methods, + sizeof(struct lpc_pwr_softc), +}; + +DRIVER_MODULE(pwr, simplebus, lpc_pwr_driver, lpc_pwr_devclass, 0, 0); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_rtc.c armv6/sys/arm/lpc/lpc_rtc.c --- head/sys/arm/lpc/lpc_rtc.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_rtc.c 2012-08-08 12:43:50.906723872 -0700 @@ -0,0 +1,147 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "clock_if.h" + +struct lpc_rtc_softc { + device_t lr_dev; + struct resource * lr_mem_res; + bus_space_tag_t lr_bst; + bus_space_handle_t lr_bsh; +}; + +static int lpc_rtc_probe(device_t dev); +static int lpc_rtc_attach(device_t dev); +static int lpc_rtc_gettime(device_t dev, struct timespec *ts); +static int lpc_rtc_settime(device_t, struct timespec *); + +static int +lpc_rtc_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "lpc,rtc")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 real time clock"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_rtc_attach(device_t dev) +{ + struct lpc_rtc_softc *sc = device_get_softc(dev); + int rid = 0; + + sc->lr_dev = dev; + + clock_register(dev, 1000000); + + sc->lr_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->lr_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->lr_bst = rman_get_bustag(sc->lr_mem_res); + sc->lr_bsh = rman_get_bushandle(sc->lr_mem_res); + + return (0); +} + +static int +lpc_rtc_gettime(device_t dev, struct timespec *ts) +{ + struct lpc_rtc_softc *sc = device_get_softc(dev); + + ts->tv_sec = bus_space_read_4(sc->lr_bst, sc->lr_bsh, LPC_RTC_UCOUNT); + ts->tv_nsec = 0; + + return (0); +} + +static int +lpc_rtc_settime(device_t dev, struct timespec *ts) +{ + struct lpc_rtc_softc *sc = device_get_softc(dev); + uint32_t ctrl; + + /* Stop RTC */ + ctrl = bus_space_read_4(sc->lr_bst, sc->lr_bsh, LPC_RTC_CTRL); + bus_space_write_4(sc->lr_bst, sc->lr_bsh, LPC_RTC_CTRL, ctrl | LPC_RTC_CTRL_DISABLE); + + /* Write actual value */ + bus_space_write_4(sc->lr_bst, sc->lr_bsh, LPC_RTC_UCOUNT, ts->tv_sec); + + /* Start RTC */ + ctrl = bus_space_read_4(sc->lr_bst, sc->lr_bsh, LPC_RTC_CTRL); + bus_space_write_4(sc->lr_bst, sc->lr_bsh, LPC_RTC_CTRL, ctrl & ~LPC_RTC_CTRL_DISABLE); + + return (0); +} + +static device_method_t lpc_rtc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_rtc_probe), + DEVMETHOD(device_attach, lpc_rtc_attach), + + /* Clock interface */ + DEVMETHOD(clock_gettime, lpc_rtc_gettime), + DEVMETHOD(clock_settime, lpc_rtc_settime), + + { 0, 0 }, +}; + +static driver_t lpc_rtc_driver = { + "rtc", + lpc_rtc_methods, + sizeof(struct lpc_rtc_softc), +}; + +static devclass_t lpc_rtc_devclass; + +DRIVER_MODULE(rtc, simplebus, lpc_rtc_driver, lpc_rtc_devclass, 0, 0); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_space.c armv6/sys/arm/lpc/lpc_space.c --- head/sys/arm/lpc/lpc_space.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_space.c 2012-08-08 12:43:50.907724520 -0700 @@ -0,0 +1,147 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include + +bs_protos(generic); +bs_protos(generic_armv4); + +static struct bus_space _base_tag = { + /* cookie */ + NULL, + + /* mapping/unmapping */ + generic_bs_map, + generic_bs_unmap, + generic_bs_subregion, + + /* allocation/deallocation */ + generic_bs_alloc, + generic_bs_free, + + /* barrier */ + generic_bs_barrier, + + /* read (single) */ + generic_bs_r_1, + generic_armv4_bs_r_2, + generic_bs_r_4, + NULL, + + /* read (multiple) */ + generic_bs_rm_1, + generic_armv4_bs_rm_2, + generic_bs_rm_4, + NULL, + + /* read region */ + generic_bs_rr_1, + generic_armv4_bs_rr_2, + generic_bs_rr_4, + NULL, + + /* write (single) */ + generic_bs_w_1, + generic_armv4_bs_w_2, + generic_bs_w_4, + NULL, + + /* write multiple */ + generic_bs_wm_1, + generic_armv4_bs_wm_2, + generic_bs_wm_4, + NULL, + + /* write region */ + NULL, + NULL, + NULL, + NULL, + + /* set multiple */ + NULL, + NULL, + NULL, + NULL, + + /* set region */ + NULL, + NULL, + NULL, + NULL, + + /* copy */ + NULL, + NULL, + NULL, + NULL, + + /* read stream (single) */ + NULL, + NULL, + NULL, + NULL, + + /* read multiple stream */ + NULL, + generic_armv4_bs_rm_2, + NULL, + NULL, + + /* read region stream */ + NULL, + NULL, + NULL, + NULL, + + /* write stream (single) */ + NULL, + NULL, + NULL, + NULL, + + /* write multiple stream */ + NULL, + generic_armv4_bs_wm_2, + NULL, + NULL, + + /* write region stream */ + NULL, + NULL, + NULL, + NULL, +}; + +bus_space_tag_t fdtbus_bs_tag = &_base_tag; diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_spi.c armv6/sys/arm/lpc/lpc_spi.c --- head/sys/arm/lpc/lpc_spi.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_spi.c 2012-08-08 12:43:50.907724520 -0700 @@ -0,0 +1,195 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +#include "spibus_if.h" + +struct lpc_spi_softc +{ + device_t ls_dev; + struct resource * ls_mem_res; + struct resource * ls_irq_res; + bus_space_tag_t ls_bst; + bus_space_handle_t ls_bsh; +}; + +static int lpc_spi_probe(device_t); +static int lpc_spi_attach(device_t); +static int lpc_spi_detach(device_t); +static int lpc_spi_transfer(device_t, device_t, struct spi_command *); + +#define lpc_spi_read_4(_sc, _reg) \ + bus_space_read_4(_sc->ls_bst, _sc->ls_bsh, _reg) +#define lpc_spi_write_4(_sc, _reg, _val) \ + bus_space_write_4(_sc->ls_bst, _sc->ls_bsh, _reg, _val) + +static int +lpc_spi_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "lpc,spi")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 PL022 SPI/SSP controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_spi_attach(device_t dev) +{ + struct lpc_spi_softc *sc = device_get_softc(dev); + int rid; + + sc->ls_dev = dev; + + rid = 0; + sc->ls_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->ls_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->ls_bst = rman_get_bustag(sc->ls_mem_res); + sc->ls_bsh = rman_get_bushandle(sc->ls_mem_res); + + rid = 0; + sc->ls_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (!sc->ls_irq_res) { + device_printf(dev, "cannot allocate interrupt\n"); + return (ENXIO); + } + + bus_space_write_4(sc->ls_bst, 0xd0028100, 0, (1<<12)|(1<<10)|(1<<9)|(1<<8)|(1<<6)|(1<<5)); + lpc_pwr_write(dev, LPC_CLKPWR_SSP_CTRL, LPC_CLKPWR_SSP_CTRL_SSP0EN); + lpc_spi_write_4(sc, LPC_SSP_CR0, LPC_SSP_CR0_DSS(8)); + lpc_spi_write_4(sc, LPC_SSP_CR1, LPC_SSP_CR1_SSE); + lpc_spi_write_4(sc, LPC_SSP_CPSR, 128); + + device_add_child(dev, "spibus", 0); + return (bus_generic_attach(dev)); +} + +static int +lpc_spi_detach(device_t dev) +{ + return (EBUSY); +} + +static int +lpc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) +{ + struct lpc_spi_softc *sc = device_get_softc(dev); + struct spibus_ivar *devi = SPIBUS_IVAR(child); + uint8_t *in_buf, *out_buf; + int i; + + /* Set CS active */ + lpc_gpio_set_state(child, devi->cs, 0); + + /* Wait for FIFO to be ready */ + while ((lpc_spi_read_4(sc, LPC_SSP_SR) & LPC_SSP_SR_TNF) == 0); + + /* Command */ + in_buf = cmd->rx_cmd; + out_buf = cmd->tx_cmd; + for (i = 0; i < cmd->tx_cmd_sz; i++) { + lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); + in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); + } + + /* Data */ + in_buf = cmd->rx_data; + out_buf = cmd->tx_data; + for (i = 0; i < cmd->tx_data_sz; i++) { + lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); + in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); + } + + /* Set CS inactive */ + lpc_gpio_set_state(child, devi->cs, 1); + + return (0); +} + +static device_method_t lpc_spi_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lpc_spi_probe), + DEVMETHOD(device_attach, lpc_spi_attach), + DEVMETHOD(device_detach, lpc_spi_detach), + + /* SPI interface */ + DEVMETHOD(spibus_transfer, lpc_spi_transfer), + + { 0, 0 } +}; + +static devclass_t lpc_spi_devclass; + +static driver_t lpc_spi_driver = { + "spi", + lpc_spi_methods, + sizeof(struct lpc_spi_softc), +}; + +DRIVER_MODULE(lpcspi, simplebus, lpc_spi_driver, lpc_spi_devclass, 0, 0); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpc_timer.c armv6/sys/arm/lpc/lpc_timer.c --- head/sys/arm/lpc/lpc_timer.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpc_timer.c 2012-08-08 12:43:50.903723953 -0700 @@ -0,0 +1,320 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +struct lpc_timer_softc { + device_t lt_dev; + struct eventtimer lt_et; + struct resource * lt_res[5]; + bus_space_tag_t lt_bst0; + bus_space_handle_t lt_bsh0; + bus_space_tag_t lt_bst1; + bus_space_handle_t lt_bsh1; + int lt_oneshot; + uint32_t lt_period; +}; + +static struct resource_spec lpc_timer_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_MEMORY, 1, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 1, RF_ACTIVE }, + { -1, 0 } +}; + +static struct lpc_timer_softc *timer_softc = NULL; +static int lpc_timer_initialized = 0; +static int lpc_timer_probe(device_t); +static int lpc_timer_attach(device_t); +static int lpc_timer_start(struct eventtimer *, struct bintime *first, + struct bintime *); +static int lpc_timer_stop(struct eventtimer *et); +static unsigned lpc_get_timecount(struct timecounter *); +static int lpc_hardclock(void *); + +#define timer0_read_4(sc, reg) \ + bus_space_read_4(sc->lt_bst0, sc->lt_bsh0, reg) +#define timer0_write_4(sc, reg, val) \ + bus_space_write_4(sc->lt_bst0, sc->lt_bsh0, reg, val) +#define timer0_clear(sc) \ + do { \ + timer0_write_4(sc, LPC_TIMER_TC, 0); \ + timer0_write_4(sc, LPC_TIMER_PR, 0); \ + timer0_write_4(sc, LPC_TIMER_PC, 0); \ + } while(0) + +#define timer1_read_4(sc, reg) \ + bus_space_read_4(sc->lt_bst1, sc->lt_bsh1, reg) +#define timer1_write_4(sc, reg, val) \ + bus_space_write_4(sc->lt_bst1, sc->lt_bsh1, reg, val) +#define timer1_clear(sc) \ + do { \ + timer1_write_4(sc, LPC_TIMER_TC, 0); \ + timer1_write_4(sc, LPC_TIMER_PR, 0); \ + timer1_write_4(sc, LPC_TIMER_PC, 0); \ + } while(0) + +static struct timecounter lpc_timecounter = { + .tc_get_timecount = lpc_get_timecount, + .tc_name = "LPC32x0 Timer1", + .tc_frequency = 0, /* will be filled later */ + .tc_counter_mask = ~0u, + .tc_quality = 1000, +}; + +static int +lpc_timer_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "lpc,timer")) + return (ENXIO); + + device_set_desc(dev, "LPC32x0 timer"); + return (BUS_PROBE_DEFAULT); +} + +static int +lpc_timer_attach(device_t dev) +{ + void *intrcookie; + struct lpc_timer_softc *sc = device_get_softc(dev); + phandle_t node; + uint32_t freq; + + if (timer_softc) + return (ENXIO); + + timer_softc = sc; + + if (bus_alloc_resources(dev, lpc_timer_spec, sc->lt_res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + sc->lt_bst0 = rman_get_bustag(sc->lt_res[0]); + sc->lt_bsh0 = rman_get_bushandle(sc->lt_res[0]); + sc->lt_bst1 = rman_get_bustag(sc->lt_res[1]); + sc->lt_bsh1 = rman_get_bushandle(sc->lt_res[1]); + + if (bus_setup_intr(dev, sc->lt_res[2], INTR_TYPE_CLK, + lpc_hardclock, NULL, sc, &intrcookie)) { + device_printf(dev, "could not setup interrupt handler\n"); + bus_release_resources(dev, lpc_timer_spec, sc->lt_res); + return (ENXIO); + } + + /* Enable timer clock */ + lpc_pwr_write(dev, LPC_CLKPWR_TIMCLK_CTRL1, + LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 | + LPC_CLKPWR_TIMCLK_CTRL1_TIMER1); + + /* Get PERIPH_CLK encoded in parent bus 'bus-frequency' property */ + node = ofw_bus_get_node(dev); + if (OF_getprop(OF_parent(node), "bus-frequency", &freq, + sizeof(pcell_t)) <= 0) { + bus_release_resources(dev, lpc_timer_spec, sc->lt_res); + bus_teardown_intr(dev, sc->lt_res[2], intrcookie); + device_printf(dev, "could not obtain base clock frequency\n"); + return (ENXIO); + } + + freq = fdt32_to_cpu(freq); + + /* Set desired frequency in event timer and timecounter */ + sc->lt_et.et_frequency = (uint64_t)freq; + lpc_timecounter.tc_frequency = (uint64_t)freq; + + sc->lt_et.et_name = "LPC32x0 Timer0"; + sc->lt_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; + sc->lt_et.et_quality = 1000; + sc->lt_et.et_min_period.sec = 0; + sc->lt_et.et_min_period.frac = + ((0x00000002LLU << 32) / sc->lt_et.et_frequency) << 32; + sc->lt_et.et_max_period.sec = 0xfffffff0U / sc->lt_et.et_frequency; + sc->lt_et.et_max_period.frac = + ((0xfffffffeLLU << 32) / sc->lt_et.et_frequency) << 32; + sc->lt_et.et_start = lpc_timer_start; + sc->lt_et.et_stop = lpc_timer_stop; + sc->lt_et.et_priv = sc; + + et_register(&sc->lt_et); + tc_init(&lpc_timecounter); + + /* Reset and enable timecounter */ + timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET); + timer1_write_4(sc, LPC_TIMER_TCR, 0); + timer1_clear(sc); + timer1_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); + + /* DELAY() now can work properly */ + lpc_timer_initialized = 1; + + return (0); +} + +static int +lpc_timer_start(struct eventtimer *et, struct bintime *first, + struct bintime *period) +{ + struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv; + uint32_t ticks; + + if (period == NULL) + sc->lt_oneshot = 1; + else { + sc->lt_oneshot = 0; + sc->lt_period = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32; + sc->lt_period += sc->lt_et.et_frequency * first->sec; + } + + if (first == NULL) + ticks = sc->lt_period; + else { + ticks = (sc->lt_et.et_frequency * (first->frac >> 32)) >> 32; + if (first->sec != 0) + ticks += sc->lt_et.et_frequency * first->sec; + } + + /* Reset timer */ + timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_RESET); + timer0_write_4(sc, LPC_TIMER_TCR, 0); + + /* Start timer */ + timer0_clear(sc); + timer0_write_4(sc, LPC_TIMER_MR0, ticks); + timer0_write_4(sc, LPC_TIMER_MCR, LPC_TIMER_MCR_MR0I | LPC_TIMER_MCR_MR0S); + timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); + return (0); +} + +static int +lpc_timer_stop(struct eventtimer *et) +{ + struct lpc_timer_softc *sc = (struct lpc_timer_softc *)et->et_priv; + + timer0_write_4(sc, LPC_TIMER_TCR, 0); + return (0); +} + +static device_method_t lpc_timer_methods[] = { + DEVMETHOD(device_probe, lpc_timer_probe), + DEVMETHOD(device_attach, lpc_timer_attach), + { 0, 0 } +}; + +static driver_t lpc_timer_driver = { + "timer", + lpc_timer_methods, + sizeof(struct lpc_timer_softc), +}; + +static devclass_t lpc_timer_devclass; + +DRIVER_MODULE(timer, simplebus, lpc_timer_driver, lpc_timer_devclass, 0, 0); + +static int +lpc_hardclock(void *arg) +{ + struct lpc_timer_softc *sc = (struct lpc_timer_softc *)arg; + + /* Reset pending interrupt */ + timer0_write_4(sc, LPC_TIMER_IR, 0xffffffff); + + /* Start timer again */ + if (!sc->lt_oneshot) { + timer0_clear(sc); + timer0_write_4(sc, LPC_TIMER_MR0, sc->lt_period); + timer0_write_4(sc, LPC_TIMER_TCR, LPC_TIMER_TCR_ENABLE); + } + + if (sc->lt_et.et_active) + sc->lt_et.et_event_cb(&sc->lt_et, sc->lt_et.et_arg); + + return (FILTER_HANDLED); +} + +static unsigned +lpc_get_timecount(struct timecounter *tc) +{ + return timer1_read_4(timer_softc, LPC_TIMER_TC); +} + +void +cpu_initclocks(void) +{ + cpu_initclocks_bsp(); +} + +void +DELAY(int usec) +{ + uint32_t counter; + uint32_t first, last; + int val = (lpc_timecounter.tc_frequency / 1000000 + 1) * usec; + + /* Timer is not initialized yet */ + if (!lpc_timer_initialized) { + for (; usec > 0; usec--) + for (counter = 100; counter > 0; counter--) + ; + return; + } + + first = lpc_get_timecount(&lpc_timecounter); + while (val > 0) { + last = lpc_get_timecount(&lpc_timecounter); + if (last < first) { + /* Timer rolled over */ + last = first; + } + + val -= (last - first); + first = last; + } +} diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpcreg.h armv6/sys/arm/lpc/lpcreg.h --- head/sys/arm/lpc/lpcreg.h 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpcreg.h 2012-08-08 12:43:50.904723926 -0700 @@ -0,0 +1,659 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM_LPC_LPCREG_H +#define _ARM_LPC_LPCREG_H + +#define LPC_DEV_PHYS_BASE 0x40000000 +#define LPC_DEV_P5_PHYS_BASE 0x20000000 +#define LPC_DEV_P6_PHYS_BASE 0x30000000 +#define LPC_DEV_BASE 0xd0000000 +#define LPC_DEV_SIZE 0x10000000 + +/* + * Interrupt controller (from UM10326: LPC32x0 User manual, page 87) + + */ +#define LPC_INTC_MIC_ER 0x0000 +#define LPC_INTC_MIC_RSR 0x0004 +#define LPC_INTC_MIC_SR 0x0008 +#define LPC_INTC_MIC_APR 0x000c +#define LPC_INTC_MIC_ATR 0x0010 +#define LPC_INTC_MIC_ITR 0x0014 +#define LPC_INTC_SIC1_ER 0x4000 +#define LPC_INTC_SIC1_RSR 0x4004 +#define LPC_INTC_SIC1_SR 0x4008 +#define LPC_INTC_SIC1_APR 0x400c +#define LPC_INTC_SIC1_ATR 0x4010 +#define LPC_INTC_SIC1_ITR 0x4014 +#define LPC_INTC_SIC2_ER 0x8000 +#define LPC_INTC_SIC2_RSR 0x8004 +#define LPC_INTC_SIC2_SR 0x8008 +#define LPC_INTC_SIC2_APR 0x800c +#define LPC_INTC_SIC2_ATR 0x8010 +#define LPC_INTC_SIC2_ITR 0x8014 + + +/* + * Timer 0|1|2|3|4|5. (from UM10326: LPC32x0 User manual, page 540) + */ +#define LPC_TIMER_IR 0x00 +#define LPC_TIMER_TCR 0x04 +#define LPC_TIMER_TCR_ENABLE (1 << 0) +#define LPC_TIMER_TCR_RESET (1 << 1) +#define LPC_TIMER_TC 0x08 +#define LPC_TIMER_PR 0x0c +#define LPC_TIMER_PC 0x10 +#define LPC_TIMER_MCR 0x14 +#define LPC_TIMER_MCR_MR0I (1 << 0) +#define LPC_TIMER_MCR_MR0R (1 << 1) +#define LPC_TIMER_MCR_MR0S (1 << 2) +#define LPC_TIMER_MCR_MR1I (1 << 3) +#define LPC_TIMER_MCR_MR1R (1 << 4) +#define LPC_TIMER_MCR_MR1S (1 << 5) +#define LPC_TIMER_MCR_MR2I (1 << 6) +#define LPC_TIMER_MCR_MR2R (1 << 7) +#define LPC_TIMER_MCR_MR2S (1 << 8) +#define LPC_TIMER_MCR_MR3I (1 << 9) +#define LPC_TIMER_MCR_MR3R (1 << 10) +#define LPC_TIMER_MCR_MR3S (1 << 11) +#define LPC_TIMER_MR0 0x18 +#define LPC_TIMER_CTCR 0x70 + +/* + * Watchdog timer. (from UM10326: LPC32x0 User manual, page 572) + */ +#define LPC_WDTIM_BASE (LPC_DEV_BASE + 0x3c000) +#define LPC_WDTIM_INT 0x00 +#define LPC_WDTIM_CTRL 0x04 +#define LPC_WDTIM_COUNTER 0x08 +#define LPC_WDTIM_MCTRL 0x0c +#define LPC_WDTIM_MATCH0 0x10 +#define LPC_WDTIM_EMR 0x14 +#define LPC_WDTIM_PULSE 0x18 +#define LPC_WDTIM_RES 0x1c + +/* + * Clocking and power control. (from UM10326: LPC32x0 User manual, page 58) + */ +#define LPC_CLKPWR_BASE (LPC_DEV_BASE + 0x4000) +#define LPC_CLKPWR_PWR_CTRL 0x44 +#define LPC_CLKPWR_OSC_CTRL 0x4c +#define LPC_CLKPWR_SYSCLK_CTRL 0x50 +#define LPC_CLKPWR_PLL397_CTRL 0x48 +#define LPC_CLKPWR_HCLKPLL_CTRL 0x58 +#define LPC_CLKPWR_HCLKDIV_CTRL 0x40 +#define LPC_CLKPWR_TEST_CTRL 0xa4 +#define LPC_CLKPWR_AUTOCLK_CTRL 0xec +#define LPC_CLKPWR_START_ER_PIN 0x30 +#define LPC_CLKPWR_START_ER_INT 0x20 +#define LPC_CLKPWR_P0_INTR_ER 0x18 +#define LPC_CLKPWR_START_SR_PIN 0x38 +#define LPC_CLKPWR_START_SR_INT 0x28 +#define LPC_CLKPWR_START_RSR_PIN 0x34 +#define LPC_CLKPWR_START_RSR_INT 0x24 +#define LPC_CLKPWR_START_APR_PIN 0x3c +#define LPC_CLKPWR_START_APR_INT 0x2c +#define LPC_CLKPWR_USB_CTRL 0x64 +#define LPC_CLKPWR_USB_CTRL_SLAVE_HCLK (1 << 24) +#define LPC_CLKPWR_USB_CTRL_I2C_EN (1 << 23) +#define LPC_CLKPWR_USB_CTRL_DEV_NEED_CLK_EN (1 << 22) +#define LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN (1 << 21) +#define LPC_CLKPWR_USB_CTRL_BUSKEEPER (1 << 19) +#define LPC_CLKPWR_USB_CTRL_CLK_EN2 (1 << 18) +#define LPC_CLKPWR_USB_CTRL_CLK_EN1 (1 << 17) +#define LPC_CLKPWR_USB_CTRL_PLL_PDOWN (1 << 16) +#define LPC_CLKPWR_USB_CTRL_BYPASS (1 << 15) +#define LPC_CLKPWR_USB_CTRL_DIRECT_OUT (1 << 14) +#define LPC_CLKPWR_USB_CTRL_FEEDBACK (1 << 13) +#define LPC_CLKPWR_USB_CTRL_POSTDIV(_x) ((_x & 0x3) << 11) +#define LPC_CLKPWR_USB_CTRL_PREDIV(_x) ((_x & 0x3) << 9) +#define LPC_CLKPWR_USB_CTRL_FDBKDIV(_x) (((_x-1) & 0xff) << 1) +#define LPC_CLKPWR_USB_CTRL_PLL_LOCK (1 << 0) +#define LPC_CLKPWR_USBDIV_CTRL 0x1c +#define LPC_CLKPWR_MS_CTRL 0x80 +#define LPC_CLKPWR_MS_CTRL_DISABLE_SD (1 << 10) +#define LPC_CLKPWR_MS_CTRL_CLOCK_EN (1 << 9) +#define LPC_CLKPWR_MS_CTRL_MSSDIO23_PAD (1 << 8) +#define LPC_CLKPWR_MS_CTRL_MSSDIO1_PAD (1 << 7) +#define LPC_CLKPWR_MS_CTRL_MSSDIO0_PAD (1 << 6) +#define LPC_CLKPWR_MS_CTRL_SD_CLOCK (1 << 5) +#define LPC_CLKPWR_MS_CTRL_CLKDIV_MASK 0xf +#define LPC_CLKPWR_DMACLK_CTRL 0xe8 +#define LPC_CLKPWR_DMACLK_CTRL_EN (1 << 0) +#define LPC_CLKPWR_FLASHCLK_CTRL 0xc8 +#define LPC_CLKPWR_MACCLK_CTRL 0x90 +#define LPC_CLKPWR_MACCLK_CTRL_REG (1 << 0) +#define LPC_CLKPWR_MACCLK_CTRL_SLAVE (1 << 1) +#define LPC_CLKPWR_MACCLK_CTRL_MASTER (1 << 2) +#define LPC_CLKPWR_MACCLK_CTRL_HDWINF(_n) ((_n & 0x3) << 3) +#define LPC_CLKPWR_LCDCLK_CTRL 0x54 +#define LPC_CLKPWR_LCDCLK_CTRL_DISPTYPE (1 << 8) +#define LPC_CLKPWR_LCDCLK_CTRL_MODE(_n) ((_n & 0x3) << 6) +#define LPC_CLKPWR_LCDCLK_CTRL_MODE_12 0x0 +#define LPC_CLKPWR_LCDCLK_CTRL_MODE_15 0x1 +#define LPC_CLKPWR_LCDCLK_CTRL_MODE_16 0x2 +#define LPC_CLKPWR_LCDCLK_CTRL_MODE_24 0x3 +#define LPC_CLKPWR_LCDCLK_CTRL_HCLKEN (1 << 5) +#define LPC_CLKPWR_LCDCLK_CTRL_CLKDIV(_n) ((_n) & 0x1f) +#define LPC_CLKPWR_I2S_CTRL 0x7c +#define LPC_CLKPWR_SSP_CTRL 0x78 +#define LPC_CLKPWR_SSP_CTRL_SSP1RXDMA (1 << 5) +#define LPC_CLKPWR_SSP_CTRL_SSP1TXDMA (1 << 4) +#define LPC_CLKPWR_SSP_CTRL_SSP0RXDMA (1 << 3) +#define LPC_CLKPWR_SSP_CTRL_SSP0TXDMA (1 << 2) +#define LPC_CLKPWR_SSP_CTRL_SSP1EN (1 << 1) +#define LPC_CLKPWR_SSP_CTRL_SSP0EN (1 << 0) +#define LPC_CLKPWR_SPI_CTRL 0xc4 +#define LPC_CLKPWR_I2CCLK_CTRL 0xac +#define LPC_CLKPWR_TIMCLK_CTRL1 0xc0 +#define LPC_CLKPWR_TIMCLK_CTRL1_TIMER4 (1 << 0) +#define LPC_CLKPWR_TIMCLK_CTRL1_TIMER5 (1 << 1) +#define LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 (1 << 2) +#define LPC_CLKPWR_TIMCLK_CTRL1_TIMER1 (1 << 3) +#define LPC_CLKPWR_TIMCLK_CTRL1_TIMER2 (1 << 4) +#define LPC_CLKPWR_TIMCLK_CTRL1_TIMER3 (1 << 5) +#define LPC_CLKPWR_TIMCLK_CTRL1_MOTORCTL (1 << 6) +#define LPC_CLKPWR_TIMCLK_CTRL 0xbc +#define LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG (1 << 0) +#define LPC_CLKPWR_TIMCLK_CTRL_HSTIMER (1 << 1) +#define LPC_CLKPWR_ADCLK_CTRL 0xb4 +#define LPC_CLKPWR_ADCLK_CTRL1 0x60 +#define LPC_CLKPWR_KEYCLK_CTRL 0xb0 +#define LPC_CLKPWR_PWMCLK_CTRL 0xb8 +#define LPC_CLKPWR_UARTCLK_CTRL 0xe4 +#define LPC_CLKPWR_POS0_IRAM_CTRL 0x110 +#define LPC_CLKPWR_POS1_IRAM_CTRL 0x114 + +/* Additional UART registers in CLKPWR address space. */ +#define LPC_CLKPWR_UART_U3CLK 0xd0 +#define LPC_CLKPWR_UART_U4CLK 0xd4 +#define LPC_CLKPWR_UART_U5CLK 0xd8 +#define LPC_CLKPWR_UART_U6CLK 0xdc +#define LPC_CLKPWR_UART_UCLK_HCLK (1 << 16) +#define LPC_CLKPWR_UART_UCLK_X(_n) (((_n) & 0xff) << 8) +#define LPC_CLKPWR_UART_UCLK_Y(_n) ((_n) & 0xff) +#define LPC_CLKPWR_UART_IRDACLK 0xe0 + +/* Additional UART registers */ +#define LPC_UART_BASE (LPC_DEV_BASE + 0x80000) +#define LPC_UART_CONTROL_BASE (LPC_DEV_BASE + 0x54000) +#define LPC_UART5_BASE (LPC_DEV_BASE + 0x90000) +#define LPC_UART_CTRL 0x00 +#define LPC_UART_CLKMODE 0x04 +#define LPC_UART_CLKMODE_UART3(_n) (((_n) & 0x3) << 4) +#define LPC_UART_CLKMODE_UART4(_n) (((_n) & 0x3) << 6) +#define LPC_UART_CLKMODE_UART5(_n) (((_n) & 0x3) << 8) +#define LPC_UART_CLKMODE_UART6(_n) (((_n) & 0x3) << 10) +#define LPC_UART_LOOP 0x08 +#define LPC_UART_FIFOSIZE 64 + +/* + * Real time clock. (from UM10326: LPC32x0 User manual, page 566) + */ +#define LPC_RTC_UCOUNT 0x00 +#define LPC_RTC_DCOUNT 0x04 +#define LPC_RTC_MATCH0 0x08 +#define LPC_RTC_MATCH1 0x0c +#define LPC_RTC_CTRL 0x10 +#define LPC_RTC_CTRL_ONSW (1 << 7) +#define LPC_RTC_CTRL_DISABLE (1 << 6) +#define LPC_RTC_CTRL_RTCRESET (1 << 4) +#define LPC_RTC_CTRL_MATCH0ONSW (1 << 3) +#define LPC_RTC_CTRL_MATCH1ONSW (1 << 2) +#define LPC_RTC_CTRL_MATCH1INTR (1 << 1) +#define LPC_RTC_CTRL_MATCH0INTR (1 << 0) +#define LPC_RTC_INTSTAT 0x14 +#define LPC_RTC_KEY 0x18 +#define LPC_RTC_SRAM_BEGIN 0x80 +#define LPC_RTC_SRAM_END 0xff + +/* + * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436) + */ +#define LPC_SD_BASE (LPC_DEV_P5_PHYS_BASE + 0x98000) +#define LPC_SD_CLK (13 * 1000 * 1000) // 13Mhz +#define LPC_SD_POWER 0x00 +#define LPC_SD_POWER_OPENDRAIN (1 << 6) +#define LPC_SD_POWER_CTRL_OFF 0x00 +#define LPC_SD_POWER_CTRL_UP 0x02 +#define LPC_SD_POWER_CTRL_ON 0x03 +#define LPC_SD_CLOCK 0x04 +#define LPC_SD_CLOCK_WIDEBUS (1 << 11) +#define LPC_SD_CLOCK_BYPASS (1 << 10) +#define LPC_SD_CLOCK_PWRSAVE (1 << 9) +#define LPC_SD_CLOCK_ENABLE (1 << 8) +#define LPC_SD_CLOCK_CLKDIVMASK 0xff +#define LPC_SD_ARGUMENT 0x08 +#define LPC_SD_COMMAND 0x0c +#define LPC_SD_COMMAND_ENABLE (1 << 10) +#define LPC_SD_COMMAND_PENDING (1 << 9) +#define LPC_SD_COMMAND_INTERRUPT (1 << 8) +#define LPC_SD_COMMAND_LONGRSP (1 << 7) +#define LPC_SD_COMMAND_RESPONSE (1 << 6) +#define LPC_SD_COMMAND_CMDINDEXMASK 0x3f +#define LPC_SD_RESPCMD 0x10 +#define LPC_SD_RESP0 0x14 +#define LPC_SD_RESP1 0x18 +#define LPC_SD_RESP2 0x1c +#define LPC_SD_RESP3 0x20 +#define LPC_SD_DATATIMER 0x24 +#define LPC_SD_DATALENGTH 0x28 +#define LPC_SD_DATACTRL 0x2c +#define LPC_SD_DATACTRL_BLOCKSIZESHIFT 4 +#define LPC_SD_DATACTRL_BLOCKSIZEMASK 0xf +#define LPC_SD_DATACTRL_DMAENABLE (1 << 3) +#define LPC_SD_DATACTRL_MODE (1 << 2) +#define LPC_SD_DATACTRL_WRITE (0 << 1) +#define LPC_SD_DATACTRL_READ (1 << 1) +#define LPC_SD_DATACTRL_ENABLE (1 << 0) +#define LPC_SD_DATACNT 0x30 +#define LPC_SD_STATUS 0x34 +#define LPC_SD_STATUS_RXDATAAVLBL (1 << 21) +#define LPC_SD_STATUS_TXDATAAVLBL (1 << 20) +#define LPC_SD_STATUS_RXFIFOEMPTY (1 << 19) +#define LPC_SD_STATUS_TXFIFOEMPTY (1 << 18) +#define LPC_SD_STATUS_RXFIFOFULL (1 << 17) +#define LPC_SD_STATUS_TXFIFOFULL (1 << 16) +#define LPC_SD_STATUS_RXFIFOHALFFULL (1 << 15) +#define LPC_SD_STATUS_TXFIFOHALFEMPTY (1 << 14) +#define LPC_SD_STATUS_RXACTIVE (1 << 13) +#define LPC_SD_STATUS_TXACTIVE (1 << 12) +#define LPC_SD_STATUS_CMDACTIVE (1 << 11) +#define LPC_SD_STATUS_DATABLOCKEND (1 << 10) +#define LPC_SD_STATUS_STARTBITERR (1 << 9) +#define LPC_SD_STATUS_DATAEND (1 << 8) +#define LPC_SD_STATUS_CMDSENT (1 << 7) +#define LPC_SD_STATUS_CMDRESPEND (1 << 6) +#define LPC_SD_STATUS_RXOVERRUN (1 << 5) +#define LPC_SD_STATUS_TXUNDERRUN (1 << 4) +#define LPC_SD_STATUS_DATATIMEOUT (1 << 3) +#define LPC_SD_STATUS_CMDTIMEOUT (1 << 2) +#define LPC_SD_STATUS_DATACRCFAIL (1 << 1) +#define LPC_SD_STATUS_CMDCRCFAIL (1 << 0) +#define LPC_SD_CLEAR 0x38 +#define LPC_SD_MASK0 0x03c +#define LPC_SD_MASK1 0x40 +#define LPC_SD_FIFOCNT 0x48 +#define LPC_SD_FIFO 0x80 + +/* + * USB OTG controller (from UM10326: LPC32x0 User manual, page 410) + */ +#define LPC_OTG_INT_STATUS 0x100 +#define LPC_OTG_INT_ENABLE 0x104 +#define LPC_OTG_INT_SET 0x108 +#define LPC_OTG_INT_CLEAR 0x10c +#define LPC_OTG_STATUS 0x110 +#define LPC_OTG_STATUS_ATOB_HNP_TRACK (1 << 9) +#define LPC_OTG_STATUS_BTOA_HNP_TACK (1 << 8) +#define LPC_OTG_STATUS_TRANSP_I2C_EN (1 << 7) +#define LPC_OTG_STATUS_TIMER_RESET (1 << 6) +#define LPC_OTG_STATUS_TIMER_EN (1 << 5) +#define LPC_OTG_STATUS_TIMER_MODE (1 << 4) +#define LPC_OTG_STATUS_TIMER_SCALE (1 << 2) +#define LPC_OTG_STATUS_HOST_EN (1 << 0) +#define LPC_OTG_TIMER 0x114 +#define LPC_OTG_I2C_TXRX 0x300 +#define LPC_OTG_I2C_STATUS 0x304 +#define LPC_OTG_I2C_STATUS_TFE (1 << 11) +#define LPC_OTG_I2C_STATUS_TFF (1 << 10) +#define LPC_OTG_I2C_STATUS_RFE (1 << 9) +#define LPC_OTG_I2C_STATUS_RFF (1 << 8) +#define LPC_OTG_I2C_STATUS_SDA (1 << 7) +#define LPC_OTG_I2C_STATUS_SCL (1 << 6) +#define LPC_OTG_I2C_STATUS_ACTIVE (1 << 5) +#define LPC_OTG_I2C_STATUS_DRSI (1 << 4) +#define LPC_OTG_I2C_STATUS_DRMI (1 << 3) +#define LPC_OTG_I2C_STATUS_NAI (1 << 2) +#define LPC_OTG_I2C_STATUS_AFI (1 << 1) +#define LPC_OTG_I2C_STATUS_TDI (1 << 0) +#define LPC_OTG_I2C_CTRL 0x308 +#define LPC_OTG_I2C_CTRL_SRST (1 << 8) +#define LPC_OTG_I2C_CTRL_TFFIE (1 << 7) +#define LPC_OTG_I2C_CTRL_RFDAIE (1 << 6) +#define LPC_OTG_I2C_CTRL_RFFIE (1 << 5) +#define LPC_OTG_I2C_CTRL_DRSIE (1 << 4) +#define LPC_OTG_I2C_CTRL_DRMIE (1 << 3) +#define LPC_OTG_I2C_CTRL_NAIE (1 << 2) +#define LPC_OTG_I2C_CTRL_AFIE (1 << 1) +#define LPC_OTG_I2C_CTRL_TDIE (1 << 0) +#define LPC_OTG_I2C_CLKHI 0x30c +#define LPC_OTG_I2C_CLKLO 0x310 +#define LPC_OTG_CLOCK_CTRL 0xff4 +#define LPC_OTG_CLOCK_CTRL_AHB_EN (1 << 4) +#define LPC_OTG_CLOCK_CTRL_OTG_EN (1 << 3) +#define LPC_OTG_CLOCK_CTRL_I2C_EN (1 << 2) +#define LPC_OTG_CLOCK_CTRL_DEV_EN (1 << 1) +#define LPC_OTG_CLOCK_CTRL_HOST_EN (1 << 0) +#define LPC_OTG_CLOCK_STATUS 0xff8 + +/* + * ISP3101 USB transceiver registers + */ +#define LPC_ISP3101_I2C_ADDR 0x2d +#define LPC_ISP3101_MODE_CONTROL_1 0x04 +#define LPC_ISP3101_MC1_SPEED_REG (1 << 0) +#define LPC_ISP3101_MC1_SUSPEND_REG (1 << 1) +#define LPC_ISP3101_MC1_DAT_SE0 (1 << 2) +#define LPC_ISP3101_MC1_TRANSPARENT (1 << 3) +#define LPC_ISP3101_MC1_BDIS_ACON_EN (1 << 4) +#define LPC_ISP3101_MC1_OE_INT_EN (1 << 5) +#define LPC_ISP3101_MC1_UART_EN (1 << 6) +#define LPC_ISP3101_MODE_CONTROL_2 0x12 +#define LPC_ISP3101_MC2_GLOBAL_PWR_DN (1 << 0) +#define LPC_ISP3101_MC2_SPD_SUSP_CTRL (1 << 1) +#define LPC_ISP3101_MC2_BI_DI (1 << 2) +#define LPC_ISP3101_MC2_TRANSP_BDIR0 (1 << 3) +#define LPC_ISP3101_MC2_TRANSP_BDIR1 (1 << 4) +#define LPC_ISP3101_MC2_AUDIO_EN (1 << 5) +#define LPC_ISP3101_MC2_PSW_EN (1 << 6) +#define LPC_ISP3101_MC2_EN2V7 (1 << 7) +#define LPC_ISP3101_OTG_CONTROL_1 0x06 +#define LPC_ISP3101_OTG1_DP_PULLUP (1 << 0) +#define LPC_ISP3101_OTG1_DM_PULLUP (1 << 1) +#define LPC_ISP3101_OTG1_DP_PULLDOWN (1 << 2) +#define LPC_ISP3101_OTG1_DM_PULLDOWN (1 << 3) +#define LPC_ISP3101_OTG1_ID_PULLDOWN (1 << 4) +#define LPC_ISP3101_OTG1_VBUS_DRV (1 << 5) +#define LPC_ISP3101_OTG1_VBUS_DISCHRG (1 << 6) +#define LPC_ISP3101_OTG1_VBUS_CHRG (1 << 7) +#define LPC_ISP3101_OTG_CONTROL_2 0x10 +#define LPC_ISP3101_OTG_INTR_LATCH 0x0a +#define LPC_ISP3101_OTG_INTR_FALLING 0x0c +#define LPC_ISP3101_OTG_INTR_RISING 0x0e +#define LPC_ISP3101_REG_CLEAR_ADDR 0x01 + +/* + * LCD Controller (from UM10326: LPC32x0 User manual, page 229) + */ +#define LPC_LCD_TIMH 0x00 +#define LPC_LCD_TIMH_HBP(_n) (((_n) & 0xff) << 24) +#define LPC_LCD_TIMH_HFP(_n) (((_n) & 0xff) << 16) +#define LPC_LCD_TIMH_HSW(_n) (((_n) & 0xff) << 8) +#define LPC_LCD_TIMH_PPL(_n) (((_n) / 16 - 1) << 2) +#define LPC_LCD_TIMV 0x04 +#define LPC_LCD_TIMV_VBP(_n) (((_n) & 0xff) << 24) +#define LPC_LCD_TIMV_VFP(_n) (((_n) & 0xff) << 16) +#define LPC_LCD_TIMV_VSW(_n) (((_n) & 0x3f) << 10) +#define LPC_LCD_TIMV_LPP(_n) ((_n) & 0x1ff) +#define LPC_LCD_POL 0x08 +#define LPC_LCD_POL_PCD_HI (((_n) & 0x1f) << 27) +#define LPC_LCD_POL_BCD (1 << 26) +#define LPC_LCD_POL_CPL(_n) (((_n) & 0x3ff) << 16) +#define LPC_LCD_POL_IOE (1 << 14) +#define LPC_LCD_POL_IPC (1 << 13) +#define LPC_LCD_POL_IHS (1 << 12) +#define LPC_LCD_POL_IVS (1 << 11) +#define LPC_LCD_POL_ACB(_n) ((_n & 0x1f) << 6) +#define LPC_LCD_POL_CLKSEL (1 << 5) +#define LPC_LCD_POL_PCD_LO(_n) ((_n) & 0x1f) +#define LPC_LCD_LE 0x0c +#define LPC_LCD_LE_LEE (1 << 16) +#define LPC_LCD_LE_LED ((_n) & 0x7f) +#define LPC_LCD_UPBASE 0x10 +#define LPC_LCD_LPBASE 0x14 +#define LPC_LCD_CTRL 0x18 +#define LPC_LCD_CTRL_WATERMARK (1 << 16) +#define LPC_LCD_CTRL_LCDVCOMP(_n) (((_n) & 0x3) << 12) +#define LPC_LCD_CTRL_LCDPWR (1 << 11) +#define LPC_LCD_CTRL_BEPO (1 << 10) +#define LPC_LCD_CTRL_BEBO (1 << 9) +#define LPC_LCD_CTRL_BGR (1 << 8) +#define LPC_LCD_CTRL_LCDDUAL (1 << 7) +#define LPC_LCD_CTRL_LCDMONO8 (1 << 6) +#define LPC_LCD_CTRL_LCDTFT (1 << 5) +#define LPC_LCD_CTRL_LCDBW (1 << 4) +#define LPC_LCD_CTRL_LCDBPP(_n) (((_n) & 0x7) << 1) +#define LPC_LCD_CTRL_BPP1 0 +#define LPC_LCD_CTRL_BPP2 1 +#define LPC_LCD_CTRL_BPP4 2 +#define LPC_LCD_CTRL_BPP8 3 +#define LPC_LCD_CTRL_BPP16 4 +#define LPC_LCD_CTRL_BPP24 5 +#define LPC_LCD_CTRL_BPP16_565 6 +#define LPC_LCD_CTRL_BPP12_444 7 +#define LPC_LCD_CTRL_LCDEN (1 << 0) +#define LPC_LCD_INTMSK 0x1c +#define LPC_LCD_INTRAW 0x20 +#define LPC_LCD_INTSTAT 0x24 +#define LPC_LCD_INTCLR 0x28 +#define LPC_LCD_UPCURR 0x2c +#define LPC_LCD_LPCURR 0x30 +#define LPC_LCD_PAL 0x200 +#define LPC_LCD_CRSR_IMG 0x800 +#define LPC_LCD_CRSR_CTRL 0xc00 +#define LPC_LCD_CRSR_CFG 0xc04 +#define LPC_LCD_CRSR_PAL0 0xc08 +#define LPC_LCD_CRSR_PAL1 0xc0c +#define LPC_LCD_CRSR_XY 0xc10 +#define LPC_LCD_CRSR_CLIP 0xc14 +#define LPC_LCD_CRSR_INTMSK 0xc20 +#define LPC_LCD_CRSR_INTCLR 0xc24 +#define LPC_LCD_CRSR_INTRAW 0xc28 +#define LPC_LCD_CRSR_INTSTAT 0xc2c + +/* + * SPI interface (from UM10326: LPC32x0 User manual, page 483) + */ +#define LPC_SPI_GLOBAL 0x00 +#define LPC_SPI_GLOBAL_RST (1 << 1) +#define LPC_SPI_GLOBAL_ENABLE (1 << 0) +#define LPC_SPI_CON 0x04 +#define LPC_SPI_CON_UNIDIR (1 << 23) +#define LPC_SPI_CON_BHALT (1 << 22) +#define LPC_SPI_CON_BPOL (1 << 21) +#define LPC_SPI_CON_MSB (1 << 19) +#define LPC_SPI_CON_MODE(_n) ((_n & 0x3) << 16) +#define LPC_SPI_CON_RXTX (1 << 15) +#define LPC_SPI_CON_THR (1 << 14) +#define LPC_SPI_CON_SHIFT_OFF (1 << 13) +#define LPC_SPI_CON_BITNUM(_n) ((_n & 0xf) << 9) +#define LPC_SPI_CON_MS (1 << 7) +#define LPC_SPI_CON_RATE(_n) (_n & 0x7f) +#define LPC_SPI_FRM 0x08 +#define LPC_SPI_IER 0x0c +#define LPC_SPI_IER_INTEOT (1 << 1) +#define LPC_SPI_IER_INTTHR (1 << 0) +#define LPC_SPI_STAT 0x10 +#define LPC_SPI_STAT_INTCLR (1 << 8) +#define LPC_SPI_STAT_EOT (1 << 7) +#define LPC_SPI_STAT_BUSYLEV (1 << 6) +#define LPC_SPI_STAT_SHIFTACT (1 << 3) +#define LPC_SPI_STAT_BF (1 << 2) +#define LPC_SPI_STAT_THR (1 << 1) +#define LPC_SPI_STAT_BE (1 << 0) +#define LPC_SPI_DAT 0x14 +#define LPC_SPI_TIM_CTRL 0x400 +#define LPC_SPI_TIM_COUNT 0x404 +#define LPC_SPI_TIM_STAT 0x408 + +/* + * SSP interface (from UM10326: LPC32x0 User manual, page 500) + */ +#define LPC_SSP0_BASE 0x4c00 +#define LPC_SSP1_BASE 0xc000 +#define LPC_SSP_CR0 0x00 +#define LPC_SSP_CR0_DSS(_n) ((_n-1) & 0xf) +#define LPC_SSP_CR0_TI (1 << 4) +#define LPC_SSP_CR0_MICROWIRE (1 << 5) +#define LPC_SSP_CR0_CPOL (1 << 6) +#define LPC_SSP_CR0_CPHA (1 << 7) +#define LPC_SSP_CR0_SCR(_n) ((_x & & 0xff) << 8) +#define LPC_SSP_CR1 0x04 +#define LPC_SSP_CR1_LBM (1 << 0) +#define LPC_SSP_CR1_SSE (1 << 1) +#define LPC_SSP_CR1_MS (1 << 2) +#define LPC_SSP_CR1_SOD (1 << 3) +#define LPC_SSP_DR 0x08 +#define LPC_SSP_SR 0x0c +#define LPC_SSP_SR_TFE (1 << 0) +#define LPC_SSP_SR_TNF (1 << 1) +#define LPC_SSP_SR_RNE (1 << 2) +#define LPC_SSP_SR_RFF (1 << 3) +#define LPC_SSP_SR_BSY (1 << 4) +#define LPC_SSP_CPSR 0x10 +#define LPC_SSP_IMSC 0x14 +#define LPC_SSP_IMSC_RORIM (1 << 0) +#define LPC_SSP_IMSC_RTIM (1 << 1) +#define LPC_SSP_IMSC_RXIM (1 << 2) +#define LPC_SSP_IMSC_TXIM (1 << 3) +#define LPC_SSP_RIS 0x18 +#define LPC_SSP_RIS_RORRIS (1 << 0) +#define LPC_SSP_RIS_RTRIS (1 << 1) +#define LPC_SSP_RIS_RXRIS (1 << 2) +#define LPC_SSP_RIS_TXRIS (1 << 3) +#define LPC_SSP_MIS 0x1c +#define LPC_SSP_ICR 0x20 +#define LPC_SSP_DMACR 0x24 + +/* + * GPIO (from UM10326: LPC32x0 User manual, page 606) + */ +#define LPC_GPIO_BASE (LPC_DEV_BASE + 0x28000) +#define LPC_GPIO_P0_COUNT 8 +#define LPC_GPIO_P1_COUNT 24 +#define LPC_GPIO_P2_COUNT 13 +#define LPC_GPIO_P3_COUNT 52 +#define LPC_GPIO_P0_INP_STATE 0x40 +#define LPC_GPIO_P0_OUTP_SET 0x44 +#define LPC_GPIO_P0_OUTP_CLR 0x48 +#define LPC_GPIO_P0_OUTP_STATE 0x4c +#define LPC_GPIO_P0_DIR_SET 0x50 +#define LPC_GPIO_P0_DIR_CLR 0x54 +#define LPC_GPIO_P0_DIR_STATE 0x58 +#define LPC_GPIO_P1_INP_STATE 0x60 +#define LPC_GPIO_P1_OUTP_SET 0x64 +#define LPC_GPIO_P1_OUTP_CLR 0x68 +#define LPC_GPIO_P1_OUTP_STATE 0x6c +#define LPC_GPIO_P1_DIR_SET 0x70 +#define LPC_GPIO_P1_DIR_CLR 0x74 +#define LPC_GPIO_P1_DIR_STATE 0x78 +#define LPC_GPIO_P2_INP_STATE 0x1c +#define LPC_GPIO_P2_OUTP_SET 0x20 +#define LPC_GPIO_P2_OUTP_CLR 0x24 +#define LPC_GPIO_P2_DIR_SET 0x10 +#define LPC_GPIO_P2_DIR_CLR 0x14 +#define LPC_GPIO_P2_DIR_STATE 0x14 +#define LPC_GPIO_P3_INP_STATE 0x00 +#define LPC_GPIO_P3_OUTP_SET 0x04 +#define LPC_GPIO_P3_OUTP_CLR 0x08 +#define LPC_GPIO_P3_OUTP_STATE 0x0c +/* Aliases for logical pin numbers: */ +#define LPC_GPIO_GPI_00(_n) (0 + _n) +#define LPC_GPIO_GPI_15(_n) (10 + _n) +#define LPC_GPIO_GPI_25 (19) +#define LPC_GPIO_GPI_27(_n) (20 + _n) +#define LPC_GPIO_GPO_00(_n) (22 + _n) +#define LPC_GPIO_GPIO_00(_n) (46 + _n) +/* SPI devices chip selects: */ +#define SSD1289_CS_PIN LPC_GPIO_GPO_00(4) +#define SSD1289_DC_PIN LPC_GPIO_GPO_00(5) +#define ADS7846_CS_PIN LPC_GPIO_GPO_00(11) +#define ADS7846_INTR_PIN LPC_GPIO_GPIO_00(0) + +/* + * GPDMA controller (from UM10326: LPC32x0 User manual, page 106) + */ +#define LPC_DMAC_INTSTAT 0x00 +#define LPC_DMAC_INTTCSTAT 0x04 +#define LPC_DMAC_INTTCCLEAR 0x08 +#define LPC_DMAC_INTERRSTAT 0x0c +#define LPC_DMAC_INTERRCLEAR 0x10 +#define LPC_DMAC_RAWINTTCSTAT 0x14 +#define LPC_DMAC_RAWINTERRSTAT 0x18 +#define LPC_DMAC_ENABLED_CHANNELS 0x1c +#define LPC_DMAC_SOFTBREQ 0x20 +#define LPC_DMAC_SOFTSREQ 0x24 +#define LPC_DMAC_SOFTLBREQ 0x28 +#define LPC_DMAC_SOFTLSREQ 0x2c +#define LPC_DMAC_CONFIG 0x30 +#define LPC_DMAC_CONFIG_M1 (1 << 2) +#define LPC_DMAC_CONFIG_M0 (1 << 1) +#define LPC_DMAC_CONFIG_ENABLE (1 << 0) +#define LPC_DMAC_CHADDR(_n) (0x100 + (_n * 0x20)) +#define LPC_DMAC_CHNUM 8 +#define LPC_DMAC_CHSIZE 0x20 +#define LPC_DMAC_CH_SRCADDR 0x00 +#define LPC_DMAC_CH_DSTADDR 0x04 +#define LPC_DMAC_CH_LLI 0x08 +#define LPC_DMAC_CH_LLI_AHB1 (1 << 0) +#define LPC_DMAC_CH_CONTROL 0x0c +#define LPC_DMAC_CH_CONTROL_I (1 << 31) +#define LPC_DMAC_CH_CONTROL_DI (1 << 27) +#define LPC_DMAC_CH_CONTROL_SI (1 << 26) +#define LPC_DMAC_CH_CONTROL_D (1 << 25) +#define LPC_DMAC_CH_CONTROL_S (1 << 24) +#define LPC_DMAC_CH_CONTROL_WIDTH_4 2 +#define LPC_DMAC_CH_CONTROL_DWIDTH(_n) ((_n & 0x7) << 21) +#define LPC_DMAC_CH_CONTROL_SWIDTH(_n) ((_n & 0x7) << 18) +#define LPC_DMAC_CH_CONTROL_BURST_8 2 +#define LPC_DMAC_CH_CONTROL_DBSIZE(_n) ((_n & 0x7) << 15) +#define LPC_DMAC_CH_CONTROL_SBSIZE(_n) ((_n & 0x7) << 12) +#define LPC_DMAC_CH_CONTROL_XFERLEN(_n) (_n & 0xfff) +#define LPC_DMAC_CH_CONFIG 0x10 +#define LPC_DMAC_CH_CONFIG_H (1 << 18) +#define LPC_DMAC_CH_CONFIG_A (1 << 17) +#define LPC_DMAC_CH_CONFIG_L (1 << 16) +#define LPC_DMAC_CH_CONFIG_ITC (1 << 15) +#define LPC_DMAC_CH_CONFIG_IE (1 << 14) +#define LPC_DMAC_CH_CONFIG_FLOWCNTL(_n) ((_n & 0x7) << 11) +#define LPC_DMAC_CH_CONFIG_DESTP(_n) ((_n & 0x1f) << 6) +#define LPC_DMAC_CH_CONFIG_SRCP(_n) ((_n & 0x1f) << 1) +#define LPC_DMAC_CH_CONFIG_E (1 << 0) + +/* DMA flow control values */ +#define LPC_DMAC_FLOW_D_M2M 0 +#define LPC_DMAC_FLOW_D_M2P 1 +#define LPC_DMAC_FLOW_D_P2M 2 +#define LPC_DMAC_FLOW_D_P2P 3 +#define LPC_DMAC_FLOW_DP_P2P 4 +#define LPC_DMAC_FLOW_P_M2P 5 +#define LPC_DMAC_FLOW_P_P2M 6 +#define LPC_DMAC_FLOW_SP_P2P 7 + +/* DMA peripheral ID's */ +#define LPC_DMAC_I2S0_DMA0_ID 0 +#define LPC_DMAC_NAND_ID 1 +#define LPC_DMAC_IS21_DMA0_ID 2 +#define LPC_DMAC_SSP1_ID 3 +#define LPC_DMAC_SPI2_ID 3 +#define LPC_DMAC_SD_ID 4 +#define LPC_DMAC_UART1_TX_ID 5 +#define LPC_DMAC_UART1_RX_ID 6 +#define LPC_DMAC_UART2_TX_ID 7 +#define LPC_DMAC_UART2_RX_ID 8 +#define LPC_DMAC_UART7_TX_ID 9 +#define LPC_DMAC_UART7_RX_ID 10 +#define LPC_DMAC_I2S1_DMA1_ID 10 +#define LPC_DMAC_SPI1_ID 11 +#define LPC_DMAC_SSP1_TX_ID 11 +#define LPC_DMAC_NAND2_ID 12 +#define LPC_DMAC_I2S0_DMA1_ID 13 +#define LPC_DMAC_SSP0_RX 14 +#define LPC_DMAC_SSP0_TX 15 + +#endif /* _ARM_LPC_LPCREG_H */ diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/lpcvar.h armv6/sys/arm/lpc/lpcvar.h --- head/sys/arm/lpc/lpcvar.h 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/lpcvar.h 2012-08-08 12:43:50.909724541 -0700 @@ -0,0 +1,67 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARM_LPC_LPCVAR_H +#define _ARM_LPC_LPCVAR_H + +#include +#include +#include + +/* Clocking and power control */ +uint32_t lpc_pwr_read(device_t, int); +void lpc_pwr_write(device_t, int, uint32_t); + +/* GPIO */ +void platform_gpio_init(void); +int lpc_gpio_set_flags(device_t, int, int); +int lpc_gpio_set_state(device_t, int, int); +int lpc_gpio_get_state(device_t, int, int *); + +/* DMA */ +struct lpc_dmac_channel_config +{ + int ldc_fcntl; + int ldc_src_periph; + int ldc_src_width; + int ldc_src_incr; + int ldc_src_burst; + int ldc_dst_periph; + int ldc_dst_width; + int ldc_dst_incr; + int ldc_dst_burst; + void (*ldc_success_handler)(void *); + void (*ldc_error_handler)(void *); + void * ldc_handler_arg; +}; + +int lpc_dmac_config_channel(device_t, int, struct lpc_dmac_channel_config *); +int lpc_dmac_setup_transfer(device_t, int, bus_addr_t, bus_addr_t, bus_size_t, int); +int lpc_dmac_enable_channel(device_t, int); +int lpc_dmac_disable_channel(device_t, int); +int lpc_dmac_start_burst(device_t, int); + +#endif /* _ARM_LPC_LPCVAR_H */ diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/ssd1289.c armv6/sys/arm/lpc/ssd1289.c --- head/sys/arm/lpc/ssd1289.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/ssd1289.c 2012-08-08 12:43:50.902723905 -0700 @@ -0,0 +1,209 @@ +/*- + * Copyright (c) 2011 Jakub Wojciech Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include "spibus_if.h" + +struct ssd1289_softc +{ + device_t ss_dev; +}; + +static int ssd1289_probe(device_t); +static int ssd1289_attach(device_t); + +static __inline void ssd1289_set_dc(struct ssd1289_softc *, int); +static __inline void ssd1289_spi_send(struct ssd1289_softc *, uint8_t *, int); +static void ssd1289_write_reg(struct ssd1289_softc *, uint16_t, uint16_t); + +static struct ssd1289_softc *ssd1289_sc = NULL; + +void ssd1289_configure(void); + +static int +ssd1289_probe(device_t dev) +{ +#if 0 + if (!ofw_bus_is_compatible(dev, "ssd1289")) + return (ENXIO); +#endif + + device_set_desc(dev, "Solomon Systech SSD1289 LCD controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +ssd1289_attach(device_t dev) +{ + struct ssd1289_softc *sc = device_get_softc(dev); + + sc->ss_dev = dev; + ssd1289_sc = sc; + + return (0); +} + +void +ssd1289_configure(void) +{ + struct ssd1289_softc *sc = ssd1289_sc; + + /* XXX will be replaced with commented code */ + ssd1289_write_reg(sc,0x00,0x0001); + DELAY(20); + + ssd1289_write_reg(sc,0x03,0xA2A4); + ssd1289_write_reg(sc,0x0C,0x0004); + ssd1289_write_reg(sc,0x0D,0x0308); + ssd1289_write_reg(sc,0x0E,0x3000); + DELAY(50); + + ssd1289_write_reg(sc,0x1E,0x00AF); + ssd1289_write_reg(sc,0x01,0x2B3F); + ssd1289_write_reg(sc,0x02,0x0600); + ssd1289_write_reg(sc,0x10,0x0000); + ssd1289_write_reg(sc,0x07,0x0233); + ssd1289_write_reg(sc,0x0B,0x0039); + ssd1289_write_reg(sc,0x0F,0x0000); + DELAY(50); + + ssd1289_write_reg(sc,0x30,0x0707); + ssd1289_write_reg(sc,0x31,0x0204); + ssd1289_write_reg(sc,0x32,0x0204); + ssd1289_write_reg(sc,0x33,0x0502); + ssd1289_write_reg(sc,0x34,0x0507); + ssd1289_write_reg(sc,0x35,0x0204); + ssd1289_write_reg(sc,0x36,0x0204); + ssd1289_write_reg(sc,0x37,0x0502); + ssd1289_write_reg(sc,0x3A,0x0302); + ssd1289_write_reg(sc,0x3B,0x0302); + + ssd1289_write_reg(sc,0x23,0x0000); + ssd1289_write_reg(sc,0x24,0x0000); + + ssd1289_write_reg(sc,0x48,0x0000); + ssd1289_write_reg(sc,0x49,0x013F); + ssd1289_write_reg(sc,0x4A,0x0000); + ssd1289_write_reg(sc,0x4B,0x0000); + + ssd1289_write_reg(sc,0x41,0x0000); + ssd1289_write_reg(sc,0x42,0x0000); + + ssd1289_write_reg(sc,0x44,0xEF00); + ssd1289_write_reg(sc,0x45,0x0000); + ssd1289_write_reg(sc,0x46,0x013F); + DELAY(50); + + ssd1289_write_reg(sc,0x44,0xEF00); + ssd1289_write_reg(sc,0x45,0x0000); + ssd1289_write_reg(sc,0x4E,0x0000); + ssd1289_write_reg(sc,0x4F,0x0000); + ssd1289_write_reg(sc,0x46,0x013F); +} + +static __inline void +ssd1289_spi_send(struct ssd1289_softc *sc, uint8_t *data, int len) +{ + struct spi_command cmd; + uint8_t buffer[8]; + cmd.tx_cmd = data; + cmd.tx_cmd_sz = len; + cmd.rx_cmd = buffer; + cmd.rx_cmd_sz = len; + cmd.tx_data_sz = 0; + cmd.rx_data_sz = 0; + SPIBUS_TRANSFER(device_get_parent(sc->ss_dev), sc->ss_dev, &cmd); +} + +static __inline void +ssd1289_set_dc(struct ssd1289_softc *sc, int value) +{ + lpc_gpio_set_state(sc->ss_dev, SSD1289_DC_PIN, value); +} + +static void +ssd1289_write_reg(struct ssd1289_softc *sc, uint16_t addr, uint16_t value) +{ + uint8_t buffer[2]; + + ssd1289_set_dc(sc, 0); + buffer[0] = 0x00; + buffer[1] = addr & 0xff; + ssd1289_spi_send(sc, buffer, 2); + + ssd1289_set_dc(sc, 1); + buffer[0] = (value >> 8) & 0xff; + buffer[1] = value & 0xff; + ssd1289_spi_send(sc, buffer, 2); +} + +static device_method_t ssd1289_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, ssd1289_probe), + DEVMETHOD(device_attach, ssd1289_attach), + + { 0, 0 } +}; + +static devclass_t ssd1289_devclass; + +static driver_t ssd1289_driver = { + "ssd1289", + ssd1289_methods, + sizeof(struct ssd1289_softc), +}; + +DRIVER_MODULE(ssd1289, spibus, ssd1289_driver, ssd1289_devclass, 0, 0); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/arm/lpc/std.lpc armv6/sys/arm/lpc/std.lpc --- head/sys/arm/lpc/std.lpc 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/arm/lpc/std.lpc 2012-08-08 12:43:50.906723872 -0700 @@ -0,0 +1,14 @@ +# $FreeBSD$ +# +# DM644x +# + +files "../lpc/files.lpc" +cpu CPU_ARM9 +makeoptions CONF_CFLAGS="-march=armv5te" +options PHYSADDR=0x80000000 +options STARTUP_PAGETABLE_ADDR=0x80000000 +makeoptions KERNPHYSADDR=0x80100000 +options KERNPHYSADDR=0x80100000 +makeoptions KERNVIRTADDR=0xc0100000 +options KERNVIRTADDR=0xc0100000 diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/boot/fdt/dts/ea3250.dts armv6/sys/boot/fdt/dts/ea3250.dts --- head/sys/boot/fdt/dts/ea3250.dts 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/boot/fdt/dts/ea3250.dts 2012-08-08 12:44:04.345723896 -0700 @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2011 Jakub Klama + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Embedded Artists LPC3250-Kit Device Tree Source. + * + * $FreeBSD$ + */ + +/dts-v1/; + +/ { + model = "ea,LPC3250-KIT"; + compatible = "LPC3250-KIT"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + soc = &soc; + serial4 = &serial4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "ARM,926EJ-S"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x4000>; // L1, 16K + i-cache-size = <0x4000>; // L1, 16K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x4000000>; // 64M at 0x80000000 + }; + + soc: ahb7@40000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x40000000 0x10000000>; + bus-frequency = <13000000>; + + pwr@4000 { + compatible = "lpc,pwr"; + reg = <0x4000 0x4000>; + }; + + PIC: pic@8000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x8000 0xc000>; + compatible = "lpc,pic"; + }; + + timer@44000 { + compatible = "lpc,timer"; + reg = <0x44000 0x4000 + 0x4c000 0x4000>; + interrupts = <16 17>; + interrupt-parent = <&PIC>; + }; + + rtc@24000 { + compatible = "lpc,rtc"; + reg = <0x24000 0x4000>; + interrupts = <52>; + interrupt-parent = <&PIC>; + }; + + serial0: serial@14000 { + compatible = "lpc,hsuart"; + status = "disabled"; + reg = <0x14000 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <26>; + interrupt-parent = <&PIC>; + }; + + serial1: serial@18000 { + compatible = "lpc,hsuart"; + status = "disabled"; + reg = <0x18000 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <25>; + interrupt-parent = <&PIC>; + }; + + serial2: serial@80000 { + compatible = "lpc,uart"; + status = "disabled"; + reg = <0x80000 0x20>; + reg-shift = <2>; + clock-frequency = <13000000>; + interrupts = <7>; + interrupt-parent = <&PIC>; + }; + + serial3: serial@88000 { + compatible = "lpc,uart"; + status = "disabled"; + reg = <0x88000 0x20>; + reg-shift = <2>; + clock-frequency = <13000000>; + interrupts = <8>; + interrupt-parent = <&PIC>; + }; + + serial4: serial@90000 { + compatible = "lpc,uart"; + reg = <0x90000 0x20>; + reg-shift = <2>; + clock-frequency = <13000000>; + current-speed = <115200>; + interrupts = <9>; + interrupt-parent = <&PIC>; + }; + + serial5: serial@98000 { + compatible = "lpc,uart"; + status = "disabled"; + reg = <0x98000 0x20>; + reg-shift = <2>; + clock-frequency = <13000000>; + interrupts = <10>; + interrupt-parent = <&PIC>; + }; + + serial6: serial@1c000 { + compatible = "lpc,uart"; + status = "disabled"; + reg = <0x1c000 0x20>; + reg-shift = <2>; + clock-frequency = <0>; + interrupts = <24>; + interrupt-parent = <&PIC>; + }; + + gpio@28000 { + compatible = "lpc,gpio"; + reg = <0x28000 0x4000>; + }; + }; + + ahb6@30000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x30000000 0x10000000>; + + dmac@1000000 { + compatible = "lpc,dmac"; + reg = <0x1000000 0x20000>; + interrupts = <28>; + interrupt-parent = <&PIC>; + }; + + usb@1020000 { + compatible = "lpc,usb-ohci", "usb-ohci"; + reg = <0x1020000 0x20000>; + interrupts = <59>; + interrupt-parent = <&PIC>; + }; + + lpcfb@1040000 { + compatible = "lpc,fb"; + reg = <0x1040000 0x20000>; + interrupts = <14>; + interrupt-parent = <&PIC>; + + /* Screen parameters: */ + is-tft = <1>; + horizontal-resolution = <240>; + vertical-resolution = <320>; + bits-per-pixel = <16>; + pixel-clock = <121654>; + left-margin = <28>; + right-margin = <10>; + upper-margin = <2>; + lower-margin = <2>; + hsync-len = <3>; + vsync-len = <2>; + }; + + lpe@1060000 { + compatible = "lpc,ethernet"; + reg = <0x1060000 0x20000>; + interrupts = <29>; + interrupt-parent = <&PIC>; + local-mac-address = [ 00 1a f1 01 1f 23 ]; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lpc,mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + }; + }; + + }; + }; + + ahb5@20000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x0 0x20000000 0x10000000>; + + spi0@84000 { + compatible = "lpc,spi"; + reg = <0x84000 0x4000>; + interrupts = <20>; + interrupt-parent = <&PIC>; + }; + + spi1@8c000 { + compatible = "lpc,spi"; + status = "disabled"; + reg = <0x8c000 0x4000>; + interrupts = <21>; + interrupt-parent = <&PIC>; + }; + + lpcmmc@98000 { + compatible = "lpc,mmc"; + reg = <0x98000 0x4000>; + interrupts = <15 13>; + interrupt-parent = <&PIC>; + }; + }; + + chosen { + stdin = "serial4"; + stdout = "serial4"; + }; +}; diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/dev/uart/uart.h armv6/sys/dev/uart/uart.h --- head/sys/dev/uart/uart.h 2012-08-08 12:42:39.128724413 -0700 +++ armv6/sys/dev/uart/uart.h 2012-08-08 12:44:13.632723874 -0700 @@ -69,6 +69,7 @@ extern struct uart_class uart_sab82532_class __attribute__((weak)); extern struct uart_class uart_sbbc_class __attribute__((weak)); extern struct uart_class uart_z8530_class __attribute__((weak)); +extern struct uart_class uart_lpc_class __attribute__((weak)); #ifdef PC98 struct uart_class *uart_pc98_getdev(u_long port); diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/dev/uart/uart_bus_fdt.c armv6/sys/dev/uart/uart_bus_fdt.c --- head/sys/dev/uart/uart_bus_fdt.c 2012-08-08 12:42:39.130724584 -0700 +++ armv6/sys/dev/uart/uart_bus_fdt.c 2012-08-08 12:44:13.634723895 -0700 @@ -100,11 +100,13 @@ pcell_t clock, shift; int err; - if (!ofw_bus_is_compatible(dev, "ns16550")) - return (ENXIO); - sc = device_get_softc(dev); - sc->sc_class = &uart_ns8250_class; + if (ofw_bus_is_compatible(dev, "ns16550")) + sc->sc_class = &uart_ns8250_class; + else if (ofw_bus_is_compatible(dev, "lpc,uart")) + sc->sc_class = &uart_lpc_class; + else + return (ENXIO); node = ofw_bus_get_node(dev); @@ -137,7 +139,7 @@ struct uart_class *class; phandle_t node, chosen; pcell_t shift, br, rclk; - u_long start, size; + u_long start, size, pbase, psize; int err; uart_bus_space_mem = fdtbus_bs_tag; @@ -180,7 +182,10 @@ /* * Finalize configuration. */ - class = &uart_quicc_class; + if (fdt_is_compatible(node, "quicc")) + class = &uart_quicc_class; + if (fdt_is_compatible(node, "lpc")) + class = &uart_lpc_class; if (fdt_is_compatible(node, "ns16550")) class = &uart_ns8250_class; @@ -197,7 +202,9 @@ err = fdt_regsize(node, &start, &size); if (err) return (ENXIO); - start += fdt_immr_va; + + fdt_get_range(OF_parent(node), 0, &pbase, &psize); + start += pbase; return (bus_space_map(di->bas.bst, start, size, 0, &di->bas.bsh)); } diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/dev/uart/uart_dev_lpc.c armv6/sys/dev/uart/uart_dev_lpc.c --- head/sys/dev/uart/uart_dev_lpc.c 1969-12-31 16:00:00.000000000 -0800 +++ armv6/sys/dev/uart/uart_dev_lpc.c 2012-08-08 12:44:13.628723908 -0700 @@ -0,0 +1,891 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: projects/armv6/sys/dev/uart/uart_dev_lpc_ns8250.c 228136 2011-11-29 15:24:19Z cognet $"); + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "uart_if.h" + +#define DEFAULT_RCLK (13 * 1000 * 1000) +#define LPC_UART_NO(_bas) (((_bas->bsh) - LPC_UART_BASE) >> 15) + +#define lpc_ns8250_get_auxreg(_bas, _reg) \ + bus_space_read_4((_bas)->bst, LPC_UART_CONTROL_BASE, _reg) +#define lpc_ns8250_set_auxreg(_bas, _reg, _val) \ + bus_space_write_4((_bas)->bst, LPC_UART_CONTROL_BASE, _reg, _val); +#define lpc_ns8250_get_clkreg(_bas, _reg) \ + bus_space_read_4((_bas)->bst, LPC_CLKPWR_BASE, (_reg)) +#define lpc_ns8250_set_clkreg(_bas, _reg, _val) \ + bus_space_write_4((_bas)->bst, LPC_CLKPWR_BASE, (_reg), (_val)) + +/* + * Clear pending interrupts. THRE is cleared by reading IIR. Data + * that may have been received gets lost here. + */ +static void +lpc_ns8250_clrint(struct uart_bas *bas) +{ + uint8_t iir, lsr; + + iir = uart_getreg(bas, REG_IIR); + while ((iir & IIR_NOPEND) == 0) { + iir &= IIR_IMASK; + if (iir == IIR_RLS) { + lsr = uart_getreg(bas, REG_LSR); + if (lsr & (LSR_BI|LSR_FE|LSR_PE)) + (void)uart_getreg(bas, REG_DATA); + } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) + (void)uart_getreg(bas, REG_DATA); + else if (iir == IIR_MLSC) + (void)uart_getreg(bas, REG_MSR); + uart_barrier(bas); + iir = uart_getreg(bas, REG_IIR); + } +} + +static int +lpc_ns8250_delay(struct uart_bas *bas) +{ + uint32_t uclk; + int x, y; + + uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK); + + x = (uclk >> 8) & 0xff; + y = uclk & 0xff; + + return (16000000 / (bas->rclk * x / y)); +} + +static void +lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y) +{ + + switch (baudrate) { + case 2400: + *x = 1; + *y = 255; + return; + case 4800: + *x = 1; + *y = 169; + return; + case 9600: + *x = 3; + *y = 254; + return; + case 19200: + *x = 3; + *y = 127; + return; + case 38400: + *x = 6; + *y = 127; + return; + case 57600: + *x = 9; + *y = 127; + return; + default: + case 115200: + *x = 19; + *y = 134; + return; + case 230400: + *x = 19; + *y = 67; + return; + case 460800: + *x = 38; + *y = 67; + return; + } +} + +static int +lpc_ns8250_drain(struct uart_bas *bas, int what) +{ + int delay, limit; + + delay = lpc_ns8250_delay(bas); + + if (what & UART_DRAIN_TRANSMITTER) { + /* + * Pick an arbitrary high limit to avoid getting stuck in + * an infinite loop when the hardware is broken. Make the + * limit high enough to handle large FIFOs. + */ + limit = 10*1024; + while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) + DELAY(delay); + if (limit == 0) { + /* printf("lpc_ns8250: transmitter appears stuck... "); */ + return (EIO); + } + } + + if (what & UART_DRAIN_RECEIVER) { + /* + * Pick an arbitrary high limit to avoid getting stuck in + * an infinite loop when the hardware is broken. Make the + * limit high enough to handle large FIFOs and integrated + * UARTs. The HP rx2600 for example has 3 UARTs on the + * management board that tend to get a lot of data send + * to it when the UART is first activated. + */ + limit=10*4096; + while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { + (void)uart_getreg(bas, REG_DATA); + uart_barrier(bas); + DELAY(delay << 2); + } + if (limit == 0) { + /* printf("lpc_ns8250: receiver appears broken... "); */ + return (EIO); + } + } + + return (0); +} + +/* + * We can only flush UARTs with FIFOs. UARTs without FIFOs should be + * drained. WARNING: this function clobbers the FIFO setting! + */ +static void +lpc_ns8250_flush(struct uart_bas *bas, int what) +{ + uint8_t fcr; + + fcr = FCR_ENABLE; + if (what & UART_FLUSH_TRANSMITTER) + fcr |= FCR_XMT_RST; + if (what & UART_FLUSH_RECEIVER) + fcr |= FCR_RCV_RST; + uart_setreg(bas, REG_FCR, fcr); + uart_barrier(bas); +} + +static int +lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, + int parity) +{ + int xdiv, ydiv; + uint8_t lcr; + + lcr = 0; + if (databits >= 8) + lcr |= LCR_8BITS; + else if (databits == 7) + lcr |= LCR_7BITS; + else if (databits == 6) + lcr |= LCR_6BITS; + else + lcr |= LCR_5BITS; + if (stopbits > 1) + lcr |= LCR_STOPB; + lcr |= parity << 3; + + /* Set baudrate. */ + if (baudrate > 0) { + uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); + uart_barrier(bas); + uart_setreg(bas, REG_DLL, 0x00); + uart_setreg(bas, REG_DLH, 0x00); + uart_barrier(bas); + + lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv); + lpc_ns8250_set_clkreg(bas, + LPC_CLKPWR_UART_U5CLK, + LPC_CLKPWR_UART_UCLK_X(xdiv) | + LPC_CLKPWR_UART_UCLK_Y(ydiv)); + } + + /* Set LCR and clear DLAB. */ + uart_setreg(bas, REG_LCR, lcr); + uart_barrier(bas); + return (0); +} + +/* + * Low-level UART interface. + */ +static int lpc_ns8250_probe(struct uart_bas *bas); +static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int); +static void lpc_ns8250_term(struct uart_bas *bas); +static void lpc_ns8250_putc(struct uart_bas *bas, int); +static int lpc_ns8250_rxready(struct uart_bas *bas); +static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *); + +static struct uart_ops uart_lpc_ns8250_ops = { + .probe = lpc_ns8250_probe, + .init = lpc_ns8250_init, + .term = lpc_ns8250_term, + .putc = lpc_ns8250_putc, + .rxready = lpc_ns8250_rxready, + .getc = lpc_ns8250_getc, +}; + +static int +lpc_ns8250_probe(struct uart_bas *bas) +{ +#if 0 + u_char val; + + /* Check known 0 bits that don't depend on DLAB. */ + val = uart_getreg(bas, REG_IIR); + if (val & 0x30) + return (ENXIO); + /* + * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 + * chip, but otherwise doesn't seem to have a function. In + * other words, uart(4) works regardless. Ignore that bit so + * the probe succeeds. + */ + val = uart_getreg(bas, REG_MCR); + if (val & 0xa0) + return (ENXIO); +#endif + return (0); +} + +static void +lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, + int parity) +{ + u_char ier; + u_long clkmode; + + /* Enable UART clock */ + clkmode = lpc_ns8250_get_auxreg(bas, LPC_UART_CLKMODE); + lpc_ns8250_set_auxreg(bas, LPC_UART_CLKMODE, + clkmode | LPC_UART_CLKMODE_UART5(1)); +#if 0 + /* Work around H/W bug */ + uart_setreg(bas, REG_DATA, 0x00); +#endif + if (bas->rclk == 0) + bas->rclk = DEFAULT_RCLK; + lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); + + /* Disable all interrupt sources. */ + /* + * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA + * UARTs split the receive time-out interrupt bit out separately as + * 0x10. This gets handled by ier_mask and ier_rxbits below. + */ + ier = uart_getreg(bas, REG_IER) & 0xe0; + uart_setreg(bas, REG_IER, ier); + uart_barrier(bas); + + /* Disable the FIFO (if present). */ + uart_setreg(bas, REG_FCR, 0); + uart_barrier(bas); + + /* Set RTS & DTR. */ + uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); + uart_barrier(bas); + + lpc_ns8250_clrint(bas); +} + +static void +lpc_ns8250_term(struct uart_bas *bas) +{ + + /* Clear RTS & DTR. */ + uart_setreg(bas, REG_MCR, MCR_IE); + uart_barrier(bas); +} + +static void +lpc_ns8250_putc(struct uart_bas *bas, int c) +{ + int limit; + + limit = 250000; + while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) + DELAY(4); + uart_setreg(bas, REG_DATA, c); + uart_barrier(bas); + limit = 250000; + while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) + DELAY(4); +} + +static int +lpc_ns8250_rxready(struct uart_bas *bas) +{ + + return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); +} + +static int +lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) +{ + int c; + + uart_lock(hwmtx); + + while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { + uart_unlock(hwmtx); + DELAY(4); + uart_lock(hwmtx); + } + + c = uart_getreg(bas, REG_DATA); + + uart_unlock(hwmtx); + + return (c); +} + +/* + * High-level UART interface. + */ +struct lpc_ns8250_softc { + struct uart_softc base; + uint8_t fcr; + uint8_t ier; + uint8_t mcr; + + uint8_t ier_mask; + uint8_t ier_rxbits; +}; + +static int lpc_ns8250_bus_attach(struct uart_softc *); +static int lpc_ns8250_bus_detach(struct uart_softc *); +static int lpc_ns8250_bus_flush(struct uart_softc *, int); +static int lpc_ns8250_bus_getsig(struct uart_softc *); +static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); +static int lpc_ns8250_bus_ipend(struct uart_softc *); +static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int); +static int lpc_ns8250_bus_probe(struct uart_softc *); +static int lpc_ns8250_bus_receive(struct uart_softc *); +static int lpc_ns8250_bus_setsig(struct uart_softc *, int); +static int lpc_ns8250_bus_transmit(struct uart_softc *); + +static kobj_method_t lpc_ns8250_methods[] = { + KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach), + KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach), + KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush), + KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig), + KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl), + KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend), + KOBJMETHOD(uart_param, lpc_ns8250_bus_param), + KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe), + KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive), + KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig), + KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit), + { 0, 0 } +}; + +struct uart_class uart_lpc_class = { + "lpc_ns8250", + lpc_ns8250_methods, + sizeof(struct lpc_ns8250_softc), + .uc_ops = &uart_lpc_ns8250_ops, + .uc_range = 8, + .uc_rclk = DEFAULT_RCLK +}; + +#define SIGCHG(c, i, s, d) \ + if (c) { \ + i |= (i & s) ? s : s | d; \ + } else { \ + i = (i & s) ? (i & ~s) | d : i; \ + } + +static int +lpc_ns8250_bus_attach(struct uart_softc *sc) +{ + struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; + struct uart_bas *bas; + unsigned int ivar; + + bas = &sc->sc_bas; + + lpc_ns8250->mcr = uart_getreg(bas, REG_MCR); + lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA; + if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", + &ivar)) { + if (UART_FLAGS_FCR_RX_LOW(ivar)) + lpc_ns8250->fcr |= FCR_RX_LOW; + else if (UART_FLAGS_FCR_RX_MEDL(ivar)) + lpc_ns8250->fcr |= FCR_RX_MEDL; + else if (UART_FLAGS_FCR_RX_HIGH(ivar)) + lpc_ns8250->fcr |= FCR_RX_HIGH; + else + lpc_ns8250->fcr |= FCR_RX_MEDH; + } else + lpc_ns8250->fcr |= FCR_RX_HIGH; + + /* Get IER mask */ + ivar = 0xf0; + resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", + &ivar); + lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff); + + /* Get IER RX interrupt bits */ + ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; + resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", + &ivar); + lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); + + uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); + uart_barrier(bas); + lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); + + if (lpc_ns8250->mcr & MCR_DTR) + sc->sc_hwsig |= SER_DTR; + if (lpc_ns8250->mcr & MCR_RTS) + sc->sc_hwsig |= SER_RTS; + lpc_ns8250_bus_getsig(sc); + + lpc_ns8250_clrint(bas); + lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; + lpc_ns8250->ier |= lpc_ns8250->ier_rxbits; + uart_setreg(bas, REG_IER, lpc_ns8250->ier); + uart_barrier(bas); + + return (0); +} + +static int +lpc_ns8250_bus_detach(struct uart_softc *sc) +{ + struct lpc_ns8250_softc *lpc_ns8250; + struct uart_bas *bas; + u_char ier; + + lpc_ns8250 = (struct lpc_ns8250_softc *)sc; + bas = &sc->sc_bas; + ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; + uart_setreg(bas, REG_IER, ier); + uart_barrier(bas); + lpc_ns8250_clrint(bas); + return (0); +} + +static int +lpc_ns8250_bus_flush(struct uart_softc *sc, int what) +{ + struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; + struct uart_bas *bas; + int error; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + if (sc->sc_rxfifosz > 1) { + lpc_ns8250_flush(bas, what); + uart_setreg(bas, REG_FCR, lpc_ns8250->fcr); + uart_barrier(bas); + error = 0; + } else + error = lpc_ns8250_drain(bas, what); + uart_unlock(sc->sc_hwmtx); + return (error); +} + +static int +lpc_ns8250_bus_getsig(struct uart_softc *sc) +{ + uint32_t new, old, sig; + uint8_t msr; + + do { + old = sc->sc_hwsig; + sig = old; + uart_lock(sc->sc_hwmtx); + msr = uart_getreg(&sc->sc_bas, REG_MSR); + uart_unlock(sc->sc_hwmtx); + SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); + SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); + SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); + SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); + new = sig & ~SER_MASK_DELTA; + } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); + return (sig); +} + +static int +lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) +{ + struct uart_bas *bas; + int baudrate, divisor, error; + uint8_t efr, lcr; + + bas = &sc->sc_bas; + error = 0; + uart_lock(sc->sc_hwmtx); + switch (request) { + case UART_IOCTL_BREAK: + lcr = uart_getreg(bas, REG_LCR); + if (data) + lcr |= LCR_SBREAK; + else + lcr &= ~LCR_SBREAK; + uart_setreg(bas, REG_LCR, lcr); + uart_barrier(bas); + break; + case UART_IOCTL_IFLOW: + lcr = uart_getreg(bas, REG_LCR); + uart_barrier(bas); + uart_setreg(bas, REG_LCR, 0xbf); + uart_barrier(bas); + efr = uart_getreg(bas, REG_EFR); + if (data) + efr |= EFR_RTS; + else + efr &= ~EFR_RTS; + uart_setreg(bas, REG_EFR, efr); + uart_barrier(bas); + uart_setreg(bas, REG_LCR, lcr); + uart_barrier(bas); + break; + case UART_IOCTL_OFLOW: + lcr = uart_getreg(bas, REG_LCR); + uart_barrier(bas); + uart_setreg(bas, REG_LCR, 0xbf); + uart_barrier(bas); + efr = uart_getreg(bas, REG_EFR); + if (data) + efr |= EFR_CTS; + else + efr &= ~EFR_CTS; + uart_setreg(bas, REG_EFR, efr); + uart_barrier(bas); + uart_setreg(bas, REG_LCR, lcr); + uart_barrier(bas); + break; + case UART_IOCTL_BAUD: + lcr = uart_getreg(bas, REG_LCR); + uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); + uart_barrier(bas); + divisor = uart_getreg(bas, REG_DLL) | + (uart_getreg(bas, REG_DLH) << 8); + uart_barrier(bas); + uart_setreg(bas, REG_LCR, lcr); + uart_barrier(bas); + baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; + if (baudrate > 0) + *(int*)data = baudrate; + else + error = ENXIO; + break; + default: + error = EINVAL; + break; + } + uart_unlock(sc->sc_hwmtx); + return (error); +} + +static int +lpc_ns8250_bus_ipend(struct uart_softc *sc) +{ + struct uart_bas *bas; + struct lpc_ns8250_softc *lpc_ns8250; + int ipend; + uint8_t iir, lsr; + + lpc_ns8250 = (struct lpc_ns8250_softc *)sc; + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + iir = uart_getreg(bas, REG_IIR); + if (iir & IIR_NOPEND) { + uart_unlock(sc->sc_hwmtx); + return (0); + } + ipend = 0; + if (iir & IIR_RXRDY) { + lsr = uart_getreg(bas, REG_LSR); + if (lsr & LSR_OE) + ipend |= SER_INT_OVERRUN; + if (lsr & LSR_BI) + ipend |= SER_INT_BREAK; + if (lsr & LSR_RXRDY) + ipend |= SER_INT_RXREADY; + } else { + if (iir & IIR_TXRDY) { + ipend |= SER_INT_TXIDLE; + uart_setreg(bas, REG_IER, lpc_ns8250->ier); + } else + ipend |= SER_INT_SIGCHG; + } + if (ipend == 0) + lpc_ns8250_clrint(bas); + uart_unlock(sc->sc_hwmtx); + return (ipend); +} + +static int +lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, + int stopbits, int parity) +{ + struct uart_bas *bas; + int error; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity); + uart_unlock(sc->sc_hwmtx); + return (error); +} + +static int +lpc_ns8250_bus_probe(struct uart_softc *sc) +{ + struct lpc_ns8250_softc *lpc_ns8250; + struct uart_bas *bas; + int count, delay, error, limit; + uint8_t lsr, mcr, ier; + + lpc_ns8250 = (struct lpc_ns8250_softc *)sc; + bas = &sc->sc_bas; + + error = lpc_ns8250_probe(bas); + if (error) + return (error); + + mcr = MCR_IE; + if (sc->sc_sysdev == NULL) { + /* By using lpc_ns8250_init() we also set DTR and RTS. */ + lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); + } else + mcr |= MCR_DTR | MCR_RTS; + + error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER); + if (error) + return (error); + + /* + * Set loopback mode. This avoids having garbage on the wire and + * also allows us send and receive data. We set DTR and RTS to + * avoid the possibility that automatic flow-control prevents + * any data from being sent. + */ + uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); + uart_barrier(bas); + + /* + * Enable FIFOs. And check that the UART has them. If not, we're + * done. Since this is the first time we enable the FIFOs, we reset + * them. + */ + uart_setreg(bas, REG_FCR, FCR_ENABLE); + uart_barrier(bas); + if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { + /* + * NS16450 or INS8250. We don't bother to differentiate + * between them. They're too old to be interesting. + */ + uart_setreg(bas, REG_MCR, mcr); + uart_barrier(bas); + sc->sc_rxfifosz = sc->sc_txfifosz = 1; + device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); + return (0); + } + + uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); + uart_barrier(bas); + + count = 0; + delay = lpc_ns8250_delay(bas); + + /* We have FIFOs. Drain the transmitter and receiver. */ + error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); + if (error) { + uart_setreg(bas, REG_MCR, mcr); + uart_setreg(bas, REG_FCR, 0); + uart_barrier(bas); + goto done; + } + + /* + * We should have a sufficiently clean "pipe" to determine the + * size of the FIFOs. We send as much characters as is reasonable + * and wait for the overflow bit in the LSR register to be + * asserted, counting the characters as we send them. Based on + * that count we know the FIFO size. + */ + do { + uart_setreg(bas, REG_DATA, 0); + uart_barrier(bas); + count++; + + limit = 30; + lsr = 0; + /* + * LSR bits are cleared upon read, so we must accumulate + * them to be able to test LSR_OE below. + */ + while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && + --limit) + DELAY(delay); + if (limit == 0) { + ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask; + uart_setreg(bas, REG_IER, ier); + uart_setreg(bas, REG_MCR, mcr); + uart_setreg(bas, REG_FCR, 0); + uart_barrier(bas); + count = 0; + goto done; + } + } while ((lsr & LSR_OE) == 0 && count < 130); + count--; + + uart_setreg(bas, REG_MCR, mcr); + + /* Reset FIFOs. */ + lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); + +done: + sc->sc_rxfifosz = 64; + device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs"); + + /* + * Force the Tx FIFO size to 16 bytes for now. We don't program the + * Tx trigger. Also, we assume that all data has been sent when the + * interrupt happens. + */ + sc->sc_txfifosz = 16; + +#if 0 + /* + * XXX there are some issues related to hardware flow control and + * it's likely that uart(4) is the cause. This basicly needs more + * investigation, but we avoid using for hardware flow control + * until then. + */ + /* 16650s or higher have automatic flow control. */ + if (sc->sc_rxfifosz > 16) { + sc->sc_hwiflow = 1; + sc->sc_hwoflow = 1; + } +#endif + return (0); +} + +static int +lpc_ns8250_bus_receive(struct uart_softc *sc) +{ + struct uart_bas *bas; + int xc; + uint8_t lsr; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + lsr = uart_getreg(bas, REG_LSR); + while (lsr & LSR_RXRDY) { + if (uart_rx_full(sc)) { + sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; + break; + } + xc = uart_getreg(bas, REG_DATA); + if (lsr & LSR_FE) + xc |= UART_STAT_FRAMERR; + if (lsr & LSR_PE) + xc |= UART_STAT_PARERR; + uart_rx_put(sc, xc); + lsr = uart_getreg(bas, REG_LSR); + } + /* Discard everything left in the Rx FIFO. */ + while (lsr & LSR_RXRDY) { + (void)uart_getreg(bas, REG_DATA); + uart_barrier(bas); + lsr = uart_getreg(bas, REG_LSR); + } + uart_unlock(sc->sc_hwmtx); + return (0); +} + +static int +lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig) +{ + struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; + struct uart_bas *bas; + uint32_t new, old; + + bas = &sc->sc_bas; + do { + old = sc->sc_hwsig; + new = old; + if (sig & SER_DDTR) { + SIGCHG(sig & SER_DTR, new, SER_DTR, + SER_DDTR); + } + if (sig & SER_DRTS) { + SIGCHG(sig & SER_RTS, new, SER_RTS, + SER_DRTS); + } + } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); + uart_lock(sc->sc_hwmtx); + lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS); + if (new & SER_DTR) + lpc_ns8250->mcr |= MCR_DTR; + if (new & SER_RTS) + lpc_ns8250->mcr |= MCR_RTS; + uart_setreg(bas, REG_MCR, lpc_ns8250->mcr); + uart_barrier(bas); + uart_unlock(sc->sc_hwmtx); + return (0); +} + +static int +lpc_ns8250_bus_transmit(struct uart_softc *sc) +{ + struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc; + struct uart_bas *bas; + int i; + + bas = &sc->sc_bas; + uart_lock(sc->sc_hwmtx); + while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) + ; + uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY); + uart_barrier(bas); + for (i = 0; i < sc->sc_txdatasz; i++) { + uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); + uart_barrier(bas); + } + sc->sc_txbusy = 1; + uart_unlock(sc->sc_hwmtx); + return (0); +} diff -x .svn -I '$FreeBSD.*$' -Naur head/sys/dev/uart/uart_subr.c armv6/sys/dev/uart/uart_subr.c --- head/sys/dev/uart/uart_subr.c 2012-08-08 12:42:39.124724221 -0700 +++ armv6/sys/dev/uart/uart_subr.c 2012-08-08 12:44:13.627724160 -0700 @@ -52,6 +52,7 @@ &uart_ns8250_class, &uart_sab82532_class, &uart_z8530_class, + &uart_lpc_class, }; static size_t uart_nclasses = sizeof(uart_classes) / sizeof(uart_classes[0]);