Index: arm/conf/RPI-B =================================================================== --- arm/conf/RPI-B (revision 240001) +++ arm/conf/RPI-B (working copy) @@ -95,6 +95,11 @@ # device smc # device smcphy +device sdhci +device mmc +device mmcsd +options ROOTDEVNAME=\"ufs:/dev/mmcsd0s2\" + # Flattened Device Tree options FDT options FDT_DTB_STATIC Index: arm/broadcom/bcm2835/files.bcm2835 =================================================================== --- arm/broadcom/bcm2835/files.bcm2835 (revision 240001) +++ arm/broadcom/bcm2835/files.bcm2835 (working copy) @@ -7,6 +7,7 @@ arm/broadcom/bcm2835/bcm2835_systimer.c standard arm/broadcom/bcm2835/bcm2835_wdog.c standard arm/broadcom/bcm2835/bus_space.c optional fdt +arm/broadcom/bcm2835/sdhci_brcm.c optional sdhci arm/broadcom/bcm2835/common.c optional fdt arm/arm/bus_space_generic.c standard Index: arm/broadcom/bcm2835/sdhci_brcm.c =================================================================== --- arm/broadcom/bcm2835/sdhci_brcm.c (revision 0) +++ arm/broadcom/bcm2835/sdhci_brcm.c (working copy) @@ -0,0 +1,391 @@ +/*- + * Copyright (c) 2012 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include "sdhci_if.h" + +#define DEBUG + +#ifdef DEBUG +#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ + printf(fmt,##args); } while (0) +#else +#define dprintf(fmt, args...) +#endif + +struct bcm_sdhci_dmamap_arg { + bus_addr_t sc_dma_busaddr; +}; + +struct bcm_sdhci_softc { + device_t sc_dev; + struct mtx sc_mtx; + struct resource * sc_mem_res; + struct resource * sc_irq_res; + bus_space_tag_t sc_bst; + bus_space_handle_t sc_bsh; + void * sc_intrhand; + struct mmc_request * sc_req; + struct mmc_data * sc_data; + uint32_t sc_flags; +#define LPC_SD_FLAGS_IGNORECRC (1 << 0) + int sc_xfer_direction; +#define DIRECTION_READ 0 +#define DIRECTION_WRITE 1 + int sc_xfer_done; + int sc_bus_busy; + bus_dma_tag_t sc_dma_tag; + bus_dmamap_t sc_dma_map; + bus_addr_t sc_buffer_phys; + void * sc_buffer; + struct sdhci_slot sc_slot; +}; + +#define SD_MAX_BLOCKSIZE 1024 +/* XXX */ + +static int bcm_sdhci_probe(device_t); +static int bcm_sdhci_attach(device_t); +static int bcm_sdhci_detach(device_t); +static void bcm_sdhci_intr(void *); + +static int bcm_sdhci_get_ro(device_t, device_t); + +static void bcm_sdhci_dmamap_cb(void *, bus_dma_segment_t *, int, int); + +#define bcm_sdhci_lock(_sc) \ + mtx_lock(&_sc->sc_mtx); +#define bcm_sdhci_unlock(_sc) \ + mtx_unlock(&_sc->sc_mtx); + +static int +bcm_sdhci_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) + return (ENXIO); + + device_set_desc(dev, "Broadcom 2708 SDHCI controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +bcm_sdhci_attach(device_t dev) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + struct bcm_sdhci_dmamap_arg ctx; + int rid, err; + + sc->sc_dev = dev; + sc->sc_req = NULL; + + mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); + + rid = 0; + sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->sc_mem_res) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + + sc->sc_bst = rman_get_bustag(sc->sc_mem_res); + sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); + + rid = 0; + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (!sc->sc_irq_res) { + device_printf(dev, "cannot allocate interrupt\n"); + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + return (ENXIO); + } + + if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) + { + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + +#if 0 + sc->sc_host.f_min = 312500; + sc->sc_host.f_max = 2500000; + sc->sc_host.host_ocr = MMC_OCR_300_310 | MMC_OCR_310_320 | + MMC_OCR_320_330 | MMC_OCR_330_340; + sc->sc_host.caps = MMC_CAP_4_BIT_DATA; +#endif + + /* Alloc DMA memory */ + err = bus_dma_tag_create( + bus_get_dma_tag(sc->sc_dev), + 4, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + SD_MAX_BLOCKSIZE, 1, /* maxsize, nsegments */ + SD_MAX_BLOCKSIZE, 0, /* maxsegsize, flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dma_tag); + + err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_buffer, + 0, &sc->sc_dma_map); + if (err) { + device_printf(dev, "cannot allocate DMA memory\n"); + goto fail; + } + + err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_buffer, + SD_MAX_BLOCKSIZE, bcm_sdhci_dmamap_cb, &ctx, BUS_DMA_NOWAIT); + if (err) { + device_printf(dev, "cannot load DMA map\n"); + goto fail; + } + + sc->sc_buffer_phys = ctx.sc_dma_busaddr; + + /* TODO: allocate DMA here */ + sdhci_init_slot(dev, &sc->sc_slot); + sc->sc_slot.mem_res = sc->sc_mem_res; + + bus_generic_probe(dev); + bus_generic_attach(dev); + + return (0); + +fail: + if (sc->sc_intrhand) + bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); + if (sc->sc_irq_res) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); + if (sc->sc_mem_res) + bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); + return (err); +} + +static int +bcm_sdhci_detach(device_t dev) +{ + + return (EBUSY); +} + +static void +bcm_sdhci_intr(void *arg) +{ + struct bcm_sdhci_softc *sc = arg; + + sdhci_generic_intr(&sc->sc_slot); +} + +static int +bcm_sdhci_get_ro(device_t bus, device_t child) +{ + + return (0); +} + +static void +bcm_sdhci_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) +{ + struct bcm_sdhci_dmamap_arg *ctx; + + if (err) + return; + + ctx = (struct bcm_sdhci_dmamap_arg *)arg; + ctx->sc_dma_busaddr = segs[0].ds_addr; +} + +static inline uint32_t +RD4(struct bcm_sdhci_softc *sc, bus_size_t off) +{ + uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); + // printf("RD4 [%02x] == %08x\n", (unsigned int)off, val); + return val; +} + +static inline void +WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) +{ + // printf("WR4 [%02x] := %08x\n", (unsigned int)off, val); + bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); + + if ((off != SDHCI_BUFFER && off != SDHCI_INT_STATUS && off != SDHCI_CLOCK_CONTROL)) + { + int timeout = 100000; + while (val != bus_space_read_4(sc->sc_bst, sc->sc_bsh, off) + && --timeout > 0) + continue; + + if (timeout <= 0) + printf("sdhci_brcm: writing 0x%X to reg 0x%X " + "always gives 0x%X\n", + val, (uint32_t)off, + bus_space_read_4(sc->sc_bst, sc->sc_bsh, off)); + } +} + +static uint8_t +bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + uint32_t val = RD4(sc, off & ~3); + + return ((val >> (off & 3)*8) & 0xff); +} + +static uint16_t +bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + uint32_t val = RD4(sc, off & ~3); + + return ((val >> (off & 3)*8) & 0xffff); +} + +static uint32_t +bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + + return RD4(sc, off); +} + +static void +bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + uint32_t val32 = RD4(sc, off & ~3); + val32 &= ~(0xff << (off & 3)*8); + val32 |= (val << (off & 3)*8); + WR4(sc, off & ~3, val32); +} + +static void +bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + static uint32_t cmd_and_trandfer_mode; + uint32_t val32; + if (off == SDHCI_COMMAND_FLAGS) + val32 = cmd_and_trandfer_mode; + else + val32 = RD4(sc, off & ~3); + val32 &= ~(0xffff << (off & 3)*8); + val32 |= (val << (off & 3)*8); + if (off == SDHCI_TRANSFER_MODE) + cmd_and_trandfer_mode = val32; + else + WR4(sc, off & ~3, val32); +} + +static void +bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) +{ + struct bcm_sdhci_softc *sc = device_get_softc(dev); + WR4(sc, off, val); +} + +static device_method_t bcm_sdhci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bcm_sdhci_probe), + DEVMETHOD(device_attach, bcm_sdhci_attach), + DEVMETHOD(device_detach, bcm_sdhci_detach), + + /* Bus interface */ + DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), + DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), + DEVMETHOD(bus_print_child, bus_generic_print_child), + + /* MMC bridge interface */ + DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), + DEVMETHOD(mmcbr_request, sdhci_generic_request), + DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), + DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), + DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), + + + /* SDHCI registers accessors */ + DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), + DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), + DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), + DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), + DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), + DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), + + { 0, 0 } +}; + +static devclass_t bcm_sdhci_devclass; + +static driver_t bcm_sdhci_driver = { + "sdhci", + bcm_sdhci_methods, + sizeof(struct bcm_sdhci_softc), +}; + +DRIVER_MODULE(sdhci, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); Property changes on: arm/broadcom/bcm2835/sdhci_brcm.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: conf/files =================================================================== --- conf/files (revision 240001) +++ conf/files (working copy) @@ -1893,7 +1893,9 @@ dev/scc/scc_dev_z8530.c optional scc dev/scd/scd.c optional scd isa dev/scd/scd_isa.c optional scd isa -dev/sdhci/sdhci.c optional sdhci pci +dev/sdhci/sdhci_if.m optional sdhci +dev/sdhci/sdhci.c optional sdhci +dev/sdhci/sdhci_pci.c optional sdhci pci dev/sf/if_sf.c optional sf pci dev/sge/if_sge.c optional sge pci dev/si/si.c optional si @@ -2071,6 +2073,7 @@ dev/uart/uart_dev_sab82532.c optional uart scc dev/uart/uart_dev_z8530.c optional uart uart_z8530 dev/uart/uart_dev_z8530.c optional uart scc +dev/uart/uart_dev_pl011.c optional uart pl011 dev/uart/uart_if.m optional uart dev/uart/uart_subr.c optional uart dev/uart/uart_tty.c optional uart @@ -2080,6 +2083,7 @@ # dev/usb/controller/at91dci.c optional at91dci dev/usb/controller/at91dci_atmelarm.c optional at91dci at91rm9200 +dev/usb/controller/dwc_otg.c optional dwc_otg dev/usb/controller/musb_otg.c optional musb dev/usb/controller/musb_otg_atmelarm.c optional musb at91rm9200 dev/usb/controller/ehci.c optional ehci Index: dev/mmc/mmc.c =================================================================== --- dev/mmc/mmc.c (revision 240001) +++ dev/mmc/mmc.c (working copy) @@ -180,8 +180,10 @@ static int mmc_send_status(struct mmc_softc *sc, uint16_t rca, uint32_t *status); static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len); +#ifdef NOT_YET_FOR_RPI static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width); +#endif static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp); static int mmc_set_timing(struct mmc_softc *sc, int timing); static int mmc_switch(struct mmc_softc *sc, uint8_t set, uint8_t index, @@ -301,9 +303,11 @@ (ivar->bus_width == bus_width_4) ? 4 : (ivar->bus_width == bus_width_8) ? 8 : 1); } +#ifdef NOT_YET_FOR_RPI mmc_set_card_bus_width(sc, rca, ivar->bus_width); mmcbr_set_bus_width(busdev, ivar->bus_width); mmcbr_update_ios(busdev); +#endif } } else { /* @@ -653,6 +657,7 @@ return (err); } +#ifdef NOT_YET_FOR_RPI static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width) { @@ -701,6 +706,7 @@ } return (err); } +#endif static int mmc_set_timing(struct mmc_softc *sc, int timing) Index: dev/sdhci/sdhci.h =================================================================== --- dev/sdhci/sdhci.h (revision 240001) +++ dev/sdhci/sdhci.h (working copy) @@ -25,26 +25,31 @@ * $FreeBSD$ */ -/* - * PCI registers - */ +#define DMA_BLOCK_SIZE 4096 +#define DMA_BOUNDARY 0 /* DMA reload every 4K */ -#define PCI_SDHCI_IFPIO 0x00 -#define PCI_SDHCI_IFDMA 0x01 -#define PCI_SDHCI_IFVENDOR 0x02 +/* Controller doesn't honor resets unless we touch the clock register */ +#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) +/* Controller really supports DMA */ +#define SDHCI_QUIRK_FORCE_DMA (1<<1) +/* Controller has unusable DMA engine */ +#define SDHCI_QUIRK_BROKEN_DMA (1<<2) +/* Controller doesn't like to be reset when there is no card inserted. */ +#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) +/* Controller has flaky internal state so reset it on each ios change */ +#define SDHCI_QUIRK_RESET_ON_IOS (1<<4) +/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ +#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) +/* Controller needs to be reset after each request to stay stable */ +#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) +/* Controller has an off-by-one issue with timeout value */ +#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) +/* Controller has broken read timings */ +#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) +/* Controller needs lowered frequency */ +#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) -#define PCI_SLOT_INFO 0x40 /* 8 bits */ -#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) -#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) -/* - * RICOH specific PCI registers - */ -#define SDHC_PCI_MODE_KEY 0xf9 -#define SDHC_PCI_MODE 0x150 -#define SDHC_PCI_MODE_SD20 0x10 -#define SDHC_PCI_BASE_FREQ_KEY 0xfc -#define SDHC_PCI_BASE_FREQ 0xe1 /* * Controller registers @@ -81,8 +86,6 @@ #define SDHCI_CMD_TYPE_ABORT 0xc0 #define SDHCI_CMD_TYPE_MASK 0xc0 -#define SDHCI_COMMAND 0x0F - #define SDHCI_RESPONSE 0x10 #define SDHCI_BUFFER 0x20 @@ -123,7 +126,11 @@ #define SDHCI_WAKE_UP_CONTROL 0x2B #define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_MASK 0xff +#define SDHCI_DIVIDER_MASK_LEN 8 #define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_MASK 3 +#define SDHCI_DIVIDER_HI_SHIFT 6 #define SDHCI_CLOCK_CARD_EN 0x0004 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 @@ -197,3 +204,57 @@ #define SDHCI_VENDOR_VER_SHIFT 8 #define SDHCI_SPEC_VER_MASK 0x00FF #define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 + + +struct sdhci_slot { + u_int quirks; /* Chip specific quirks */ + device_t bus; /* Bus device */ + device_t dev; /* Slot device */ + u_char num; /* Slot number */ + u_char opt; /* Slot options */ + u_char version; +#define SDHCI_HAVE_DMA 1 + uint32_t max_clk; /* Max possible freq */ + uint32_t timeout_clk; /* Timeout freq */ + struct resource *mem_res; /* Memory resource */ + int mem_rid; + bus_dma_tag_t dmatag; + bus_dmamap_t dmamap; + u_char *dmamem; + bus_addr_t paddr; /* DMA buffer address */ + struct task card_task; /* Card presence check task */ + struct callout card_callout; /* Card insert delay callout */ + struct mmc_host host; /* Host parameters */ + struct mmc_request *req; /* Current request */ + struct mmc_command *curcmd; /* Current command of current request */ + + uint32_t intmask; /* Current interrupt mask */ + uint32_t clock; /* Current clock freq. */ + size_t offset; /* Data buffer offset */ + uint8_t hostctrl; /* Current host control register */ + u_char power; /* Current power */ + u_char bus_busy; /* Bus busy status */ + u_char cmd_done; /* CMD command part done flag */ + u_char data_done; /* DAT command part done flag */ + u_char flags; /* Request execution flags */ +#define CMD_STARTED 1 +#define STOP_STARTED 2 +#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ + struct mtx mtx; /* Slot mutex */ +}; + +int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); +int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value); +int sdhci_init_slot(device_t dev, struct sdhci_slot *slot); +int sdhci_cleanup_slot(struct sdhci_slot *slot); +int sdhci_generic_suspend(struct sdhci_slot *slot); +int sdhci_generic_resume(struct sdhci_slot *slot); +int sdhci_generic_update_ios(device_t brdev, device_t reqdev); +int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req); +int sdhci_generic_get_ro(device_t brdev, device_t reqdev); +int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); +int sdhci_generic_release_host(device_t brdev, device_t reqdev); +void sdhci_generic_intr(struct sdhci_slot *slot); Index: dev/sdhci/sdhci_if.m =================================================================== --- dev/sdhci/sdhci_if.m (revision 0) +++ dev/sdhci/sdhci_if.m (working copy) @@ -0,0 +1,105 @@ +#- +# Copyright (c) 2006 M. Warner Losh +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# Portions of this software may have been developed with reference to +# the SD Simplified Specification. The following disclaimer may apply: +# +# The following conditions apply to the release of the simplified +# specification ("Simplified Specification") by the SD Card Association and +# the SD Group. The Simplified Specification is a subset of the complete SD +# Specification which is owned by the SD Card Association and the SD +# Group. This Simplified Specification is provided on a non-confidential +# basis subject to the disclaimers below. Any implementation of the +# Simplified Specification may require a license from the SD Card +# Association, SD Group, SD-3C LLC or other third parties. +# +# Disclaimers: +# +# The information contained in the Simplified Specification is presented only +# as a standard specification for SD Cards and SD Host/Ancillary products and +# is provided "AS-IS" without any representations or warranties of any +# kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD +# Card Association for any damages, any infringements of patents or other +# right of the SD Group, SD-3C LLC, the SD Card Association or any third +# parties, which may result from its use. No license is granted by +# implication, estoppel or otherwise under any patent or other rights of the +# SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing +# herein shall be construed as an obligation by the SD Group, the SD-3C LLC +# or the SD Card Association to disclose or distribute any technical +# information, know-how or other confidential information to any third party. +# +# $FreeBSD: projects/armv6/sys/dev/mmc/mmcbus_if.m 170002 2007-05-26 05:23:36Z imp $ +# + +# +# This is the set of callbacks that mmc bridges call into the bus, or +# that mmc/sd card drivers call to make requests. +# + +#include +CODE { + struct sdhci_slot; +} + +INTERFACE sdhci; + +METHOD uint8_t read_1 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; +} + +METHOD uint16_t read_2 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; +} + +METHOD uint32_t read_4 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; +} + +METHOD void write_1 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; + uint8_t val; +} + +METHOD void write_2 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; + uint16_t val; +} + +METHOD void write_4 { + device_t brdev; + struct sdhci_slot *slot; + bus_size_t off; + uint32_t val; +} Index: dev/sdhci/sdhci_pci.c =================================================================== --- dev/sdhci/sdhci_pci.c (revision 0) +++ dev/sdhci/sdhci_pci.c (working copy) @@ -0,0 +1,1599 @@ +/*- + * Copyright (c) 2008 Alexander Motin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "mmcbr_if.h" +#include "sdhci.h" + +/* + * PCI registers + */ + +#define PCI_SDHCI_IFPIO 0x00 +#define PCI_SDHCI_IFDMA 0x01 +#define PCI_SDHCI_IFVENDOR 0x02 + +#define PCI_SLOT_INFO 0x40 /* 8 bits */ +#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) +#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) + +/* + * RICOH specific PCI registers + */ +#define SDHC_PCI_MODE_KEY 0xf9 +#define SDHC_PCI_MODE 0x150 +#define SDHC_PCI_MODE_SD20 0x10 +#define SDHC_PCI_BASE_FREQ_KEY 0xfc +#define SDHC_PCI_BASE_FREQ 0xe1 + +static const struct sdhci_device { + uint32_t model; + uint16_t subvendor; + char *desc; + u_int quirks; +} sdhci_devices[] = { + { 0x08221180, 0xffff, "RICOH R5C822 SD", + SDHCI_QUIRK_FORCE_DMA }, + { 0xe8221180, 0xffff, "RICOH SD", + SDHCI_QUIRK_FORCE_DMA }, + { 0xe8231180, 0xffff, "RICOH R5CE823 SD", + SDHCI_QUIRK_LOWER_FREQUENCY }, + { 0x8034104c, 0xffff, "TI XX21/XX11 SD", + SDHCI_QUIRK_FORCE_DMA }, + { 0x05501524, 0xffff, "ENE CB712 SD", + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x05511524, 0xffff, "ENE CB712 SD 2", + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x07501524, 0xffff, "ENE CB714 SD", + SDHCI_QUIRK_RESET_ON_IOS | + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x07511524, 0xffff, "ENE CB714 SD 2", + SDHCI_QUIRK_RESET_ON_IOS | + SDHCI_QUIRK_BROKEN_TIMINGS }, + { 0x410111ab, 0xffff, "Marvell CaFe SD", + SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, + { 0x2381197B, 0xffff, "JMicron JMB38X SD", + SDHCI_QUIRK_32BIT_DMA_SIZE | + SDHCI_QUIRK_RESET_AFTER_REQUEST }, + { 0, 0xffff, NULL, + 0 } +}; + +struct sdhci_softc; + +struct sdhci_slot { + struct sdhci_softc *sc; + device_t dev; /* Slot device */ + u_char num; /* Slot number */ + u_char opt; /* Slot options */ +#define SDHCI_HAVE_DMA 1 + uint32_t max_clk; /* Max possible freq */ + uint32_t timeout_clk; /* Timeout freq */ + struct resource *mem_res; /* Memory resource */ + int mem_rid; + bus_dma_tag_t dmatag; + bus_dmamap_t dmamap; + u_char *dmamem; + bus_addr_t paddr; /* DMA buffer address */ + struct task card_task; /* Card presence check task */ + struct callout card_callout; /* Card insert delay callout */ + struct mmc_host host; /* Host parameters */ + struct mmc_request *req; /* Current request */ + struct mmc_command *curcmd; /* Current command of current request */ + + uint32_t intmask; /* Current interrupt mask */ + uint32_t clock; /* Current clock freq. */ + size_t offset; /* Data buffer offset */ + uint8_t hostctrl; /* Current host control register */ + u_char power; /* Current power */ + u_char bus_busy; /* Bus busy status */ + u_char cmd_done; /* CMD command part done flag */ + u_char data_done; /* DAT command part done flag */ + u_char flags; /* Request execution flags */ +#define CMD_STARTED 1 +#define STOP_STARTED 2 +#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ + struct mtx mtx; /* Slot mutex */ +}; + +struct sdhci_softc { + device_t dev; /* Controller device */ + u_int quirks; /* Chip specific quirks */ + struct resource *irq_res; /* IRQ resource */ + int irq_rid; + void *intrhand; /* Interrupt handle */ + + int num_slots; /* Number of slots on this controller */ + struct sdhci_slot slots[6]; +}; + +static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); + +int sdhci_debug; +TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); +SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); + +static inline uint8_t +RD1(struct sdhci_slot *slot, bus_size_t off) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + return bus_read_1(slot->mem_res, off); +} + +static inline void +WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + bus_write_1(slot->mem_res, off, val); +} + +static inline uint16_t +RD2(struct sdhci_slot *slot, bus_size_t off) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + return bus_read_2(slot->mem_res, off); +} + +static inline void +WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + bus_write_2(slot->mem_res, off, val); +} + +static inline uint32_t +RD4(struct sdhci_slot *slot, bus_size_t off) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + return bus_read_4(slot->mem_res, off); +} + +static inline void +WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) +{ + bus_barrier(slot->mem_res, 0, 0xFF, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + bus_write_4(slot->mem_res, off, val); +} + +/* bus entry points */ +static int sdhci_probe(device_t dev); +static int sdhci_attach(device_t dev); +static int sdhci_detach(device_t dev); +static void sdhci_intr(void *); + +static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); +static void sdhci_start(struct sdhci_slot *slot); +static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); + +static void sdhci_card_task(void *, int); + +/* helper routines */ +#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) +#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) +#define SDHCI_LOCK_INIT(_slot) \ + mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) +#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); +#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); +#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); + +static int +slot_printf(struct sdhci_slot *slot, const char * fmt, ...) +{ + va_list ap; + int retval; + + retval = printf("%s-slot%d: ", + device_get_nameunit(slot->sc->dev), slot->num); + + va_start(ap, fmt); + retval += vprintf(fmt, ap); + va_end(ap); + return (retval); +} + +static void +sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + if (error != 0) { + printf("getaddr: error %d\n", error); + return; + } + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +static void +sdhci_dumpregs(struct sdhci_slot *slot) +{ + slot_printf(slot, + "============== REGISTER DUMP ==============\n"); + + slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", + RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); + slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", + RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); + slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", + RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); + slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", + RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); + slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", + RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); + slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", + RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); + slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", + RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); + slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", + RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); + slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", + RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); + slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", + RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); + + slot_printf(slot, + "===========================================\n"); +} + +static void +sdhci_reset(struct sdhci_slot *slot, uint8_t mask) +{ + int timeout; + uint8_t res; + + if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { + if (!(RD4(slot, SDHCI_PRESENT_STATE) & + SDHCI_CARD_PRESENT)) + return; + } + + /* Some controllers need this kick or reset won't work. */ + if ((mask & SDHCI_RESET_ALL) == 0 && + (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { + uint32_t clock; + + /* This is to force an update */ + clock = slot->clock; + slot->clock = 0; + sdhci_set_clock(slot, clock); + } + + WR1(slot, SDHCI_SOFTWARE_RESET, mask); + + if (mask & SDHCI_RESET_ALL) { + slot->clock = 0; + slot->power = 0; + } + + /* Wait max 100 ms */ + timeout = 100; + /* Controller clears the bits when it's done */ + while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { + if (timeout == 0) { + slot_printf(slot, + "Reset 0x%x never completed - 0x%x.\n", + (int)mask, (int)res); + sdhci_dumpregs(slot); + return; + } + timeout--; + DELAY(1000); + } +} + +static void +sdhci_init(struct sdhci_slot *slot) +{ + + sdhci_reset(slot, SDHCI_RESET_ALL); + + /* Enable interrupts. */ + slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | + SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | + SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | + SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | + SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | + SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | + SDHCI_INT_ACMD12ERR; + WR4(slot, SDHCI_INT_ENABLE, slot->intmask); + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); +} + +static void +sdhci_lower_frequency(device_t dev) +{ + + /* Enable SD2.0 mode. */ + pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); + pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); + pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); + + /* + * Some SD/MMC cards don't work with the default base + * clock frequency of 200MHz. Lower it to 50Hz. + */ + pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); + pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); + pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); +} + +static void +sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) +{ + uint32_t res; + uint16_t clk; + int timeout; + + if (clock == slot->clock) + return; + slot->clock = clock; + + /* Turn off the clock. */ + WR2(slot, SDHCI_CLOCK_CONTROL, 0); + /* If no clock requested - left it so. */ + if (clock == 0) + return; + /* Looking for highest freq <= clock. */ + res = slot->max_clk; + for (clk = 1; clk < 256; clk <<= 1) { + if (res <= clock) + break; + res >>= 1; + } + /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ + clk >>= 1; + /* Now we have got divider, set it. */ + clk <<= SDHCI_DIVIDER_SHIFT; + WR2(slot, SDHCI_CLOCK_CONTROL, clk); + /* Enable clock. */ + clk |= SDHCI_CLOCK_INT_EN; + WR2(slot, SDHCI_CLOCK_CONTROL, clk); + /* Wait up to 10 ms until it stabilize. */ + timeout = 10; + while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + slot_printf(slot, + "Internal clock never stabilised.\n"); + sdhci_dumpregs(slot); + return; + } + timeout--; + DELAY(1000); + } + /* Pass clock signal to the bus. */ + clk |= SDHCI_CLOCK_CARD_EN; + WR2(slot, SDHCI_CLOCK_CONTROL, clk); +} + +static void +sdhci_set_power(struct sdhci_slot *slot, u_char power) +{ + uint8_t pwr; + + if (slot->power == power) + return; + slot->power = power; + + /* Turn off the power. */ + pwr = 0; + WR1(slot, SDHCI_POWER_CONTROL, pwr); + /* If power down requested - left it so. */ + if (power == 0) + return; + /* Set voltage. */ + switch (1 << power) { + case MMC_OCR_LOW_VOLTAGE: + pwr |= SDHCI_POWER_180; + break; + case MMC_OCR_290_300: + case MMC_OCR_300_310: + pwr |= SDHCI_POWER_300; + break; + case MMC_OCR_320_330: + case MMC_OCR_330_340: + pwr |= SDHCI_POWER_330; + break; + } + WR1(slot, SDHCI_POWER_CONTROL, pwr); + /* Turn on the power. */ + pwr |= SDHCI_POWER_ON; + WR1(slot, SDHCI_POWER_CONTROL, pwr); +} + +static void +sdhci_read_block_pio(struct sdhci_slot *slot) +{ + uint32_t data; + char *buffer; + size_t left; + + buffer = slot->curcmd->data->data; + buffer += slot->offset; + /* Transfer one block at a time. */ + left = min(512, slot->curcmd->data->len - slot->offset); + slot->offset += left; + + /* If we are too fast, broken controllers return zeroes. */ + if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) + DELAY(10); + /* Handle unalligned and alligned buffer cases. */ + if ((intptr_t)buffer & 3) { + while (left > 3) { + data = RD4(slot, SDHCI_BUFFER); + buffer[0] = data; + buffer[1] = (data >> 8); + buffer[2] = (data >> 16); + buffer[3] = (data >> 24); + buffer += 4; + left -= 4; + } + } else { + bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + (uint32_t *)buffer, left >> 2); + left &= 3; + } + /* Handle uneven size case. */ + if (left > 0) { + data = RD4(slot, SDHCI_BUFFER); + while (left > 0) { + *(buffer++) = data; + data >>= 8; + left--; + } + } +} + +static void +sdhci_write_block_pio(struct sdhci_slot *slot) +{ + uint32_t data = 0; + char *buffer; + size_t left; + + buffer = slot->curcmd->data->data; + buffer += slot->offset; + /* Transfer one block at a time. */ + left = min(512, slot->curcmd->data->len - slot->offset); + slot->offset += left; + + /* Handle unalligned and alligned buffer cases. */ + if ((intptr_t)buffer & 3) { + while (left > 3) { + data = buffer[0] + + (buffer[1] << 8) + + (buffer[2] << 16) + + (buffer[3] << 24); + left -= 4; + buffer += 4; + WR4(slot, SDHCI_BUFFER, data); + } + } else { + bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + (uint32_t *)buffer, left >> 2); + left &= 3; + } + /* Handle uneven size case. */ + if (left > 0) { + while (left > 0) { + data <<= 8; + data += *(buffer++); + left--; + } + WR4(slot, SDHCI_BUFFER, data); + } +} + +static void +sdhci_transfer_pio(struct sdhci_slot *slot) +{ + + /* Read as many blocks as possible. */ + if (slot->curcmd->data->flags & MMC_DATA_READ) { + while (RD4(slot, SDHCI_PRESENT_STATE) & + SDHCI_DATA_AVAILABLE) { + sdhci_read_block_pio(slot); + if (slot->offset >= slot->curcmd->data->len) + break; + } + } else { + while (RD4(slot, SDHCI_PRESENT_STATE) & + SDHCI_SPACE_AVAILABLE) { + sdhci_write_block_pio(slot); + if (slot->offset >= slot->curcmd->data->len) + break; + } + } +} + +static void +sdhci_card_delay(void *arg) +{ + struct sdhci_slot *slot = arg; + + taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); +} + +static void +sdhci_card_task(void *arg, int pending) +{ + struct sdhci_slot *slot = arg; + + SDHCI_LOCK(slot); + if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { + if (slot->dev == NULL) { + /* If card is present - attach mmc bus. */ + slot->dev = device_add_child(slot->sc->dev, "mmc", -1); + device_set_ivars(slot->dev, slot); + SDHCI_UNLOCK(slot); + device_probe_and_attach(slot->dev); + } else + SDHCI_UNLOCK(slot); + } else { + if (slot->dev != NULL) { + /* If no card present - detach mmc bus. */ + device_t d = slot->dev; + slot->dev = NULL; + SDHCI_UNLOCK(slot); + device_delete_child(slot->sc->dev, d); + } else + SDHCI_UNLOCK(slot); + } +} + +static int +sdhci_probe(device_t dev) +{ + uint32_t model; + uint16_t subvendor; + uint8_t class, subclass; + int i, result; + + model = (uint32_t)pci_get_device(dev) << 16; + model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; + subvendor = pci_get_subvendor(dev); + class = pci_get_class(dev); + subclass = pci_get_subclass(dev); + + result = ENXIO; + for (i = 0; sdhci_devices[i].model != 0; i++) { + if (sdhci_devices[i].model == model && + (sdhci_devices[i].subvendor == 0xffff || + sdhci_devices[i].subvendor == subvendor)) { + device_set_desc(dev, sdhci_devices[i].desc); + result = BUS_PROBE_DEFAULT; + break; + } + } + if (result == ENXIO && class == PCIC_BASEPERIPH && + subclass == PCIS_BASEPERIPH_SDHC) { + device_set_desc(dev, "Generic SD HCI"); + result = BUS_PROBE_GENERIC; + } + + return (result); +} + +static int +sdhci_attach(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + uint32_t model; + uint16_t subvendor; + uint8_t class, subclass, progif; + int err, slots, bar, i; + + sc->dev = dev; + model = (uint32_t)pci_get_device(dev) << 16; + model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; + subvendor = pci_get_subvendor(dev); + class = pci_get_class(dev); + subclass = pci_get_subclass(dev); + progif = pci_get_progif(dev); + /* Apply chip specific quirks. */ + for (i = 0; sdhci_devices[i].model != 0; i++) { + if (sdhci_devices[i].model == model && + (sdhci_devices[i].subvendor == 0xffff || + sdhci_devices[i].subvendor == subvendor)) { + sc->quirks = sdhci_devices[i].quirks; + break; + } + } + /* Some controllers need to be bumped into the right mode. */ + if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) + sdhci_lower_frequency(dev); + /* Read slots info from PCI registers. */ + slots = pci_read_config(dev, PCI_SLOT_INFO, 1); + bar = PCI_SLOT_INFO_FIRST_BAR(slots); + slots = PCI_SLOT_INFO_SLOTS(slots); + if (slots > 6 || bar > 5) { + device_printf(dev, "Incorrect slots information (%d, %d).\n", + slots, bar); + return (EINVAL); + } + /* Allocate IRQ. */ + sc->irq_rid = 0; + sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->irq_res == NULL) { + device_printf(dev, "Can't allocate IRQ\n"); + return (ENOMEM); + } + /* Scan all slots. */ + for (i = 0; i < slots; i++) { + struct sdhci_slot *slot = &sc->slots[sc->num_slots]; + uint32_t caps; + + SDHCI_LOCK_INIT(slot); + slot->sc = sc; + slot->num = sc->num_slots; + /* Allocate memory. */ + slot->mem_rid = PCIR_BAR(bar + i); + slot->mem_res = bus_alloc_resource(dev, + SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); + if (slot->mem_res == NULL) { + device_printf(dev, "Can't allocate memory\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Allocate DMA tag. */ + err = bus_dma_tag_create(bus_get_dma_tag(dev), + DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, + DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, + BUS_DMA_ALLOCNOW, NULL, NULL, + &slot->dmatag); + if (err != 0) { + device_printf(dev, "Can't create DMA tag\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Allocate DMA memory. */ + err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, + BUS_DMA_NOWAIT, &slot->dmamap); + if (err != 0) { + device_printf(dev, "Can't alloc DMA memory\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Map the memory. */ + err = bus_dmamap_load(slot->dmatag, slot->dmamap, + (void *)slot->dmamem, DMA_BLOCK_SIZE, + sdhci_getaddr, &slot->paddr, 0); + if (err != 0 || slot->paddr == 0) { + device_printf(dev, "Can't load DMA memory\n"); + SDHCI_LOCK_DESTROY(slot); + continue; + } + /* Initialize slot. */ + sdhci_init(slot); + caps = RD4(slot, SDHCI_CAPABILITIES); + /* Calculate base clock frequency. */ + slot->max_clk = + (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; + if (slot->max_clk == 0) { + device_printf(dev, "Hardware doesn't specify base clock " + "frequency.\n"); + } + slot->max_clk *= 1000000; + /* Calculate timeout clock frequency. */ + slot->timeout_clk = + (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; + if (slot->timeout_clk == 0) { + device_printf(dev, "Hardware doesn't specify timeout clock " + "frequency.\n"); + } + if (caps & SDHCI_TIMEOUT_CLK_UNIT) + slot->timeout_clk *= 1000; + + slot->host.f_min = slot->max_clk / 256; + slot->host.f_max = slot->max_clk; + slot->host.host_ocr = 0; + if (caps & SDHCI_CAN_VDD_330) + slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; + if (caps & SDHCI_CAN_VDD_300) + slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; + if (caps & SDHCI_CAN_VDD_180) + slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; + if (slot->host.host_ocr == 0) { + device_printf(dev, "Hardware doesn't report any " + "support voltages.\n"); + } + slot->host.caps = MMC_CAP_4_BIT_DATA; + if (caps & SDHCI_CAN_DO_HISPD) + slot->host.caps |= MMC_CAP_HSPEED; + /* Decide if we have usable DMA. */ + if (caps & SDHCI_CAN_DO_DMA) + slot->opt |= SDHCI_HAVE_DMA; + if (class == PCIC_BASEPERIPH && + subclass == PCIS_BASEPERIPH_SDHC && + progif != PCI_SDHCI_IFDMA) + slot->opt &= ~SDHCI_HAVE_DMA; + if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) + slot->opt &= ~SDHCI_HAVE_DMA; + if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) + slot->opt |= SDHCI_HAVE_DMA; + + if (bootverbose || sdhci_debug) { + slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", + slot->max_clk / 1000000, + (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", + (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", + (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", + (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", + (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); + sdhci_dumpregs(slot); + } + + TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); + callout_init(&slot->card_callout, 1); + sc->num_slots++; + } + device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); + /* Activate the interrupt */ + err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, sdhci_intr, sc, &sc->intrhand); + if (err) + device_printf(dev, "Can't setup IRQ\n"); + pci_enable_busmaster(dev); + /* Process cards detection. */ + for (i = 0; i < sc->num_slots; i++) { + struct sdhci_slot *slot = &sc->slots[i]; + + sdhci_card_task(slot, 0); + } + + return (0); +} + +static int +sdhci_detach(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + int i; + + bus_teardown_intr(dev, sc->irq_res, sc->intrhand); + bus_release_resource(dev, SYS_RES_IRQ, + sc->irq_rid, sc->irq_res); + + for (i = 0; i < sc->num_slots; i++) { + struct sdhci_slot *slot = &sc->slots[i]; + device_t d; + + callout_drain(&slot->card_callout); + taskqueue_drain(taskqueue_swi_giant, &slot->card_task); + + SDHCI_LOCK(slot); + d = slot->dev; + slot->dev = NULL; + SDHCI_UNLOCK(slot); + if (d != NULL) + device_delete_child(dev, d); + + SDHCI_LOCK(slot); + sdhci_reset(slot, SDHCI_RESET_ALL); + SDHCI_UNLOCK(slot); + bus_dmamap_unload(slot->dmatag, slot->dmamap); + bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); + bus_dma_tag_destroy(slot->dmatag); + bus_release_resource(dev, SYS_RES_MEMORY, + slot->mem_rid, slot->mem_res); + SDHCI_LOCK_DESTROY(slot); + } + return (0); +} + +static int +sdhci_suspend(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + int i, err; + + err = bus_generic_suspend(dev); + if (err) + return (err); + for (i = 0; i < sc->num_slots; i++) + sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); + return (0); +} + +static int +sdhci_resume(device_t dev) +{ + struct sdhci_softc *sc = device_get_softc(dev); + int i; + + for (i = 0; i < sc->num_slots; i++) + sdhci_init(&sc->slots[i]); + return (bus_generic_resume(dev)); +} + +static int +sdhci_update_ios(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + struct mmc_ios *ios = &slot->host.ios; + + SDHCI_LOCK(slot); + /* Do full reset on bus power down to clear from any state. */ + if (ios->power_mode == power_off) { + WR4(slot, SDHCI_SIGNAL_ENABLE, 0); + sdhci_init(slot); + } + /* Configure the bus. */ + sdhci_set_clock(slot, ios->clock); + sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); + if (ios->bus_width == bus_width_4) + slot->hostctrl |= SDHCI_CTRL_4BITBUS; + else + slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; + if (ios->timing == bus_timing_hs) + slot->hostctrl |= SDHCI_CTRL_HISPD; + else + slot->hostctrl &= ~SDHCI_CTRL_HISPD; + WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); + /* Some controllers like reset after bus changes. */ + if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) + sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + + SDHCI_UNLOCK(slot); + return (0); +} + +static void +sdhci_set_transfer_mode(struct sdhci_slot *slot, + struct mmc_data *data) +{ + uint16_t mode; + + if (data == NULL) + return; + + mode = SDHCI_TRNS_BLK_CNT_EN; + if (data->len > 512) + mode |= SDHCI_TRNS_MULTI; + if (data->flags & MMC_DATA_READ) + mode |= SDHCI_TRNS_READ; + if (slot->req->stop) + mode |= SDHCI_TRNS_ACMD12; + if (slot->flags & SDHCI_USE_DMA) + mode |= SDHCI_TRNS_DMA; + + WR2(slot, SDHCI_TRANSFER_MODE, mode); +} + +static void +sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) +{ + struct mmc_request *req = slot->req; + int flags, timeout; + uint32_t mask, state; + + slot->curcmd = cmd; + slot->cmd_done = 0; + + cmd->error = MMC_ERR_NONE; + + /* This flags combination is not supported by controller. */ + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + slot_printf(slot, "Unsupported response type!\n"); + cmd->error = MMC_ERR_FAILED; + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); + return; + } + + /* Read controller present state. */ + state = RD4(slot, SDHCI_PRESENT_STATE); + /* Do not issue command if there is no card, clock or power. + * Controller will not detect timeout without clock active. */ + if ((state & SDHCI_CARD_PRESENT) == 0 || + slot->power == 0 || + slot->clock == 0) { + cmd->error = MMC_ERR_FAILED; + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); + return; + } + /* Always wait for free CMD bus. */ + mask = SDHCI_CMD_INHIBIT; + /* Wait for free DAT if we have data or busy signal. */ + if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) + mask |= SDHCI_DAT_INHIBIT; + /* We shouldn't wait for DAT for stop commands. */ + if (cmd == slot->req->stop) + mask &= ~SDHCI_DAT_INHIBIT; + /* Wait for bus no more then 10 ms. */ + timeout = 10; + while (state & mask) { + if (timeout == 0) { + slot_printf(slot, "Controller never released " + "inhibit bit(s).\n"); + sdhci_dumpregs(slot); + cmd->error = MMC_ERR_FAILED; + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); + return; + } + timeout--; + DELAY(1000); + state = RD4(slot, SDHCI_PRESENT_STATE); + } + + /* Prepare command flags. */ + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = SDHCI_CMD_RESP_SHORT; + if (cmd->flags & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + if (cmd->data) + flags |= SDHCI_CMD_DATA; + if (cmd->opcode == MMC_STOP_TRANSMISSION) + flags |= SDHCI_CMD_TYPE_ABORT; + /* Prepare data. */ + sdhci_start_data(slot, cmd->data); + /* + * Interrupt aggregation: To reduce total number of interrupts + * group response interrupt with data interrupt when possible. + * If there going to be data interrupt, mask response one. + */ + if (slot->data_done == 0) { + WR4(slot, SDHCI_SIGNAL_ENABLE, + slot->intmask &= ~SDHCI_INT_RESPONSE); + } + /* Set command argument. */ + WR4(slot, SDHCI_ARGUMENT, cmd->arg); + /* Set data transfer mode. */ + sdhci_set_transfer_mode(slot, cmd->data); + /* Set command flags. */ + WR1(slot, SDHCI_COMMAND_FLAGS, flags); + /* Start command. */ + WR1(slot, SDHCI_COMMAND, cmd->opcode); +} + +static void +sdhci_finish_command(struct sdhci_slot *slot) +{ + int i; + + slot->cmd_done = 1; + /* Interrupt aggregation: Restore command interrupt. + * Main restore point for the case when command interrupt + * happened first. */ + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); + /* In case of error - reset host and return. */ + if (slot->curcmd->error) { + sdhci_reset(slot, SDHCI_RESET_CMD); + sdhci_reset(slot, SDHCI_RESET_DATA); + sdhci_start(slot); + return; + } + /* If command has response - fetch it. */ + if (slot->curcmd->flags & MMC_RSP_PRESENT) { + if (slot->curcmd->flags & MMC_RSP_136) { + /* CRC is stripped so we need one byte shift. */ + uint8_t extra = 0; + for (i = 0; i < 4; i++) { + uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); + slot->curcmd->resp[3 - i] = (val << 8) + extra; + extra = val >> 24; + } + } else + slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); + } + /* If data ready - finish. */ + if (slot->data_done) + sdhci_start(slot); +} + +static void +sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) +{ + uint32_t target_timeout, current_timeout; + uint8_t div; + + if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { + slot->data_done = 1; + return; + } + + slot->data_done = 0; + + /* Calculate and set data timeout.*/ + /* XXX: We should have this from mmc layer, now assume 1 sec. */ + target_timeout = 1000000; + div = 0; + current_timeout = (1 << 13) * 1000 / slot->timeout_clk; + while (current_timeout < target_timeout) { + div++; + current_timeout <<= 1; + if (div >= 0xF) + break; + } + /* Compensate for an off-by-one error in the CaFe chip.*/ + if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) + div++; + if (div >= 0xF) { + slot_printf(slot, "Timeout too large!\n"); + div = 0xE; + } + WR1(slot, SDHCI_TIMEOUT_CONTROL, div); + + if (data == NULL) + return; + + /* Use DMA if possible. */ + if ((slot->opt & SDHCI_HAVE_DMA)) + slot->flags |= SDHCI_USE_DMA; + /* If data is small, broken DMA may return zeroes instead of data, */ + if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && + (data->len <= 512)) + slot->flags &= ~SDHCI_USE_DMA; + /* Some controllers require even block sizes. */ + if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && + ((data->len) & 0x3)) + slot->flags &= ~SDHCI_USE_DMA; + /* Load DMA buffer. */ + if (slot->flags & SDHCI_USE_DMA) { + if (data->flags & MMC_DATA_READ) + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); + else { + memcpy(slot->dmamem, data->data, + (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); + } + WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); + /* Interrupt aggregation: Mask border interrupt + * for the last page and unmask else. */ + if (data->len == DMA_BLOCK_SIZE) + slot->intmask &= ~SDHCI_INT_DMA_END; + else + slot->intmask |= SDHCI_INT_DMA_END; + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); + } + /* Current data offset for both PIO and DMA. */ + slot->offset = 0; + /* Set block size and request IRQ on 4K border. */ + WR2(slot, SDHCI_BLOCK_SIZE, + SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); + /* Set block count. */ + WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); +} + +static void +sdhci_finish_data(struct sdhci_slot *slot) +{ + struct mmc_data *data = slot->curcmd->data; + + slot->data_done = 1; + /* Interrupt aggregation: Restore command interrupt. + * Auxillary restore point for the case when data interrupt + * happened first. */ + if (!slot->cmd_done) { + WR4(slot, SDHCI_SIGNAL_ENABLE, + slot->intmask |= SDHCI_INT_RESPONSE); + } + /* Unload rest of data from DMA buffer. */ + if (slot->flags & SDHCI_USE_DMA) { + if (data->flags & MMC_DATA_READ) { + size_t left = data->len - slot->offset; + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); + memcpy((u_char*)data->data + slot->offset, slot->dmamem, + (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); + } else + bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); + } + /* If there was error - reset the host. */ + if (slot->curcmd->error) { + sdhci_reset(slot, SDHCI_RESET_CMD); + sdhci_reset(slot, SDHCI_RESET_DATA); + sdhci_start(slot); + return; + } + /* If we already have command response - finish. */ + if (slot->cmd_done) + sdhci_start(slot); +} + +static void +sdhci_start(struct sdhci_slot *slot) +{ + struct mmc_request *req; + + req = slot->req; + if (req == NULL) + return; + + if (!(slot->flags & CMD_STARTED)) { + slot->flags |= CMD_STARTED; + sdhci_start_command(slot, req->cmd); + return; + } +/* We don't need this until using Auto-CMD12 feature + if (!(slot->flags & STOP_STARTED) && req->stop) { + slot->flags |= STOP_STARTED; + sdhci_start_command(slot, req->stop); + return; + } +*/ + if (sdhci_debug > 1) + slot_printf(slot, "result: %d\n", req->cmd->error); + if (!req->cmd->error && + (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { + sdhci_reset(slot, SDHCI_RESET_CMD); + sdhci_reset(slot, SDHCI_RESET_DATA); + } + + /* We must be done -- bad idea to do this while locked? */ + slot->req = NULL; + slot->curcmd = NULL; + req->done(req); +} + +static int +sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + + SDHCI_LOCK(slot); + if (slot->req != NULL) { + SDHCI_UNLOCK(slot); + return (EBUSY); + } + if (sdhci_debug > 1) { + slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", + req->cmd->opcode, req->cmd->arg, req->cmd->flags, + (req->cmd->data)?(u_int)req->cmd->data->len:0, + (req->cmd->data)?req->cmd->data->flags:0); + } + slot->req = req; + slot->flags = 0; + sdhci_start(slot); + SDHCI_UNLOCK(slot); + if (dumping) { + while (slot->req != NULL) { + sdhci_intr(slot->sc); + DELAY(10); + } + } + return (0); +} + +static int +sdhci_get_ro(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + uint32_t val; + + SDHCI_LOCK(slot); + val = RD4(slot, SDHCI_PRESENT_STATE); + SDHCI_UNLOCK(slot); + return (!(val & SDHCI_WRITE_PROTECT)); +} + +static int +sdhci_acquire_host(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + int err = 0; + + SDHCI_LOCK(slot); + while (slot->bus_busy) + msleep(slot, &slot->mtx, 0, "sdhciah", 0); + slot->bus_busy++; + /* Activate led. */ + WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); + SDHCI_UNLOCK(slot); + return (err); +} + +static int +sdhci_release_host(device_t brdev, device_t reqdev) +{ + struct sdhci_slot *slot = device_get_ivars(reqdev); + + SDHCI_LOCK(slot); + /* Deactivate led. */ + WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); + slot->bus_busy--; + SDHCI_UNLOCK(slot); + wakeup(slot); + return (0); +} + +static void +sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) +{ + + if (!slot->curcmd) { + slot_printf(slot, "Got command interrupt 0x%08x, but " + "there is no active command.\n", intmask); + sdhci_dumpregs(slot); + return; + } + if (intmask & SDHCI_INT_TIMEOUT) + slot->curcmd->error = MMC_ERR_TIMEOUT; + else if (intmask & SDHCI_INT_CRC) + slot->curcmd->error = MMC_ERR_BADCRC; + else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) + slot->curcmd->error = MMC_ERR_FIFO; + + sdhci_finish_command(slot); +} + +static void +sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) +{ + + if (!slot->curcmd) { + slot_printf(slot, "Got data interrupt 0x%08x, but " + "there is no active command.\n", intmask); + sdhci_dumpregs(slot); + return; + } + if (slot->curcmd->data == NULL && + (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { + slot_printf(slot, "Got data interrupt 0x%08x, but " + "there is no active data operation.\n", + intmask); + sdhci_dumpregs(slot); + return; + } + if (intmask & SDHCI_INT_DATA_TIMEOUT) + slot->curcmd->error = MMC_ERR_TIMEOUT; + else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) + slot->curcmd->error = MMC_ERR_BADCRC; + if (slot->curcmd->data == NULL && + (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | + SDHCI_INT_DMA_END))) { + slot_printf(slot, "Got data interrupt 0x%08x, but " + "there is busy-only command.\n", intmask); + sdhci_dumpregs(slot); + slot->curcmd->error = MMC_ERR_INVALID; + } + if (slot->curcmd->error) { + /* No need to continue after any error. */ + sdhci_finish_data(slot); + return; + } + + /* Handle PIO interrupt. */ + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) + sdhci_transfer_pio(slot); + /* Handle DMA border. */ + if (intmask & SDHCI_INT_DMA_END) { + struct mmc_data *data = slot->curcmd->data; + size_t left; + + /* Unload DMA buffer... */ + left = data->len - slot->offset; + if (data->flags & MMC_DATA_READ) { + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_POSTREAD); + memcpy((u_char*)data->data + slot->offset, slot->dmamem, + (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); + } else { + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_POSTWRITE); + } + /* ... and reload it again. */ + slot->offset += DMA_BLOCK_SIZE; + left = data->len - slot->offset; + if (data->flags & MMC_DATA_READ) { + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_PREREAD); + } else { + memcpy(slot->dmamem, (u_char*)data->data + slot->offset, + (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); + bus_dmamap_sync(slot->dmatag, slot->dmamap, + BUS_DMASYNC_PREWRITE); + } + /* Interrupt aggregation: Mask border interrupt + * for the last page. */ + if (left == DMA_BLOCK_SIZE) { + slot->intmask &= ~SDHCI_INT_DMA_END; + WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); + } + /* Restart DMA. */ + WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); + } + /* We have got all data. */ + if (intmask & SDHCI_INT_DATA_END) + sdhci_finish_data(slot); +} + +static void +sdhci_acmd_irq(struct sdhci_slot *slot) +{ + uint16_t err; + + err = RD4(slot, SDHCI_ACMD12_ERR); + if (!slot->curcmd) { + slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " + "there is no active command.\n", err); + sdhci_dumpregs(slot); + return; + } + slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); + sdhci_reset(slot, SDHCI_RESET_CMD); +} + +static void +sdhci_intr(void *arg) +{ + struct sdhci_softc *sc = (struct sdhci_softc *)arg; + int i; + + for (i = 0; i < sc->num_slots; i++) { + struct sdhci_slot *slot = &sc->slots[i]; + uint32_t intmask; + + SDHCI_LOCK(slot); + /* Read slot interrupt status. */ + intmask = RD4(slot, SDHCI_INT_STATUS); + if (intmask == 0 || intmask == 0xffffffff) { + SDHCI_UNLOCK(slot); + continue; + } + if (sdhci_debug > 2) + slot_printf(slot, "Interrupt %#x\n", intmask); + + /* Handle card presence interrupts. */ + if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + WR4(slot, SDHCI_INT_STATUS, intmask & + (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); + + if (intmask & SDHCI_INT_CARD_REMOVE) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card removed\n"); + callout_stop(&slot->card_callout); + taskqueue_enqueue(taskqueue_swi_giant, + &slot->card_task); + } + if (intmask & SDHCI_INT_CARD_INSERT) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card inserted\n"); + callout_reset(&slot->card_callout, hz / 2, + sdhci_card_delay, slot); + } + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); + } + /* Handle command interrupts. */ + if (intmask & SDHCI_INT_CMD_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); + sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); + } + /* Handle data interrupts. */ + if (intmask & SDHCI_INT_DATA_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); + sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); + } + /* Handle AutoCMD12 error interrupt. */ + if (intmask & SDHCI_INT_ACMD12ERR) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); + sdhci_acmd_irq(slot); + } + intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); + intmask &= ~SDHCI_INT_ACMD12ERR; + intmask &= ~SDHCI_INT_ERROR; + /* Handle bus power interrupt. */ + if (intmask & SDHCI_INT_BUS_POWER) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); + slot_printf(slot, + "Card is consuming too much power!\n"); + intmask &= ~SDHCI_INT_BUS_POWER; + } + /* The rest is unknown. */ + if (intmask) { + WR4(slot, SDHCI_INT_STATUS, intmask); + slot_printf(slot, "Unexpected interrupt 0x%08x.\n", + intmask); + sdhci_dumpregs(slot); + } + + SDHCI_UNLOCK(slot); + } +} + +static int +sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) +{ + struct sdhci_slot *slot = device_get_ivars(child); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + *result = slot->host.ios.bus_mode; + break; + case MMCBR_IVAR_BUS_WIDTH: + *result = slot->host.ios.bus_width; + break; + case MMCBR_IVAR_CHIP_SELECT: + *result = slot->host.ios.chip_select; + break; + case MMCBR_IVAR_CLOCK: + *result = slot->host.ios.clock; + break; + case MMCBR_IVAR_F_MIN: + *result = slot->host.f_min; + break; + case MMCBR_IVAR_F_MAX: + *result = slot->host.f_max; + break; + case MMCBR_IVAR_HOST_OCR: + *result = slot->host.host_ocr; + break; + case MMCBR_IVAR_MODE: + *result = slot->host.mode; + break; + case MMCBR_IVAR_OCR: + *result = slot->host.ocr; + break; + case MMCBR_IVAR_POWER_MODE: + *result = slot->host.ios.power_mode; + break; + case MMCBR_IVAR_VDD: + *result = slot->host.ios.vdd; + break; + case MMCBR_IVAR_CAPS: + *result = slot->host.caps; + break; + case MMCBR_IVAR_TIMING: + *result = slot->host.ios.timing; + break; + case MMCBR_IVAR_MAX_DATA: + *result = 65535; + break; + } + return (0); +} + +static int +sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) +{ + struct sdhci_slot *slot = device_get_ivars(child); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + slot->host.ios.bus_mode = value; + break; + case MMCBR_IVAR_BUS_WIDTH: + slot->host.ios.bus_width = value; + break; + case MMCBR_IVAR_CHIP_SELECT: + slot->host.ios.chip_select = value; + break; + case MMCBR_IVAR_CLOCK: + if (value > 0) { + uint32_t clock = slot->max_clk; + int i; + + for (i = 0; i < 8; i++) { + if (clock <= value) + break; + clock >>= 1; + } + slot->host.ios.clock = clock; + } else + slot->host.ios.clock = 0; + break; + case MMCBR_IVAR_MODE: + slot->host.mode = value; + break; + case MMCBR_IVAR_OCR: + slot->host.ocr = value; + break; + case MMCBR_IVAR_POWER_MODE: + slot->host.ios.power_mode = value; + break; + case MMCBR_IVAR_VDD: + slot->host.ios.vdd = value; + break; + case MMCBR_IVAR_TIMING: + slot->host.ios.timing = value; + break; + case MMCBR_IVAR_CAPS: + case MMCBR_IVAR_HOST_OCR: + case MMCBR_IVAR_F_MIN: + case MMCBR_IVAR_F_MAX: + case MMCBR_IVAR_MAX_DATA: + return (EINVAL); + } + return (0); +} + +static device_method_t sdhci_methods[] = { + /* device_if */ + DEVMETHOD(device_probe, sdhci_probe), + DEVMETHOD(device_attach, sdhci_attach), + DEVMETHOD(device_detach, sdhci_detach), + DEVMETHOD(device_suspend, sdhci_suspend), + DEVMETHOD(device_resume, sdhci_resume), + + /* Bus interface */ + DEVMETHOD(bus_read_ivar, sdhci_read_ivar), + DEVMETHOD(bus_write_ivar, sdhci_write_ivar), + + /* mmcbr_if */ + DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), + DEVMETHOD(mmcbr_request, sdhci_request), + DEVMETHOD(mmcbr_get_ro, sdhci_get_ro), + DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host), + DEVMETHOD(mmcbr_release_host, sdhci_release_host), + + {0, 0}, +}; + +static driver_t sdhci_driver = { + "sdhci", + sdhci_methods, + sizeof(struct sdhci_softc), +}; +static devclass_t sdhci_devclass; + + +DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); Property changes on: dev/sdhci/sdhci_pci.c ___________________________________________________________________ Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: dev/sdhci/sdhci.c =================================================================== --- dev/sdhci/sdhci.c (revision 240001) +++ dev/sdhci/sdhci.c (working copy) @@ -39,9 +39,6 @@ #include #include -#include -#include - #include #include #include @@ -52,6 +49,7 @@ #include "mmcbr_if.h" #include "sdhci.h" +#include "sdhci_if.h" #define DMA_BLOCK_SIZE 4096 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ @@ -77,79 +75,10 @@ /* Controller needs lowered frequency */ #define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) -static const struct sdhci_device { - uint32_t model; - uint16_t subvendor; - char *desc; - u_int quirks; -} sdhci_devices[] = { - { 0x08221180, 0xffff, "RICOH R5C822 SD", - SDHCI_QUIRK_FORCE_DMA }, - { 0xe8221180, 0xffff, "RICOH SD", - SDHCI_QUIRK_FORCE_DMA }, - { 0xe8231180, 0xffff, "RICOH R5CE823 SD", - SDHCI_QUIRK_LOWER_FREQUENCY }, - { 0x8034104c, 0xffff, "TI XX21/XX11 SD", - SDHCI_QUIRK_FORCE_DMA }, - { 0x05501524, 0xffff, "ENE CB712 SD", - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x05511524, 0xffff, "ENE CB712 SD 2", - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x07501524, 0xffff, "ENE CB714 SD", - SDHCI_QUIRK_RESET_ON_IOS | - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x07511524, 0xffff, "ENE CB714 SD 2", - SDHCI_QUIRK_RESET_ON_IOS | - SDHCI_QUIRK_BROKEN_TIMINGS }, - { 0x410111ab, 0xffff, "Marvell CaFe SD", - SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, - { 0x2381197B, 0xffff, "JMicron JMB38X SD", - SDHCI_QUIRK_32BIT_DMA_SIZE | - SDHCI_QUIRK_RESET_AFTER_REQUEST }, - { 0, 0xffff, NULL, - 0 } -}; - struct sdhci_softc; -struct sdhci_slot { - struct sdhci_softc *sc; - device_t dev; /* Slot device */ - u_char num; /* Slot number */ - u_char opt; /* Slot options */ -#define SDHCI_HAVE_DMA 1 - uint32_t max_clk; /* Max possible freq */ - uint32_t timeout_clk; /* Timeout freq */ - struct resource *mem_res; /* Memory resource */ - int mem_rid; - bus_dma_tag_t dmatag; - bus_dmamap_t dmamap; - u_char *dmamem; - bus_addr_t paddr; /* DMA buffer address */ - struct task card_task; /* Card presence check task */ - struct callout card_callout; /* Card insert delay callout */ - struct mmc_host host; /* Host parameters */ - struct mmc_request *req; /* Current request */ - struct mmc_command *curcmd; /* Current command of current request */ - - uint32_t intmask; /* Current interrupt mask */ - uint32_t clock; /* Current clock freq. */ - size_t offset; /* Data buffer offset */ - uint8_t hostctrl; /* Current host control register */ - u_char power; /* Current power */ - u_char bus_busy; /* Bus busy status */ - u_char cmd_done; /* CMD command part done flag */ - u_char data_done; /* DAT command part done flag */ - u_char flags; /* Request execution flags */ -#define CMD_STARTED 1 -#define STOP_STARTED 2 -#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ - struct mtx mtx; /* Slot mutex */ -}; - struct sdhci_softc { device_t dev; /* Controller device */ - u_int quirks; /* Chip specific quirks */ struct resource *irq_res; /* IRQ resource */ int irq_rid; void *intrhand; /* Interrupt handle */ @@ -160,64 +89,18 @@ static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); -int sdhci_debug; +int sdhci_debug = 0; TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); -static inline uint8_t -RD1(struct sdhci_slot *slot, bus_size_t off) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - return bus_read_1(slot->mem_res, off); -} +#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) +#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) +#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) -static inline void -WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - bus_write_1(slot->mem_res, off, val); -} +#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) +#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) +#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) -static inline uint16_t -RD2(struct sdhci_slot *slot, bus_size_t off) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - return bus_read_2(slot->mem_res, off); -} - -static inline void -WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - bus_write_2(slot->mem_res, off, val); -} - -static inline uint32_t -RD4(struct sdhci_slot *slot, bus_size_t off) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - return bus_read_4(slot->mem_res, off); -} - -static inline void -WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) -{ - bus_barrier(slot->mem_res, 0, 0xFF, - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); - bus_write_4(slot->mem_res, off, val); -} - -/* bus entry points */ -static int sdhci_probe(device_t dev); -static int sdhci_attach(device_t dev); -static int sdhci_detach(device_t dev); -static void sdhci_intr(void *); - static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); static void sdhci_start(struct sdhci_slot *slot); static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); @@ -240,7 +123,7 @@ int retval; retval = printf("%s-slot%d: ", - device_get_nameunit(slot->sc->dev), slot->num); + device_get_nameunit(slot->bus), slot->num); va_start(ap, fmt); retval += vprintf(fmt, ap); @@ -249,16 +132,6 @@ } static void -sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) -{ - if (error != 0) { - printf("getaddr: error %d\n", error); - return; - } - *(bus_addr_t *)arg = segs[0].ds_addr; -} - -static void sdhci_dumpregs(struct sdhci_slot *slot) { slot_printf(slot, @@ -295,7 +168,7 @@ int timeout; uint8_t res; - if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { + if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { if (!(RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) return; @@ -303,7 +176,7 @@ /* Some controllers need this kick or reset won't work. */ if ((mask & SDHCI_RESET_ALL) == 0 && - (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { + (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { uint32_t clock; /* This is to force an update */ @@ -354,28 +227,11 @@ } static void -sdhci_lower_frequency(device_t dev) -{ - - /* Enable SD2.0 mode. */ - pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); - pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); - pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); - - /* - * Some SD/MMC cards don't work with the default base - * clock frequency of 200MHz. Lower it to 50MHz. - */ - pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); - pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); - pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); -} - -static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) { uint32_t res; - uint16_t clk; + uint16_t clk = 0; + uint16_t div; int timeout; if (clock == slot->clock) @@ -387,18 +243,44 @@ /* If no clock requested - left it so. */ if (clock == 0) return; - /* Looking for highest freq <= clock. */ - res = slot->max_clk; - for (clk = 1; clk < 256; clk <<= 1) { - if (res <= clock) - break; - res >>= 1; + if (slot->version < SDHCI_SPEC_300) { + /* Looking for highest freq <= clock. */ + res = slot->max_clk; + for (div = 1; div < 256; div <<= 1) { + if (res <= clock) + break; + res >>= 1; + } + /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ + div >>= 1; + /* Now we have got divider, set it. */ + div <<= SDHCI_DIVIDER_SHIFT; + WR2(slot, SDHCI_CLOCK_CONTROL, div); } - /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ - clk >>= 1; - /* Now we have got divider, set it. */ - clk <<= SDHCI_DIVIDER_SHIFT; + else { + /* Version 3.0 divisors are multiple of two up to 1023*12 */ + if (clock > slot->max_clk) + div = 1; + else { + for (div = 2; div < 1023*2; div += 2) { + if ((slot->max_clk / div) <= clock) + break; + } + div /= 2; + } + div >>= 1; + } + + if (sdhci_debug) + slot_printf(slot, "Divider %d for freq %d (max %d)\n", + div, clock, slot->max_clk); + + /* Now we have got clkider, set it. */ + clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; + clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) + << SDHCI_DIVIDER_HI_SHIFT; WR2(slot, SDHCI_CLOCK_CONTROL, clk); + /* Enable clock. */ clk |= SDHCI_CLOCK_INT_EN; WR2(slot, SDHCI_CLOCK_CONTROL, clk); @@ -427,6 +309,7 @@ if (slot->power == power) return; + slot->power = power; /* Turn off the power. */ @@ -469,7 +352,7 @@ slot->offset += left; /* If we are too fast, broken controllers return zeroes. */ - if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) + if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) DELAY(10); /* Handle unalligned and alligned buffer cases. */ if ((intptr_t)buffer & 3) { @@ -483,7 +366,7 @@ left -= 4; } } else { - bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + bus_read_multi_4(slot->mem_res, SDHCI_BUFFER, (uint32_t *)buffer, left >> 2); left &= 3; } @@ -523,7 +406,7 @@ WR4(slot, SDHCI_BUFFER, data); } } else { - bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, + bus_write_multi_4(slot->mem_res, SDHCI_BUFFER, (uint32_t *)buffer, left >> 2); left &= 3; } @@ -577,7 +460,7 @@ if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { if (slot->dev == NULL) { /* If card is present - attach mmc bus. */ - slot->dev = device_add_child(slot->sc->dev, "mmc", -1); + slot->dev = device_add_child(slot->bus, "mmc", -1); device_set_ivars(slot->dev, slot); SDHCI_UNLOCK(slot); device_probe_and_attach(slot->dev); @@ -589,281 +472,132 @@ device_t d = slot->dev; slot->dev = NULL; SDHCI_UNLOCK(slot); - device_delete_child(slot->sc->dev, d); + device_delete_child(slot->bus, d); } else SDHCI_UNLOCK(slot); } } -static int -sdhci_probe(device_t dev) +int +sdhci_init_slot(device_t dev, struct sdhci_slot *slot) { - uint32_t model; - uint16_t subvendor; - uint8_t class, subclass; - int i, result; - - model = (uint32_t)pci_get_device(dev) << 16; - model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; - subvendor = pci_get_subvendor(dev); - class = pci_get_class(dev); - subclass = pci_get_subclass(dev); - - result = ENXIO; - for (i = 0; sdhci_devices[i].model != 0; i++) { - if (sdhci_devices[i].model == model && - (sdhci_devices[i].subvendor == 0xffff || - sdhci_devices[i].subvendor == subvendor)) { - device_set_desc(dev, sdhci_devices[i].desc); - result = BUS_PROBE_DEFAULT; - break; - } - } - if (result == ENXIO && class == PCIC_BASEPERIPH && - subclass == PCIS_BASEPERIPH_SDHC) { - device_set_desc(dev, "Generic SD HCI"); - result = BUS_PROBE_GENERIC; - } - - return (result); -} + uint32_t caps; -static int -sdhci_attach(device_t dev) -{ - struct sdhci_softc *sc = device_get_softc(dev); - uint32_t model; - uint16_t subvendor; - uint8_t class, subclass, progif; - int err, slots, bar, i; + SDHCI_LOCK_INIT(slot); + slot->num = 0; /* XXX: add slot number */ + slot->bus = dev; - sc->dev = dev; - model = (uint32_t)pci_get_device(dev) << 16; - model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; - subvendor = pci_get_subvendor(dev); - class = pci_get_class(dev); - subclass = pci_get_subclass(dev); - progif = pci_get_progif(dev); - /* Apply chip specific quirks. */ - for (i = 0; sdhci_devices[i].model != 0; i++) { - if (sdhci_devices[i].model == model && - (sdhci_devices[i].subvendor == 0xffff || - sdhci_devices[i].subvendor == subvendor)) { - sc->quirks = sdhci_devices[i].quirks; - break; - } + /* Initialize slot. */ + sdhci_init(slot); + slot->version = (RD2(slot, SDHCI_HOST_VERSION) + >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; + caps = RD4(slot, SDHCI_CAPABILITIES); + /* Calculate base clock frequency. */ + slot->max_clk = + (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; + if (slot->max_clk == 0) { + slot->max_clk = 50; + device_printf(dev, "Hardware doesn't specify base clock " + "frequency.\n"); } - /* Some controllers need to be bumped into the right mode. */ - if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) - sdhci_lower_frequency(dev); - /* Read slots info from PCI registers. */ - slots = pci_read_config(dev, PCI_SLOT_INFO, 1); - bar = PCI_SLOT_INFO_FIRST_BAR(slots); - slots = PCI_SLOT_INFO_SLOTS(slots); - if (slots > 6 || bar > 5) { - device_printf(dev, "Incorrect slots information (%d, %d).\n", - slots, bar); - return (EINVAL); + slot->max_clk *= 1000000; + /* Calculate timeout clock frequency. */ + slot->timeout_clk = + (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; + if (slot->timeout_clk == 0) { + device_printf(dev, "Hardware doesn't specify timeout clock " + "frequency.\n"); } - /* Allocate IRQ. */ - sc->irq_rid = 0; - sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, - RF_SHAREABLE | RF_ACTIVE); - if (sc->irq_res == NULL) { - device_printf(dev, "Can't allocate IRQ\n"); - return (ENOMEM); + if (caps & SDHCI_TIMEOUT_CLK_UNIT) + slot->timeout_clk *= 1000; + + slot->host.f_min = slot->max_clk / 256; + slot->host.f_max = slot->max_clk; + if (1 /*FIXME: SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK*/) + slot->timeout_clk = slot->max_clk / 1000; + slot->host.host_ocr = 0; + caps |= SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; + if (caps & SDHCI_CAN_VDD_330) + slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; + if (caps & SDHCI_CAN_VDD_300) + slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; + if (caps & SDHCI_CAN_VDD_180) + slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; + if (slot->host.host_ocr == 0) { + device_printf(dev, "Hardware doesn't report any " + "support voltages.\n"); } - /* Scan all slots. */ - for (i = 0; i < slots; i++) { - struct sdhci_slot *slot = &sc->slots[sc->num_slots]; - uint32_t caps; + slot->host.caps = MMC_CAP_4_BIT_DATA; + if (caps & SDHCI_CAN_DO_HISPD) + slot->host.caps |= MMC_CAP_HSPEED; + /* Decide if we have usable DMA. */ + if (caps & SDHCI_CAN_DO_DMA) + slot->opt |= SDHCI_HAVE_DMA; - SDHCI_LOCK_INIT(slot); - slot->sc = sc; - slot->num = sc->num_slots; - /* Allocate memory. */ - slot->mem_rid = PCIR_BAR(bar + i); - slot->mem_res = bus_alloc_resource(dev, - SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); - if (slot->mem_res == NULL) { - device_printf(dev, "Can't allocate memory\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Allocate DMA tag. */ - err = bus_dma_tag_create(bus_get_dma_tag(dev), - DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, - BUS_SPACE_MAXADDR, NULL, NULL, - DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, - BUS_DMA_ALLOCNOW, NULL, NULL, - &slot->dmatag); - if (err != 0) { - device_printf(dev, "Can't create DMA tag\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Allocate DMA memory. */ - err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, - BUS_DMA_NOWAIT, &slot->dmamap); - if (err != 0) { - device_printf(dev, "Can't alloc DMA memory\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Map the memory. */ - err = bus_dmamap_load(slot->dmatag, slot->dmamap, - (void *)slot->dmamem, DMA_BLOCK_SIZE, - sdhci_getaddr, &slot->paddr, 0); - if (err != 0 || slot->paddr == 0) { - device_printf(dev, "Can't load DMA memory\n"); - SDHCI_LOCK_DESTROY(slot); - continue; - } - /* Initialize slot. */ - sdhci_init(slot); - caps = RD4(slot, SDHCI_CAPABILITIES); - /* Calculate base clock frequency. */ - slot->max_clk = - (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; - if (slot->max_clk == 0) { - device_printf(dev, "Hardware doesn't specify base clock " - "frequency.\n"); - } - slot->max_clk *= 1000000; - /* Calculate timeout clock frequency. */ - slot->timeout_clk = - (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; - if (slot->timeout_clk == 0) { - device_printf(dev, "Hardware doesn't specify timeout clock " - "frequency.\n"); - } - if (caps & SDHCI_TIMEOUT_CLK_UNIT) - slot->timeout_clk *= 1000; + if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) + slot->opt &= ~SDHCI_HAVE_DMA; + if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) + slot->opt |= SDHCI_HAVE_DMA; - slot->host.f_min = slot->max_clk / 256; - slot->host.f_max = slot->max_clk; - slot->host.host_ocr = 0; - if (caps & SDHCI_CAN_VDD_330) - slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; - if (caps & SDHCI_CAN_VDD_300) - slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; - if (caps & SDHCI_CAN_VDD_180) - slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; - if (slot->host.host_ocr == 0) { - device_printf(dev, "Hardware doesn't report any " - "support voltages.\n"); - } - slot->host.caps = MMC_CAP_4_BIT_DATA; - if (caps & SDHCI_CAN_DO_HISPD) - slot->host.caps |= MMC_CAP_HSPEED; - /* Decide if we have usable DMA. */ - if (caps & SDHCI_CAN_DO_DMA) - slot->opt |= SDHCI_HAVE_DMA; - if (class == PCIC_BASEPERIPH && - subclass == PCIS_BASEPERIPH_SDHC && - progif != PCI_SDHCI_IFDMA) - slot->opt &= ~SDHCI_HAVE_DMA; - if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) - slot->opt &= ~SDHCI_HAVE_DMA; - if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) - slot->opt |= SDHCI_HAVE_DMA; - - if (bootverbose || sdhci_debug) { - slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", - slot->max_clk / 1000000, - (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", - (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", - (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", - (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", - (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); - sdhci_dumpregs(slot); - } - - TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); - callout_init(&slot->card_callout, 1); - sc->num_slots++; + if (bootverbose || sdhci_debug) { + slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", + slot->max_clk / 1000000, + (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", + (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", + (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", + (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", + (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); + sdhci_dumpregs(slot); } - device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); - /* Activate the interrupt */ - err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, - NULL, sdhci_intr, sc, &sc->intrhand); - if (err) - device_printf(dev, "Can't setup IRQ\n"); - pci_enable_busmaster(dev); - /* Process cards detection. */ - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - - sdhci_card_task(slot, 0); - } + + TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); + callout_init(&slot->card_callout, 1); + sdhci_card_task(slot, 0); return (0); } -static int -sdhci_detach(device_t dev) +int +sdhci_cleanup_slot(struct sdhci_slot *slot) { - struct sdhci_softc *sc = device_get_softc(dev); - int i; + device_t d; - bus_teardown_intr(dev, sc->irq_res, sc->intrhand); - bus_release_resource(dev, SYS_RES_IRQ, - sc->irq_rid, sc->irq_res); + callout_drain(&slot->card_callout); + taskqueue_drain(taskqueue_swi_giant, &slot->card_task); - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - device_t d; + SDHCI_LOCK(slot); + d = slot->dev; + slot->dev = NULL; + SDHCI_UNLOCK(slot); + if (d != NULL) + device_delete_child(slot->bus, d); - callout_drain(&slot->card_callout); - taskqueue_drain(taskqueue_swi_giant, &slot->card_task); + SDHCI_LOCK(slot); + sdhci_reset(slot, SDHCI_RESET_ALL); + SDHCI_UNLOCK(slot); + SDHCI_LOCK_DESTROY(slot); - SDHCI_LOCK(slot); - d = slot->dev; - slot->dev = NULL; - SDHCI_UNLOCK(slot); - if (d != NULL) - device_delete_child(dev, d); - - SDHCI_LOCK(slot); - sdhci_reset(slot, SDHCI_RESET_ALL); - SDHCI_UNLOCK(slot); - bus_dmamap_unload(slot->dmatag, slot->dmamap); - bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); - bus_dma_tag_destroy(slot->dmatag); - bus_release_resource(dev, SYS_RES_MEMORY, - slot->mem_rid, slot->mem_res); - SDHCI_LOCK_DESTROY(slot); - } return (0); } -static int -sdhci_suspend(device_t dev) +int +sdhci_generic_suspend(struct sdhci_slot *slot) { - struct sdhci_softc *sc = device_get_softc(dev); - int i, err; + sdhci_reset(slot, SDHCI_RESET_ALL); - err = bus_generic_suspend(dev); - if (err) - return (err); - for (i = 0; i < sc->num_slots; i++) - sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); return (0); } -static int -sdhci_resume(device_t dev) +int +sdhci_generic_resume(struct sdhci_slot *slot) { - struct sdhci_softc *sc = device_get_softc(dev); - int i; + sdhci_init(slot); - for (i = 0; i < sc->num_slots; i++) - sdhci_init(&sc->slots[i]); - return (bus_generic_resume(dev)); + return (0); } -static int -sdhci_update_ios(device_t brdev, device_t reqdev) +int +sdhci_generic_update_ios(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); struct mmc_ios *ios = &slot->host.ios; @@ -887,7 +621,7 @@ slot->hostctrl &= ~SDHCI_CTRL_HISPD; WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); /* Some controllers like reset after bus changes. */ - if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) + if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); SDHCI_UNLOCK(slot); @@ -945,6 +679,7 @@ if ((state & SDHCI_CARD_PRESENT) == 0 || slot->power == 0 || slot->clock == 0) { + printf("NO SD CARD\n"); cmd->error = MMC_ERR_FAILED; slot->req = NULL; slot->curcmd = NULL; @@ -1009,10 +744,8 @@ WR4(slot, SDHCI_ARGUMENT, cmd->arg); /* Set data transfer mode. */ sdhci_set_transfer_mode(slot, cmd->data); - /* Set command flags. */ - WR1(slot, SDHCI_COMMAND_FLAGS, flags); /* Start command. */ - WR1(slot, SDHCI_COMMAND, cmd->opcode); + WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); } static void @@ -1075,12 +808,14 @@ break; } /* Compensate for an off-by-one error in the CaFe chip.*/ - if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) + if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) div++; if (div >= 0xF) { slot_printf(slot, "Timeout too large!\n"); div = 0xE; } + /* FIXME: SDHCI_QUIRK_BROKEN_TIMEOUT_VAL */ + div = 0x0e; WR1(slot, SDHCI_TIMEOUT_CONTROL, div); if (data == NULL) @@ -1090,11 +825,11 @@ if ((slot->opt & SDHCI_HAVE_DMA)) slot->flags |= SDHCI_USE_DMA; /* If data is small, broken DMA may return zeroes instead of data, */ - if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && + if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && (data->len <= 512)) slot->flags &= ~SDHCI_USE_DMA; /* Some controllers require even block sizes. */ - if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && + if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && ((data->len) & 0x3)) slot->flags &= ~SDHCI_USE_DMA; /* Load DMA buffer. */ @@ -1183,7 +918,7 @@ if (sdhci_debug > 1) slot_printf(slot, "result: %d\n", req->cmd->error); if (!req->cmd->error && - (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { + (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { sdhci_reset(slot, SDHCI_RESET_CMD); sdhci_reset(slot, SDHCI_RESET_DATA); } @@ -1194,8 +929,8 @@ req->done(req); } -static int -sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) +int +sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) { struct sdhci_slot *slot = device_get_ivars(reqdev); @@ -1216,15 +951,15 @@ SDHCI_UNLOCK(slot); if (dumping) { while (slot->req != NULL) { - sdhci_intr(slot->sc); + /* XXX: Fixme intr here? */ DELAY(10); } } return (0); } -static int -sdhci_get_ro(device_t brdev, device_t reqdev) +int +sdhci_generic_get_ro(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); uint32_t val; @@ -1235,8 +970,8 @@ return (!(val & SDHCI_WRITE_PROTECT)); } -static int -sdhci_acquire_host(device_t brdev, device_t reqdev) +int +sdhci_generic_acquire_host(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); int err = 0; @@ -1251,8 +986,8 @@ return (err); } -static int -sdhci_release_host(device_t brdev, device_t reqdev) +int +sdhci_generic_release_host(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); @@ -1322,8 +1057,9 @@ } /* Handle PIO interrupt. */ - if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { sdhci_transfer_pio(slot); + } /* Handle DMA border. */ if (intmask & SDHCI_INT_DMA_END) { struct mmc_data *data = slot->curcmd->data; @@ -1382,85 +1118,79 @@ sdhci_reset(slot, SDHCI_RESET_CMD); } -static void -sdhci_intr(void *arg) +void +sdhci_generic_intr(struct sdhci_slot *slot) { - struct sdhci_softc *sc = (struct sdhci_softc *)arg; - int i; + uint32_t intmask; + + SDHCI_LOCK(slot); + /* Read slot interrupt status. */ + intmask = RD4(slot, SDHCI_INT_STATUS); + if (intmask == 0 || intmask == 0xffffffff) { + SDHCI_UNLOCK(slot); + return; + } + if (sdhci_debug > 2) + slot_printf(slot, "Interrupt %#x\n", intmask); - for (i = 0; i < sc->num_slots; i++) { - struct sdhci_slot *slot = &sc->slots[i]; - uint32_t intmask; - - SDHCI_LOCK(slot); - /* Read slot interrupt status. */ - intmask = RD4(slot, SDHCI_INT_STATUS); - if (intmask == 0 || intmask == 0xffffffff) { - SDHCI_UNLOCK(slot); - continue; - } - if (sdhci_debug > 2) - slot_printf(slot, "Interrupt %#x\n", intmask); + /* Handle card presence interrupts. */ + if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + WR4(slot, SDHCI_INT_STATUS, intmask & + (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); - /* Handle card presence interrupts. */ - if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { - WR4(slot, SDHCI_INT_STATUS, intmask & - (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); - - if (intmask & SDHCI_INT_CARD_REMOVE) { - if (bootverbose || sdhci_debug) - slot_printf(slot, "Card removed\n"); - callout_stop(&slot->card_callout); - taskqueue_enqueue(taskqueue_swi_giant, - &slot->card_task); - } - if (intmask & SDHCI_INT_CARD_INSERT) { - if (bootverbose || sdhci_debug) - slot_printf(slot, "Card inserted\n"); - callout_reset(&slot->card_callout, hz / 2, - sdhci_card_delay, slot); - } - intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); + if (intmask & SDHCI_INT_CARD_REMOVE) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card removed\n"); + callout_stop(&slot->card_callout); + taskqueue_enqueue(taskqueue_swi_giant, + &slot->card_task); } - /* Handle command interrupts. */ - if (intmask & SDHCI_INT_CMD_MASK) { - WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); - sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); + if (intmask & SDHCI_INT_CARD_INSERT) { + if (bootverbose || sdhci_debug) + slot_printf(slot, "Card inserted\n"); + callout_reset(&slot->card_callout, hz / 2, + sdhci_card_delay, slot); } - /* Handle data interrupts. */ - if (intmask & SDHCI_INT_DATA_MASK) { - WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); - sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); - } - /* Handle AutoCMD12 error interrupt. */ - if (intmask & SDHCI_INT_ACMD12ERR) { - WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); - sdhci_acmd_irq(slot); - } - intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); - intmask &= ~SDHCI_INT_ACMD12ERR; - intmask &= ~SDHCI_INT_ERROR; - /* Handle bus power interrupt. */ - if (intmask & SDHCI_INT_BUS_POWER) { - WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); - slot_printf(slot, - "Card is consuming too much power!\n"); - intmask &= ~SDHCI_INT_BUS_POWER; - } - /* The rest is unknown. */ - if (intmask) { - WR4(slot, SDHCI_INT_STATUS, intmask); - slot_printf(slot, "Unexpected interrupt 0x%08x.\n", - intmask); - sdhci_dumpregs(slot); - } - - SDHCI_UNLOCK(slot); + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); } + /* Handle command interrupts. */ + if (intmask & SDHCI_INT_CMD_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); + sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); + } + /* Handle data interrupts. */ + if (intmask & SDHCI_INT_DATA_MASK) { + WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); + sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); + } + /* Handle AutoCMD12 error interrupt. */ + if (intmask & SDHCI_INT_ACMD12ERR) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); + sdhci_acmd_irq(slot); + } + intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); + intmask &= ~SDHCI_INT_ACMD12ERR; + intmask &= ~SDHCI_INT_ERROR; + /* Handle bus power interrupt. */ + if (intmask & SDHCI_INT_BUS_POWER) { + WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); + slot_printf(slot, + "Card is consuming too much power!\n"); + intmask &= ~SDHCI_INT_BUS_POWER; + } + /* The rest is unknown. */ + if (intmask) { + WR4(slot, SDHCI_INT_STATUS, intmask); + slot_printf(slot, "Unexpected interrupt 0x%08x.\n", + intmask); + sdhci_dumpregs(slot); + } + + SDHCI_UNLOCK(slot); } -static int -sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) +int +sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct sdhci_slot *slot = device_get_ivars(child); @@ -1513,8 +1243,8 @@ return (0); } -static int -sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) +int +sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { struct sdhci_slot *slot = device_get_ivars(child); @@ -1569,18 +1299,14 @@ return (0); } +#if 0 static device_method_t sdhci_methods[] = { /* device_if */ - DEVMETHOD(device_probe, sdhci_probe), DEVMETHOD(device_attach, sdhci_attach), DEVMETHOD(device_detach, sdhci_detach), DEVMETHOD(device_suspend, sdhci_suspend), DEVMETHOD(device_resume, sdhci_resume), - /* Bus interface */ - DEVMETHOD(bus_read_ivar, sdhci_read_ivar), - DEVMETHOD(bus_write_ivar, sdhci_write_ivar), - /* mmcbr_if */ DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), DEVMETHOD(mmcbr_request, sdhci_request), @@ -1590,13 +1316,4 @@ {0, 0}, }; - -static driver_t sdhci_driver = { - "sdhci", - sdhci_methods, - sizeof(struct sdhci_softc), -}; -static devclass_t sdhci_devclass; - - -DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); +#endif