Index: conf/files.arm64
===================================================================
--- conf/files.arm64	(revision 315175)
+++ conf/files.arm64	(working copy)
@@ -163,6 +163,7 @@
 dev/pci/pci_host_generic_fdt.c	optional	pci fdt
 dev/psci/psci.c			optional	psci
 dev/psci/psci_arm64.S		optional	psci
+dev/sdhci/fsl_sdhci.c		optional	sdhci
 dev/uart/uart_cpu_arm64.c	optional	uart
 dev/uart/uart_dev_pl011.c	optional	uart pl011
 dev/usb/controller/dwc_otg_hisi.c optional	dwcotg fdt soc_hisi_hi6220
Index: dev/sdhci/fsl_sdhci.c
===================================================================
--- dev/sdhci/fsl_sdhci.c	(revision 315175)
+++ dev/sdhci/fsl_sdhci.c	(working copy)
@@ -763,7 +763,7 @@
 	return (sdhci_fdt_gpio_get_present(sc->gpio));
 }
 
-#ifdef __powerpc__
+#if defined(__powerpc__) || defined(__aarch64__)
 static uint32_t
 fsl_sdhci_get_platform_clock(device_t dev)
 {
@@ -817,7 +817,7 @@
 {
 	struct fsl_sdhci_softc *sc = device_get_softc(dev);
 	int rid, err;
-#ifdef __powerpc__
+#if defined(__powerpc__) || defined(__aarch64__)
 	phandle_t node;
 	uint32_t protctl;
 #endif
@@ -886,7 +886,7 @@
 	 * We read in native byte order in the main driver, but the register
 	 * defaults to little endian.
 	 */
-#ifdef __powerpc__
+#if defined(__powerpc__) || defined(__aarch64__)
 	sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev);
 #else
 	sc->baseclk_hz = imx_ccm_sdhci_hz();
@@ -899,7 +899,7 @@
 	 */
 	sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
 
-#ifdef __powerpc__
+#if defined(__powerpc__) || defined(__aarch64__)
 	node = ofw_bus_get_node(dev);
 	/* Default to big-endian on powerpc */
 	protctl = RD4(sc, SDHC_PROT_CTRL);