Index: sys/arm/conf/BEAGLEBONE =================================================================== --- sys/arm/conf/BEAGLEBONE (revision 277406) +++ sys/arm/conf/BEAGLEBONE (working copy) @@ -160,4 +160,13 @@ # Flattened Device Tree options FDT # Configure using FDT/DTB data options FDT_DTB_STATIC -makeoptions FDT_DTS_FILE=beaglebone.dts +makeoptions FDT_DTS_FILE=beaglebone-black.dts + +# Comment following lines for boot console on serial port +device sc +options SC_DFLT_FONT # compile font in +makeoptions SC_DFLT_FONT=cp437 +device ums +device ukbd +device kbdmux +device tda19988 Index: sys/arm/ti/ti_i2c.c =================================================================== --- sys/arm/ti/ti_i2c.c (revision 277406) +++ sys/arm/ti/ti_i2c.c (working copy) @@ -442,7 +442,7 @@ ti_i2c_write_2(sc, I2C_REG_CON, reg); /* Wait for an event. */ - err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", hz); + err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", 0); if (err == 0) err = sc->sc_error; Index: sys/boot/fdt/dts/arm/beaglebone-black.dts =================================================================== --- sys/boot/fdt/dts/arm/beaglebone-black.dts (revision 277406) +++ sys/boot/fdt/dts/arm/beaglebone-black.dts (working copy) @@ -110,18 +110,30 @@ "GPMC_BEn1", "gpio1_28", "input_pulldown", "GPMC_CSn0", "gpio1_29", "input_pulldown", "GPMC_CLK", "gpio2_1", "input_pulldown", - "LCD_DATA0", "gpio2_6", "input_pulldown", - "LCD_DATA1", "gpio2_7", "input_pulldown", - "LCD_DATA2", "gpio2_8", "input_pulldown", - "LCD_DATA3", "gpio2_9", "input_pulldown", - "LCD_DATA4", "gpio2_10", "input_pulldown", - "LCD_DATA5", "gpio2_11", "input_pulldown", - "LCD_DATA6", "gpio2_12", "input_pulldown", - "LCD_DATA7", "gpio2_13", "input_pulldown", - "LCD_VSYNC", "gpio2_22", "input_pulldown", - "LCD_HSYNC", "gpio2_23", "input_pulldown", - "LCD_PCLK", "gpio2_24", "input_pulldown", - "LCD_AC_BIAS_EN", "gpio2_25", "input_pulldown", + + /* HDMI */ + "LCD_DATA0", "lcd_data0", "output", + "LCD_DATA1", "lcd_data1", "output", + "LCD_DATA2", "lcd_data2", "output", + "LCD_DATA3", "lcd_data3", "output", + "LCD_DATA4", "lcd_data4", "output", + "LCD_DATA5", "lcd_data5", "output", + "LCD_DATA6", "lcd_data6", "output", + "LCD_DATA7", "lcd_data7", "output", + "LCD_DATA8", "lcd_data8", "output", + "LCD_DATA9", "lcd_data9", "output", + "LCD_DATA10", "lcd_data10", "output", + "LCD_DATA11", "lcd_data11", "output", + "LCD_DATA12", "lcd_data12", "output", + "LCD_DATA13", "lcd_data13", "output", + "LCD_DATA14", "lcd_data14", "output", + "LCD_DATA15", "lcd_data15", "output", + "LCD_VSYNC", "lcd_vsync", "output", + "LCD_HSYNC", "lcd_hsync", "output", + "LCD_PCLK", "lcd_pclk", "output", + "LCD_AC_BIAS_EN", "lcd_ac_bias_en", "output", + "XDMA_EVENT_INTR0", "clkout1", "output", + "MCASP0_FSR", "gpio3_19", "input_pulldown", "MCASP0_AHCLKX", "gpio3_21", "input_pulldown", /* TIMERs */ @@ -139,6 +151,37 @@ "GPMC_AD9", "ehrpwm2B", "output"; }; + lcd@4830e000 { + panel_name = "640x480at60Hz"; + panel_width = <640>; + panel_height = <480>; + panel_hfp = <16>; + panel_hbp = <48>; + panel_hsw = <96>; + panel_vfp = <10>; + panel_vbp = <33>; + panel_vsw = <2>; + panel_pxl_clk = <25175000>; + panel_invert_pxl_clk = <0>; + panel_type = <1>; /* Active or passive, compatibility */ + panel_max_bpp = <16>; /* compatibility */ + panel_min_bpp = <16>; /* compatibility */ + panel_shade = <1>; /* compatibility */ + ac_bias = <255>; + ac_bias_intrpt = <0>; + dma_burst_sz = <16>; + bpp = <16>; + fdd = <128>; + tft_alt_mode = <0>; /* compatiblity */ + stn_565_mode = <0>; /* compatibility */ + mono_8bit_mode = <0>; /* compatibilty */ + invert_line_clock = <0>; + invert_frm_clock = <1>; + sync_edge = <0>; + sync_ctrl = <1>; + raster_order = <0>; /* compatibity */ + }; + mmchs1@481D8000 { bus-width = <8>; status = "okay"; @@ -150,6 +193,11 @@ compatible = "ti,am335x-pmic"; reg = <0x48>; }; + + tda19988@50 { + compatible = "nxp,tda19988"; + reg = <0xe0>; + }; }; }; Index: sys/conf/files =================================================================== --- sys/conf/files (revision 277406) +++ sys/conf/files (working copy) @@ -1452,6 +1452,7 @@ dev/iicbus/ds1374.c optional ds1374 dev/iicbus/ds1672.c optional ds1672 dev/iicbus/icee.c optional icee +dev/iicbus/tda19988.c optional tda19988 dev/iicbus/if_ic.c optional ic dev/iicbus/iic.c optional iic dev/iicbus/iicbb.c optional iicbb Index: sys/dev/iicbus/tda19988.c =================================================================== --- sys/dev/iicbus/tda19988.c (revision 0) +++ sys/dev/iicbus/tda19988.c (working copy) @@ -0,0 +1,846 @@ +/*- + * Copyright (c) 2015 Oleksandr Tymoshenko + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); +/* +* NXP TDA19988 HDMI encoder +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include "iicbus_if.h" + +#define MKREG(page, addr) (((page) << 8) | (addr)) + +#define REGPAGE(reg) (((reg) >> 8) & 0xff) +#define REGADDR(reg) ((reg) & 0xff) + +#define TDA_VERSION MKREG(0x00, 0x00) +#define TDA_MAIN_CNTRL0 MKREG(0x00, 0x01) +#define MAIN_CNTRL0_SR (1 << 0) +#define TDA_VERSION_MSB MKREG(0x00, 0x02) +#define TDA_SOFTRESET MKREG(0x00, 0x0a) +#define SOFTRESET_I2C (1 << 1) +#define SOFTRESET_AUDIO (1 << 0) +#define TDA_DDC_CTRL MKREG(0x00, 0x0b) +#define DDC_ENABLE 0 +#define TDA_CCLK MKREG(0x00, 0x0c) +#define CCLK_ENABLE 1 +#define TDA_INT_FLAGS_2 MKREG(0x00, 0x11) +#define INT_FLAGS_2_EDID_BLK_RD (1 << 1) + +#define TDA_VIP_CNTRL_0 MKREG(0x00, 0x20) +#define TDA_VIP_CNTRL_1 MKREG(0x00, 0x21) +#define TDA_VIP_CNTRL_2 MKREG(0x00, 0x22) +#define TDA_VIP_CNTRL_3 MKREG(0x00, 0x23) +#define VIP_CNTRL_3_SYNC_HS (2 << 4) +#define VIP_CNTRL_3_V_TGL (1 << 2) +#define VIP_CNTRL_3_H_TGL (1 << 1) + +#define TDA_VIP_CNTRL_4 MKREG(0x00, 0x24) +#define VIP_CNTRL_4_BLANKIT_NDE (0 << 2) +#define VIP_CNTRL_4_BLANKIT_HS_VS (1 << 2) +#define VIP_CNTRL_4_BLANKIT_NHS_VS (2 << 2) +#define VIP_CNTRL_4_BLANKIT_HE_VE (3 << 2) +#define VIP_CNTRL_4_BLC_NONE (0 << 0) +#define VIP_CNTRL_4_BLC_RGB444 (1 << 0) +#define VIP_CNTRL_4_BLC_YUV444 (2 << 0) +#define VIP_CNTRL_4_BLC_YUV422 (3 << 0) +#define TDA_VIP_CNTRL_5 MKREG(0x00, 0x25) +#define VIP_CNTRL_5_SP_CNT(n) (((n) & 3) << 1) +#define TDA_MUX_VP_VIP_OUT MKREG(0x00, 0x27) +#define TDA_MAT_CONTRL MKREG(0x00, 0x80) +#define MAT_CONTRL_MAT_BP (1 << 2) +#define TDA_VIDFORMAT MKREG(0x00, 0xa0) +#define TDA_REFPIX_MSB MKREG(0x00, 0xa1) +#define TDA_REFPIX_LSB MKREG(0x00, 0xa2) +#define TDA_REFLINE_MSB MKREG(0x00, 0xa3) +#define TDA_REFLINE_LSB MKREG(0x00, 0xa4) +#define TDA_NPIX_MSB MKREG(0x00, 0xa5) +#define TDA_NPIX_LSB MKREG(0x00, 0xa6) +#define TDA_NLINE_MSB MKREG(0x00, 0xa7) +#define TDA_NLINE_LSB MKREG(0x00, 0xa8) +#define TDA_VS_LINE_STRT_1_MSB MKREG(0x00, 0xa9) +#define TDA_VS_LINE_STRT_1_LSB MKREG(0x00, 0xaa) +#define TDA_VS_PIX_STRT_1_MSB MKREG(0x00, 0xab) +#define TDA_VS_PIX_STRT_1_LSB MKREG(0x00, 0xac) +#define TDA_VS_LINE_END_1_MSB MKREG(0x00, 0xad) +#define TDA_VS_LINE_END_1_LSB MKREG(0x00, 0xae) +#define TDA_VS_PIX_END_1_MSB MKREG(0x00, 0xaf) +#define TDA_VS_PIX_END_1_LSB MKREG(0x00, 0xb0) +#define TDA_VS_LINE_STRT_2_MSB MKREG(0x00, 0xb1) +#define TDA_VS_LINE_STRT_2_LSB MKREG(0x00, 0xb2) +#define TDA_VS_PIX_STRT_2_MSB MKREG(0x00, 0xb3) +#define TDA_VS_PIX_STRT_2_LSB MKREG(0x00, 0xb4) +#define TDA_VS_LINE_END_2_MSB MKREG(0x00, 0xb5) +#define TDA_VS_LINE_END_2_LSB MKREG(0x00, 0xb6) +#define TDA_VS_PIX_END_2_MSB MKREG(0x00, 0xb7) +#define TDA_VS_PIX_END_2_LSB MKREG(0x00, 0xb8) +#define TDA_HS_PIX_START_MSB MKREG(0x00, 0xb9) +#define TDA_HS_PIX_START_LSB MKREG(0x00, 0xba) +#define TDA_HS_PIX_STOP_MSB MKREG(0x00, 0xbb) +#define TDA_HS_PIX_STOP_LSB MKREG(0x00, 0xbc) +#define TDA_VWIN_START_1_MSB MKREG(0x00, 0xbd) +#define TDA_VWIN_START_1_LSB MKREG(0x00, 0xbe) +#define TDA_VWIN_END_1_MSB MKREG(0x00, 0xbf) +#define TDA_VWIN_END_1_LSB MKREG(0x00, 0xc0) +#define TDA_VWIN_START_2_MSB MKREG(0x00, 0xc1) +#define TDA_VWIN_START_2_LSB MKREG(0x00, 0xc2) +#define TDA_VWIN_END_2_MSB MKREG(0x00, 0xc3) +#define TDA_VWIN_END_2_LSB MKREG(0x00, 0xc4) +#define TDA_DE_START_MSB MKREG(0x00, 0xc5) +#define TDA_DE_START_LSB MKREG(0x00, 0xc6) +#define TDA_DE_STOP_MSB MKREG(0x00, 0xc7) +#define TDA_DE_STOP_LSB MKREG(0x00, 0xc8) + +#define TDA_TBG_CNTRL_0 MKREG(0x00, 0xca) +#define TBG_CNTRL_0_SYNC_ONCE (1 << 7) +#define TBG_CNTRL_0_SYNC_MTHD (1 << 6) + +#define TDA_TBG_CNTRL_1 MKREG(0x00, 0xcb) +#define TBG_CNTRL_1_DWIN_DIS (1 << 6) +#define TBG_CNTRL_1_TGL_EN (1 << 2) +#define TBG_CNTRL_1_V_TGL (1 << 1) +#define TBG_CNTRL_1_H_TGL (1 << 0) + +#define TDA_HVF_CNTRL_0 MKREG(0x00, 0xe4) +#define HVF_CNTRL_0_PREFIL_NONE (0 << 2) +#define HVF_CNTRL_0_INTPOL_BYPASS (0 << 0) +#define TDA_HVF_CNTRL_1 MKREG(0x00, 0xe5) +#define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) +#define HVF_CNTRL_1_VQR_FULL HVF_CNTRL_1_VQR(0) +#define TDA_ENABLE_SPACE MKREG(0x00, 0xd6) +#define TDA_RPT_CNTRL MKREG(0x00, 0xf0) + +#define TDA_PLL_SERIAL_1 MKREG(0x02, 0x00) +#define PLL_SERIAL_1_SRL_MAN_IP (1 << 6) +#define TDA_PLL_SERIAL_2 MKREG(0x02, 0x01) +#define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) +#define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 0x3) << 0) +#define TDA_PLL_SERIAL_3 MKREG(0x02, 0x02) +#define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) +#define PLL_SERIAL_3_SRL_DE (1 << 2) +#define PLL_SERIAL_3_SRL_CCIR (1 << 0) +#define TDA_SERIALIZER MKREG(0x02, 0x03) +#define TDA_BUFFER_OUT MKREG(0x02, 0x04) +#define TDA_PLL_SCG1 MKREG(0x02, 0x05) +#define TDA_PLL_SCG2 MKREG(0x02, 0x06) +#define TDA_PLL_SCGN1 MKREG(0x02, 0x07) +#define TDA_PLL_SCGN2 MKREG(0x02, 0x08) +#define TDA_PLL_SCGR1 MKREG(0x02, 0x09) +#define TDA_PLL_SCGR2 MKREG(0x02, 0x0a) + +#define TDA_SEL_CLK MKREG(0x02, 0x11) +#define SEL_CLK_ENA_SC_CLK (1 << 3) +#define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) +#define SEL_CLK_SEL_CLK1 (1 << 0) +#define TDA_ANA_GENERAL MKREG(0x02, 0x12) + +#define TDA_EDID_DATA0 MKREG(0x09, 0x00) +#define TDA_EDID_CTRL MKREG(0x09, 0xfa) +#define TDA_DDC_ADDR MKREG(0x09, 0xfb) +#define TDA_DDC_OFFS MKREG(0x09, 0xfc) +#define TDA_DDC_SEGM_ADDR MKREG(0x09, 0xfd) +#define TDA_DDC_SEGM MKREG(0x09, 0xfe) + +#define TDA_IF_VSP MKREG(0x10, 0x20) +#define TDA_IF_AVI MKREG(0x10, 0x40) +#define TDA_IF_SPD MKREG(0x10, 0x60) +#define TDA_IF_AUD MKREG(0x10, 0x80) +#define TDA_IF_MPS MKREG(0x10, 0xa0) + +#define TDA_ENC_CNTRL MKREG(0x11, 0x0d) +#define ENC_CNTRL_DVI_MODE (0 << 2) +#define ENC_CNTRL_HDMI_MODE (1 << 2) +#define TDA_DIP_IF_FLAGS MKREG(0x11, 0x0f) +#define DIP_IF_FLAGS_IF5 (1 << 5) +#define DIP_IF_FLAGS_IF4 (1 << 4) +#define DIP_IF_FLAGS_IF3 (1 << 3) +#define DIP_IF_FLAGS_IF2 (1 << 2) /* AVI IF on page 10h */ +#define DIP_IF_FLAGS_IF1 (1 << 1) + + +#define TDA_TX3 MKREG(0x12, 0x9a) +#define TDA_TX4 MKREG(0x12, 0x9b) +#define TX4_PD_RAM (1 << 1) +#define TDA_HDCP_TX33 MKREG(0x12, 0xb8) +#define HDCP_TX33_HDMI (1 << 1) + +#define TDA_CURPAGE_ADDR 0xff + +#define TDA_CEC_ENAMODS 0xff +#define ENAMODS_RXSENS (1 << 2) +#define ENAMODS_HDMI (1 << 1) +#define TDA_CEC_FRO_IM_CLK_CTRL 0xfb +#define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) +#define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) + +/* EDID reading */ +#define EDID_LENGTH 0x80 +#define MAX_READ_ATTEMPTS 100 + +/* EDID fields */ +#define EDID_MODES0 35 +#define EDID_MODES1 36 +#define EDID_TIMING_START 38 +#define EDID_TIMING_END 54 +#define EDID_TIMING_X(v) (((v) + 31) * 8) +#define EDID_FREQ(v) (((v) & 0x3f) + 60) +#define EDID_RATIO(v) (((v) >> 6) & 0x3) +#define EDID_RATIO_10x16 0 +#define EDID_RATIO_3x4 1 +#define EDID_RATIO_4x5 2 +#define EDID_RATIO_9x16 3 + +#define MODES_ARRAY_SIZE 8 +static char *edid_modes0[MODES_ARRAY_SIZE] = { + "800x600 @ 60 Hz", + "800x600 @ 56 Hz", + "640x480 @ 75 Hz", + "640x480 @ 72 Hz", + "640x480 @ 67 Hz", + "640x480 @ 60 Hz", + "720x400 @ 88 Hz", + "720x400 @ 70 Hz" +}; + +static char *edid_modes1[MODES_ARRAY_SIZE] = { + "1280x1024 @ 75 Hz", + "1024x768 @ 75 Hz", + "1024x768 @ 72 Hz", + "1024x768 @ 60 Hz", + "1024x768i @ 87 Hz", + "832x624 @ 75 Hz", + "800x600 @ 75 Hz", + "800x600 @ 72 Hz" +}; + +struct drm_display_mode { + char name[32]; + + unsigned int type; + + /* Proposed mode values */ + int clock; /* in kHz */ + int hdisplay; + int hsync_start; + int hsync_end; + int htotal; + int hskew; + int vdisplay; + int vsync_start; + int vsync_end; + int vtotal; + int vscan; + unsigned int flags; +}; + +#define DRM_MODE_FLAG_NHSYNC (1 << 0) +#define DRM_MODE_FLAG_NVSYNC (1 << 1) +#define DRM_MODE_FLAG_INTERLACE (1 << 2) +#define DRM_MODE_FLAG_HSKEW (1 << 3) + +#define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \ + .name = nm, .type = (t), .clock = (c), \ + .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ + .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \ + .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ + .vscan = (vs), .flags = (f) + +/* + * This is standard 640x480@60Hz mode timing with HSKEW to + * compensate for inability of TI LCDC to generate VESA timing: TDA19988 + * detects frame start by deecting rising VSYNC and rising HSYNC signals but + * LCDC can not provide it + */ +static struct drm_display_mode mode_std640x480 = + { DRM_MODE("640x480", 0, 25175, 640, 656, + 752, 800, (752 - 656), 480, 490, 492, 525, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_HSKEW) }; + +#define TDA19988 0x0301 + +struct tda19988_softc { + device_t sc_dev; + uint32_t sc_addr; + uint32_t sc_cec_addr; + uint16_t sc_version; + struct intr_config_hook enum_hook; + int sc_current_page; + uint8_t sc_edid[EDID_LENGTH]; +}; + +static int +tda19988_set_page(struct tda19988_softc *sc, uint8_t page) +{ + uint8_t addr = TDA_CURPAGE_ADDR; + uint8_t cmd[2]; + int result; + struct iic_msg msg[] = { + { sc->sc_addr, IIC_M_WR, 2, cmd }, + }; + + cmd[0] = addr; + cmd[1] = page; + + result = (iicbus_transfer(sc->sc_dev, msg, 1)); + if (result) + printf("tda19988_set_page failed: %d\n", result); + else + sc->sc_current_page = page; + + return (result); +} + +static int +tda19988_cec_read(struct tda19988_softc *sc, uint8_t addr, uint8_t *data) +{ + int result; + struct iic_msg msg[] = { + { sc->sc_cec_addr, IIC_M_WR, 1, &addr }, + { sc->sc_cec_addr, IIC_M_RD, 1, data }, + }; + + result = iicbus_transfer(sc->sc_dev, msg, 2); + if (result) + printf("tda19988_cec_read failed: %d\n", result); + return (result); +} + +static int +tda19988_cec_write(struct tda19988_softc *sc, uint8_t address, uint8_t data) +{ + uint8_t cmd[2]; + int result; + struct iic_msg msg[] = { + { sc->sc_cec_addr, IIC_M_WR, 2, cmd }, + }; + + cmd[0] = address; + cmd[1] = data; + + result = iicbus_transfer(sc->sc_dev, msg, 1); + if (result) + printf("tda19988_cec_write failed: %d\n", result); + return (result); +} + +static int +tda19988_block_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data, int len) +{ + uint8_t reg; + int result; + struct iic_msg msg[] = { + { sc->sc_addr, IIC_M_WR, 1, ® }, + { sc->sc_addr, IIC_M_RD, len, data }, + }; + + reg = REGADDR(addr); + + if (sc->sc_current_page != REGPAGE(addr)) + tda19988_set_page(sc, REGPAGE(addr)); + + result = (iicbus_transfer(sc->sc_dev, msg, 2)); + if (result) + device_printf(sc->sc_dev, "tda19988_block_read failed: %d\n", result); + return (result); +} + + +static int +tda19988_reg_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data) +{ + uint8_t reg; + int result; + struct iic_msg msg[] = { + { sc->sc_addr, IIC_M_WR, 1, ® }, + { sc->sc_addr, IIC_M_RD, 1, data }, + }; + + reg = REGADDR(addr); + + if (sc->sc_current_page != REGPAGE(addr)) + tda19988_set_page(sc, REGPAGE(addr)); + + result = (iicbus_transfer(sc->sc_dev, msg, 2)); + if (result) + device_printf(sc->sc_dev, "tda19988_reg_read failed: %d\n", result); + return (result); +} + +static int +tda19988_reg_write(struct tda19988_softc *sc, uint16_t address, uint8_t data) +{ + uint8_t cmd[2]; + int result; + struct iic_msg msg[] = { + { sc->sc_addr, IIC_M_WR, 2, cmd }, + }; + + cmd[0] = REGADDR(address); + cmd[1] = data; + + if (sc->sc_current_page != REGPAGE(address)) + tda19988_set_page(sc, REGPAGE(address)); + + result = iicbus_transfer(sc->sc_dev, msg, 1); + if (result) + device_printf(sc->sc_dev, "tda19988_reg_write failed: %d\n", result); + + return (result); +} + +static int +tda19988_reg_write2(struct tda19988_softc *sc, uint16_t address, uint16_t data) +{ + uint8_t cmd[3]; + int result; + struct iic_msg msg[] = { + { sc->sc_addr, IIC_M_WR, 3, cmd }, + }; + + cmd[0] = REGADDR(address); + cmd[1] = (data >> 8); + cmd[2] = (data & 0xff); + + if (sc->sc_current_page != REGPAGE(address)) + tda19988_set_page(sc, REGPAGE(address)); + + result = iicbus_transfer(sc->sc_dev, msg, 1); + if (result) + device_printf(sc->sc_dev, "tda19988_reg_write2 failed: %d\n", result); + + return (result); +} + +static void +tda19988_reg_set(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) +{ + uint8_t data; + + tda19988_reg_read(sc, addr, &data); + data |= flags; + tda19988_reg_write(sc, addr, data); +} + +static void +tda19988_reg_clear(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) +{ + uint8_t data; + + tda19988_reg_read(sc, addr, &data); + data &= ~flags; + tda19988_reg_write(sc, addr, data); +} + +static int +tda19988_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "nxp,tda19988")) + return (ENXIO); + + return (BUS_PROBE_DEFAULT); +} + +static void +tda19988_init_encoder(struct tda19988_softc *sc, struct drm_display_mode *mode) +{ + uint16_t ref_pix, ref_line, n_pix, n_line; + uint16_t hs_pix_start, hs_pix_stop; + uint16_t vs1_pix_start, vs1_pix_stop; + uint16_t vs1_line_start, vs1_line_end; + uint16_t vs2_pix_start, vs2_pix_stop; + uint16_t vs2_line_start, vs2_line_end; + uint16_t vwin1_line_start, vwin1_line_end; + uint16_t vwin2_line_start, vwin2_line_end; + uint16_t de_start, de_stop; + uint8_t reg, div; + + n_pix = mode->htotal; + n_line = mode->vtotal; + + hs_pix_stop = mode->hsync_end - mode->hdisplay; + hs_pix_start = mode->hsync_start - mode->hdisplay; + + de_stop = mode->htotal; + de_start = mode->htotal - mode->hdisplay; + ref_pix = hs_pix_start + 3; + + if (mode->flags & DRM_MODE_FLAG_HSKEW) + ref_pix += mode->hskew; + + if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { + ref_line = 1 + mode->vsync_start - mode->vdisplay; + vwin1_line_start = mode->vtotal - mode->vdisplay - 1; + vwin1_line_end = vwin1_line_start + mode->vdisplay; + + vs1_pix_start = vs1_pix_stop = hs_pix_start; + vs1_line_start = mode->vsync_start - mode->vdisplay; + vs1_line_end = vs1_line_start + mode->vsync_end - mode->vsync_start; + + vwin2_line_start = vwin2_line_end = 0; + vs2_pix_start = vs2_pix_stop = 0; + vs2_line_start = vs2_line_end = 0; + } else { + ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; + vwin1_line_start = (mode->vtotal - mode->vdisplay)/2; + vwin1_line_end = vwin1_line_start + mode->vdisplay/2; + + vs1_pix_start = vs1_pix_stop = hs_pix_start; + vs1_line_start = (mode->vsync_start - mode->vdisplay)/2; + vs1_line_end = vs1_line_start + (mode->vsync_end - mode->vsync_start)/2; + + vwin2_line_start = vwin1_line_start + mode->vtotal/2; + vwin2_line_end = vwin2_line_start + mode->vdisplay/2; + + vs2_pix_start = vs2_pix_stop = hs_pix_start + mode->htotal/2; + vs2_line_start = vs1_line_start + mode->vtotal/2 ; + vs2_line_end = vs2_line_start + (mode->vsync_end - mode->vsync_start)/2; + } + + div = 148500 / mode->clock; + if (div != 0) { + div--; + if (div > 3) + div = 3; + } + + /* set HDMI HDCP mode off */ + tda19988_reg_set(sc, TDA_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); + tda19988_reg_clear(sc, TDA_HDCP_TX33, HDCP_TX33_HDMI); + tda19988_reg_write(sc, TDA_ENC_CNTRL, ENC_CNTRL_DVI_MODE); + + /* no pre-filter or interpolator */ + tda19988_reg_write(sc, TDA_HVF_CNTRL_0, + HVF_CNTRL_0_INTPOL_BYPASS | HVF_CNTRL_0_PREFIL_NONE); + tda19988_reg_write(sc, TDA_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); + tda19988_reg_write(sc, TDA_VIP_CNTRL_4, + VIP_CNTRL_4_BLANKIT_NDE | VIP_CNTRL_4_BLC_NONE); + + tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); + tda19988_reg_clear(sc, TDA_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IP); + tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); + tda19988_reg_write(sc, TDA_SERIALIZER, 0); + tda19988_reg_write(sc, TDA_HVF_CNTRL_1, HVF_CNTRL_1_VQR_FULL); + + tda19988_reg_write(sc, TDA_RPT_CNTRL, 0); + tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | + SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); + + tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | + PLL_SERIAL_2_SRL_PR(0)); + + tda19988_reg_set(sc, TDA_MAT_CONTRL, MAT_CONTRL_MAT_BP); + + tda19988_reg_write(sc, TDA_ANA_GENERAL, 0x09); + + tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); + + /* + * Sync on rising HSYNC/VSYNC + */ + reg = VIP_CNTRL_3_SYNC_HS; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + reg |= VIP_CNTRL_3_H_TGL; + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + reg |= VIP_CNTRL_3_V_TGL; + tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg); + + reg = TBG_CNTRL_1_TGL_EN; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) + reg |= TBG_CNTRL_1_H_TGL; + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + reg |= TBG_CNTRL_1_V_TGL; + tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg); + + /* Program timing */ + tda19988_reg_write(sc, TDA_VIDFORMAT, 0x00); + + tda19988_reg_write2(sc, TDA_REFPIX_MSB, ref_pix); + tda19988_reg_write2(sc, TDA_REFLINE_MSB, ref_line); + tda19988_reg_write2(sc, TDA_NPIX_MSB, n_pix); + tda19988_reg_write2(sc, TDA_NLINE_MSB, n_line); + + tda19988_reg_write2(sc, TDA_VS_LINE_STRT_1_MSB, vs1_line_start); + tda19988_reg_write2(sc, TDA_VS_PIX_STRT_1_MSB, vs1_pix_start); + tda19988_reg_write2(sc, TDA_VS_LINE_END_1_MSB, vs1_line_end); + tda19988_reg_write2(sc, TDA_VS_PIX_END_1_MSB, vs1_pix_stop); + tda19988_reg_write2(sc, TDA_VS_LINE_STRT_2_MSB, vs2_line_start); + tda19988_reg_write2(sc, TDA_VS_PIX_STRT_2_MSB, vs2_pix_start); + tda19988_reg_write2(sc, TDA_VS_LINE_END_2_MSB, vs2_line_end); + tda19988_reg_write2(sc, TDA_VS_PIX_END_2_MSB, vs2_pix_stop); + tda19988_reg_write2(sc, TDA_HS_PIX_START_MSB, hs_pix_start); + tda19988_reg_write2(sc, TDA_HS_PIX_STOP_MSB, hs_pix_stop); + tda19988_reg_write2(sc, TDA_VWIN_START_1_MSB, vwin1_line_start); + tda19988_reg_write2(sc, TDA_VWIN_END_1_MSB, vwin1_line_end); + tda19988_reg_write2(sc, TDA_VWIN_START_2_MSB, vwin2_line_start); + tda19988_reg_write2(sc, TDA_VWIN_END_2_MSB, vwin2_line_end); + tda19988_reg_write2(sc, TDA_DE_START_MSB, de_start); + tda19988_reg_write2(sc, TDA_DE_STOP_MSB, de_stop); + + if (sc->sc_version == TDA19988) + tda19988_reg_write(sc, TDA_ENABLE_SPACE, 0x00); + + /* must be last register set */ + tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); +} + +static void +tda19988_parse_edid(struct tda19988_softc *sc) +{ + int i; + char edid_header[] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + if (memcmp(sc->sc_edid, edid_header, 8) != 0) { + device_printf(sc->sc_dev, "invalid EDID header\n"); + return; + } + + device_printf(sc->sc_dev, "EDID v%d.%d\n", sc->sc_edid[18], sc->sc_edid[19]); + device_printf(sc->sc_dev, "Supported modes:\n"); + + for (i = 0; i < MODES_ARRAY_SIZE; i++) + if (sc->sc_edid[EDID_MODES0] & (1 << i)) + device_printf(sc->sc_dev, "\t%s\n", edid_modes0[i]); + + for (i = 0; i < 8; i++) + if (sc->sc_edid[EDID_MODES1] & (1 << i)) + device_printf(sc->sc_dev, "\t%s\n", edid_modes1[i]); + + for (i = EDID_TIMING_START; i < EDID_TIMING_END; i += 2) { + int x, y, f; + x = y = f = 0; + /* <1,1> means unused entry */ + if ((sc->sc_edid[i] == 1) && (sc->sc_edid[i+1] == 1)) + continue; + + x = EDID_TIMING_X(sc->sc_edid[i]); + switch (EDID_RATIO(sc->sc_edid[i+1])) { + case EDID_RATIO_10x16: + y = x*10/16; + break; + case EDID_RATIO_3x4: + y = x*3/4; + break; + case EDID_RATIO_4x5: + y = x*4/5; + break; + case EDID_RATIO_9x16: + y = x*9/16; + break; + } + + f = EDID_FREQ(sc->sc_edid[i+1]); + device_printf(sc->sc_dev, "\t%dx%d @ %dHz\n", x, y, f); + } +} + +static int +tda19988_read_edid(struct tda19988_softc *sc) +{ + int attempt, err; + uint8_t data; + + err = 0; + + if (sc->sc_version == TDA19988) + tda19988_reg_clear(sc, TDA_TX4, TX4_PD_RAM); + + tda19988_reg_set(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); + + /* Block 0 */ + tda19988_reg_write(sc, TDA_DDC_ADDR, 0xa0); + tda19988_reg_write(sc, TDA_DDC_OFFS, 0); + tda19988_reg_write(sc, TDA_DDC_SEGM_ADDR, 0x60); + tda19988_reg_write(sc, TDA_DDC_SEGM, 0); + + tda19988_reg_write(sc, TDA_EDID_CTRL, 1); + tda19988_reg_write(sc, TDA_EDID_CTRL, 0); + + data = 0; + for (attempt = 0; attempt < MAX_READ_ATTEMPTS; attempt++) { + tda19988_reg_read(sc, TDA_INT_FLAGS_2, &data); + if (data & INT_FLAGS_2_EDID_BLK_RD) + break; + pause("EDID", 1); + } + + if (attempt == MAX_READ_ATTEMPTS) { + err = -1; + goto done; + } + + if (tda19988_block_read(sc, TDA_EDID_DATA0, sc->sc_edid, EDID_LENGTH) != 0) { + err = -1; + goto done; + } + +done: + tda19988_reg_clear(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); + if (sc->sc_version == TDA19988) + tda19988_reg_set(sc, TDA_TX4, TX4_PD_RAM); + + return (err); +} + +static void +tda19988_start(void *xdev) +{ + struct tda19988_softc *sc; + device_t dev = (device_t)xdev; + uint8_t data; + uint16_t version; + + sc = device_get_softc(dev); + + tda19988_cec_write(sc, TDA_CEC_ENAMODS, ENAMODS_RXSENS | ENAMODS_HDMI); + DELAY(1000); + tda19988_cec_read(sc, 0xfe, &data); + + /* Reset core */ + tda19988_reg_set(sc, TDA_SOFTRESET, 3); + DELAY(100); + tda19988_reg_clear(sc, TDA_SOFTRESET, 3); + DELAY(100); + + /* reset transmitter: */ + tda19988_reg_set(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); + tda19988_reg_clear(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); + + /* PLL registers common configuration */ + tda19988_reg_write(sc, TDA_PLL_SERIAL_1, 0x00); + tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); + tda19988_reg_write(sc, TDA_PLL_SERIAL_3, 0x00); + tda19988_reg_write(sc, TDA_SERIALIZER, 0x00); + tda19988_reg_write(sc, TDA_BUFFER_OUT, 0x00); + tda19988_reg_write(sc, TDA_PLL_SCG1, 0x00); + tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); + tda19988_reg_write(sc, TDA_PLL_SCGN1, 0xfa); + tda19988_reg_write(sc, TDA_PLL_SCGN2, 0x00); + tda19988_reg_write(sc, TDA_PLL_SCGR1, 0x5b); + tda19988_reg_write(sc, TDA_PLL_SCGR2, 0x00); + tda19988_reg_write(sc, TDA_PLL_SCG2, 0x10); + + /* Write the default value MUX register */ + tda19988_reg_write(sc, TDA_MUX_VP_VIP_OUT, 0x24); + + version = 0; + tda19988_reg_read(sc, TDA_VERSION, &data); + version |= data; + tda19988_reg_read(sc, TDA_VERSION_MSB, &data); + version |= (data << 8); + + /* Clear feature bits */ + sc->sc_version = version & ~0x30; + switch (sc->sc_version) { + case TDA19988: + device_printf(dev, "TDA19988\n"); + break; + default: + device_printf(dev, "Unknown device: %04x\n", sc->sc_version); + goto done; + } + + tda19988_reg_write(sc, TDA_DDC_CTRL, DDC_ENABLE); + tda19988_reg_write(sc, TDA_TX3, 39); + + tda19988_cec_write(sc, TDA_CEC_FRO_IM_CLK_CTRL, + CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); + + if (tda19988_read_edid(sc) < 0) { + device_printf(dev, "failed to read EDID\n"); + goto done; + } + + tda19988_parse_edid(sc); + + tda19988_init_encoder(sc, &mode_std640x480); + + /* Default values for RGB 4:4:4 mapping */ + tda19988_reg_write(sc, TDA_VIP_CNTRL_0, 0x23); + tda19988_reg_write(sc, TDA_VIP_CNTRL_1, 0x45); + tda19988_reg_write(sc, TDA_VIP_CNTRL_2, 0x01); + +done: + config_intrhook_disestablish(&sc->enum_hook); +} + +static int +tda19988_attach(device_t dev) +{ + struct tda19988_softc *sc; + + sc = device_get_softc(dev); + + sc->sc_dev = dev; + sc->sc_addr = iicbus_get_addr(dev); + sc->sc_cec_addr = (0x34 << 1); /* hardcoded */ + + device_set_desc(dev, "NXP TDA19988 HDMI transmitter"); + + sc->enum_hook.ich_func = tda19988_start; + sc->enum_hook.ich_arg = dev; + + if (config_intrhook_establish(&sc->enum_hook) != 0) + return (ENOMEM); + + return (0); +} + +static device_method_t tda_methods[] = { + DEVMETHOD(device_probe, tda19988_probe), + DEVMETHOD(device_attach, tda19988_attach), + {0, 0}, +}; + +static driver_t tda_driver = { + "tda", + tda_methods, + sizeof(struct tda19988_softc), +}; + +static devclass_t tda_devclass; + +DRIVER_MODULE(tda, iicbus, tda_driver, tda_devclass, 0, 0); +MODULE_VERSION(tda, 1); +MODULE_DEPEND(tda, iicbus, 1, 1, 1); Property changes on: sys/dev/iicbus/tda19988.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property