/*-
 * Copyright (c) 2000 Doug Rabson
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPELCAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: src/sys/alpha/pci/t2_pci.c,v 1.11 2002/03/21 06:14:58 imp Exp $
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <pci/pcivar.h>
#include <machine/swiz.h>
#include <machine/md_var.h>
#include <machine/resource.h>

#include <alpha/pci/t2reg.h>
#include <alpha/pci/t2var.h>
#include <alpha/pci/pcibus.h>

#include "alphapci_if.h"
#include "pcib_if.h"

#define KV(pa)			ALPHA_PHYS_TO_K0SEG((pa) + sable_lynx_base)

struct t2_hose_softc {
	struct swiz_space io;	/* accessor for ports */
	struct swiz_space mem;	/* accessor for memory */
	struct rman	io_rman; /* resource manager for ports */
	struct rman	mem_rman; /* resource manager for memory */
};

static devclass_t	pcib_devclass;

static int
t2_pcib_probe(device_t dev)
{
	struct t2_hose_softc *sc = device_get_softc(dev);
	device_t child;
	int unit;

	device_set_desc(dev, "T2 PCI host bus adapter");

	unit = device_get_unit(dev);
	if (unit > 1) {
		printf ("unit = %d > 1, not attaching\n", unit);
		return ENOENT;
	}

	pci_init_resources();

	child = device_add_child(dev, "pci", -1);

	swiz_init_space(&sc->io, KV(T2_PCI_SIO(unit)));
	swiz_init_space_hae(&sc->mem, KV(T2_PCI_SPARSE(unit)),
		    t2_set_hae_mem, (void *)(uintptr_t)unit);

	sc->io_rman.rm_start = 0;
	sc->io_rman.rm_end = ~0u;
	sc->io_rman.rm_type = RMAN_ARRAY;
	sc->io_rman.rm_descr = "I/O ports";
	if (rman_init(&sc->io_rman)
	    || rman_manage_region(&sc->io_rman, 0x0, (1L << 32)))
		panic("t2_pcib_probe: io_rman");
	
	sc->mem_rman.rm_start = 0;
	sc->mem_rman.rm_end = ~0u;
	sc->mem_rman.rm_type = RMAN_ARRAY;
	sc->mem_rman.rm_descr = "I/O memory";
	if (rman_init(&sc->mem_rman)
	    || rman_manage_region(&sc->mem_rman, 0x0, (1L << 32)))
		panic("t2_pcib_probe: mem_rman");

	/*
	 * Replace the temporary bootstrap spaces with real ones. This
	 * isn't stictly necessary but it keeps things tidy.
	 */
	if (device_get_unit(dev) == 0) {
		busspace_isa_io = (struct alpha_busspace *) &sc->io;
		busspace_isa_mem = (struct alpha_busspace *) &sc->mem;
	}


	return 0;
}

static int
t2_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
{
	if (which == PCIB_IVAR_BUS) {
		*result = 0;
		return 0;
	}
	return ENOENT;
}

static void *
t2_pcib_cvt_dense(device_t dev, vm_offset_t addr)
{
	int h =  device_get_unit(dev);
	addr &= 0xffffffffUL;
	
	return (void *) KV(addr | T2_PCI_DENSE(h));
}

static kobj_t
t2_pcib_get_bustag(device_t dev, int type)
{
	struct t2_hose_softc *sc = device_get_softc(dev);

	switch (type) {
	case SYS_RES_IOPORT:
		return (kobj_t) &sc->io;

	case SYS_RES_MEMORY:
		return (kobj_t) &sc->mem;
	}

	return 0;
}

static struct rman *
t2_pcib_get_rman(device_t dev, int type)
{
	struct t2_hose_softc *sc = device_get_softc(dev);

	switch (type) {
	case SYS_RES_IOPORT:
		return &sc->io_rman;

	case SYS_RES_MEMORY:
		return &sc->mem_rman;
	}

	return 0;
}


static int
t2_pcib_maxslots(device_t dev)
{
	return 9;
}

#define T2_CFGOFF(b, s, f, r)					\
	((b) ? (((b) << 16) | ((s) << 11) | ((f) << 8) | (r))	\
	 : ((1 << ((s) + 11)) | ((f) << 8) | (r)))

#define T2_TYPE1_SETUP(h, b,s,old_hae3) if((b)) {			\
        do {							\
		(s) = intr_disable();				\
		(old_hae3) = t2_csr[h]->hae0_3;			\
		alpha_mb();					\
		t2_csr[h]->hae0_3 = (old_hae3) | (1<<30);	\
		alpha_mb();					\
        } while(0);						\
}

#define T2_TYPE1_TEARDOWN(h, b,s,old_hae3) if((b)) {	\
        do {						\
		alpha_mb();				\
		t2_csr[h]->hae0_3 = (old_hae3);		\
		alpha_mb();				\
		intr_restore((s));			\
        } while(0);					\
}

#define SWIZ_CFGREAD(h, b, s, f, r, width, type) do {			 \
	type val = ~0;							 \
	register_t ipl = 0;						 \
	u_int32_t old_hae3 = 0;						 \
	vm_offset_t off = T2_CFGOFF(b, s, f, r);			 \
	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF(h)), off); \
	alpha_mb();							 \
	T2_TYPE1_SETUP(h, b,ipl,old_hae3);					 \
	if (!badaddr((caddr_t)kv, sizeof(type))) {			 \
		val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv));	 \
	}								 \
        T2_TYPE1_TEARDOWN(h,b,ipl,old_hae3);				 \
	return val;							 \
} while (0)

#define SWIZ_CFGWRITE(h, b, s, f, r, data, width, type) do {		 \
	register_t ipl = 0;						 \
	u_int32_t old_hae3 = 0;						 \
	vm_offset_t off = T2_CFGOFF(b, s, f, r);			 \
	vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(T2_PCI_CONF(h)), off); \
	alpha_mb();							 \
	T2_TYPE1_SETUP(h, b,ipl,old_hae3);				 \
	if (!badaddr((caddr_t)kv, sizeof(type))) {			 \
                SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data));	 \
		alpha_wmb();						 \
	}								 \
        T2_TYPE1_TEARDOWN(h, b,ipl,old_hae3);				 \
	return;								 \
} while (0)

static u_int32_t
t2_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
		    u_int reg, int width)
{
	int h = device_get_unit(dev);


	switch (width) {
	case 1:
		SWIZ_CFGREAD(h, b, s, f, reg, BYTE, u_int8_t);
		break;
	case 2:
		SWIZ_CFGREAD(h, b, s, f, reg, WORD, u_int16_t);
		break;
	case 4:
		SWIZ_CFGREAD(h, b, s, f, reg, LONG, u_int32_t);
	}
	return ~0;
}

static void
t2_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
		     u_int reg, u_int32_t val, int width)
{
	int h = device_get_unit(dev);


	switch (width) {
	case 1:
		SWIZ_CFGWRITE(h, b, s, f, reg, val, BYTE, u_int8_t);
		break;
	case 2:
		SWIZ_CFGWRITE(h, b, s, f, reg, val, WORD, u_int16_t);
		break;
	case 4:
		SWIZ_CFGWRITE(h, b, s, f, reg, val, LONG, u_int32_t);
	}
}

static device_method_t t2_pcib_methods[] = {
	/* Device interface */
	DEVMETHOD(device_probe,		t2_pcib_probe),
	DEVMETHOD(device_attach,	bus_generic_attach),

	/* Bus interface */
	DEVMETHOD(bus_print_child,	bus_generic_print_child),
	DEVMETHOD(bus_read_ivar,	t2_pcib_read_ivar),
	DEVMETHOD(bus_alloc_resource,	alpha_pci_alloc_resource),
	DEVMETHOD(bus_release_resource,	pci_release_resource),
	DEVMETHOD(bus_activate_resource, pci_activate_resource),
	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),

	/* alphapci interface */
	DEVMETHOD(alphapci_cvt_dense,	t2_pcib_cvt_dense),
	DEVMETHOD(alphapci_get_bustag,	t2_pcib_get_bustag),
	DEVMETHOD(alphapci_get_rman,	t2_pcib_get_rman),

	/* pcib interface */
	DEVMETHOD(pcib_maxslots,	t2_pcib_maxslots),
	DEVMETHOD(pcib_read_config,	t2_pcib_read_config),
	DEVMETHOD(pcib_write_config,	t2_pcib_write_config),
	DEVMETHOD(pcib_route_interrupt,	alpha_pci_route_interrupt),

	{ 0, 0 }
};

static driver_t t2_pcib_driver = {
	"pcib",
	t2_pcib_methods,
	sizeof(struct t2_hose_softc),
};

DRIVER_MODULE(pcib, t2, t2_pcib_driver, pcib_devclass, 0, 0);