Index: src/sys/amd64/amd64/mp_machdep.c
===================================================================
RCS file: /home/ncvs/src/sys/amd64/amd64/mp_machdep.c,v
retrieving revision 1.242.2.8
diff -u -r1.242.2.8 mp_machdep.c
--- src/sys/amd64/amd64/mp_machdep.c	6 Apr 2005 01:05:51 -0000	1.242.2.8
+++ src/sys/amd64/amd64/mp_machdep.c	30 Apr 2005 16:46:52 -0000
@@ -731,8 +731,16 @@
 	smp_tlb_addr2 = addr2;
 	atomic_store_rel_int(&smp_tlb_wait, 0);
 	ipi_all_but_self(vector);
+	/* 
+	* Enable interrupts here to workaround Opteron Errata 106.
+	* The while loop runs entirely out of instruction cache,
+	* which blocks updates to the cache from other CPUs.
+	* Interrupts break the lock, allowing the write to post.
+	*/
+	enable_intr();
 	while (smp_tlb_wait < ncpu)
 		ia32_pause();
+	disable_intr();
 }
 
 /*
@@ -820,8 +828,16 @@
 		ipi_all_but_self(vector);
 	else
 		ipi_selected(mask, vector);
+	/* 
+	* Enable interrupts here to workaround Opteron Errata 106.
+	* The while loop runs entirely out of instruction cache,
+	* which blocks updates to the cache from other CPUs.
+	* Interrupts break the lock, allowing the write to post.
+	*/
+	enable_intr();
 	while (smp_tlb_wait < ncpu)
 		ia32_pause();
+	disable_intr();
 }
 
 void
Index: src/sys/i386/i386/mp_machdep.c
===================================================================
RCS file: /home/ncvs/src/sys/i386/i386/mp_machdep.c,v
retrieving revision 1.235.2.7
diff -u -r1.235.2.7 mp_machdep.c
--- src/sys/i386/i386/mp_machdep.c	26 Apr 2005 21:20:19 -0000	1.235.2.7
+++ src/sys/i386/i386/mp_machdep.c	30 Apr 2005 16:46:52 -0000
@@ -931,8 +931,16 @@
 	smp_tlb_addr2 = addr2;
 	atomic_store_rel_int(&smp_tlb_wait, 0);
 	ipi_all_but_self(vector);
+	/* 
+	 * Enable interrupts here to workaround Opteron Errata 106.
+	 * The while loop runs entirely out of instruction cache,
+	 * which blocks updates to the cache from other CPUs.
+	 * Interrupts break the lock, allowing the write to post.
+	 */
+	enable_intr();
 	while (smp_tlb_wait < ncpu)
 		ia32_pause();
+	disable_intr();
 }
 
 /*
@@ -1020,8 +1028,16 @@
 		ipi_all_but_self(vector);
 	else
 		ipi_selected(mask, vector);
+	/* 
+	 * Enable interrupts here to workaround Opteron Errata 106.
+	 * The while loop runs entirely out of instruction cache,
+	 * which blocks updates to the cache from other CPUs.
+	 * Interrupts break the lock, allowing the write to post.
+	 */
+	enable_intr();
 	while (smp_tlb_wait < ncpu)
 		ia32_pause();
+	disable_intr();
 }
 
 void