Index: dev/nvme/nvme.c =================================================================== --- dev/nvme/nvme.c (revision 346643) +++ dev/nvme/nvme.c (working copy) @@ -36,9 +36,6 @@ #include -#include -#include - #include "nvme_private.h" struct nvme_consumer { @@ -57,107 +54,8 @@ MALLOC_DEFINE(M_NVME, "nvme", "nvme(4) memory allocations"); -static int nvme_probe(device_t); -static int nvme_attach(device_t); -static int nvme_detach(device_t); -static int nvme_shutdown(device_t); +devclass_t nvme_devclass; -static devclass_t nvme_devclass; - -static device_method_t nvme_pci_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, nvme_probe), - DEVMETHOD(device_attach, nvme_attach), - DEVMETHOD(device_detach, nvme_detach), - DEVMETHOD(device_shutdown, nvme_shutdown), - { 0, 0 } -}; - -static driver_t nvme_pci_driver = { - "nvme", - nvme_pci_methods, - sizeof(struct nvme_controller), -}; - -DRIVER_MODULE(nvme, pci, nvme_pci_driver, nvme_devclass, NULL, NULL); -MODULE_VERSION(nvme, 1); -MODULE_DEPEND(nvme, cam, 1, 1, 1); - -static struct _pcsid -{ - uint32_t devid; - int match_subdevice; - uint16_t subdevice; - const char *desc; - uint32_t quirks; -} pci_ids[] = { - { 0x01118086, 0, 0, "NVMe Controller" }, - { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, - { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, - { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, - { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, - { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, - { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, - { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, - { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, - { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, - { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, - { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, - { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, - { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, - { 0x01161179, 0, 0, "Toshiba XG5", QUIRK_DISABLE_TIMEOUT }, - { 0x00000000, 0, 0, NULL } -}; - -static int -nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) -{ - if (devid != ep->devid) - return 0; - - if (!ep->match_subdevice) - return 1; - - if (subdevice == ep->subdevice) - return 1; - else - return 0; -} - -static int -nvme_probe (device_t device) -{ - struct _pcsid *ep; - uint32_t devid; - uint16_t subdevice; - - devid = pci_get_devid(device); - subdevice = pci_get_subdevice(device); - ep = pci_ids; - - while (ep->devid) { - if (nvme_match(devid, subdevice, ep)) - break; - ++ep; - } - - if (ep->desc) { - device_set_desc(device, ep->desc); - return (BUS_PROBE_DEFAULT); - } - -#if defined(PCIS_STORAGE_NVM) - if (pci_get_class(device) == PCIC_STORAGE && - pci_get_subclass(device) == PCIS_STORAGE_NVM && - pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { - device_set_desc(device, "Generic NVMe Device"); - return (BUS_PROBE_GENERIC); - } -#endif - - return (ENXIO); -} - static void nvme_init(void) { @@ -180,7 +78,7 @@ SYSUNINIT(nvme_unregister, SI_SUB_DRIVERS, SI_ORDER_SECOND, nvme_uninit, NULL); -static int +int nvme_shutdown(device_t dev) { struct nvme_controller *ctrlr; @@ -224,25 +122,12 @@ cpl->cid, p, sc, sct, m, dnr); } -static int +int nvme_attach(device_t dev) { struct nvme_controller *ctrlr = DEVICE2SOFTC(dev); int status; - struct _pcsid *ep; - uint32_t devid; - uint16_t subdevice; - devid = pci_get_devid(dev); - subdevice = pci_get_subdevice(dev); - ep = pci_ids; - while (ep->devid) { - if (nvme_match(devid, subdevice, ep)) - break; - ++ep; - } - ctrlr->quirks = ep->quirks; - status = nvme_ctrlr_construct(ctrlr, dev); if (status != 0) { @@ -251,32 +136,8 @@ } /* - * Some drives do not implement the completion timeout feature - * correctly. There's a WAR from the manufacturer to just disable it. - * The driver wouldn't respond correctly to a timeout anyway. - */ - if (ep->quirks & QUIRK_DISABLE_TIMEOUT) { - int ptr; - uint16_t devctl2; - - status = pci_find_cap(dev, PCIY_EXPRESS, &ptr); - if (status) { - device_printf(dev, "Can't locate PCIe capability?"); - return (status); - } - devctl2 = pci_read_config(dev, ptr + PCIER_DEVICE_CTL2, sizeof(devctl2)); - devctl2 |= PCIEM_CTL2_COMP_TIMO_DISABLE; - pci_write_config(dev, ptr + PCIER_DEVICE_CTL2, devctl2, sizeof(devctl2)); - } - - /* - * Enable busmastering so the completion status messages can - * be busmastered back to the host. - */ - pci_enable_busmaster(dev); - - /* * Reset controller twice to ensure we do a transition from cc.en==1 + * Reset controller twice to ensure we do a transition from cc.en==1 * to cc.en==0. This is because we don't really know what status * the controller was left in when boot handed off to OS. */ @@ -300,13 +161,12 @@ return (0); } -static int +int nvme_detach (device_t dev) { struct nvme_controller *ctrlr = DEVICE2SOFTC(dev); nvme_ctrlr_destruct(ctrlr, dev); - pci_disable_busmaster(dev); return (0); } Index: dev/nvme/nvme_ahci.c =================================================================== --- dev/nvme/nvme_ahci.c (nonexistent) +++ dev/nvme/nvme_ahci.c (working copy) @@ -0,0 +1,127 @@ +/*- + * Copyright (C) 2017 Olivier Houchard + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); +#include +#include +#include +#include +#include +#include +#include + +#include "nvme_private.h" + +static int nvme_ahci_probe(device_t dev); +static int nvme_ahci_attach(device_t dev); +static int nvme_ahci_detach(device_t dev); + +static device_method_t nvme_ahci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, nvme_ahci_probe), + DEVMETHOD(device_attach, nvme_ahci_attach), + DEVMETHOD(device_detach, nvme_ahci_detach), + DEVMETHOD(device_shutdown, nvme_shutdown), + { 0, 0 } +}; + +static driver_t nvme_ahci_driver = { + "nvme", + nvme_ahci_methods, + sizeof(struct nvme_controller), +}; + +DRIVER_MODULE(nvme, ahci, nvme_ahci_driver, nvme_devclass, NULL, 0); +MODULE_VERSION(nvme_ahci, 1); + +static int +nvme_ahci_probe (device_t device) +{ + return (0); +} + +static int +nvme_ahci_attach(device_t dev) +{ + struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); + int ret; + + /* Map MMIO registers */ + ctrlr->resource_id = 0; + + ctrlr->resource = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &ctrlr->resource_id, RF_ACTIVE); + + if(ctrlr->resource == NULL) { + nvme_printf(ctrlr, "unable to allocate mem resource\n"); + ret = ENOMEM; + goto bad; + } + ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); + ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); + ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; + + /* Allocate and setup IRQ */ + ctrlr->rid = 0; + ctrlr->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, + &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); + + if (ctrlr->res == NULL) { + nvme_printf(ctrlr, "unable to allocate shared IRQ\n"); + ret = ENOMEM; + goto bad; + } + + ctrlr->msix_enabled = 0; + ctrlr->num_io_queues = 1; + ctrlr->num_cpus_per_ioq = mp_ncpus; + if (bus_setup_intr(dev, ctrlr->res, + INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler, + ctrlr, &ctrlr->tag) != 0) { + nvme_printf(ctrlr, "unable to setup intx handler\n"); + ret = ENOMEM; + goto bad; + } + ctrlr->tag = (void *)0x1; + + return nvme_attach(dev); +bad: + if (ctrlr->resource != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, + ctrlr->resource_id, ctrlr->resource); + } + if (ctrlr->res) + bus_release_resource(ctrlr->dev, SYS_RES_IRQ, + rman_get_rid(ctrlr->res), ctrlr->res); + return (ret); +} + +static int +nvme_ahci_detach(device_t dev) +{ + + return (nvme_detach(dev)); +} Property changes on: dev/nvme/nvme_ahci.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: dev/nvme/nvme_ctrlr.c =================================================================== --- dev/nvme/nvme_ctrlr.c (revision 346643) +++ dev/nvme/nvme_ctrlr.c (working copy) @@ -42,9 +42,6 @@ #include #include -#include -#include - #include "nvme_private.h" #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */ @@ -51,41 +48,8 @@ static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, struct nvme_async_event_request *aer); -static void nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); static int -nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) -{ - - ctrlr->resource_id = PCIR_BAR(0); - - ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, - &ctrlr->resource_id, RF_ACTIVE); - - if(ctrlr->resource == NULL) { - nvme_printf(ctrlr, "unable to allocate pci resource\n"); - return (ENOMEM); - } - - ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); - ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); - ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; - - /* - * The NVMe spec allows for the MSI-X table to be placed behind - * BAR 4/5, separate from the control/doorbell registers. Always - * try to map this bar, because it must be mapped prior to calling - * pci_alloc_msix(). If the table isn't behind BAR 4/5, - * bus_alloc_resource() will just return NULL which is OK. - */ - ctrlr->bar4_resource_id = PCIR_BAR(4); - ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, - &ctrlr->bar4_resource_id, RF_ACTIVE); - - return (0); -} - -static int nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) { struct nvme_qpair *qpair; @@ -841,9 +805,8 @@ * the number of I/O queues supported, so cannot reset * the adminq again here. */ - if (ctrlr->is_resetting) { + if (ctrlr->is_resetting) nvme_qpair_reset(&ctrlr->adminq); - } for (i = 0; i < ctrlr->num_io_queues; i++) nvme_qpair_reset(&ctrlr->ioq[i]); @@ -969,34 +932,6 @@ nvme_mmio_write_4(ctrlr, intmc, 1); } -static int -nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr) -{ - - ctrlr->msix_enabled = 0; - ctrlr->num_io_queues = 1; - ctrlr->num_cpus_per_ioq = mp_ncpus; - ctrlr->rid = 0; - ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, - &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); - - if (ctrlr->res == NULL) { - nvme_printf(ctrlr, "unable to allocate shared IRQ\n"); - return (ENOMEM); - } - - bus_setup_intr(ctrlr->dev, ctrlr->res, - INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler, - ctrlr, &ctrlr->tag); - - if (ctrlr->tag == NULL) { - nvme_printf(ctrlr, "unable to setup intx handler\n"); - return (ENOMEM); - } - - return (0); -} - static void nvme_pt_done(void *arg, const struct nvme_completion *cpl) { @@ -1134,88 +1069,6 @@ .d_ioctl = nvme_ctrlr_ioctl }; -static void -nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) -{ - device_t dev; - int per_cpu_io_queues; - int min_cpus_per_ioq; - int num_vectors_requested, num_vectors_allocated; - int num_vectors_available; - - dev = ctrlr->dev; - min_cpus_per_ioq = 1; - TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); - - if (min_cpus_per_ioq < 1) { - min_cpus_per_ioq = 1; - } else if (min_cpus_per_ioq > mp_ncpus) { - min_cpus_per_ioq = mp_ncpus; - } - - per_cpu_io_queues = 1; - TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); - - if (per_cpu_io_queues == 0) { - min_cpus_per_ioq = mp_ncpus; - } - - ctrlr->force_intx = 0; - TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx); - - /* - * FreeBSD currently cannot allocate more than about 190 vectors at - * boot, meaning that systems with high core count and many devices - * requesting per-CPU interrupt vectors will not get their full - * allotment. So first, try to allocate as many as we may need to - * understand what is available, then immediately release them. - * Then figure out how many of those we will actually use, based on - * assigning an equal number of cores to each I/O queue. - */ - - /* One vector for per core I/O queue, plus one vector for admin queue. */ - num_vectors_available = min(pci_msix_count(dev), mp_ncpus + 1); - if (pci_alloc_msix(dev, &num_vectors_available) != 0) { - num_vectors_available = 0; - } - pci_release_msi(dev); - - if (ctrlr->force_intx || num_vectors_available < 2) { - nvme_ctrlr_configure_intx(ctrlr); - return; - } - - /* - * Do not use all vectors for I/O queues - one must be saved for the - * admin queue. - */ - ctrlr->num_cpus_per_ioq = max(min_cpus_per_ioq, - howmany(mp_ncpus, num_vectors_available - 1)); - - ctrlr->num_io_queues = howmany(mp_ncpus, ctrlr->num_cpus_per_ioq); - num_vectors_requested = ctrlr->num_io_queues + 1; - num_vectors_allocated = num_vectors_requested; - - /* - * Now just allocate the number of vectors we need. This should - * succeed, since we previously called pci_alloc_msix() - * successfully returning at least this many vectors, but just to - * be safe, if something goes wrong just revert to INTx. - */ - if (pci_alloc_msix(dev, &num_vectors_allocated) != 0) { - nvme_ctrlr_configure_intx(ctrlr); - return; - } - - if (num_vectors_allocated < num_vectors_requested) { - pci_release_msi(dev); - nvme_ctrlr_configure_intx(ctrlr); - return; - } - - ctrlr->msix_enabled = 1; -} - int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) { @@ -1231,11 +1084,6 @@ mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); - status = nvme_ctrlr_allocate_bar(ctrlr); - - if (status != 0) - return (status); - /* * Software emulators may set the doorbell stride to something * other than zero, but this driver is not set up to handle that. @@ -1265,8 +1113,6 @@ ctrlr->enable_aborts = 0; TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); - nvme_ctrlr_setup_interrupts(ctrlr); - ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE; if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0) return (ENXIO); @@ -1343,9 +1189,6 @@ bus_release_resource(ctrlr->dev, SYS_RES_IRQ, rman_get_rid(ctrlr->res), ctrlr->res); - if (ctrlr->msix_enabled) - pci_release_msi(dev); - if (ctrlr->bar4_resource != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, ctrlr->bar4_resource_id, ctrlr->bar4_resource); Index: dev/nvme/nvme_pci.c =================================================================== --- dev/nvme/nvme_pci.c (nonexistent) +++ dev/nvme/nvme_pci.c (working copy) @@ -0,0 +1,334 @@ +/*- + * Copyright (C) 2012-2016 Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "nvme_private.h" + +static int nvme_pci_probe(device_t); +static int nvme_pci_attach(device_t); +static int nvme_pci_detach(device_t); + +static void nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); + +static device_method_t nvme_pci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, nvme_pci_probe), + DEVMETHOD(device_attach, nvme_pci_attach), + DEVMETHOD(device_detach, nvme_pci_detach), + DEVMETHOD(device_shutdown, nvme_shutdown), + { 0, 0 } +}; + +static driver_t nvme_pci_driver = { + "nvme", + nvme_pci_methods, + sizeof(struct nvme_controller), +}; + +DRIVER_MODULE(nvme, pci, nvme_pci_driver, nvme_devclass, NULL, 0); +MODULE_VERSION(nvme_pci, 1); + +static struct _pcsid +{ + uint32_t devid; + int match_subdevice; + uint16_t subdevice; + const char *desc; + uint32_t quirks; +} pci_ids[] = { + { 0x01118086, 0, 0, "NVMe Controller" }, + { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, + { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, + { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, + { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, + { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, + { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, + { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, + { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, + { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, + { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, + { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, + { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, + { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, + { 0x00000000, 0, 0, NULL } +}; + + +static int +nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) +{ + if (devid != ep->devid) + return 0; + + if (!ep->match_subdevice) + return 1; + + if (subdevice == ep->subdevice) + return 1; + else + return 0; +} + +static int +nvme_pci_probe (device_t device) +{ + struct nvme_controller *ctrlr = DEVICE2SOFTC(device); + struct _pcsid *ep; + uint32_t devid; + uint16_t subdevice; + + devid = pci_get_devid(device); + subdevice = pci_get_subdevice(device); + ep = pci_ids; + + while (ep->devid) { + if (nvme_match(devid, subdevice, ep)) + break; + ++ep; + } + if (ep->devid) + ctrlr->quirks = ep->quirks; + + if (ep->desc) { + device_set_desc(device, ep->desc); + return (BUS_PROBE_DEFAULT); + } + +#if defined(PCIS_STORAGE_NVM) + if (pci_get_class(device) == PCIC_STORAGE && + pci_get_subclass(device) == PCIS_STORAGE_NVM && + pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { + device_set_desc(device, "Generic NVMe Device"); + return (BUS_PROBE_GENERIC); + } +#endif + + return (ENXIO); +} + +static int +nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) +{ + + ctrlr->resource_id = PCIR_BAR(0); + + ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, + &ctrlr->resource_id, RF_ACTIVE); + + if(ctrlr->resource == NULL) { + nvme_printf(ctrlr, "unable to allocate pci resource\n"); + return (ENOMEM); + } + + ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); + ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); + ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; + + /* + * The NVMe spec allows for the MSI-X table to be placed behind + * BAR 4/5, separate from the control/doorbell registers. Always + * try to map this bar, because it must be mapped prior to calling + * pci_alloc_msix(). If the table isn't behind BAR 4/5, + * bus_alloc_resource() will just return NULL which is OK. + */ + ctrlr->bar4_resource_id = PCIR_BAR(4); + ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, + &ctrlr->bar4_resource_id, RF_ACTIVE); + + return (0); +} + +static int +nvme_pci_attach(device_t dev) +{ + struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); + int status; + + ctrlr->dev = dev; + status = nvme_ctrlr_allocate_bar(ctrlr); + if (status != 0) + goto bad; + pci_enable_busmaster(dev); + nvme_ctrlr_setup_interrupts(ctrlr); + return nvme_attach(dev); +bad: + if (ctrlr->resource != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, + ctrlr->resource_id, ctrlr->resource); + } + + if (ctrlr->bar4_resource != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, + ctrlr->bar4_resource_id, ctrlr->bar4_resource); + } + + if (ctrlr->tag) + bus_teardown_intr(dev, ctrlr->res, ctrlr->tag); + + if (ctrlr->res) + bus_release_resource(dev, SYS_RES_IRQ, + rman_get_rid(ctrlr->res), ctrlr->res); + + if (ctrlr->msix_enabled) + pci_release_msi(dev); + + return status; +} + +static int +nvme_pci_detach(device_t dev) +{ + struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); + + if (ctrlr->msix_enabled) + pci_release_msi(dev); + pci_disable_busmaster(dev); + return (nvme_detach(dev)); +} + +static int +nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr) +{ + + ctrlr->msix_enabled = 0; + ctrlr->num_io_queues = 1; + ctrlr->num_cpus_per_ioq = mp_ncpus; + ctrlr->rid = 0; + ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, + &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); + + if (ctrlr->res == NULL) { + nvme_printf(ctrlr, "unable to allocate shared IRQ\n"); + return (ENOMEM); + } + + bus_setup_intr(ctrlr->dev, ctrlr->res, + INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler, + ctrlr, &ctrlr->tag); + + if (ctrlr->tag == NULL) { + nvme_printf(ctrlr, "unable to setup intx handler\n"); + return (ENOMEM); + } + + return (0); +} + +static void +nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) +{ + device_t dev; + int per_cpu_io_queues; + int min_cpus_per_ioq; + int num_vectors_requested, num_vectors_allocated; + int num_vectors_available; + + dev = ctrlr->dev; + min_cpus_per_ioq = 1; + TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); + + if (min_cpus_per_ioq < 1) { + min_cpus_per_ioq = 1; + } else if (min_cpus_per_ioq > mp_ncpus) { + min_cpus_per_ioq = mp_ncpus; + } + + per_cpu_io_queues = 1; + TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); + + if (per_cpu_io_queues == 0) { + min_cpus_per_ioq = mp_ncpus; + } + + ctrlr->force_intx = 0; + TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx); + + /* + * FreeBSD currently cannot allocate more than about 190 vectors at + * boot, meaning that systems with high core count and many devices + * requesting per-CPU interrupt vectors will not get their full + * allotment. So first, try to allocate as many as we may need to + * understand what is available, then immediately release them. + * Then figure out how many of those we will actually use, based on + * assigning an equal number of cores to each I/O queue. + */ + + /* One vector for per core I/O queue, plus one vector for admin queue. */ + num_vectors_available = min(pci_msix_count(dev), mp_ncpus + 1); + if (pci_alloc_msix(dev, &num_vectors_available) != 0) { + num_vectors_available = 0; + } + pci_release_msi(dev); + + if (ctrlr->force_intx || num_vectors_available < 2) { + nvme_ctrlr_configure_intx(ctrlr); + return; + } + + /* + * Do not use all vectors for I/O queues - one must be saved for the + * admin queue. + */ + ctrlr->num_cpus_per_ioq = max(min_cpus_per_ioq, + howmany(mp_ncpus, num_vectors_available - 1)); + + ctrlr->num_io_queues = howmany(mp_ncpus, ctrlr->num_cpus_per_ioq); + num_vectors_requested = ctrlr->num_io_queues + 1; + num_vectors_allocated = num_vectors_requested; + + /* + * Now just allocate the number of vectors we need. This should + * succeed, since we previously called pci_alloc_msix() + * successfully returning at least this many vectors, but just to + * be safe, if something goes wrong just revert to INTx. + */ + if (pci_alloc_msix(dev, &num_vectors_allocated) != 0) { + nvme_ctrlr_configure_intx(ctrlr); + return; + } + + if (num_vectors_allocated < num_vectors_requested) { + pci_release_msi(dev); + nvme_ctrlr_configure_intx(ctrlr); + return; + } + + ctrlr->msix_enabled = 1; +} + Property changes on: dev/nvme/nvme_pci.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: dev/nvme/nvme_private.h =================================================================== --- dev/nvme/nvme_private.h (revision 346643) +++ dev/nvme/nvme_private.h (working copy) @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -121,6 +122,8 @@ int done; }; +extern devclass_t nvme_devclass; + #define NVME_REQUEST_VADDR 1 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */ #define NVME_REQUEST_UIO 3 @@ -436,6 +439,10 @@ void nvme_dump_command(struct nvme_command *cmd); void nvme_dump_completion(struct nvme_completion *cpl); +int nvme_attach(device_t dev); +int nvme_shutdown(device_t dev); +int nvme_detach(device_t dev); + static __inline void nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) { Index: dev/ahci/ahci.c =================================================================== --- dev/ahci/ahci.c (revision 346643) +++ dev/ahci/ahci.c (working copy) @@ -346,6 +346,16 @@ if ((ctlr->ichannels & (1 << unit)) == 0) device_disable(child); } + /* Attach any remapped NVME device */ + for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) { + child = device_add_child(dev, "nvme", -1); + if (child == NULL) { + device_printf(dev, "failed to add remapped NVMe device"); + continue; + } + device_set_ivars(child, (void *)(intptr_t)(unit | AHCI_REMAPPED_UNIT)); + } + if (ctlr->caps & AHCI_CAP_EMS) { child = device_add_child(dev, "ahciem", -1); if (child == NULL) @@ -495,6 +505,12 @@ ctlr->interrupt[unit].function(arg); } } + for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) { + if ((arg = ctlr->interrupt[unit].argument)) { + ctlr->interrupt[unit].function(arg); + } + } + /* AHCI declares level triggered IS. */ if (!(ctlr->quirks & AHCI_Q_EDGEIS)) ATA_OUTL(ctlr->r_mem, AHCI_IS, is); @@ -544,12 +560,23 @@ struct resource *res; rman_res_t st; int offset, size, unit; + bool is_remapped; unit = (intptr_t)device_get_ivars(child); + if (unit & AHCI_REMAPPED_UNIT) { + unit &= ~AHCI_REMAPPED_UNIT; + unit -= ctlr->channels; + is_remapped = true; + } else + is_remapped = false; res = NULL; switch (type) { case SYS_RES_MEMORY: - if (unit >= 0) { + if (is_remapped) { + offset = ctlr->remap_offset + unit * ctlr->remap_size; + size = ctlr->remap_size; + } + else if (unit >= 0) { offset = AHCI_OFFSET + (unit << 7); size = 128; } else if (*rid == 0) { @@ -612,6 +639,8 @@ struct ahci_controller *ctlr = device_get_softc(dev); int unit = (intptr_t)device_get_ivars(child); + if (unit & AHCI_REMAPPED_UNIT) + unit &= ~ AHCI_REMAPPED_UNIT; if (filter != NULL) { printf("ahci.c: we cannot use a filter here\n"); return (EINVAL); @@ -628,6 +657,8 @@ struct ahci_controller *ctlr = device_get_softc(dev); int unit = (intptr_t)device_get_ivars(child); + if (unit & AHCI_REMAPPED_UNIT) + unit &= ~ AHCI_REMAPPED_UNIT; ctlr->interrupt[unit].function = NULL; ctlr->interrupt[unit].argument = NULL; return (0); @@ -640,6 +671,9 @@ retval = bus_print_child_header(dev, child); channel = (int)(intptr_t)device_get_ivars(child); + + if (channel & AHCI_REMAPPED_UNIT) + channel &= ~AHCI_REMAPPED_UNIT; if (channel >= 0) retval += printf(" at channel %d", channel); retval += bus_print_child_footer(dev, child); @@ -653,6 +687,8 @@ int channel; channel = (int)(intptr_t)device_get_ivars(child); + if (channel & AHCI_REMAPPED_UNIT) + channel &= ~AHCI_REMAPPED_UNIT; if (channel >= 0) snprintf(buf, buflen, "channel=%d", channel); return (0); Index: dev/ahci/ahci.h =================================================================== --- dev/ahci/ahci.h (revision 346643) +++ dev/ahci/ahci.h (working copy) @@ -214,6 +214,7 @@ #define AHCI_CAP2_SADM 0x00000010 #define AHCI_CAP2_DESO 0x00000020 +#define AHCI_VSCAP 0xa4 #define AHCI_OFFSET 0x100 #define AHCI_STEP 0x80 @@ -318,6 +319,10 @@ /* Total main work area. */ #define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) + +/* NVMe remapped device */ +#define AHCI_REMAPPED_UNIT (1 << 31) + struct ahci_dma_prd { u_int64_t dba; u_int32_t reserved; @@ -518,6 +523,9 @@ int cccv; /* CCC vector */ int direct; /* Direct command completion */ int msi; /* MSI interupts */ + int remapped_devices; /* Remapped NVMe devices */ + uint32_t remap_offset; + uint32_t remap_size; struct { void (*function)(void *); void *argument; Index: dev/ahci/ahci_pci.c =================================================================== --- dev/ahci/ahci_pci.c (revision 346643) +++ dev/ahci/ahci_pci.c (working copy) @@ -495,6 +495,38 @@ &ctlr->r_rid, RF_ACTIVE))) return ENXIO; + /* + * Intel RAID hardware can remap NVMe devices inside its BAR. + * Try to detect this. + */ + if (pci_get_vendor(dev) == 0x8086) { + uint32_t vscap; + + vscap = ATA_INL(ctlr->r_mem, AHCI_VSCAP); + if (vscap & 1) { + uint32_t cap = ATA_INL(ctlr->r_mem, 0x800); /* Intel's REMAP CAP */ + int i; + + ctlr->remap_offset = 0x4000; + ctlr->remap_size = 0x4000; + + for (i = 0; i < 3; i++) { + if (cap & (1 << i) && + (ATA_INL(ctlr->r_mem, 0x880 + i * 0x80) == + ((PCIC_STORAGE << 16) | + (PCIS_STORAGE_NVM << 8) | + PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0))) { + ctlr->remapped_devices++; + } + } + + /* If we have any remapped device, disable MSI */ + if (ctlr->remapped_devices > 0) + ctlr->quirks |= (AHCI_Q_NOMSIX | AHCI_Q_NOMSI); + } + } + + if (ctlr->quirks & AHCI_Q_NOMSIX) msix_count = 0;