In the course of developing the CHERI processor as part of the CTSRD project SRI International's Computer Science Laboratory and the University of Cambridge Computer Laboratory have developed support for a number of general purpose IP cores for Altera FPGAs including the Altera Triple Speed Ethernet (ATSE) MAC core, the Altera University Program SD Card core, and the Altera JTAG UART. We have also added support for general access to memory mapped devices on the Avalon bus via the avgen bus. We have implemented both nexus and flattened device tree (FDT) attachments for these devices.

In addition to these softcore we have developed support for the Terasic multi-touch LCD and are working to provide support for the Terasic HDMI Transmitter Daughter Card. Both of these work with common development and/or reference boards for Altera FPGAs. They do require additional IP cores which we plan to release to the open source community in the near future.

With exception of the ATSE and HDMI drivers we have merged all of these changes to FreeBSD-CURRENT. We anticipate that these drivers will be useful for users who with to run FreeBSD on either hard or soft core CPUs on Altera FPGAs.

This work has been sponsored by DARPA, AFRL, and Google