diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c index 3e29a58..39abfd4 100644 --- a/sys/amd64/pci/pci_cfgreg.c +++ b/sys/amd64/pci/pci_cfgreg.c @@ -90,9 +90,17 @@ pci_cfgregopen(void) /* * Grope around in the PCI config space to see if this is a - * chipset that is capable of doing memory-mapped config cycles. + * northbridge that is capable of doing memory-mapped config cycles. * This also implies that it can do PCIe extended config cycles. */ + if (cpu_vendor_id == CPU_VENDOR_AMD && + CPUID_TO_FAMILY(cpu_id) >= 0x10) { + pciebar = rdmsr(0xc0010058); + if ((pciebar & 0x1) != 0) + pcie_cfgregopen(pciebar & 0xfffffff00000ull, 0, + (1ul << ((pciebar >> 2) & 0xf)) - 1); + return (1); + } /* Check for supported chipsets */ vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2); @@ -317,13 +325,19 @@ pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg, switch (bytes) { case 4: - data = *(volatile uint32_t *)(va); +// data = *(volatile uint32_t *)(va); + __asm __volatile("mov %1, %%eax" : "=a" (data) + : "m" (*(uint32_t *) va)); break; case 2: - data = *(volatile uint16_t *)(va); +// data = *(volatile uint16_t *)(va); + __asm __volatile("movzwl %1, %%eax" : "=a" (data) + : "m" (*(uint16_t *) va)); break; case 1: - data = *(volatile uint8_t *)(va); +// data = *(volatile uint8_t *)(va); + __asm __volatile("movzbl %1, %%eax" : "=a" (data) + : "m" (*(uint8_t *) va)); break; } @@ -344,13 +358,19 @@ pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data, switch (bytes) { case 4: - *(volatile uint32_t *)(va) = data; +// *(volatile uint32_t *)(va) = data; + __asm __volatile("mov %%eax, %0" : "=m" (*(uint32_t *) va) + : "a" (data)); break; case 2: - *(volatile uint16_t *)(va) = data; +// *(volatile uint16_t *)(va) = data; + __asm __volatile("mov %%ax, %0" : "=m" (*(uint16_t *) va) + : "a" (data)); break; case 1: - *(volatile uint8_t *)(va) = data; +// *(volatile uint8_t *)(va) = data; + __asm __volatile("mov %%al, %0" : "=m" (*(uint8_t *) va) + : "a" (data)); break; } }