Index: sys/dev/acpica/acpi_cpu.c
===================================================================
--- sys/dev/acpica/acpi_cpu.c	(revision 242615)
+++ sys/dev/acpica/acpi_cpu.c	(working copy)
@@ -38,6 +38,7 @@
 #include <sys/pcpu.h>
 #include <sys/power.h>
 #include <sys/proc.h>
+#include <sys/sched.h>
 #include <sys/sbuf.h>
 #include <sys/smp.h>
 
@@ -68,6 +69,7 @@
     uint32_t		 trans_lat;	/* Transition latency (usec). */
     uint32_t		 power;		/* Power consumed (mW). */
     int			 res_type;	/* Resource type for p_lvlx. */
+    int			 res_rid;	/* Resource ID for p_lvlx. */
 };
 #define MAX_CX_STATES	 8
 
@@ -91,7 +93,6 @@
     int			 cpu_cx_lowest;
     int			 cpu_cx_lowest_lim;
     char 		 cpu_cx_supported[64];
-    int			 cpu_rid;
 };
 
 struct acpi_cpu_device {
@@ -648,10 +649,10 @@
     gas.BitWidth = 8;
     if (AcpiGbl_FADT.C2Latency <= 100) {
 	gas.Address = sc->cpu_p_blk + 4;
-	acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid,
+	cx_ptr->res_rid = 0;
+	acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
 	    &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
 	if (cx_ptr->p_lvlx != NULL) {
-	    sc->cpu_rid++;
 	    cx_ptr->type = ACPI_STATE_C2;
 	    cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency;
 	    cx_ptr++;
@@ -665,10 +666,10 @@
     /* Validate and allocate resources for C3 (P_LVL3). */
     if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) {
 	gas.Address = sc->cpu_p_blk + 5;
-	acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, &gas,
-	    &cx_ptr->p_lvlx, RF_SHAREABLE);
+	cx_ptr->res_rid = 1;
+	acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
+	    &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
 	if (cx_ptr->p_lvlx != NULL) {
-	    sc->cpu_rid++;
 	    cx_ptr->type = ACPI_STATE_C3;
 	    cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency;
 	    cx_ptr++;
@@ -770,19 +771,18 @@
 	    break;
 	}
 
-#ifdef notyet
 	/* Free up any previous register. */
 	if (cx_ptr->p_lvlx != NULL) {
-	    bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx);
+	    bus_release_resource(sc->cpu_dev, cx_ptr->res_type, cx_ptr->res_rid,
+	        cx_ptr->p_lvlx);
 	    cx_ptr->p_lvlx = NULL;
 	}
-#endif
 
 	/* Allocate the control register for C2 or C3. */
-	acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &sc->cpu_rid,
+	cx_ptr->res_rid = sc->cpu_cx_count;
+	acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->res_rid,
 	    &cx_ptr->p_lvlx, RF_SHAREABLE);
 	if (cx_ptr->p_lvlx) {
-	    sc->cpu_rid++;
 	    ACPI_DEBUG_PRINT((ACPI_DB_INFO,
 			     "acpi_cpu%d: Got C%d - %d latency\n",
 			     device_get_unit(sc->cpu_dev), cx_ptr->type,
@@ -1047,7 +1047,16 @@
 	return;
 
     /* Update the list of Cx states. */
+    thread_lock(curthread);
+    sched_bind(curthread, sc->cpu_pcpu->pc_cpuid);
+    thread_unlock(curthread);
+    critical_enter();
     acpi_cpu_cx_cst(sc);
+    critical_exit();
+    thread_lock(curthread);
+    sched_unbind(curthread);
+    thread_unlock(curthread);
+
     acpi_cpu_cx_list(sc);
 
     ACPI_SERIAL_BEGIN(cpu);