--- /usr/src/sys/i386/i386/mp_machdep.c 2007-07-26 20:04:53.000000000 +0200 +++ i386/i386/mp_machdep.c 2007-07-27 01:10:44.000000000 +0200 @@ -248,8 +248,15 @@ int cpu; /* Build the smp_topology map. */ - /* Nothing to do if there is no HTT support. */ - if ((cpu_feature & CPUID_HTT) == 0) + /* + * HTT support detected through CNXT-ID bit. CNXT-ID assumes L1 + * caches shared between CPUs, which designes a less aggressive + * scheduling algorithm. + * In this case, if cores don'tshare the same L1 caches, there is + * nothing to do. + */ + if ((cpu_feature & CPUID_HTT) == 0 || + (cpu_feature2 & CPUID2_CNXTID) == 0) return; logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; if (logical_cpus <= 1) @@ -423,7 +430,7 @@ /* Setup the initial logical CPUs info. */ logical_cpus = logical_cpus_mask = 0; - if (cpu_feature & CPUID_HTT) + if ((cpu_feature & CPUID_HTT) && (cpu_feature2 & CPUID2_CNXTID)) logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; /* @@ -441,7 +448,7 @@ * First determine if this is an Intel processor which claims * to have hyperthreading support. */ - if ((cpu_feature & CPUID_HTT) && + if ((cpu_feature & CPUID_HTT) && (cpu_feature2 & CPUID2_CNXTID) && (strcmp(cpu_vendor, "GenuineIntel") == 0)) { /* * If the "deterministic cache parameters" cpuid calls --- /usr/src/sys/amd64/amd64/mp_machdep.c Thu Jun 7 23:32:44 2007 +++ amd64/amd64/mp_machdep.c Fri Jul 27 01:44:15 2007 @@ -194,7 +194,8 @@ /* Build the smp_topology map. */ /* Nothing to do if there is no HTT support. */ - if ((cpu_feature & CPUID_HTT) == 0) + if ((cpu_feature & CPUID_HTT) == 0 || + (cpu_feature2 & CPUID2_CNXTID) == 0) return; logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; if (logical_cpus <= 1) @@ -374,7 +375,7 @@ /* Setup the initial logical CPUs info. */ logical_cpus = logical_cpus_mask = 0; - if (cpu_feature & CPUID_HTT) + if ((cpu_feature & CPUID_HTT) && (cpu_feature2 & CPUID2_CNXTID)) logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; /* @@ -392,7 +393,7 @@ * First determine if this is an Intel processor which claims * to have hyperthreading support. */ - if ((cpu_feature & CPUID_HTT) && + if ((cpu_feature & CPUID_HTT) && (cpu_feature2 & CPUID2_CNXTID) && (strcmp(cpu_vendor, "GenuineIntel") == 0)) { /* * If the "deterministic cache parameters" cpuid calls