Index: sys/amd64/include/md_var.h
===================================================================
--- sys/amd64/include/md_var.h	(revision 266262)
+++ sys/amd64/include/md_var.h	(working copy)
@@ -107,6 +107,7 @@ void	dump_add_page(vm_paddr_t);
 void	dump_drop_page(vm_paddr_t);
 void	initializecpu(void);
 void	initializecpucache(void);
+void	initializeest(void);
 void	fillw(int /*u_short*/ pat, void *base, size_t cnt);
 void	fpstate_drop(struct thread *td);
 int	is_physical_memory(vm_paddr_t addr);
Index: sys/amd64/amd64/initcpu.c
===================================================================
--- sys/amd64/amd64/initcpu.c	(revision 266262)
+++ sys/amd64/amd64/initcpu.c	(working copy)
@@ -218,3 +218,15 @@ initializecpucache(void)
 	if (hw_clflush_disable == 1)
 		cpu_feature &= ~CPUID_CLFSH;
 }
+
+void
+initializeest(void)
+{
+	uint64_t msr;
+
+	msr = rdmsr(MSR_PLATFORM_INFO) & 0xFF00;
+
+	/* Disable turbo-mode by default. */
+	msr |= (uint64_t)1 << 32;
+	wrmsr(MSR_PERF_CTL, msr);
+}
Index: sys/amd64/amd64/mp_machdep.c
===================================================================
--- sys/amd64/amd64/mp_machdep.c	(revision 266262)
+++ sys/amd64/amd64/mp_machdep.c	(working copy)
@@ -746,6 +746,7 @@ init_secondary(void)
 	PCPU_SET(curthread, PCPU_GET(idlethread));
 
 	mca_init();
+	initializeest();
 
 	mtx_lock_spin(&ap_boot_mtx);
 
Index: sys/amd64/amd64/machdep.c
===================================================================
--- sys/amd64/amd64/machdep.c	(revision 266262)
+++ sys/amd64/amd64/machdep.c	(working copy)
@@ -2067,6 +2067,7 @@ hammer_time(u_int64_t modulep, u_int64_t physfree)
 		strlcpy(kernelname, env, sizeof(kernelname));
 
 	cpu_probe_amdc1e();
+	initializeest();
 
 #ifdef FDT
 	x86_init_fdt();
Index: sys/x86/include/specialreg.h
===================================================================
--- sys/x86/include/specialreg.h	(revision 266262)
+++ sys/x86/include/specialreg.h	(working copy)
@@ -359,6 +359,7 @@
 #define	MSR_BIOS_SIGN		0x08b
 #define	MSR_PERFCTR0		0x0c1
 #define	MSR_PERFCTR1		0x0c2
+#define	MSR_PLATFORM_INFO	0x0ce
 #define	MSR_MPERF		0x0e7
 #define	MSR_APERF		0x0e8
 #define	MSR_IA32_EXT_CONFIG	0x0ee	/* Undocumented. Core Solo/Duo only */
@@ -377,6 +378,8 @@
 #define	MSR_MCG_CTL		0x17b
 #define	MSR_EVNTSEL0		0x186
 #define	MSR_EVNTSEL1		0x187
+#define	MSR_PERF_STATUS		0x198
+#define	MSR_PERF_CTL		0x199
 #define	MSR_THERM_CONTROL	0x19a
 #define	MSR_THERM_INTERRUPT	0x19b
 #define	MSR_THERM_STATUS	0x19c
Index: sys/x86/cpufreq/est.c
===================================================================
--- sys/x86/cpufreq/est.c	(revision 266262)
+++ sys/x86/cpufreq/est.c	(working copy)
@@ -48,12 +48,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/acpica/acpivar.h>
 #include "acpi_if.h"
 
-/* Status/control registers (from the IA-32 System Programming Guide). */
-#define MSR_PERF_STATUS		0x198
-#define MSR_PERF_CTL		0x199
-
 /* Register and bit for enabling SpeedStep. */
-#define MSR_MISC_ENABLE		0x1a0
 #define MSR_SS_ENABLE		(1<<16)
 
 /* Frequency and MSR control values. */
@@ -1006,14 +1001,14 @@ est_probe(device_t dev)
 	}
 
 	/* Attempt to enable SpeedStep if not currently enabled. */
-	msr = rdmsr(MSR_MISC_ENABLE);
+	msr = rdmsr(MSR_IA32_MISC_ENABLE);
 	if ((msr & MSR_SS_ENABLE) == 0) {
-		wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
+		wrmsr(MSR_IA32_MISC_ENABLE, msr | MSR_SS_ENABLE);
 		if (bootverbose)
 			device_printf(dev, "enabling SpeedStep\n");
 
 		/* Check if the enable failed. */
-		msr = rdmsr(MSR_MISC_ENABLE);
+		msr = rdmsr(MSR_IA32_MISC_ENABLE);
 		if ((msr & MSR_SS_ENABLE) == 0) {
 			device_printf(dev, "failed to enable SpeedStep\n");
 			return (ENXIO);