--- sys/amd64/amd64/amd64_mem.c	(revision 217079)
+++ sys/amd64/amd64/amd64_mem.c	(working copy)
@@ -307,7 +307,7 @@
 	struct mem_range_desc *mrd;
 	u_int64_t omsrv, msrv;
 	int i, j, msr;
-	u_long cr0, cr4;
+	u_long cr4;
 
 	mrd = sc->mr_desc;
 
@@ -316,8 +316,7 @@
 	load_cr4(cr4 & ~CR4_PGE);
 
 	/* Disable caches (CD = 1, NW = 0). */
-	cr0 = rcr0();
-	load_cr0((cr0 & ~CR0_NW) | CR0_CD);
+	load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
 
 	/* Flushes caches and TLBs. */
 	wbinvd();
@@ -397,7 +396,7 @@
 	wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
 
 	/* Restore caches and PGE. */
-	load_cr0(cr0);
+	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
 	load_cr4(cr4);
 }
 
--- sys/i386/i386/i686_mem.c	(revision 217079)
+++ sys/i386/i386/i686_mem.c	(working copy)
@@ -301,7 +301,7 @@
 	struct mem_range_desc *mrd;
 	u_int64_t omsrv, msrv;
 	int i, j, msr;
-	u_long cr0, cr4;
+	u_long cr4;
 
 	mrd = sc->mr_desc;
 
@@ -310,8 +310,7 @@
 	load_cr4(cr4 & ~CR4_PGE);
 
 	/* Disable caches (CD = 1, NW = 0). */
-	cr0 = rcr0();
-	load_cr0((cr0 & ~CR0_NW) | CR0_CD);
+	load_cr0((rcr0() & ~CR0_NW) | CR0_CD);
 
 	/* Flushes caches and TLBs. */
 	wbinvd();
@@ -391,7 +390,7 @@
 	wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
 
 	/* Restore caches and PGE. */
-	load_cr0(cr0);
+	load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
 	load_cr4(cr4);
 }