Index: agp_i810.c
===================================================================
RCS file: /home/ncvs/src/sys/pci/agp_i810.c,v
retrieving revision 1.32
diff -u -r1.32 agp_i810.c
--- agp_i810.c	24 Feb 2005 21:32:55 -0000	1.32
+++ agp_i810.c	7 May 2005 03:59:11 -0000
@@ -65,10 +65,12 @@
 #define READ1(off)	bus_space_read_1(sc->bst, sc->bsh, off)
 #define READ4(off)	bus_space_read_4(sc->bst, sc->bsh, off)
 #define WRITE4(off,v)	bus_space_write_4(sc->bst, sc->bsh, off, v)
+#define WRITEGTT(off,v)	bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v)
 
 #define CHIP_I810 0	/* i810/i815 */
 #define CHIP_I830 1	/* 830M/845G */
 #define CHIP_I855 2	/* 852GM/855GM/865G */
+#define CHIP_I915 3	/* 915G */
 
 struct agp_i810_softc {
 	struct agp_softc agp;
@@ -78,9 +80,14 @@
 	u_int32_t dcache_size;		/* i810 only */
 	u_int32_t stolen;		/* number of i830/845 gtt entries for stolen memory */
 	device_t bdev;			/* bridge device */
+
 	struct resource *regs;		/* memory mapped GC registers */
 	bus_space_tag_t bst;		/* bus_space tag */
 	bus_space_handle_t bsh;		/* bus_space handle */
+
+	struct resource *gtt;		/* memory mapped GATT entries */
+	bus_space_tag_t gtt_bst;	/* bus_space tag */
+	bus_space_handle_t gtt_bsh;	/* bus_space handle */
 };
 
 static const char*
@@ -129,6 +136,9 @@
 
 	case 0x25728086:
 		return ("Intel 82865G (865G GMCH) SVGA controller");
+
+	case 0x25828086:
+		return ("Intel 82915G (915G GMCH) SVGA controller");
 	};
 
 	return NULL;
@@ -160,6 +170,7 @@
 	case 0x25628086:
 	case 0x35828086:
 	case 0x25728086:
+	case 0x25828086:
 		devid -= 0x20000;
 		break;
 	};
@@ -222,6 +233,7 @@
 		case 0x35828086:
 		case 0x25628086:
 		case 0x25728086:
+		case 0x25828086:	/* XXX: Is this the right way? */
 			gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
 			if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) {
 				if (bootverbose)
@@ -272,19 +284,40 @@
 	case 0x25728086:
 		sc->chiptype = CHIP_I855;
 		break;
+	case 0x25828086:
+		sc->chiptype = CHIP_I915;
+		break;
 	};
 
 	/* Same for i810 and i830 */
-	rid = AGP_I810_MMADR;
+	if (sc->chiptype == CHIP_I915)
+		rid = AGP_I915_MMADR;
+	else
+		rid = AGP_I810_MMADR;
+
 	sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 					  RF_ACTIVE);
 	if (!sc->regs) {
 		agp_generic_detach(dev);
-		return ENOMEM;
+		return ENODEV;
 	}
 	sc->bst = rman_get_bustag(sc->regs);
 	sc->bsh = rman_get_bushandle(sc->regs);
 
+	if (sc->chiptype == CHIP_I915) {
+		rid = AGP_I915_GTTADR;
+		sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+						 RF_ACTIVE);
+		if (!sc->gtt) {
+			bus_release_resource(dev, SYS_RES_MEMORY,
+					     AGP_I810_MMADR, sc->regs);
+			agp_generic_detach(dev);
+			return ENODEV;
+		}
+		sc->gtt_bst = rman_get_bustag(sc->regs);
+		sc->gtt_bsh = rman_get_bushandle(sc->regs);
+	}
+
 	sc->initial_aperture = AGP_GET_APERTURE(dev);
 
 	gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
@@ -350,7 +383,7 @@
 		WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
 
 		gatt->ag_physical = pgtblctl & ~1;
-	} else {	/* CHIP_I855 */
+	} else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) {	/* CHIP_I855 */
 		/* The i855 automatically initializes the 128k gatt on boot. */
 		unsigned int gcc1, pgtblctl;
 		
@@ -371,6 +404,12 @@
 			case AGP_I855_GCC1_GMS_STOLEN_32M: 
 				sc->stolen = (32768 - 132) * 1024 / 4096;
 				break;
+			case AGP_I915_GCC1_GMS_STOLEN_48M: 
+				sc->stolen = (49152 - 132) * 1024 / 4096;
+				break;
+			case AGP_I915_GCC1_GMS_STOLEN_64M: 
+				sc->stolen = (65536 - 132) * 1024 / 4096;
+				break;
 			default:
 				sc->stolen = 0;
 				device_printf(dev, "unknown memory configuration, disabling\n");
@@ -425,8 +464,15 @@
 	}
 	free(sc->gatt, M_AGP);
 
-	bus_release_resource(dev, SYS_RES_MEMORY,
-			     AGP_I810_MMADR, sc->regs);
+	if (sc->chiptype == CHIP_I915) {
+		bus_release_resource(dev, SYS_RES_MEMORY,
+				     AGP_I915_GTTADR, sc->regs);
+		bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR,
+				     sc->regs);
+	} else {
+		bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR,
+				     sc->regs);
+	}
 
 	child = device_find_child( dev, "drmsub", 0 );
 	if (child)
@@ -439,34 +485,45 @@
 agp_i810_get_aperture(device_t dev)
 {
 	struct agp_i810_softc *sc = device_get_softc(dev);
+	uint32_t temp;
+	u_int16_t miscc;
 
-	if ( sc->chiptype == CHIP_I810 ) {
-		u_int16_t miscc;
+	switch (sc->chiptype) {
+	case CHIP_I810:
 		miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
 		if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
 			return 32 * 1024 * 1024;
 		else
 			return 64 * 1024 * 1024;
-	} else if ( sc->chiptype == CHIP_I830 ) {
-		unsigned int gcc1;
-
-		gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
-		if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
+	case CHIP_I830:
+		temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
+		if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
 			return 64 * 1024 * 1024;
 		else
 			return 128 * 1024 * 1024;
-	} else { /* CHIP_I855 */
+	case CHIP_I855:
 		return 128 * 1024 * 1024;
+	case CHIP_I915:
+		temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);
+		if (temp & (1 << 27)) {
+			return 128 * 1024 * 1024;
+		} else {
+			return 256 * 1024 * 1024;
+		}
 	}
+
+	return 0;
 }
 
 static int
 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
 {
 	struct agp_i810_softc *sc = device_get_softc(dev);
-	u_int16_t miscc;
+	u_int16_t miscc, gcc1;
+	u_int32_t temp;
 
-	if ( sc->chiptype == CHIP_I810 ) {
+	switch (sc->chiptype) {
+	case CHIP_I810:
 		/*
 		 * Double check for sanity.
 		 */
@@ -474,7 +531,7 @@
 			device_printf(dev, "bad aperture size %d\n", aperture);
 			return EINVAL;
 		}
-	
+
 		miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
 		miscc &= ~AGP_I810_MISCC_WINSIZE;
 		if (aperture == 32 * 1024 * 1024)
@@ -483,10 +540,10 @@
 			miscc |= AGP_I810_MISCC_WINSIZE_64;
 	
 		pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
-	} else if ( sc->chiptype == CHIP_I830 ) {
-		unsigned int gcc1;
-
-		if (aperture != 64 * 1024 * 1024 && aperture != 128 * 1024 * 1024) {
+		break;
+	case CHIP_I830:
+		if (aperture != 64 * 1024 * 1024 &&
+		    aperture != 128 * 1024 * 1024) {
 			device_printf(dev, "bad aperture size %d\n", aperture);
 			return EINVAL;
 		}
@@ -498,11 +555,30 @@
 			gcc1 |= AGP_I830_GCC1_GMASIZE_128;
 
 		pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
-	} else {	/* CHIP_I855 */
+		break;
+	case CHIP_I855:
 		if (aperture != 128 * 1024 * 1024) {
 			device_printf(dev, "bad aperture size %d\n", aperture);
 			return EINVAL;
 		}
+		break;
+	case CHIP_I915:
+		temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);
+
+		switch (aperture) {
+		case 128 * 1024 * 1024:
+			temp |= (1 << 27);
+			break;
+		case 256 * 1024 * 1024:
+			temp &= ~(1 << 27);
+			break;
+		default:
+			device_printf(dev, "bad aperture size %d\n", aperture);
+			return EINVAL;
+		}
+
+		pci_write_config(sc->bdev, AGP_I915_GMADR, temp, 4);
+		break;
 	}
 
 	return 0;
@@ -525,7 +601,12 @@
 		}
 	}
 
-	WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1);
+	if (sc->chiptype == CHIP_I915) {
+		WRITEGTT(offset >> AGP_PAGE_SHIFT, physical | 1);
+	} else {
+		WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1);
+	}
+
 	return 0;
 }
 
@@ -544,7 +625,12 @@
 		}
 	}
 
-	WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0);
+	if (sc->chiptype == CHIP_I915) {
+		WRITE4(offset >> AGP_PAGE_SHIFT, 0);
+	} else {
+		WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0);
+	}
+	
 	return 0;
 }
 
@@ -669,8 +755,8 @@
 		return EINVAL;
 
 	for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
-		WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4,
-		       i | 3);
+		WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4,
+		       offset | 3);
 	}
 
 	return 0;
Index: agpreg.h
===================================================================
RCS file: /home/ncvs/src/sys/pci/agpreg.h,v
retrieving revision 1.13
diff -u -r1.13 agpreg.h
--- agpreg.h	16 Aug 2004 12:25:48 -0000	1.13
+++ agpreg.h	6 May 2005 20:21:30 -0000
@@ -233,6 +233,15 @@
 #define AGP_I852_GM			0x5
 
 /*
+ * 915G registers
+ */
+#define AGP_I915_GMADR			0x18
+#define AGP_I915_MMADR			0x10
+#define AGP_I915_GTTADR			0x1C
+#define AGP_I915_GCC1_GMS_STOLEN_48M	0x60
+#define AGP_I915_GCC1_GMS_STOLEN_64M	0x70
+
+/*
  * NVIDIA nForce/nForce2 registers
  */
 #define	AGP_NVIDIA_0_APBASE		0x10