Index: sys/mips/atheros/ar71xx_spi.c =================================================================== --- sys/mips/atheros/ar71xx_spi.c (revision 203909) +++ sys/mips/atheros/ar71xx_spi.c (working copy) @@ -119,7 +119,9 @@ /* * Put respective CSx to low */ - ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); + /* RSPRO: only set cs low if cs=0; otherwise leave high */ + if (cs == 0) + ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl); } @@ -127,9 +129,13 @@ static void ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs) { + uint32_t ioctrl = SPI_IO_CTRL_CSMASK; /* * Put all CSx to high */ + /* RSPRO: only set cs high if cs=0; otherwise set that CS low */ + if (cs > 0) + ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK); } @@ -142,7 +148,9 @@ /* * low-level for selected CS */ - ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); + /* XXX RSPRO: if cs > 0, leave that bit high */ + if (cs == 0) + ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); uint32_t iod, rds; for (bit = 7; bit >=0; bit--) { Index: sys/mips/conf/AR71XX.hints =================================================================== --- sys/mips/conf/AR71XX.hints (revision 203909) +++ sys/mips/conf/AR71XX.hints (working copy) @@ -58,8 +58,10 @@ # shares the same bus with mx25l. # CE low for flash, CE high for RTC # at the moment it's just stub until SPI bus is ready for such hacks -# hint.rtc.0.at="spibus0" -# hint.rtc.0.cs=0 +hint.rtc.0.at="spibus0" +# XXX this CS hint will translate via magic patches to the local +# XXX SPI bus to mean "CS bit being set high first" +hint.rtc.0.cs=1 # Watchdog hint.ar71xx_wdog.0.at="nexus0"