/* RSD PTR: OEM=CORE, ACPI_Rev=2.0x (2) XSDT=0x000000007fbe4ee0, length=36, cksum=113 */ /* XSDT: Length=84, Revision=1, Checksum=174, OEMID=CORE, OEM Table ID=COREBOOT, OEM Revision=0x0, Creator ID=CORE, Creator Revision=0x0 Entries={ 0x000000007fbe73c0, 0x000000007fbe74c0, 0x000000007fbe7510, 0x000000007fbe7550, 0x000000007fbe75c0, 0x000000007fbe7700 } */ /* FACP: Length=244, Revision=4, Checksum=42, OEMID=CORE, OEM Table ID=COREBOOT, OEM Revision=0x0, Creator ID=CORE, Creator Revision=0x1 FACS=0x7fbe5010, DSDT=0x7fbe5050 INT_MODEL=PIC Preferred_PM_Profile=Desktop (1) SCI_INT=9 SMI_CMD=0x0, ACPI_ENABLE=0x0, ACPI_DISABLE=0x0, S4BIOS_REQ=0x0 PSTATE_CNT=0x0 PM1a_EVT_BLK=0x400-0x403 PM1a_CNT_BLK=0x404-0x405 PM2_CNT_BLK=0x450-0x450 PM_TMR_BLK=0x408-0x40b GPE0_BLK=0x420-0x427 P_LVL2_LAT=101 us, P_LVL3_LAT=1001 us FLUSH_SIZE=0, FLUSH_STRIDE=0 DUTY_OFFSET=1, DUTY_WIDTH=0 DAY_ALRM=13, MON_ALRM=0, CENTURY=50 IAPC_BOOT_ARCH= Flags={WBINVD,C1_SUPPORTED,C2_MP_SUPPORTED,SLEEP_BUTTON,S4_RTC_WAKE,RESET_REGISTER,SLEEP_TYPE,PLATFORM_CLOCK} RESET_REG=0xcf9:0[8] (IO), RESET_VALUE=0x6 X_FACS=0x000000007fbe5010, X_DSDT=0x000000007fbe5050 X_PM1a_EVT_BLK=0x400:0[32] (IO) X_PM1a_CNT_BLK=0x404:0[16] (IO) X_PM2_CNT_BLK=0x450:0[8] (IO) X_PM_TMR_BLK=0x408:0[32] (IO) X_GPE0_BLK=0x420:0[64] (IO) */ /* FACS: Length=64, HwSig=0x00000000, Firm_Wake_Vec=0x00000000 Global_Lock= Flags= Version=1 */ /* DSDT: Length=9057, Revision=2, Checksum=116, OEMID=COREv4, OEM Table ID=COREBOOT, OEM Revision=0x20110725, Creator ID=INTL, Creator Revision=0x20121114 */ /* SPCR: Length=80, Revision=1, Checksum=125, OEMID=CORE, OEM Table ID=COREBOOT, OEM Revision=0x0, Creator ID=CORE, Creator Revision=0x0 InterfaceType=0 (Fully 16550-compatible) SerialPort=0x2f8:0[8] (IO) InterruptType=0x1 (PC/AT IRQ) PcInterrupt=3 (Valid) Interrupt=0 BaudRate=115200 (7) Parity=0 StopBits=1 FlowControl=0 TerminalType=0 (VT100) PciDeviceId=0xffff PciVendorId=0xffff PciBus=0 PciDevice=0 PciFunction=0 PciFlags=0 PciSegment=0 */ /* HPET: Length=56, Revision=1, Checksum=112, OEMID=CORE, OEM Table ID=COREBOOT, OEM Revision=0x0, Creator ID=CORE, Creator Revision=0x0 HPET Number=0 ADDR=0x00000000fed00000:0[64] (Memory) HW Rev=0x1 Comparators=2 Counter Size=1 Legacy IRQ routing capable={TRUE} PCI Vendor ID=0x8086 Minimal Tick=128 Flags=0x00 */ /* APIC: Length=108, Revision=1, Checksum=108, OEMID=CORE, OEM Table ID=COREBOOT, OEM Revision=0x0, Creator ID=CORE, Creator Revision=0x0 Local APIC ADDR=0xfee00000 Flags={PC-AT} Type=Local APIC ACPI CPU=0 Flags={ENABLED} APIC ID=0 Type=Local APIC ACPI CPU=1 Flags={ENABLED} APIC ID=2 Type=Local APIC ACPI CPU=2 Flags={ENABLED} APIC ID=4 Type=Local APIC ACPI CPU=3 Flags={ENABLED} APIC ID=6 Type=IO APIC APIC ID=2 INT BASE=0 ADDR=0x00000000fec00000 Type=INT Override BUS=0 IRQ=0 INTR=2 Flags={Polarity=conforming, Trigger=conforming} Type=INT Override BUS=0 IRQ=9 INTR=9 Flags={Polarity=active-hi, Trigger=level} */ /* MCFG: Length=60, Revision=1, Checksum=186, OEMID=CORE, OEM Table ID=COREBOOT, OEM Revision=0x0, Creator ID=CORE, Creator Revision=0x0 Base Address=0x00000000e0000000 Segment Group=0x0000 Start Bus=0 End Bus=255 */ /* SSDT: Length=2875, Revision=2, Checksum=115, OEMID=CORE, OEM Table ID=COREBOOT, OEM Revision=0x2a, Creator ID=CORE, Creator Revision=0x2a */ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20241212 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembling to symbolic ASL+ operators * * Disassembly of /tmp/acpidump.8izmmj/acpdump.din * * Original Table Header: * Signature "DSDT" * Length 0x00002E78 (11896) * Revision 0x02 * Checksum 0x8E * OEM ID "COREv4" * OEM Table ID "COREBOOT" * OEM Revision 0x20110725 (537986853) * Compiler ID "INTL" * Compiler Version 0x20121114 (538054932) */ DefinitionBlock ("", "DSDT", 2, "COREv4", "COREBOOT", 0x20110725) { External (_PR_.CPU4, UnknownObj) External (_PR_.CPU5, UnknownObj) External (_PR_.CPU6, UnknownObj) External (_PR_.CPU7, UnknownObj) External (_TZ_.SKIN, UnknownObj) External (_TZ_.THRM, UnknownObj) OperationRegion (X80, SystemIO, 0x80, One) Field (X80, ByteAcc, NoLock, Preserve) { P80, 8 } OperationRegion (CREG, SystemIO, 0x02F8, 0x08) Field (CREG, ByteAcc, NoLock, Preserve) { CDAT, 8, CDLM, 8, Offset (0x03), DLCR, 8, CMCR, 8, CLSR, 8 } Method (DINI, 0, NotSerialized) { DLCR = 0x83 CDAT = One CDLM = Zero DLCR = 0x03 CMCR = 0x03 CDLM = Zero } Method (THRE, 0, NotSerialized) { Local0 = (CLSR & 0x20) While ((Local0 == Zero)) { Local0 = (CLSR & 0x20) } } Method (OUTX, 1, NotSerialized) { THRE () CDAT = Arg0 } Method (OUTC, 1, NotSerialized) { If ((Arg0 == 0x0A)) { OUTX (0x0D) } OUTX (Arg0) } Method (DBGN, 1, NotSerialized) { Local0 = (Arg0 & 0x0F) If ((Local0 < 0x0A)) { Local0 += 0x30 } Else { Local0 += 0x37 } OUTC (Local0) } Method (DBGB, 1, NotSerialized) { Local0 = (Arg0 >> 0x04) DBGN (Local0) DBGN (Arg0) } Method (DBGW, 1, NotSerialized) { Local0 = (Arg0 >> 0x08) DBGB (Local0) DBGB (Arg0) } Method (DBGD, 1, NotSerialized) { Local0 = (Arg0 >> 0x10) DBGW (Local0) DBGW (Arg0) } Method (DBGO, 1, NotSerialized) { If ((ObjectType (Arg0) == One)) { If ((Arg0 > 0xFFFF)) { DBGD (Arg0) } ElseIf ((Arg0 > 0xFF)) { DBGW (Arg0) } Else { DBGB (Arg0) } } Else { Name (BDBG, Buffer (0x50){}) BDBG = Arg0 Local1 = Zero While (One) { Local0 = GETC (BDBG, Local1) If ((Local0 == Zero)) { Return (Zero) } OUTC (Local0) Local1++ } } Return (Zero) } Method (GETC, 2, NotSerialized) { CreateByteField (Arg0, Arg1, DBGC) Return (DBGC) /* \GETC.DBGC */ } OperationRegion (APMP, SystemIO, 0xB2, 0x02) Field (APMP, ByteAcc, NoLock, Preserve) { APMC, 8, APMS, 8 } OperationRegion (POST, SystemIO, 0x80, One) Field (POST, ByteAcc, Lock, Preserve) { DBG0, 8 } Method (TRAP, 1, Serialized) { SMIF = Arg0 TRP0 = Zero Return (SMIF) /* \SMIF */ } Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model { PICM = Arg0 } Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep { If (S3U0) { GP47 = One } Else { GP47 = Zero } If (S3U1) { GP56 = One } Else { GP56 = Zero } } Method (_WAK, 1, NotSerialized) // _WAK: Wake { Return (Package (0x02) { Zero, Zero }) } Name (PICM, Zero) Name (DSEN, One) OperationRegion (GNVS, SystemMemory, 0x7FBE7600, 0x0F00) Field (GNVS, ByteAcc, NoLock, Preserve) { OSYS, 16, SMIF, 8, PRM0, 8, PRM1, 8, SCIF, 8, PRM2, 8, PRM3, 8, LCKF, 8, PRM4, 8, PRM5, 8, P80D, 32, LIDS, 8, PWRS, 8, TLVL, 8, FLVL, 8, TCRT, 8, TPSV, 8, TMAX, 8, F0OF, 8, F0ON, 8, F0PW, 8, F1OF, 8, F1ON, 8, F1PW, 8, F2OF, 8, F2ON, 8, F2PW, 8, F3OF, 8, F3ON, 8, F3PW, 8, F4OF, 8, F4ON, 8, F4PW, 8, TMPS, 8, Offset (0x28), APIC, 8, MPEN, 8, PCP0, 8, PCP1, 8, PPCM, 8, PCNT, 8, Offset (0x32), NATP, 8, S5U0, 8, S5U1, 8, S3U0, 8, S3U1, 8, S33G, 8, CMEM, 32, IGDS, 8, TLST, 8, CADL, 8, PADL, 8, CSTE, 16, NSTE, 16, SSTE, 16, NDID, 8, DID1, 32, DID2, 32, DID3, 32, DID4, 32, DID5, 32, Offset (0x64), BLCS, 8, BRTL, 8, ODDS, 8, Offset (0x6E), ALSE, 8, ALAF, 8, LLOW, 8, LHIH, 8, Offset (0x78), EMAE, 8, EMAP, 16, EMAL, 16, Offset (0x82), MEFE, 8, Offset (0x8C), TPMP, 8, TPME, 8, Offset (0x96), GTF0, 56, GTF1, 56, GTF2, 56, IDEM, 8, IDET, 8, Offset (0xB4), ASLB, 32, IBTT, 8, IPAT, 8, ITVF, 8, ITVM, 8, IPSC, 8, IBLC, 8, IBIA, 8, ISSC, 8, I409, 8, I509, 8, I609, 8, I709, 8, IDMM, 8, IDMS, 8, IF1E, 8, HVCO, 8, NXD1, 32, NXD2, 32, NXD3, 32, NXD4, 32, NXD5, 32, NXD6, 32, NXD7, 32, NXD8, 32, ISCI, 8, PAVP, 8, Offset (0xEB), OSCC, 8, NPCE, 8, PLFL, 8, BREV, 8, DPBM, 8, DPCM, 8, DPDM, 8, ALFP, 8, IMON, 8, MMIO, 8 } Method (S3UE, 0, NotSerialized) { S3U0 = One S3U1 = One } Method (S3UD, 0, NotSerialized) { S3U0 = Zero S3U1 = Zero } Method (S5UE, 0, NotSerialized) { S5U0 = One S5U1 = One } Method (S5UD, 0, NotSerialized) { S5U0 = Zero S5U1 = Zero } Method (S3GE, 0, NotSerialized) { S33G = One } Method (S3GD, 0, NotSerialized) { S33G = Zero } Method (TZUP, 0, NotSerialized) { If (CondRefOf (\_TZ.THRM, Local0)) { Notify (\_TZ.THRM, 0x81) // Information Change } If (CondRefOf (\_TZ.SKIN, Local0)) { Notify (\_TZ.SKIN, 0x81) // Information Change } } Method (F0UT, 2, NotSerialized) { F0OF = Arg0 F0ON = Arg1 TZUP () } Method (F1UT, 2, NotSerialized) { F1OF = Arg0 F1ON = Arg1 TZUP () } Method (F2UT, 2, NotSerialized) { F2OF = Arg0 F2ON = Arg1 TZUP () } Method (F3UT, 2, NotSerialized) { F3OF = Arg0 F3ON = Arg1 TZUP () } Method (F4UT, 2, NotSerialized) { F4OF = Arg0 F4ON = Arg1 TZUP () } Method (TMPU, 1, NotSerialized) { TMPS = Arg0 TZUP () } Method (PNOT, 0, NotSerialized) { If ((PCNT >= 0x02)) { Notify (\_PR.CPU0, 0x81) // C-State Change Notify (\_PR.CPU1, 0x81) // C-State Change } If ((PCNT >= 0x04)) { Notify (\_PR.CPU2, 0x81) // C-State Change Notify (\_PR.CPU3, 0x81) // C-State Change } If ((PCNT >= 0x08)) { Notify (\_PR.CPU4, 0x81) // Information Change Notify (\_PR.CPU5, 0x81) // Information Change Notify (\_PR.CPU6, 0x81) // Information Change Notify (\_PR.CPU7, 0x81) // Information Change } } Method (PPCN, 0, NotSerialized) { If ((PCNT >= 0x02)) { Notify (\_PR.CPU0, 0x80) // Performance Capability Change Notify (\_PR.CPU1, 0x80) // Performance Capability Change } If ((PCNT >= 0x04)) { Notify (\_PR.CPU2, 0x80) // Performance Capability Change Notify (\_PR.CPU3, 0x80) // Performance Capability Change } If ((PCNT >= 0x08)) { Notify (\_PR.CPU4, 0x80) // Status Change Notify (\_PR.CPU5, 0x80) // Status Change Notify (\_PR.CPU6, 0x80) // Status Change Notify (\_PR.CPU7, 0x80) // Status Change } } Method (TNOT, 0, NotSerialized) { If ((PCNT >= 0x02)) { Notify (\_PR.CPU0, 0x82) // Throttling Capability Change Notify (\_PR.CPU1, 0x82) // Throttling Capability Change } If ((PCNT >= 0x04)) { Notify (\_PR.CPU2, 0x82) // Throttling Capability Change Notify (\_PR.CPU3, 0x82) // Throttling Capability Change } If ((PCNT >= 0x08)) { Notify (\_PR.CPU4, 0x82) // Device-Specific Change Notify (\_PR.CPU5, 0x82) // Device-Specific Change Notify (\_PR.CPU6, 0x82) // Device-Specific Change Notify (\_PR.CPU7, 0x82) // Device-Specific Change } } Method (PPKG, 0, NotSerialized) { If ((PCNT >= 0x08)) { Return (Package (0x08) { \_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3, \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7 }) } ElseIf ((PCNT >= 0x04)) { Return (Package (0x04) { \_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3 }) } ElseIf ((PCNT >= 0x02)) { Return (Package (0x02) { \_PR.CPU0, \_PR.CPU1 }) } Else { Return (Package (0x01) { \_PR.CPU0 }) } } Scope (_SB) { Device (PCI0) { Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_ADR, Zero) // _ADR: Address Name (_BBN, Zero) // _BBN: BIOS Bus Number Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (MCRS, ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum 0x00FF, // Range Maximum 0x0000, // Translation Offset 0x0100, // Length ,, ) DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00000000, // Granularity 0x00000000, // Range Minimum 0x00000CF7, // Range Maximum 0x00000000, // Translation Offset 0x00000CF8, // Length ,, , TypeStatic, DenseTranslation) IO (Decode16, 0x0CF8, // Range Minimum 0x0CF8, // Range Maximum 0x01, // Alignment 0x08, // Length ) DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00000000, // Granularity 0x00000D00, // Range Minimum 0x0000FFFF, // Range Maximum 0x00000000, // Translation Offset 0x0000F300, // Length ,, , TypeStatic, DenseTranslation) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000A0000, // Range Minimum 0x000BFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00020000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000D0000, // Range Minimum 0x000D3FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000D4000, // Range Minimum 0x000D7FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000D8000, // Range Minimum 0x000DBFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000DC000, // Range Minimum 0x000DFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000E0000, // Range Minimum 0x000E3FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000E4000, // Range Minimum 0x000E7FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000E8000, // Range Minimum 0x000EBFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000EC000, // Range Minimum 0x000EFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000F0000, // Range Minimum 0x000FFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00010000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x00000000, // Range Minimum 0xFEBFFFFF, // Range Maximum 0x00000000, // Translation Offset 0xFEC00000, // Length ,, _Y00, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0xFED40000, // Range Minimum 0xFED44FFF, // Range Maximum 0x00000000, // Translation Offset 0x00005000, // Length ,, , AddressRangeMemory, TypeStatic) }) CreateDWordField (MCRS, \_SB.PCI0._CRS._Y00._MIN, PMIN) // _MIN: Minimum Base Address CreateDWordField (MCRS, \_SB.PCI0._CRS._Y00._MAX, PMAX) // _MAX: Maximum Base Address CreateDWordField (MCRS, \_SB.PCI0._CRS._Y00._LEN, PLEN) // _LEN: Length PMIN = BMBD /* \_SB_.PCI0.BMBD */ PLEN = ((PMAX - PMIN) + One) Return (MCRS) /* \_SB_.PCI0._CRS.MCRS */ } Device (PDRC) { Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (PDRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xE0000000, // Address Base 0x04000000, // Address Length ) }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Return (PDRS) /* \_SB_.PCI0.PDRC.PDRS */ } } Scope (\) { OperationRegion (IO_T, SystemIO, 0x0800, 0x10) Field (IO_T, ByteAcc, NoLock, Preserve) { Offset (0x08), TRP0, 8 } OperationRegion (PMIO, SystemIO, 0x0400, 0x80) Field (PMIO, ByteAcc, NoLock, Preserve) { Offset (0x20), Offset (0x22), GS00, 1, GS01, 1, GS02, 1, GS03, 1, GS04, 1, GS05, 1, GS06, 1, GS07, 1, GS08, 1, GS09, 1, GS10, 1, GS11, 1, GS12, 1, GS13, 1, GS14, 1, GS15, 1, Offset (0x28), Offset (0x2A), GE00, 1, GE01, 1, GE02, 1, GE03, 1, GE04, 1, GE05, 1, GE06, 1, GE07, 1, GE08, 1, GE09, 1, GE10, 1, GE11, 1, GE12, 1, GE13, 1, GE14, 1, GE15, 1, Offset (0x42), , 1, GPEC, 1 } OperationRegion (GPIO, SystemIO, 0x0500, 0x6C) Field (GPIO, ByteAcc, NoLock, Preserve) { GU00, 8, GU01, 8, GU02, 8, GU03, 8, GIO0, 8, GIO1, 8, GIO2, 8, GIO3, 8, Offset (0x0C), GL00, 1, GP01, 1, GP02, 1, GP0E, 1, GP04, 1, GP05, 1, GP06, 1, GP07, 1, GP08, 1, GP09, 1, GP10, 1, GP11, 1, GP12, 1, GP13, 1, GP14, 1, GP15, 1, GP16, 1, GP17, 1, GP18, 1, GP19, 1, GP20, 1, GP21, 1, GP22, 1, GP23, 1, GP24, 1, GP25, 1, GP26, 1, GP27, 1, GP28, 1, GP29, 1, GP30, 1, GP31, 1, Offset (0x18), GB00, 8, GB01, 8, GB02, 8, GB03, 8, Offset (0x2C), GIV0, 8, GIV1, 8, GIV2, 8, GIV3, 8, GU04, 8, GU05, 8, GU06, 8, GU07, 8, GIO4, 8, GIO5, 8, GIO6, 8, GIO7, 8, GP32, 1, GP33, 1, GP34, 1, GP35, 1, GP36, 1, GP37, 1, GP38, 1, GP39, 1, GP40, 1, GP41, 1, GP42, 1, GP43, 1, GP44, 1, GP45, 1, GP46, 1, GP47, 1, GP48, 1, GP49, 1, GP50, 1, GP51, 1, GP52, 1, GP53, 1, GP54, 1, GP55, 1, GP56, 1, GP57, 1, GP58, 1, GP59, 1, GP60, 1, GP61, 1, GP62, 1, GP63, 1, Offset (0x40), GU08, 8, GU09, 4, Offset (0x44), GIO8, 8, GIO9, 4, Offset (0x48), GP64, 1, GP65, 1, GP66, 1, GP67, 1, GP68, 1, GP69, 1, GP70, 1, GP71, 1, GP72, 1, GP73, 1, GP74, 1, GP75, 1 } OperationRegion (RCRB, SystemMemory, 0xFED1C000, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x1000), Offset (0x3000), Offset (0x3404), HPAS, 2, , 5, HPTE, 1, Offset (0x3418), , 1, PCID, 1, SA1D, 1, SMBD, 1, HDAD, 1, , 8, EH2D, 1, LPBD, 1, EH1D, 1, RP1D, 1, RP2D, 1, RP3D, 1, RP4D, 1, TTRD, 1, SA2D, 1, Offset (0x3428), BDFD, 1, ME1D, 1, ME2D, 1, IDRD, 1, KTCT, 1 } } Method (IRQM, 1, Serialized) { Name (IQAA, Package (0x04) { Package (0x04) { 0xFFFF, Zero, Zero, 0x10 }, Package (0x04) { 0xFFFF, One, Zero, 0x11 }, Package (0x04) { 0xFFFF, 0x02, Zero, 0x12 }, Package (0x04) { 0xFFFF, 0x03, Zero, 0x13 } }) Name (IQAP, Package (0x04) { Package (0x04) { 0xFFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0xFFFF, One, ^LPCB.LNKB, Zero }, Package (0x04) { 0xFFFF, 0x02, ^LPCB.LNKC, Zero }, Package (0x04) { 0xFFFF, 0x03, ^LPCB.LNKD, Zero } }) Name (IQBA, Package (0x04) { Package (0x04) { 0xFFFF, Zero, Zero, 0x11 }, Package (0x04) { 0xFFFF, One, Zero, 0x12 }, Package (0x04) { 0xFFFF, 0x02, Zero, 0x13 }, Package (0x04) { 0xFFFF, 0x03, Zero, 0x10 } }) Name (IQBP, Package (0x04) { Package (0x04) { 0xFFFF, Zero, ^LPCB.LNKB, Zero }, Package (0x04) { 0xFFFF, One, ^LPCB.LNKC, Zero }, Package (0x04) { 0xFFFF, 0x02, ^LPCB.LNKD, Zero }, Package (0x04) { 0xFFFF, 0x03, ^LPCB.LNKA, Zero } }) Name (IQCA, Package (0x04) { Package (0x04) { 0xFFFF, Zero, Zero, 0x12 }, Package (0x04) { 0xFFFF, One, Zero, 0x13 }, Package (0x04) { 0xFFFF, 0x02, Zero, 0x10 }, Package (0x04) { 0xFFFF, 0x03, Zero, 0x11 } }) Name (IQCP, Package (0x04) { Package (0x04) { 0xFFFF, Zero, ^LPCB.LNKC, Zero }, Package (0x04) { 0xFFFF, One, ^LPCB.LNKD, Zero }, Package (0x04) { 0xFFFF, 0x02, ^LPCB.LNKA, Zero }, Package (0x04) { 0xFFFF, 0x03, ^LPCB.LNKB, Zero } }) Name (IQDA, Package (0x04) { Package (0x04) { 0xFFFF, Zero, Zero, 0x13 }, Package (0x04) { 0xFFFF, One, Zero, 0x10 }, Package (0x04) { 0xFFFF, 0x02, Zero, 0x11 }, Package (0x04) { 0xFFFF, 0x03, Zero, 0x12 } }) Name (IQDP, Package (0x04) { Package (0x04) { 0xFFFF, Zero, ^LPCB.LNKD, Zero }, Package (0x04) { 0xFFFF, One, ^LPCB.LNKA, Zero }, Package (0x04) { 0xFFFF, 0x02, ^LPCB.LNKB, Zero }, Package (0x04) { 0xFFFF, 0x03, ^LPCB.LNKC, Zero } }) Switch (ToInteger (Arg0)) { Case (Package (0x01) { One } ) { If (PICM) { Return (IQAA) /* \_SB_.PCI0.IRQM.IQAA */ } Else { Return (IQAP) /* \_SB_.PCI0.IRQM.IQAP */ } } Case (Package (0x01) { 0x02 } ) { If (PICM) { Return (IQBA) /* \_SB_.PCI0.IRQM.IQBA */ } Else { Return (IQBP) /* \_SB_.PCI0.IRQM.IQBP */ } } Case (Package (0x01) { 0x03 } ) { If (PICM) { Return (IQCA) /* \_SB_.PCI0.IRQM.IQCA */ } Else { Return (IQCP) /* \_SB_.PCI0.IRQM.IQCP */ } } Case (Package (0x01) { 0x04 } ) { If (PICM) { Return (IQDA) /* \_SB_.PCI0.IRQM.IQDA */ } Else { Return (IQDP) /* \_SB_.PCI0.IRQM.IQDP */ } } Default { If (PICM) { Return (IQDA) /* \_SB_.PCI0.IRQM.IQDA */ } Else { Return (IQDP) /* \_SB_.PCI0.IRQM.IQDP */ } } } } Device (RP01) { Name (_ADR, 0x00010000) // _ADR: Address OperationRegion (RPCS, PCI_Config, Zero, 0xFF) Field (RPCS, AnyAcc, NoLock, Preserve) { Offset (0x4C), Offset (0x4F), RPPN, 8 } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { Return (IRQM (RPPN)) } } Device (RP02) { Name (_ADR, 0x00020000) // _ADR: Address OperationRegion (RPCS, PCI_Config, Zero, 0xFF) Field (RPCS, AnyAcc, NoLock, Preserve) { Offset (0x4C), Offset (0x4F), RPPN, 8 } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { Return (IRQM (RPPN)) } } Device (RP03) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (RPCS, PCI_Config, Zero, 0xFF) Field (RPCS, AnyAcc, NoLock, Preserve) { Offset (0x4C), Offset (0x4F), RPPN, 8 } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { Return (IRQM (RPPN)) } } Device (RP04) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (RPCS, PCI_Config, Zero, 0xFF) Field (RPCS, AnyAcc, NoLock, Preserve) { Offset (0x4C), Offset (0x4F), RPPN, 8 } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { Return (IRQM (RPPN)) } } Device (EHC1) { Name (_ADR, 0x00160000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x0D, 0x04 }) Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x02) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x02) } Device (HUB7) { Name (_ADR, Zero) // _ADR: Address Device (PRT1) { Name (_ADR, One) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address } Device (PRT3) { Name (_ADR, 0x03) // _ADR: Address } Device (PRT4) { Name (_ADR, 0x04) // _ADR: Address } Device (PRT5) { Name (_ADR, 0x05) // _ADR: Address } Device (PRT6) { Name (_ADR, 0x06) // _ADR: Address } } } Device (LPCB) { Name (_ADR, 0x001F0000) // _ADR: Address OperationRegion (LPC0, PCI_Config, Zero, 0x0100) Field (LPC0, AnyAcc, NoLock, Preserve) { Offset (0x40), PMBS, 16, Offset (0x60), PRTA, 8, PRTB, 8, PRTC, 8, PRTD, 8, Offset (0x68), PRTE, 8, PRTF, 8, PRTG, 8, PRTH, 8, Offset (0x80), IOD0, 8, IOD1, 8, Offset (0xB8), GR00, 2, GR01, 2, GR02, 2, GR03, 2, GR04, 2, GR05, 2, GR06, 2, GR07, 2, GR08, 2, GR09, 2, GR10, 2, GR11, 2, GR12, 2, GR13, 2, GR14, 2, GR15, 2, Offset (0xF0), RCEN, 1, , 13, RCBA, 18 } Device (LNKA) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTA = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLA, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTA & 0x0F)) Return (RTLA) /* \_SB_.PCI0.LPCB.LNKA._CRS.RTLA */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTA = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTA & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKB) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTB = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLB, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLB, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTB & 0x0F)) Return (RTLB) /* \_SB_.PCI0.LPCB.LNKB._CRS.RTLB */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTB = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTB & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKC) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x03) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLC, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLC, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTC & 0x0F)) Return (RTLC) /* \_SB_.PCI0.LPCB.LNKC._CRS.RTLC */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKD) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x04) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTD = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLD, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLD, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTD & 0x0F)) Return (RTLD) /* \_SB_.PCI0.LPCB.LNKD._CRS.RTLD */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTD = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTD & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKE) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x05) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTE = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLE, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLE, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTE & 0x0F)) Return (RTLE) /* \_SB_.PCI0.LPCB.LNKE._CRS.RTLE */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTE = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTE & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKF) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x06) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTF = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLF, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLF, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTF & 0x0F)) Return (RTLF) /* \_SB_.PCI0.LPCB.LNKF._CRS.RTLF */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTF = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTF & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKG) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x07) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTG = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLG, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLG, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTG & 0x0F)) Return (RTLG) /* \_SB_.PCI0.LPCB.LNKG._CRS.RTLG */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTG = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTG & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKH) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x08) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PRTH = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLH, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, ) {} }) CreateWordField (RTLH, One, IRQ0) IRQ0 = Zero IRQ0 = (One << (PRTH & 0x0F)) Return (RTLH) /* \_SB_.PCI0.LPCB.LNKH._CRS.RTLH */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, One, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PRTH = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PRTH & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (DMAC) { Name (_HID, EisaId ("PNP0200") /* PC-class DMA Controller */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0000, // Range Minimum 0x0000, // Range Maximum 0x01, // Alignment 0x20, // Length ) IO (Decode16, 0x0081, // Range Minimum 0x0081, // Range Maximum 0x01, // Alignment 0x11, // Length ) IO (Decode16, 0x0093, // Range Minimum 0x0093, // Range Maximum 0x01, // Alignment 0x0D, // Length ) IO (Decode16, 0x00C0, // Range Minimum 0x00C0, // Range Maximum 0x01, // Alignment 0x20, // Length ) DMA (Compatibility, NotBusMaster, Transfer8_16, ) {4} }) } Device (FWH) { Name (_HID, EisaId ("INT0800") /* Intel 82802 Firmware Hub Device */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadOnly, 0xFF000000, // Address Base 0x01000000, // Address Length ) }) } Device (HPET) { Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0C01") /* System Board */) // _CID: Compatible ID Name (BUF0, ResourceTemplate () { Memory32Fixed (ReadOnly, 0xFED00000, // Address Base 0x00000400, // Address Length _Y01) }) Method (_STA, 0, NotSerialized) // _STA: Status { If (HPTE) { If ((OSYS >= 0x07D1)) { Return (0x0F) } Else { Return (0x0B) } } Return (Zero) } Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { If (HPTE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET._Y01._BAS, HPT0) // _BAS: Base Address If ((HPAS == One)) { HPT0 = 0xFED01000 } If ((HPAS == 0x02)) { HPT0 = 0xFED02000 } If ((HPAS == 0x03)) { HPT0 = 0xFED03000 } } Return (BUF0) /* \_SB_.PCI0.LPCB.HPET.BUF0 */ } } Device (PIC) { Name (_HID, EisaId ("PNP0000") /* 8259-compatible Programmable Interrupt Controller */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0020, // Range Minimum 0x0020, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0024, // Range Minimum 0x0024, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0028, // Range Minimum 0x0028, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x002C, // Range Minimum 0x002C, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0030, // Range Minimum 0x0030, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0034, // Range Minimum 0x0034, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0038, // Range Minimum 0x0038, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x003C, // Range Minimum 0x003C, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00A0, // Range Minimum 0x00A0, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00A4, // Range Minimum 0x00A4, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00A8, // Range Minimum 0x00A8, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00AC, // Range Minimum 0x00AC, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00B0, // Range Minimum 0x00B0, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00B4, // Range Minimum 0x00B4, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00B8, // Range Minimum 0x00B8, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00BC, // Range Minimum 0x00BC, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x04D0, // Range Minimum 0x04D0, // Range Maximum 0x01, // Alignment 0x02, // Length ) IRQNoFlags () {2} }) } Device (MATH) { Name (_HID, EisaId ("PNP0C04") /* x87-compatible Floating Point Processing Unit */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x00F0, // Range Minimum 0x00F0, // Range Maximum 0x01, // Alignment 0x01, // Length ) IRQNoFlags () {13} }) } Device (LDRC) { Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x002E, // Range Minimum 0x002E, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x004E, // Range Minimum 0x004E, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0061, // Range Minimum 0x0061, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0063, // Range Minimum 0x0063, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0065, // Range Minimum 0x0065, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0067, // Range Minimum 0x0067, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0080, // Range Minimum 0x0080, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0092, // Range Minimum 0x0092, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x00B2, // Range Minimum 0x00B2, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0400, // Range Minimum 0x0400, // Range Maximum 0x01, // Alignment 0x80, // Length ) IO (Decode16, 0x0500, // Range Minimum 0x0500, // Range Maximum 0x01, // Alignment 0x40, // Length ) }) } Device (RTC) { Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0070, // Range Minimum 0x0070, // Range Maximum 0x01, // Alignment 0x08, // Length ) }) } Device (TIMR) { Name (_HID, EisaId ("PNP0100") /* PC-class System Timer */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0040, // Range Minimum 0x0040, // Range Maximum 0x01, // Alignment 0x04, // Length ) IO (Decode16, 0x0050, // Range Minimum 0x0050, // Range Maximum 0x10, // Alignment 0x04, // Length ) IRQNoFlags () {0} }) } } Device (SATA) { Name (_ADR, 0x00170000) // _ADR: Address Device (PRID) { Name (_ADR, Zero) // _ADR: Address Method (_GTM, 0, Serialized) // _GTM: Get Timing Mode { Name (PBUF, Buffer (0x14) { /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ /* 0010 */ 0x00, 0x00, 0x00, 0x00 // .... }) CreateDWordField (PBUF, Zero, PIO0) CreateDWordField (PBUF, 0x04, DMA0) CreateDWordField (PBUF, 0x08, PIO1) CreateDWordField (PBUF, 0x0C, DMA1) CreateDWordField (PBUF, 0x10, FLAG) Return (PBUF) /* \_SB_.PCI0.SATA.PRID._GTM.PBUF */ } Method (_STM, 3, NotSerialized) // _STM: Set Timing Mode { CreateDWordField (Arg0, Zero, PIO0) CreateDWordField (Arg0, 0x04, DMA0) CreateDWordField (Arg0, 0x08, PIO1) CreateDWordField (Arg0, 0x0C, DMA1) CreateDWordField (Arg0, 0x10, FLAG) } Device (DSK0) { Name (_ADR, Zero) // _ADR: Address } Device (DSK1) { Name (_ADR, One) // _ADR: Address } } } Device (SBUS) { Name (_ADR, 0x001F0003) // _ADR: Address } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x34) { Package (0x04) { 0x0001FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0001FFFF, One, Zero, 0x11 }, Package (0x04) { 0x0001FFFF, 0x02, Zero, 0x12 }, Package (0x04) { 0x0001FFFF, 0x03, Zero, 0x13 }, Package (0x04) { 0x0002FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0002FFFF, One, Zero, 0x11 }, Package (0x04) { 0x0002FFFF, 0x02, Zero, 0x12 }, Package (0x04) { 0x0002FFFF, 0x03, Zero, 0x13 }, Package (0x04) { 0x0003FFFF, Zero, Zero, 0x14 }, Package (0x04) { 0x0003FFFF, One, Zero, 0x15 }, Package (0x04) { 0x0003FFFF, 0x02, Zero, 0x16 }, Package (0x04) { 0x0003FFFF, 0x03, Zero, 0x17 }, Package (0x04) { 0x0004FFFF, Zero, Zero, 0x17 }, Package (0x04) { 0x0004FFFF, One, Zero, 0x16 }, Package (0x04) { 0x0004FFFF, 0x02, Zero, 0x15 }, Package (0x04) { 0x0004FFFF, 0x03, Zero, 0x14 }, Package (0x04) { 0x000BFFFF, Zero, Zero, 0x14 }, Package (0x04) { 0x000BFFFF, One, Zero, 0x15 }, Package (0x04) { 0x000BFFFF, 0x02, Zero, 0x16 }, Package (0x04) { 0x000BFFFF, 0x03, Zero, 0x17 }, Package (0x04) { 0x000EFFFF, Zero, Zero, 0x17 }, Package (0x04) { 0x000EFFFF, One, Zero, 0x10 }, Package (0x04) { 0x000EFFFF, 0x02, Zero, 0x10 }, Package (0x04) { 0x000EFFFF, 0x03, Zero, 0x10 }, Package (0x04) { 0x000FFFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x000FFFFF, One, Zero, 0x10 }, Package (0x04) { 0x000FFFFF, 0x02, Zero, 0x10 }, Package (0x04) { 0x000FFFFF, 0x03, Zero, 0x11 }, Package (0x04) { 0x0013FFFF, Zero, Zero, 0x11 }, Package (0x04) { 0x0013FFFF, One, Zero, 0x10 }, Package (0x04) { 0x0013FFFF, 0x02, Zero, 0x10 }, Package (0x04) { 0x0013FFFF, 0x03, Zero, 0x10 }, Package (0x04) { 0x0014FFFF, Zero, Zero, 0x12 }, Package (0x04) { 0x0014FFFF, One, Zero, 0x13 }, Package (0x04) { 0x0014FFFF, 0x02, Zero, 0x14 }, Package (0x04) { 0x0014FFFF, 0x03, Zero, 0x15 }, Package (0x04) { 0x0016FFFF, Zero, Zero, 0x16 }, Package (0x04) { 0x0016FFFF, One, Zero, 0x10 }, Package (0x04) { 0x0016FFFF, 0x02, Zero, 0x10 }, Package (0x04) { 0x0016FFFF, 0x03, Zero, 0x10 }, Package (0x04) { 0x0017FFFF, Zero, Zero, 0x17 }, Package (0x04) { 0x0017FFFF, One, Zero, 0x10 }, Package (0x04) { 0x0017FFFF, 0x02, Zero, 0x10 }, Package (0x04) { 0x0017FFFF, 0x03, Zero, 0x10 }, Package (0x04) { 0x0018FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0018FFFF, One, Zero, 0x10 }, Package (0x04) { 0x0018FFFF, 0x02, Zero, 0x10 }, Package (0x04) { 0x0018FFFF, 0x03, Zero, 0x11 }, Package (0x04) { 0x001FFFFF, Zero, Zero, 0x17 }, Package (0x04) { 0x001FFFFF, One, Zero, 0x16 }, Package (0x04) { 0x001FFFFF, 0x02, Zero, 0x11 }, Package (0x04) { 0x001FFFFF, 0x03, Zero, 0x12 } }) } Else { Return (Package (0x34) { Package (0x04) { 0x0001FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0001FFFF, One, ^LPCB.LNKB, Zero }, Package (0x04) { 0x0001FFFF, 0x02, ^LPCB.LNKC, Zero }, Package (0x04) { 0x0001FFFF, 0x03, ^LPCB.LNKD, Zero }, Package (0x04) { 0x0002FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0002FFFF, One, ^LPCB.LNKB, Zero }, Package (0x04) { 0x0002FFFF, 0x02, ^LPCB.LNKC, Zero }, Package (0x04) { 0x0002FFFF, 0x03, ^LPCB.LNKD, Zero }, Package (0x04) { 0x0003FFFF, Zero, ^LPCB.LNKE, Zero }, Package (0x04) { 0x0003FFFF, One, ^LPCB.LNKF, Zero }, Package (0x04) { 0x0003FFFF, 0x02, ^LPCB.LNKG, Zero }, Package (0x04) { 0x0003FFFF, 0x03, ^LPCB.LNKH, Zero }, Package (0x04) { 0x0004FFFF, Zero, ^LPCB.LNKH, Zero }, Package (0x04) { 0x0004FFFF, One, ^LPCB.LNKG, Zero }, Package (0x04) { 0x0004FFFF, 0x02, ^LPCB.LNKF, Zero }, Package (0x04) { 0x0004FFFF, 0x03, ^LPCB.LNKE, Zero }, Package (0x04) { 0x000BFFFF, Zero, ^LPCB.LNKE, Zero }, Package (0x04) { 0x000BFFFF, One, ^LPCB.LNKF, Zero }, Package (0x04) { 0x000BFFFF, 0x02, ^LPCB.LNKG, Zero }, Package (0x04) { 0x000BFFFF, 0x03, ^LPCB.LNKH, Zero }, Package (0x04) { 0x000EFFFF, Zero, ^LPCB.LNKH, Zero }, Package (0x04) { 0x000EFFFF, One, ^LPCB.LNKA, Zero }, Package (0x04) { 0x000EFFFF, 0x02, ^LPCB.LNKA, Zero }, Package (0x04) { 0x000EFFFF, 0x03, ^LPCB.LNKA, Zero }, Package (0x04) { 0x000FFFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x000FFFFF, One, ^LPCB.LNKA, Zero }, Package (0x04) { 0x000FFFFF, 0x02, ^LPCB.LNKA, Zero }, Package (0x04) { 0x000FFFFF, 0x03, ^LPCB.LNKB, Zero }, Package (0x04) { 0x0013FFFF, Zero, ^LPCB.LNKB, Zero }, Package (0x04) { 0x0013FFFF, One, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0013FFFF, 0x02, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0013FFFF, 0x03, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0014FFFF, Zero, ^LPCB.LNKC, Zero }, Package (0x04) { 0x0014FFFF, One, ^LPCB.LNKD, Zero }, Package (0x04) { 0x0014FFFF, 0x02, ^LPCB.LNKE, Zero }, Package (0x04) { 0x0014FFFF, 0x03, ^LPCB.LNKF, Zero }, Package (0x04) { 0x0016FFFF, Zero, ^LPCB.LNKG, Zero }, Package (0x04) { 0x0016FFFF, One, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0016FFFF, 0x02, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0016FFFF, 0x03, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0017FFFF, Zero, ^LPCB.LNKH, Zero }, Package (0x04) { 0x0017FFFF, One, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0017FFFF, 0x02, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0017FFFF, 0x03, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0018FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0018FFFF, One, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0018FFFF, 0x02, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0018FFFF, 0x03, ^LPCB.LNKB, Zero }, Package (0x04) { 0x001FFFFF, Zero, ^LPCB.LNKH, Zero }, Package (0x04) { 0x001FFFFF, One, ^LPCB.LNKG, Zero }, Package (0x04) { 0x001FFFFF, 0x02, ^LPCB.LNKB, Zero }, Package (0x04) { 0x001FFFFF, 0x03, ^LPCB.LNKC, Zero } }) } } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) { Return (Arg3) } Else { CreateDWordField (Arg3, Zero, CDW1) CDW1 |= 0x04 Return (Arg3) } } } } Name (_S0, Package (0x04) // _S0_: S0 System State { Zero, Zero, Zero, Zero }) Name (_S4, Package (0x04) // _S4_: S4 System State { 0x06, 0x06, Zero, Zero }) Name (_S5, Package (0x04) // _S5_: S5 System State { 0x07, 0x07, Zero, Zero }) Scope (\_SB.PCI0) { Name (BMBD, 0x80000000) } Processor (\_PR.CPU0, 0x00, 0x00000510, 0x06) { Name (_PCT, Package (0x02) // _PCT: Performance Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities { Return (PPCM) /* \PPCM */ } Name (_PSD, Package (0x01) // _PSD: Power State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FE, 0x00000004 } }) Name (_PSS, Package (0x07) // _PSS: Performance Supported States { Package (0x06) { 0x00000960, 0x00000008, 0x0000000A, 0x0000000A, 0x00001800, 0x00001800 }, Package (0x06) { 0x00000898, 0x00000000, 0x0000000A, 0x0000000A, 0x00001600, 0x00001600 }, Package (0x06) { 0x000007D0, 0x00000000, 0x0000000A, 0x0000000A, 0x00001400, 0x00001400 }, Package (0x06) { 0x00000708, 0x00000000, 0x0000000A, 0x0000000A, 0x00001200, 0x00001200 }, Package (0x06) { 0x00000640, 0x00000000, 0x0000000A, 0x0000000A, 0x00001000, 0x00001000 }, Package (0x06) { 0x00000578, 0x00000000, 0x0000000A, 0x0000000A, 0x00000E00, 0x00000E00 }, Package (0x06) { 0x000004B0, 0x00000000, 0x0000000A, 0x0000000A, 0x00000C00, 0x00000C00 } }) Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FC, 0x00000004 } }) Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities { Return (\TLVL) } Name (_TSS, Package (0x08) // _TSS: Throttling Supported States { Package (0x05) { 0x00000064, 0x000003E8, 0x00000000, 0x00000000, 0x00000000 }, Package (0x05) { 0x00000058, 0x0000036B, 0x00000000, 0x0000001F, 0x00000000 }, Package (0x05) { 0x0000004B, 0x000002EE, 0x00000000, 0x0000001E, 0x00000000 }, Package (0x05) { 0x0000003F, 0x00000271, 0x00000000, 0x0000001D, 0x00000000 }, Package (0x05) { 0x00000032, 0x000001F4, 0x00000000, 0x0000001C, 0x00000000 }, Package (0x05) { 0x00000026, 0x00000177, 0x00000000, 0x0000001B, 0x00000000 }, Package (0x05) { 0x00000019, 0x000000FA, 0x00000000, 0x0000001A, 0x00000000 }, Package (0x05) { 0x0000000D, 0x0000007D, 0x00000000, 0x00000019, 0x00000000 } }) } Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00) { Name (_PCT, Package (0x02) // _PCT: Performance Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities { Return (PPCM) /* \PPCM */ } Name (_PSD, Package (0x01) // _PSD: Power State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FE, 0x00000004 } }) Name (_PSS, Package (0x07) // _PSS: Performance Supported States { Package (0x06) { 0x00000960, 0x00000008, 0x0000000A, 0x0000000A, 0x00001800, 0x00001800 }, Package (0x06) { 0x00000898, 0x00000000, 0x0000000A, 0x0000000A, 0x00001600, 0x00001600 }, Package (0x06) { 0x000007D0, 0x00000000, 0x0000000A, 0x0000000A, 0x00001400, 0x00001400 }, Package (0x06) { 0x00000708, 0x00000000, 0x0000000A, 0x0000000A, 0x00001200, 0x00001200 }, Package (0x06) { 0x00000640, 0x00000000, 0x0000000A, 0x0000000A, 0x00001000, 0x00001000 }, Package (0x06) { 0x00000578, 0x00000000, 0x0000000A, 0x0000000A, 0x00000E00, 0x00000E00 }, Package (0x06) { 0x000004B0, 0x00000000, 0x0000000A, 0x0000000A, 0x00000C00, 0x00000C00 } }) Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FC, 0x00000004 } }) Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities { Return (\TLVL) } Name (_TSS, Package (0x08) // _TSS: Throttling Supported States { Package (0x05) { 0x00000064, 0x000003E8, 0x00000000, 0x00000000, 0x00000000 }, Package (0x05) { 0x00000058, 0x0000036B, 0x00000000, 0x0000001F, 0x00000000 }, Package (0x05) { 0x0000004B, 0x000002EE, 0x00000000, 0x0000001E, 0x00000000 }, Package (0x05) { 0x0000003F, 0x00000271, 0x00000000, 0x0000001D, 0x00000000 }, Package (0x05) { 0x00000032, 0x000001F4, 0x00000000, 0x0000001C, 0x00000000 }, Package (0x05) { 0x00000026, 0x00000177, 0x00000000, 0x0000001B, 0x00000000 }, Package (0x05) { 0x00000019, 0x000000FA, 0x00000000, 0x0000001A, 0x00000000 }, Package (0x05) { 0x0000000D, 0x0000007D, 0x00000000, 0x00000019, 0x00000000 } }) } Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00) { Name (_PCT, Package (0x02) // _PCT: Performance Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities { Return (PPCM) /* \PPCM */ } Name (_PSD, Package (0x01) // _PSD: Power State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FE, 0x00000004 } }) Name (_PSS, Package (0x07) // _PSS: Performance Supported States { Package (0x06) { 0x00000960, 0x00000008, 0x0000000A, 0x0000000A, 0x00001800, 0x00001800 }, Package (0x06) { 0x00000898, 0x00000000, 0x0000000A, 0x0000000A, 0x00001600, 0x00001600 }, Package (0x06) { 0x000007D0, 0x00000000, 0x0000000A, 0x0000000A, 0x00001400, 0x00001400 }, Package (0x06) { 0x00000708, 0x00000000, 0x0000000A, 0x0000000A, 0x00001200, 0x00001200 }, Package (0x06) { 0x00000640, 0x00000000, 0x0000000A, 0x0000000A, 0x00001000, 0x00001000 }, Package (0x06) { 0x00000578, 0x00000000, 0x0000000A, 0x0000000A, 0x00000E00, 0x00000E00 }, Package (0x06) { 0x000004B0, 0x00000000, 0x0000000A, 0x0000000A, 0x00000C00, 0x00000C00 } }) Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FC, 0x00000004 } }) Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities { Return (\TLVL) } Name (_TSS, Package (0x08) // _TSS: Throttling Supported States { Package (0x05) { 0x00000064, 0x000003E8, 0x00000000, 0x00000000, 0x00000000 }, Package (0x05) { 0x00000058, 0x0000036B, 0x00000000, 0x0000001F, 0x00000000 }, Package (0x05) { 0x0000004B, 0x000002EE, 0x00000000, 0x0000001E, 0x00000000 }, Package (0x05) { 0x0000003F, 0x00000271, 0x00000000, 0x0000001D, 0x00000000 }, Package (0x05) { 0x00000032, 0x000001F4, 0x00000000, 0x0000001C, 0x00000000 }, Package (0x05) { 0x00000026, 0x00000177, 0x00000000, 0x0000001B, 0x00000000 }, Package (0x05) { 0x00000019, 0x000000FA, 0x00000000, 0x0000001A, 0x00000000 }, Package (0x05) { 0x0000000D, 0x0000007D, 0x00000000, 0x00000019, 0x00000000 } }) } Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00) { Name (_PCT, Package (0x02) // _PCT: Performance Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities { Return (PPCM) /* \PPCM */ } Name (_PSD, Package (0x01) // _PSD: Power State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FE, 0x00000004 } }) Name (_PSS, Package (0x07) // _PSS: Performance Supported States { Package (0x06) { 0x00000960, 0x00000008, 0x0000000A, 0x0000000A, 0x00001800, 0x00001800 }, Package (0x06) { 0x00000898, 0x00000000, 0x0000000A, 0x0000000A, 0x00001600, 0x00001600 }, Package (0x06) { 0x000007D0, 0x00000000, 0x0000000A, 0x0000000A, 0x00001400, 0x00001400 }, Package (0x06) { 0x00000708, 0x00000000, 0x0000000A, 0x0000000A, 0x00001200, 0x00001200 }, Package (0x06) { 0x00000640, 0x00000000, 0x0000000A, 0x0000000A, 0x00001000, 0x00001000 }, Package (0x06) { 0x00000578, 0x00000000, 0x0000000A, 0x0000000A, 0x00000E00, 0x00000E00 }, Package (0x06) { 0x000004B0, 0x00000000, 0x0000000A, 0x0000000A, 0x00000C00, 0x00000C00 } }) Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies { Package (0x05) { 0x05, 0x00, 0x00000000, 0x000000FC, 0x00000004 } }) Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities { Return (\TLVL) } Name (_TSS, Package (0x08) // _TSS: Throttling Supported States { Package (0x05) { 0x00000064, 0x000003E8, 0x00000000, 0x00000000, 0x00000000 }, Package (0x05) { 0x00000058, 0x0000036B, 0x00000000, 0x0000001F, 0x00000000 }, Package (0x05) { 0x0000004B, 0x000002EE, 0x00000000, 0x0000001E, 0x00000000 }, Package (0x05) { 0x0000003F, 0x00000271, 0x00000000, 0x0000001D, 0x00000000 }, Package (0x05) { 0x00000032, 0x000001F4, 0x00000000, 0x0000001C, 0x00000000 }, Package (0x05) { 0x00000026, 0x00000177, 0x00000000, 0x0000001B, 0x00000000 }, Package (0x05) { 0x00000019, 0x000000FA, 0x00000000, 0x0000001A, 0x00000000 }, Package (0x05) { 0x0000000D, 0x0000007D, 0x00000000, 0x00000019, 0x00000000 } }) } }