diff --git a/sys/dev/rtwn/rtl8192e/r92e_chan.c b/sys/dev/rtwn/rtl8192e/r92e_chan.c
index 4c7121a80c89..173fb336ca91 100644
--- a/sys/dev/rtwn/rtl8192e/r92e_chan.c
+++ b/sys/dev/rtwn/rtl8192e/r92e_chan.c
@@ -209,7 +209,8 @@ r92e_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo)
 	rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
 	    R92C_FPGA0_ANAPARAM2_CBW20, 0);
 
-	rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
+	rtwn_bb_setbits(sc, R92C_FPGA0_POWER_SAVE, 0x0c000000,
+	    (prichlo ? 2 : 1) << 26);
 }
 
 static void
diff --git a/sys/dev/rtwn/rtl8192e/r92e_init.c b/sys/dev/rtwn/rtl8192e/r92e_init.c
index 077c64626f8c..1667da5153f2 100644
--- a/sys/dev/rtwn/rtl8192e/r92e_init.c
+++ b/sys/dev/rtwn/rtl8192e/r92e_init.c
@@ -368,6 +368,10 @@ r92e_power_off(struct rtwn_softc *sc)
 		return;
 	}
 
+	/*
+	 * This is disabled for now; it causes the NIC to not
+	 * power back on again successfully.
+	 */
 #if 0
 	/* SOP option to disable BG/MB. */
 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
@@ -384,6 +388,10 @@ r92e_power_off(struct rtwn_softc *sc)
 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
 	    R92C_APS_FSMCO_AFSM_HSUS, 1);
 
+	/*
+	 * This is disabled for now; it causes the NIC to not
+	 * power back on again successfully.
+	 */
 #if 0
 	/* Enable SW LPS. */
 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
diff --git a/sys/dev/rtwn/rtl8192e/r92e_rf.c b/sys/dev/rtwn/rtl8192e/r92e_rf.c
index 8e05a827262b..74552282f36f 100644
--- a/sys/dev/rtwn/rtl8192e/r92e_rf.c
+++ b/sys/dev/rtwn/rtl8192e/r92e_rf.c
@@ -63,10 +63,12 @@ r92e_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr)
 	rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
 	    RW(val, R92C_HSSI_PARAM2_READ_ADDR, addr) &
 	    ~R92C_HSSI_PARAM2_READ_EDGE);
+	rtwn_delay(sc, 10);
 
 	rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), R92C_HSSI_PARAM2_READ_EDGE, 0);
+	rtwn_delay(sc, 100);
 	rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), 0, R92C_HSSI_PARAM2_READ_EDGE);
-	rtwn_delay(sc, 20);
+	rtwn_delay(sc, 10);
 
 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
 		val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
@@ -79,8 +81,9 @@ void
 r92e_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
 {
 
-	rtwn_bb_setbits(sc, 0x818, 0x20000, 0);
+	rtwn_bb_setbits(sc, R92C_FPGA0_POWER_SAVE, 0x20000, 0);
 	rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
 	    SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
-	rtwn_bb_setbits(sc, 0x818, 0, 0x20000);
+	rtwn_delay(sc, 1);
+	rtwn_bb_setbits(sc, R92C_FPGA0_POWER_SAVE, 0, 0x20000);
 }