/*- * Copyright (c) 2004 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD: src/sys/dev/vge/if_vge.c,v 1.32 2007/11/22 02:45:00 yongari Exp $"); /* * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. * * Written by Bill Paul * Senior Networking Software Engineer * Wind River Systems */ /* * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that * combines a tri-speed ethernet MAC and PHY, with the following * features: * * o Jumbo frame support up to 16K * o Transmit and receive flow control * o IPv4 checksum offload * o VLAN tag insertion and stripping * o TCP large send * o 64-bit multicast hash table filter * o 64 entry CAM filter * o 16K RX FIFO and 48K TX FIFO memory * o Interrupt moderation * * The VT6122 supports up to four transmit DMA queues. The descriptors * in the transmit ring can address up to 7 data fragments; frames which * span more than 7 data buffers must be coalesced, but in general the * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments * long. The receive descriptors address only a single buffer. * * There are two peculiar design issues with the VT6122. One is that * receive data buffers must be aligned on a 32-bit boundary. This is * not a problem where the VT6122 is used as a LOM device in x86-based * systems, but on architectures that generate unaligned access traps, we * have to do some copying. * * The other issue has to do with the way 64-bit addresses are handled. * The DMA descriptors only allow you to specify 48 bits of addressing * information. The remaining 16 bits are specified using one of the * I/O registers. If you only have a 32-bit system, then this isn't * an issue, but if you have a 64-bit system and more than 4GB of * memory, you must have to make sure your network data buffers reside * in the same 48-bit 'segment.' * * Special thanks to Ryan Fu at VIA Networking for providing documentation * and sample NICs for testing. */ #ifdef HAVE_KERNEL_OPTION_HEADERS #include "opt_device_polling.h" #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if 1 #include #include #else #include "if_vgereg.h" #include "if_vgevar.h" #endif /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" /* Define the following to disable printing Rx errors. */ #undef VGE_SHOW_ERRORS #undef VGE_EEPROM #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) MODULE_DEPEND(vge, pci, 1, 1, 1); MODULE_DEPEND(vge, ether, 1, 1, 1); MODULE_DEPEND(vge, miibus, 1, 1, 1); /* Tunables. */ static int msi_disable = 0; static int msix_disable = 0; TUNABLE_INT("hw.vge.msi_disable", &msi_disable); TUNABLE_INT("hw.vge.msix_disable", &msix_disable); /* * Various supported device vendors/types and their names. */ static struct vge_type vge_devs[] = { { VIA_VENDORID, VIA_DEVICEID_61XX, "VIA Networking Gigabit Ethernet" }, { 0, 0, NULL } }; static int vge_probe (device_t); static int vge_attach (device_t); static int vge_detach (device_t); static int vge_encap (struct vge_softc *, struct mbuf **); static void vge_sysctl_node (struct vge_softc *); static void vge_dmamap_cb (void *, bus_dma_segment_t *, int, int); static int vge_dma_alloc (struct vge_softc *); static void vge_dma_free (struct vge_softc *); static void vge_discard_rxbuf (struct vge_softc *, int); static int vge_newbuf (struct vge_softc *, int); static int vge_rx_list_init (struct vge_softc *); static int vge_tx_list_init (struct vge_softc *); static void vge_freebufs (struct vge_softc *); #ifndef __NO_STRICT_ALIGNMENT static __inline void vge_fixup_rx (struct mbuf *); #endif static int vge_rxeof (struct vge_softc *, int); static void vge_txeof (struct vge_softc *); static int vge_intr (void *); static void vge_int_task (void *, int); static void vge_tick (void *); static void vge_tx_task (void *, int); static void vge_start (struct ifnet *); static void vge_mac_config (struct vge_softc *); static int vge_ioctl (struct ifnet *, u_long, caddr_t); static void vge_init (void *); static void vge_init_locked (struct vge_softc *); static void vge_intr_holdoff (struct vge_softc *); static void vge_stats_clear (struct vge_softc *); static void vge_stats_update (struct vge_softc *); static void vge_start_mac (struct vge_softc *); static void vge_stop_mac (struct vge_softc *); static void vge_stop (struct vge_softc *); static void vge_watchdog (struct vge_softc *); static int vge_suspend (device_t); static int vge_resume (device_t); static int vge_shutdown (device_t); static int vge_ifmedia_upd (struct ifnet *); static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); #ifdef VGE_EEPROM static void vge_eeprom_getword (struct vge_softc *, int, uint16_t *); #endif static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); static int vge_miibus_readreg (device_t, int, int); static int vge_miibus_writereg (device_t, int, int, int); static void vge_miibus_statchg (device_t); static void vge_cam_init (struct vge_softc *); static void vge_cam_mask (struct vge_softc *, int, uint8_t *); static int vge_cam_data (struct vge_softc *, int, int, uint8_t *); static void vge_rxfilter (struct vge_softc *); static void vge_reset (struct vge_softc *); static void vge_setlinkspeed (struct vge_softc *); static void vge_setwol (struct vge_softc *); static void vge_clrwol (struct vge_softc *); static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); static int sysctl_hw_vge_int_holdoff (SYSCTL_HANDLER_ARGS); static int sysctl_hw_vge_proc_limit (SYSCTL_HANDLER_ARGS); static int sysctl_hw_vge_rx_coal_pkt (SYSCTL_HANDLER_ARGS); static int sysctl_hw_vge_tx_coal_pkt (SYSCTL_HANDLER_ARGS); static device_method_t vge_methods[] = { /* Device interface */ DEVMETHOD(device_probe, vge_probe), DEVMETHOD(device_attach, vge_attach), DEVMETHOD(device_detach, vge_detach), DEVMETHOD(device_suspend, vge_suspend), DEVMETHOD(device_resume, vge_resume), DEVMETHOD(device_shutdown, vge_shutdown), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* MII interface */ DEVMETHOD(miibus_readreg, vge_miibus_readreg), DEVMETHOD(miibus_writereg, vge_miibus_writereg), DEVMETHOD(miibus_statchg, vge_miibus_statchg), { 0, 0 } }; static driver_t vge_driver = { "vge", vge_methods, sizeof(struct vge_softc) }; static devclass_t vge_devclass; DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); static struct resource_spec vge_res_spec_mem[] = { { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, { -1, 0, 0 } }; static struct resource_spec vge_irq_spec_legacy[] = { { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0, 0 } }; static struct resource_spec vge_irq_spec_msi[] = { { SYS_RES_IRQ, 1, RF_ACTIVE }, { -1, 0, 0 } }; #ifdef VGE_EEPROM /* * Read a word of data stored in the EEPROM at address 'addr.' */ static void vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) { int i; uint16_t word = 0; /* * Enter EEPROM embedded programming mode. In order to * access the EEPROM at all, we first have to set the * EELOAD bit in the CHIPCFG2 register. */ CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); /* Select the address of the word we want to read */ CSR_WRITE_1(sc, VGE_EEADDR, addr); /* Issue read command */ CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); /* Wait for the done bit to be set. */ for (i = 0; i < VGE_TIMEOUT; i++) { if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "EEPROM read timed out\n"); *dest = 0; return; } /* Read the result */ word = CSR_READ_2(sc, VGE_EERDDAT); /* Turn off EEPROM access mode. */ CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); *dest = word; } #endif /* * Read a sequence of words from the EEPROM. */ static void vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) { int i; #ifdef VGE_EEPROM uint16_t word = 0, *ptr; for (i = 0; i < cnt; i++) { vge_eeprom_getword(sc, off + i, &word); ptr = (uint16_t *)(dest + (i * 2)); if (swap) *ptr = ntohs(word); else *ptr = word; } #else for (i = 0; i < ETHER_ADDR_LEN; i++) dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); #endif } static void vge_mii_idle(struct vge_softc *sc) { int i; CSR_WRITE_1(sc, VGE_MIICMD, 0); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) != 0) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); } static int vge_miibus_readreg(device_t dev, int phy, int reg) { struct vge_softc *sc; int i; sc = device_get_softc(dev); if (phy != sc->vge_phyaddr) return (0); /* Specify the register we want to read. */ CSR_WRITE_1(sc, VGE_MIIADDR, reg); /* Issue read command. */ CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); /* Wait for the read command bit to self-clear. */ for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(10); if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "MII read timed out\n"); return (0); } return (CSR_READ_2(sc, VGE_MIIDATA)); } static int vge_miibus_writereg(device_t dev, int phy, int reg, int data) { struct vge_softc *sc; int i; sc = device_get_softc(dev); if (phy != sc->vge_phyaddr) return (0); /* Specify the register we want to write. */ CSR_WRITE_1(sc, VGE_MIIADDR, reg); /* Specify the data we want to write. */ CSR_WRITE_2(sc, VGE_MIIDATA, data); /* Issue write command. */ CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); /* Wait for the write command bit to self-clear. */ for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "MII write timed out\n"); return (0); } static void vge_cam_init(struct vge_softc *sc) { uint8_t cam_mask[VGE_CAM_MAXADDRS / 8]; uint8_t vid[2]; /* Disable all CAM entries. */ bzero(cam_mask, sizeof(cam_mask)); vge_cam_mask(sc, VGE_MCAST_CAM, cam_mask); vge_cam_mask(sc, VGE_VLAN_CAM, cam_mask); /* Enable the the first VLAN entry. */ vid[0] = vid[1] = 0; vge_cam_data(sc, VGE_VLAN_CAM, 0, vid); cam_mask[0] |= 1; vge_cam_mask(sc, VGE_VLAN_CAM, cam_mask); } static void vge_cam_mask(struct vge_softc *sc, int type, uint8_t *mask) { uint8_t cam; int i; cam = CSR_READ_1(sc, VGE_CAMCTL); cam &= ~VGE_PAGESEL_CAMMASK; cam |= VGE_PAGESEL_CAMMASK; CSR_WRITE_1(sc, VGE_CAMCTL, cam); if (type == VGE_MCAST_CAM) { CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | VGE_CAMADDR_MARCAM); } else { CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | VGE_CAMADDR_VLANCAM); } for (i = 0; i < VGE_CAM_MAXADDRS / 8; i++) CSR_WRITE_1(sc, VGE_CAM0 + i, *mask++); CSR_WRITE_1(sc, VGE_CAMADDR, 0); cam = CSR_READ_1(sc, VGE_CAMCTL); cam &= ~VGE_PAGESEL_CAMMASK; cam |= VGE_PAGESEL_MAR; CSR_WRITE_1(sc, VGE_CAMCTL, cam); } static int vge_cam_data(struct vge_softc *sc, int type, int idx, uint8_t *addr) { uint8_t cam; int error, i; if (idx >= VGE_CAM_MAXADDRS) return (EINVAL); error = 0; cam = CSR_READ_1(sc, VGE_CAMCTL); cam &= ~VGE_PAGESEL_CAMMASK; cam |= VGE_PAGESEL_CAMDATA; CSR_WRITE_1(sc, VGE_CAMCTL, cam); if (type == VGE_MCAST_CAM) { CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | idx); for (i = 0; i < ETHER_ADDR_LEN; i++) CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); } else { CSR_WRITE_1(sc, VGE_CAMADDR, idx | VGE_CAMADDR_ENABLE | VGE_CAMADDR_VLANCAM); CSR_WRITE_1(sc, VGE_CAM0, addr[0]); CSR_WRITE_1(sc, VGE_CAM1, addr[1]); } /* Issue a write command. */ CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "writing CAM entry timedout!\n"); error = ETIMEDOUT; } CSR_WRITE_1(sc, VGE_CAMADDR, 0); cam = CSR_READ_1(sc, VGE_CAMCTL); cam &= ~VGE_PAGESEL_CAMMASK; cam |= VGE_PAGESEL_MAR; CSR_WRITE_1(sc, VGE_CAMCTL, cam); return (error); } static void vge_set_vlan(struct vge_softc *sc) { struct ifnet *ifp; uint32_t cfg; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; cfg = CSR_READ_1(sc, VGE_RXCFG); if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) cfg |= VGE_VTAG_OPT2; else cfg &= ~VGE_VTAG_OPT2; CSR_WRITE_1(sc, VGE_RXCFG, cfg); } /* * Program the multicast filter. We use the 64-entry CAM filter * for perfect filtering. If there's more than 64 multicast addresses, * we use the hash filter insted. */ static void vge_rxfilter(struct vge_softc *sc) { struct ifnet *ifp; int cam_idx, error = 0; struct ifmultiaddr *ifma; uint8_t cam_mask[VGE_CAM_MAXADDRS / 8]; uint32_t h, hashes[2], rxcfg; VGE_LOCK_ASSERT(sc); /* First, zot all the multicast entries. */ hashes[0] = 0; hashes[1] = 0; rxcfg = CSR_READ_1(sc, VGE_RXCTL); rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_PROMISC); /* * Always allow VLAN oversized frames and frames for * this host. */ rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST; ifp = sc->vge_ifp; if ((ifp->if_flags & IFF_BROADCAST) != 0) rxcfg |= VGE_RXCTL_RX_BCAST; if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { if ((ifp->if_flags & IFF_PROMISC) != 0) rxcfg |= VGE_RXCTL_RX_PROMISC; if ((ifp->if_flags & IFF_ALLMULTI) != 0) { hashes[0] = 0xFFFFFFFF; hashes[1] = 0xFFFFFFFF; } goto done; } /* Now program new ones */ IF_ADDR_LOCK(ifp); cam_idx = 0; bzero(cam_mask, sizeof(cam_mask)); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; error = vge_cam_data(sc, VGE_MCAST_CAM, cam_idx, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); if (error != 0) { bzero(cam_mask, sizeof(cam_mask)); break; } cam_mask[cam_idx / 8] |= 1 << (cam_idx & 7); cam_idx++; } vge_cam_mask(sc, VGE_MCAST_CAM, cam_mask); /* If there were too many addresses, use the hash filter. */ if (error != 0) { TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; if (h < 32) hashes[0] |= (1 << h); else hashes[1] |= (1 << (h - 32)); } } IF_ADDR_UNLOCK(ifp); done: if (hashes[0] != 0 || hashes[1] != 0) rxcfg |= VGE_RXCTL_RX_MCAST; CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); CSR_WRITE_1(sc, VGE_RXCTL, rxcfg); } static void vge_reset(struct vge_softc *sc) { int i; CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(5); if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "soft reset timed out"); CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); DELAY(2000); } } /* * Probe for a VIA gigabit chip. Check the PCI vendor and device * IDs against our list and return a device name if we find a match. */ static int vge_probe(device_t dev) { struct vge_type *t; struct vge_softc *sc; t = vge_devs; sc = device_get_softc(dev); while (t->vge_name != NULL) { if ((pci_get_vendor(dev) == t->vge_vid) && (pci_get_device(dev) == t->vge_did)) { device_set_desc(dev, t->vge_name); return (BUS_PROBE_DEFAULT); } t++; } return (ENXIO); } #define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) static void vge_sysctl_node(struct vge_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid_list *child, *parent; struct sysctl_oid *tree; struct vge_hw_stats *stats; int error; stats = &sc->vge_stats; ctx = device_get_sysctl_ctx(sc->vge_dev); child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev)); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff", CTLTYPE_INT | CTLFLAG_RW, &sc->vge_int_holdoff, 0, sysctl_hw_vge_int_holdoff, "I", "interrupt holdoff"); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, sysctl_hw_vge_rx_coal_pkt, "I", "rx coalescing packet"); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, sysctl_hw_vge_tx_coal_pkt, "I", "tx coalescing packet"); SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->vge_process_limit, 0, sysctl_hw_vge_proc_limit, "I", "max number of Rx events to process"); /* Pull in device tunables. */ sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT; error = resource_int_value(device_get_name(sc->vge_dev), device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff); if (error == 0) { if (sc->vge_int_holdoff < VGE_INT_HOLDOFF_MIN || sc->vge_int_holdoff > VGE_INT_HOLDOFF_MAX) { device_printf(sc->vge_dev, "int_holdoff value out of range; " "using default: %d\n", VGE_INT_HOLDOFF_DEFAULT); sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT; } } sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT; error = resource_int_value(device_get_name(sc->vge_dev), device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt); if (error == 0) { if (sc->vge_rx_coal_pkt < VGE_RX_COAL_PKT_MIN || sc->vge_rx_coal_pkt > VGE_RX_COAL_PKT_MAX) { device_printf(sc->vge_dev, "rx_coal_pkt value out of range; " "using default: %d\n", VGE_RX_COAL_PKT_DEFAULT); sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT; } } sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT; error = resource_int_value(device_get_name(sc->vge_dev), device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt); if (error == 0) { if (sc->vge_tx_coal_pkt < VGE_TX_COAL_PKT_MIN || sc->vge_tx_coal_pkt > VGE_TX_COAL_PKT_MAX) { device_printf(sc->vge_dev, "tx_coal_pkt value out of range; " "using default: %d\n", VGE_TX_COAL_PKT_DEFAULT); sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT; } } sc->vge_process_limit = VGE_PROC_DEFAULT; error = resource_int_value(device_get_name(sc->vge_dev), device_get_unit(sc->vge_dev), "process_limit", &sc->vge_process_limit); if (error == 0) { if (sc->vge_process_limit < VGE_PROC_MIN || sc->vge_process_limit > VGE_PROC_MAX) { device_printf(sc->vge_dev, "process_limit value out of range; " "using default: %d\n", VGE_PROC_DEFAULT); sc->vge_process_limit = VGE_PROC_DEFAULT; } } tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, NULL, "VGE statistics"); parent = SYSCTL_CHILDREN(tree); /* Rx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, NULL, "Rx MAC statistics"); child = SYSCTL_CHILDREN(tree); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames", &stats->rx_frames, "frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->rx_good_frames, "Good frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", &stats->rx_fifo_oflows, "FIFO overflows"); VGE_SYSCTL_STAT_ADD32(ctx, child, "runts", &stats->rx_runts, "Too short frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs", &stats->rx_runts_errs, "Too short frames with errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->rx_pkts_64, "64 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->rx_pkts_65_127, "65 to 127 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->rx_pkts_128_255, "128 to 255 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->rx_pkts_256_511, "256 to 511 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", &stats->rx_pkts_1519_max, "1519 to max frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs", &stats->rx_pkts_1519_max_errs, "1519 to max frames with error"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", &stats->rx_jumbos, "Jumbo frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", &stats->rx_crcerrs, "CRC errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->rx_pause_frames, "CRC errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", &stats->rx_alignerrs, "Alignment errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs", &stats->rx_nobufs, "Frames with no buffer event"); VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", &stats->rx_symerrs, "Frames with symbol errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", &stats->rx_lenerrs, "Frames with length mismatched"); /* Tx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, NULL, "Tx MAC statistics"); child = SYSCTL_CHILDREN(tree); VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->tx_good_frames, "Good frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->tx_pkts_64, "64 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->tx_pkts_65_127, "65 to 127 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->tx_pkts_128_255, "128 to 255 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->tx_pkts_256_511, "256 to 511 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", &stats->tx_jumbos, "Jumbo frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "colls", &stats->tx_colls, "Collisions"); VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", &stats->tx_latecolls, "Late collisions"); VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->tx_pause, "Pause frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs", &stats->tx_sqeerrs, "SQE errors"); } #undef VGE_SYSCTL_STAT_ADD32 /* * Map a single buffer address. */ struct vge_dmamap_arg { bus_addr_t vge_busaddr; }; static void vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { struct vge_dmamap_arg *ctx; if (error != 0) return; KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); ctx = (struct vge_dmamap_arg *)arg; ctx->vge_busaddr = segs[0].ds_addr; } static int vge_dma_alloc(struct vge_softc *sc) { struct vge_dmamap_arg ctx; struct vge_txdesc *txd; struct vge_rxdesc *rxd; bus_addr_t lowaddr, tx_ring_end, rx_ring_end; int error, i; lowaddr = BUS_SPACE_MAXADDR; again: /* Create parent ring tag. */ error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 1, 0, /* algnmnt, boundary */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_ring_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create parent DMA tag.\n"); goto fail; } /* Create tag for Tx ring. */ error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ VGE_TX_LIST_SZ, /* maxsize */ 1, /* nsegments */ VGE_TX_LIST_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_tx_ring_tag); if (error != 0) { device_printf(sc->vge_dev, "could not allocate Tx ring DMA tag.\n"); goto fail; } /* Create tag for Rx ring. */ error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ VGE_RX_LIST_SZ, /* maxsize */ 1, /* nsegments */ VGE_RX_LIST_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_rx_ring_tag); if (error != 0) { device_printf(sc->vge_dev, "could not allocate Rx ring DMA tag.\n"); goto fail; } /* Allocate DMA'able memory and load the DMA map for Tx ring. */ error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, (void **)&sc->vge_rdata.vge_tx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->vge_cdata.vge_tx_ring_map); if (error != 0) { device_printf(sc->vge_dev, "could not allocate DMA'able memory for Tx ring.\n"); goto fail; } ctx.vge_busaddr = 0; error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); if (error != 0 || ctx.vge_busaddr == 0) { device_printf(sc->vge_dev, "could not load DMA'able memory for Tx ring.\n"); goto fail; } sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; /* Allocate DMA'able memory and load the DMA map for Rx ring. */ error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, (void **)&sc->vge_rdata.vge_rx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->vge_cdata.vge_rx_ring_map); if (error != 0) { device_printf(sc->vge_dev, "could not allocate DMA'able memory for Rx ring.\n"); goto fail; } ctx.vge_busaddr = 0; error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); if (error != 0 || ctx.vge_busaddr == 0) { device_printf(sc->vge_dev, "could not load DMA'able memory for Rx ring.\n"); goto fail; } sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; /* Tx/Rx descriptor queue should reside within 4GB boundary. */ tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; if ((VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || (VGE_ADDR_HI(rx_ring_end) != VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { device_printf(sc->vge_dev, "4GB boundary crossed, " "switching to 32bit DMA address mode.\n"); vge_dma_free(sc); /* Limit DMA address space to 32bit and try again. */ lowaddr = BUS_SPACE_MAXADDR_32BIT; goto again; } /* Create parent buffer tag. */ error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 1, 0, /* algnmnt, boundary */ VGE_BUF_DMA_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_buffer_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create parent buffer DMA tag.\n"); goto fail; } /* Create tag for Tx buffers. */ error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 1, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ VGE_MAXTXSEGS, /* nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_tx_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); goto fail; } /* Create tag for Rx buffers. */ error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, /* maxsize */ 1, /* nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_rx_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); goto fail; } /* Create DMA maps for Tx buffers. */ for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; txd->tx_m = NULL; txd->tx_dmamap = NULL; error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, &txd->tx_dmamap); if (error != 0) { device_printf(sc->vge_dev, "could not create Tx dmamap.\n"); goto fail; } } /* Create DMA maps for Rx buffers. */ if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, &sc->vge_cdata.vge_rx_sparemap)) != 0) { device_printf(sc->vge_dev, "could not create spare Rx dmamap.\n"); goto fail; } for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_dmamap = NULL; error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, &rxd->rx_dmamap); if (error != 0) { device_printf(sc->vge_dev, "could not create Rx dmamap.\n"); goto fail; } } fail: return (error); } static void vge_dma_free(struct vge_softc *sc) { struct vge_txdesc *txd; struct vge_rxdesc *rxd; int i; /* Tx ring. */ if (sc->vge_cdata.vge_tx_ring_tag != NULL) { if (sc->vge_cdata.vge_tx_ring_map) bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map); if (sc->vge_cdata.vge_tx_ring_map && sc->vge_rdata.vge_tx_ring) bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, sc->vge_rdata.vge_tx_ring, sc->vge_cdata.vge_tx_ring_map); sc->vge_rdata.vge_tx_ring = NULL; sc->vge_cdata.vge_tx_ring_map = NULL; bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); sc->vge_cdata.vge_tx_ring_tag = NULL; } /* Rx ring. */ if (sc->vge_cdata.vge_rx_ring_tag != NULL) { if (sc->vge_cdata.vge_rx_ring_map) bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map); if (sc->vge_cdata.vge_rx_ring_map && sc->vge_rdata.vge_rx_ring) bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, sc->vge_rdata.vge_rx_ring, sc->vge_cdata.vge_rx_ring_map); sc->vge_rdata.vge_rx_ring = NULL; sc->vge_cdata.vge_rx_ring_map = NULL; bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); sc->vge_cdata.vge_rx_ring_tag = NULL; } /* Tx buffers. */ if (sc->vge_cdata.vge_tx_tag != NULL) { for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; if (txd->tx_dmamap != NULL) { bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); txd->tx_dmamap = NULL; } } bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); sc->vge_cdata.vge_tx_tag = NULL; } /* Rx buffers. */ if (sc->vge_cdata.vge_rx_tag != NULL) { for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; if (rxd->rx_dmamap != NULL) { bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); rxd->rx_dmamap = NULL; } } if (sc->vge_cdata.vge_rx_sparemap != NULL) { bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, sc->vge_cdata.vge_rx_sparemap); sc->vge_cdata.vge_rx_sparemap = NULL; } bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); sc->vge_cdata.vge_rx_tag = NULL; } if (sc->vge_cdata.vge_buffer_tag != NULL) { bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); sc->vge_cdata.vge_buffer_tag = NULL; } if (sc->vge_cdata.vge_ring_tag != NULL) { bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); sc->vge_cdata.vge_ring_tag = NULL; } } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int vge_attach(device_t dev) { u_char eaddr[ETHER_ADDR_LEN]; struct vge_softc *sc; struct ifnet *ifp; int error, i, msic, msixc, pmc; uint16_t burst; uint8_t mdc; sc = device_get_softc(dev); sc->vge_dev = dev; mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->vge_tick_ch, &sc->vge_mtx, 0); TASK_INIT(&sc->vge_int_task, 0, vge_int_task, sc); /* * Map control/status registers. */ pci_enable_busmaster(dev); sc->vge_res_spec = vge_res_spec_mem; sc->vge_irq_spec = vge_irq_spec_legacy; error = bus_alloc_resources(dev, sc->vge_res_spec, sc->vge_res); if (error != 0) { device_printf(dev, "cannot allocate memory resources.\n"); goto fail; } /* Allocate IRQ resources. */ msixc = pci_msix_count(dev); msic = pci_msi_count(dev); if (1 || bootverbose) { device_printf(dev, "MSIX count : %d\n", msixc); device_printf(dev, "MSI count : %d\n", msic); } /* Prefer MSIX over MSI. */ if (msix_disable == 0 || msi_disable == 0) { if (msix_disable == 0 && msixc == VGE_MSIX_MESSAGES && pci_alloc_msix(dev, &msixc) == 0) { if (msic == VGE_MSIX_MESSAGES) { device_printf(dev, "Using %d MSIX messages.\n", msixc); sc->vge_flags |= VGE_FLAG_MSIX; sc->vge_irq_spec = vge_irq_spec_msi; } else pci_release_msi(dev); } if (msi_disable == 0 && (sc->vge_flags & VGE_FLAG_MSIX) == 0 && msic == VGE_MSI_MESSAGES && pci_alloc_msi(dev, &msic) == 0) { if (msic == VGE_MSI_MESSAGES) { device_printf(dev, "Using %d MSI messages.\n", msic); sc->vge_flags |= VGE_FLAG_MSI; sc->vge_irq_spec = vge_irq_spec_msi; } else pci_release_msi(dev); } } error = bus_alloc_resources(dev, sc->vge_irq_spec, sc->vge_irq); if (error != 0) { device_printf(dev, "cannot allocate IRQ resources.\n"); goto fail; } /* Reset the adapter. */ vge_reset(sc); /* Reload EEPROM. */ CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(5); if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "EEPROM reload timed out\n"); /* Clear PACPI as EEPROM reload will set the bit. */ CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); /* * Get station address from the EEPROM. */ vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); /* Set max allowable DMA size. */ if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { sc->vge_flags |= VGE_FLAG_PCIE; burst = pci_read_config(dev, i + 0x08, 2); if (1 || bootverbose) { device_printf(dev, "Read request size : %d bytes.\n", 128 << ((burst >> 12) & 0x07)); device_printf(dev, "TLP payload size : %d bytes.\n", 128 << ((burst >> 5) & 0x07)); } switch ((burst >> 12) & 0x07) { case 0: sc->vge_dma_burst = VGE_DMABURST_128; break; case 1: sc->vge_dma_burst = VGE_DMABURST_256; break; default: sc->vge_dma_burst = VGE_DMABURST_STRFWD; break; } } else sc->vge_dma_burst = VGE_DMABURST_128; /* Disable MII auto-poll. */ vge_mii_idle(sc); /* Save configured PHY address. */ mdc = CSR_READ_1(sc, VGE_MIICFG) & VGE_MIICFG_PHYADDR; sc->vge_phyaddr = mdc & VGE_MIICFG_PHYADDR; #if 0 /* Accelerate MDC spped x 4. */ mdc |= VGE_MIICFG_MDCSPEED; CSR_WRITE_1(sc, VGE_MIICFG, mdc); #endif if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0); sc->vge_flags |= VGE_FLAG_PMCAP; /* Take hardware from powerdown. */ vge_clrwol(sc); vge_sysctl_node(sc); if ((error = vge_dma_alloc(sc)) != 0) goto fail; ifp = sc->vge_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "cannot allocate ifnet structure.\n"); error = ENOSPC; goto fail; } /* Do MII setup */ error = mii_phy_probe(dev, &sc->vge_miibus, vge_ifmedia_upd, vge_ifmedia_sts); if (error != 0) { device_printf(dev, "no PHY found!\n"); goto fail; } ifp->if_softc = sc; if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = vge_ioctl; ifp->if_start = vge_start; ifp->if_init = vge_init; ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); IFQ_SET_READY(&ifp->if_snd); ifp->if_capabilities = IFCAP_HWCSUM; ifp->if_hwassist = VGE_CSUM_FEATURES; if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) ifp->if_capabilities |= IFCAP_WOL; ifp->if_capenable = ifp->if_capabilities; /* * Call MI attach routine. */ ether_ifattach(ifp, eaddr); /* VLAN capability setup */ ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; ifp->if_capenable = ifp->if_capabilities; #ifdef DEVICE_POLLING ifp->if_capabilities |= IFCAP_POLLING; #endif /* Tell the upper layer(s) we support long frames. */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); /* Create local taskq. */ TASK_INIT(&sc->vge_tx_task, 1, vge_tx_task, ifp); sc->vge_tq = taskqueue_create_fast("vge_taskq", M_WAITOK, taskqueue_thread_enqueue, &sc->vge_tq); if (sc->vge_tq == NULL) { device_printf(dev, "could not create taskqueue.\n"); ether_ifdetach(ifp); error = ENXIO; goto fail; } taskqueue_start_threads(&sc->vge_tq, 1, PI_NET, "%s taskq", device_get_nameunit(sc->vge_dev)); if ((sc->vge_flags & VGE_FLAG_MSIX) != 0) msic = VGE_MSIX_MESSAGES; else if ((sc->vge_flags & VGE_FLAG_MSI) != 0) msic = VGE_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { error = bus_setup_intr(dev, sc->vge_irq[i], INTR_TYPE_NET | INTR_MPSAFE, vge_intr, NULL, sc, &sc->vge_intrhand[i]); if (error != 0) break; } if (error != 0) { device_printf(dev, "could not set up interrupt handler.\n"); taskqueue_free(sc->vge_tq); sc->vge_tq = NULL; ether_ifdetach(ifp); goto fail; } fail: if (error != 0) vge_detach(dev); return (error); } /* * Shutdown hardware and free up resources. This can be called any * time after the mutex has been initialized. It is called in both * the error case in attach and the normal detach case so it needs * to be careful about only freeing resources that have actually been * allocated. */ static int vge_detach(device_t dev) { struct vge_softc *sc; struct ifnet *ifp; int i, msic; sc = device_get_softc(dev); ifp = sc->vge_ifp; /* These should only be active if attach succeeded */ if (device_is_attached(dev)) { #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) ether_poll_deregister(ifp); #endif VGE_LOCK(sc); vge_stop(sc); /* * Force off the IFF_UP flag here, in case someone * still had a BPF descriptor attached to this * interface. If they do, ether_ifattach() will cause * the BPF code to try and clear the promisc mode * flag, which will bubble down to vge_ioctl(), * which will try to call vge_init() again. This will * turn the NIC back on and restart the MII ticker, * which will panic the system when the kernel tries * to invoke the vge_tick() function that isn't there * anymore. */ ifp->if_flags &= ~IFF_UP; sc->vge_flags |= VGE_FLAG_DETACH; VGE_UNLOCK(sc); callout_drain(&sc->vge_tick_ch); taskqueue_drain(sc->vge_tq, &sc->vge_int_task); taskqueue_drain(sc->vge_tq, &sc->vge_tx_task); ether_ifdetach(ifp); } if (sc->vge_tq != NULL) { taskqueue_drain(sc->vge_tq, &sc->vge_int_task); taskqueue_free(sc->vge_tq); sc->vge_tq = NULL; } if (sc->vge_miibus != NULL) { device_delete_child(dev, sc->vge_miibus); sc->vge_miibus = NULL; } bus_generic_detach(dev); vge_dma_free(sc); if (ifp != NULL) { if_free(ifp); sc->vge_ifp = NULL; } msic = 1; if ((sc->vge_flags & VGE_FLAG_MSIX) != 0) msic = VGE_MSIX_MESSAGES; else if ((sc->vge_flags & VGE_FLAG_MSI) != 0) msic = VGE_MSI_MESSAGES; else msic = 1; for (i = 0; i < msic; i++) { if (sc->vge_intrhand[i] != NULL) { bus_teardown_intr(dev, sc->vge_irq[i], sc->vge_intrhand[i]); sc->vge_intrhand[i] = NULL; } } bus_release_resources(dev, sc->vge_irq_spec, sc->vge_irq); if ((sc->vge_flags & (VGE_FLAG_MSIX | VGE_FLAG_MSI)) != 0) pci_release_msi(dev); bus_release_resources(dev, sc->vge_res_spec, sc->vge_res); mtx_destroy(&sc->vge_mtx); return (0); } static void vge_discard_rxbuf(struct vge_softc *sc, int prod) { struct vge_rxdesc *rxd; int i; rxd = &sc->vge_cdata.vge_rxdesc[prod]; rxd->rx_desc->vge_sts = 0; rxd->rx_desc->vge_ctl = 0; /* * Note: the manual fails to document the fact that for * proper opration, the driver needs to replentish the RX * DMA ring 4 descriptors at a time (rather than one at a * time, like most chips). We can allocate the new buffers * but we should not set the OWN bits until we're ready * to hand back 4 of them in one shot. */ if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); for (i = VGE_RXCHUNK - 1; i > 0; i--) { rxd = rxd->rxd_prev; rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); } sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; } } static int vge_newbuf(struct vge_softc *sc, int prod) { struct vge_rxdesc *rxd; struct mbuf *m; bus_dma_segment_t segs[1]; bus_dmamap_t map; int i, nsegs; m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); /* * This is part of an evil trick to deal with strict-alignment * architectures. The VIA chip requires RX buffers to be aligned * on 32-bit boundaries, but that will hose strict-alignment * architectures. To get around this, we leave some empty space * at the start of each buffer and for non-strcit-alignment hosts, * we copy the buffer back two bytes to achieve word alignment. * This is slightly more efficient than allocating a new buffer, * copying the contents, and discarding the old buffer. */ m->m_len = m->m_pkthdr.len = MCLBYTES; m_adj(m, VGE_RX_BUF_ALIGN); if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { m_freem(m); return (ENOBUFS); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); rxd = &sc->vge_cdata.vge_rxdesc[prod]; if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); } map = rxd->rx_dmamap; rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; sc->vge_cdata.vge_rx_sparemap = map; bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); rxd->rx_m = m; rxd->rx_desc->vge_sts = 0; rxd->rx_desc->vge_ctl = 0; rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); /* * Note: the manual fails to document the fact that for * proper opration, the driver needs to replentish the RX * DMA ring 4 descriptors at a time (rather than one at a * time, like most chips). We can allocate the new buffers * but we should not set the OWN bits until we're ready * to hand back 4 of them in one shot. */ if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); for (i = VGE_RXCHUNK - 1; i > 0; i--) { rxd = rxd->rxd_prev; rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); } sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; } return (0); } static int vge_tx_list_init(struct vge_softc *sc) { struct vge_ring_data *rd; struct vge_txdesc *txd; int i; VGE_LOCK_ASSERT(sc); sc->vge_cdata.vge_tx_prodidx = 0; sc->vge_cdata.vge_tx_considx = 0; sc->vge_cdata.vge_tx_cnt = 0; rd = &sc->vge_rdata; bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; txd->tx_m = NULL; txd->tx_desc = &rd->vge_tx_ring[i]; if (i == 0) txd->txd_prev = &sc->vge_cdata.vge_txdesc[VGE_TX_DESC_CNT - 1]; else txd->txd_prev = &sc->vge_cdata.vge_txdesc[i - 1]; } bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); return (0); } static int vge_rx_list_init(struct vge_softc *sc) { struct vge_ring_data *rd; struct vge_rxdesc *rxd; int i; VGE_LOCK_ASSERT(sc); sc->vge_cdata.vge_rx_prodidx = 0; sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; sc->vge_morework = 0; sc->vge_cdata.vge_rx_commit = 0; rd = &sc->vge_rdata; bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_desc = &rd->vge_rx_ring[i]; if (i == 0) rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; else rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; if (vge_newbuf(sc, i) != 0) return (ENOBUFS); } bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); sc->vge_cdata.vge_rx_commit = 0; return (0); } static void vge_freebufs(struct vge_softc *sc) { struct vge_txdesc *txd; struct vge_rxdesc *rxd; struct ifnet *ifp; int i; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; /* * Free RX and TX mbufs still in the queues. */ for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); m_freem(rxd->rx_m); rxd->rx_m = NULL; } } for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; if (txd->tx_m != NULL) { bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; ifp->if_oerrors++; } } } #ifndef __NO_STRICT_ALIGNMENT static __inline void vge_fixup_rx(struct mbuf *m) { int i; uint16_t *src, *dst; src = mtod(m, uint16_t *); dst = src - 1; for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) *dst++ = *src++; m->m_data -= ETHER_ALIGN; } #endif /* * RX handler. We support the reception of jumbo frames that have * been fragmented across multiple 2K mbuf cluster buffers. */ static int vge_rxeof(struct vge_softc *sc, int count) { struct mbuf *m; struct ifnet *ifp; int prod, prog, total_len; struct vge_rxdesc *rxd; struct vge_rx_desc *cur_rx; uint32_t rxstat, rxctl; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); prod = sc->vge_cdata.vge_rx_prodidx; for (prog = 0; count > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; VGE_RX_DESC_INC(prod)) { #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) { if (sc->rxcycles <= 0) break; sc->rxcycles--; } #endif cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; rxstat = le32toh(cur_rx->vge_sts); if ((rxstat & VGE_RDSTS_OWN) != 0) break; count--; prog++; rxctl = le32toh(cur_rx->vge_ctl); total_len = VGE_RXBYTES(rxstat); rxd = &sc->vge_cdata.vge_rxdesc[prod]; m = rxd->rx_m; /* * If the 'start of frame' bit is set, this indicates * either the first fragment in a multi-fragment receive, * or an intermediate fragment. Either way, we want to * accumulate the buffers. */ if ((rxstat & VGE_RXPKT_SOF) != 0) { if (vge_newbuf(sc, prod) != 0) { ifp->if_iqdrops++; if (sc->vge_cdata.vge_head != NULL) { m_freem(sc->vge_cdata.vge_head); sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; } vge_discard_rxbuf(sc, prod); continue; } m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; if (sc->vge_cdata.vge_head == NULL) { sc->vge_cdata.vge_head = m; sc->vge_cdata.vge_tail = m; } else { m->m_flags &= ~M_PKTHDR; sc->vge_cdata.vge_tail->m_next = m; sc->vge_cdata.vge_tail = m; } continue; } /* * Bad/error frames will have the RXOK bit cleared. * However, there's one error case we want to allow: * if a VLAN tagged frame arrives and the chip can't * match it against the CAM filter, it considers this * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. * We don't want to drop the frame though: our VLAN * filtering is done in software. * We also want to receive bad-checksummed frames and * and frames with bad-length. */ if ((rxstat & VGE_RDSTS_RXOK) == 0 && (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | VGE_RDSTS_CSUMERR)) == 0) { ifp->if_ierrors++; /* * If this is part of a multi-fragment packet, * discard all the pieces. */ if (sc->vge_cdata.vge_head != NULL) { m_freem(sc->vge_cdata.vge_head); sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; } vge_discard_rxbuf(sc, prod); continue; } if (vge_newbuf(sc, prod) != 0) { ifp->if_iqdrops++; if (sc->vge_cdata.vge_head != NULL) { m_freem(sc->vge_cdata.vge_head); sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; } vge_discard_rxbuf(sc, prod); continue; } /* Chain receved mbufs. */ if (sc->vge_cdata.vge_head != NULL) { m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); /* * Special case: if there's 4 bytes or less * in this buffer, the mbuf can be discarded: * the last 4 bytes is the CRC, which we don't * care about anyway. */ if (m->m_len <= ETHER_CRC_LEN) { sc->vge_cdata.vge_tail->m_len -= (ETHER_CRC_LEN - m->m_len); m_freem(m); } else { m->m_len -= ETHER_CRC_LEN; m->m_flags &= ~M_PKTHDR; sc->vge_cdata.vge_tail->m_next = m; } m = sc->vge_cdata.vge_head; m->m_flags |= M_PKTHDR; sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; m->m_pkthdr.len = total_len - ETHER_CRC_LEN; } else { m->m_flags |= M_PKTHDR; m->m_pkthdr.len = m->m_len = (total_len - ETHER_CRC_LEN); } #ifndef __NO_STRICT_ALIGNMENT vge_fixup_rx(m); #endif m->m_pkthdr.rcvif = ifp; /* Do RX checksumming if enabled */ if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && (rxctl & VGE_RDCTL_FRAG) == 0) { /* Check IP header checksum */ if ((rxctl & VGE_RDCTL_IPPKT) != 0) m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) m->m_pkthdr.csum_flags |= CSUM_IP_VALID; /* Check TCP/UDP checksum */ if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && rxctl & VGE_RDCTL_PROTOCSUMOK) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } } if ((rxstat & VGE_RDSTS_VTAG) != 0) { /* * The 32-bit rxctl register is stored in little-endian. * However, the 16-bit vlan tag is stored in big-endian, * so we have to byte swap it. */ m->m_pkthdr.ether_vtag = bswap16(rxctl & VGE_RDCTL_VLANID); m->m_flags |= M_VLANTAG; } VGE_UNLOCK(sc); (*ifp->if_input)(ifp, m); VGE_LOCK(sc); } if (prog > 0) { sc->vge_cdata.vge_rx_prodidx = prod; bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* Update residue counter. */ if (sc->vge_cdata.vge_rx_commit != 0) { CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, sc->vge_cdata.vge_rx_commit); sc->vge_cdata.vge_rx_commit = 0; } } if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) return (0); return (count > 0 ? 0 : EAGAIN); } static void vge_txeof(struct vge_softc *sc) { struct ifnet *ifp; struct vge_tx_desc *cur_tx; struct vge_txdesc *txd; uint32_t txstat; int cons, prod; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; if (sc->vge_cdata.vge_tx_cnt == 0) return; bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); /* * Go through our tx list and free mbufs for those * frames that have been transmitted. */ cons = sc->vge_cdata.vge_tx_considx; prod = sc->vge_cdata.vge_tx_prodidx; for (; cons != prod; VGE_TX_DESC_INC(cons)) { cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; txstat = le32toh(cur_tx->vge_sts); if ((txstat & VGE_TDSTS_OWN) != 0) break; sc->vge_cdata.vge_tx_cnt--; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; txd = &sc->vge_cdata.vge_txdesc[cons]; bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", __func__)); m_freem(txd->tx_m); txd->tx_m = NULL; } sc->vge_cdata.vge_tx_considx = cons; if (sc->vge_cdata.vge_tx_cnt == 0) sc->vge_watchdog_timer = 0; } static void vge_tick(void *xsc) { struct vge_softc *sc; struct mii_data *mii; sc = xsc; VGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->vge_miibus); mii_tick(mii); vge_stats_update(sc); vge_watchdog(sc); callout_reset(&sc->vge_tick_ch, hz, vge_tick, sc); } #ifdef DEVICE_POLLING static void vge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct vge_softc *sc = ifp->if_softc; VGE_LOCK(sc); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) goto done; sc->rxcycles = count; vge_rxeof(sc, count); vge_txeof(sc); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ uint32_t status; status = CSR_READ_4(sc, VGE_ISR); if (status == 0xFFFFFFFF) goto done; if (status) CSR_WRITE_4(sc, VGE_ISR, status); /* * XXX check behaviour on receiver stalls. */ if ((status & (VGE_ISR_TXDMA_STALL | VGE_ISR_RXDMA_STALL)) != 0) { device_printf(sc->vge_dev, "DMA stalled, restarting\n"); vge_init_locked(sc); } if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { vge_rxeof(sc, count); ifp->if_ierrors++; CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); } } done: VGE_UNLOCK(sc); } #endif /* DEVICE_POLLING */ static int vge_intr(void *arg) { struct vge_softc *sc; uint32_t status; sc = (struct vge_softc *)arg; status = CSR_READ_4(sc, VGE_ISR); if ((status & VGE_INTRS) == 0 || status == 0xFFFFFFFF) return (FILTER_STRAY); /* Disable interrupts. */ #if 0 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); #else CSR_WRITE_4(sc, VGE_IMR, 0); #endif taskqueue_enqueue(sc->vge_tq, &sc->vge_int_task); return (FILTER_HANDLED); } static void vge_int_task(void *arg, int pending) { struct vge_softc *sc; struct ifnet *ifp; uint32_t status; sc = (struct vge_softc *)arg; ifp = sc->vge_ifp; VGE_LOCK(sc); ifp = sc->vge_ifp; if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0) goto done; #ifdef DEVICE_POLLING if ((ifp->if_capenable & IFCAP_POLLING) != 0) goto done; #endif status = CSR_READ_4(sc, VGE_ISR); if (((status == 0xFFFFFFFF || (status & VGE_INTRS) == 0)) && sc->vge_morework == 0) goto done; /* Clear interrupts and reload holdoff timer. */ CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD); /*printf("INTR = 0x%08x\n", status);*/ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { sc->vge_morework = vge_rxeof(sc, sc->vge_process_limit); if ((status & (VGE_ISR_RXOFLOW | VGE_ISR_RXNODESC)) != 0) { #if 0 printf("RXOFLOW : 0x%08x\n", status); #endif #if 0 /* XXX it seems that no need to set RUN bit! */ CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); #endif CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); } vge_txeof(sc); if ((status & (VGE_ISR_TXDMA_STALL | VGE_ISR_RXDMA_STALL)) != 0) { device_printf(sc->vge_dev, "DMA stalled, restarting\n"); vge_init_locked(sc); goto done; } if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) taskqueue_enqueue(sc->vge_tq, &sc->vge_tx_task); } if (sc->vge_morework != 0 || (CSR_READ_4(sc, VGE_ISR) & VGE_INTRS) != 0) { taskqueue_enqueue(sc->vge_tq, &sc->vge_int_task); goto done; } /* Re-enable interrupts */ #if 0 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); #else CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); #endif done: VGE_UNLOCK(sc); } static int vge_encap(struct vge_softc *sc, struct mbuf **m_head) { struct vge_txdesc *txd; struct vge_tx_frag *frag; struct mbuf *m; bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; int error, i, nsegs, padlen; uint32_t cflags; VGE_LOCK_ASSERT(sc); M_ASSERTPKTHDR((*m_head)); /* Argh. This chip does not autopad short frames. */ if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { m = *m_head; padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ m = m_dup(*m_head, M_DONTWAIT); m_freem(*m_head); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } *m_head = m; } if (M_TRAILINGSPACE(m) < padlen) { m = m_defrag(m, M_DONTWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOBUFS); } } /* * Manually pad short frames, and zero the pad space * to avoid leaking data. */ bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); m->m_pkthdr.len += padlen; m->m_len = m->m_pkthdr.len; *m_head = m; } txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOMEM); } *m_head = m; error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); if (error != 0) { m_freem(*m_head); *m_head = NULL; return (error); } } else if (error != 0) return (error); if (nsegs == 0) { m_freem(*m_head); *m_head = NULL; return (EIO); } bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); m = *m_head; cflags = 0; /* Confugre checksum offload. */ if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) cflags |= VGE_TDCTL_IPCSUM; if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) cflags |= VGE_TDCTL_TCPCSUM; if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) cflags |= VGE_TDCTL_UDPCSUM; /* Configure VLAN. */ if ((m->m_flags & M_VLANTAG) != 0) cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; if (m->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) cflags |= VGE_TDCTL_JUMBO; txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); /* * XXX * Velocity family seems to support TSO but no information * for MSS configuration is available. Also the number of * fragments supported by a descriptor is too small to hold * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build * longer chain of buffers but no additional information is * available. * * When telling the chip how many segments there are, we * must use nsegs + 1 instead of just nsegs. Darned if I * know why. */ txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | VGE_TD_LS_NORM); for (i = 0; i < nsegs; i++) { frag = &txd->tx_desc->vge_frag[i]; frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | (VGE_BUFLEN(txsegs[i].ds_len) << 16)); } sc->vge_cdata.vge_tx_cnt++; VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); /* * Finally request interrupt and give the first descriptor * owenership to hardware. */ txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); txd->tx_m = m; return (0); } static void vge_tx_task(void *arg, int npending) { struct ifnet *ifp; ifp = arg; vge_start(ifp); } /* * Main transmit routine. */ static void vge_start(struct ifnet *ifp) { struct vge_softc *sc; struct vge_txdesc *txd; struct mbuf *m_head; int enq, idx; sc = ifp->if_softc; VGE_LOCK(sc); if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING || (sc->vge_flags & VGE_FLAG_LINK) == 0) { VGE_UNLOCK(sc); return; } if (sc->vge_cdata.vge_tx_cnt > VGE_TX_DESC_HIWAT) vge_txeof(sc); idx = sc->vge_cdata.vge_tx_prodidx; VGE_TX_DESC_DEC(idx); for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; /* * Pack the data into the transmit ring. If we * don't have room, set the OACTIVE flag and wait * for the NIC to drain the ring. */ if (vge_encap(sc, &m_head)) { if (m_head == NULL) break; IFQ_DRV_PREPEND(&ifp->if_snd, m_head); ifp->if_drv_flags |= IFF_DRV_OACTIVE; break; } txd = &sc->vge_cdata.vge_txdesc[idx]; txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); VGE_TX_DESC_INC(idx); enq++; /* * If there's a BPF listener, bounce a copy of this frame * to him. */ ETHER_BPF_MTAP(ifp, m_head); } if (enq > 0) { bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* Issue a transmit command. */ CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); /* Set a timeout in case the chip goes out to lunch. */ sc->vge_watchdog_timer = VGE_TX_TIMEOUT; } VGE_UNLOCK(sc); } static void vge_init(void *xsc) { struct vge_softc *sc; sc = xsc; VGE_LOCK(sc); vge_init_locked(sc); VGE_UNLOCK(sc); } static void vge_init_locked(struct vge_softc *sc) { struct ifnet *ifp = sc->vge_ifp; struct mii_data *mii; uint32_t reg; int error, i; mii = device_get_softc(sc->vge_miibus); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* * Cancel pending I/O and free all RX/TX buffers. */ vge_stop(sc); vge_reset(sc); /* * Initialize the RX and TX descriptors and mbufs. */ error = vge_rx_list_init(sc); if (error != 0) { device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); vge_stop(sc); return; } vge_tx_list_init(sc); /* Clear MAC statistics. */ vge_stats_clear(sc); /* Set our station address */ for (i = 0; i < ETHER_ADDR_LEN; i++) CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); /* Set receive FIFO threshold. */ reg = CSR_READ_1(sc, VGE_RXCFG); reg &= ~(VGE_RXCFG_FIFO_THR | VGE_RXCFG_VTAGOPT); reg |= VGE_RXFIFOTHR_128BYTES; CSR_WRITE_1(sc, VGE_RXCFG, reg); /* Set DMA burst length */ reg = CSR_READ_1(sc, VGE_DMACFG0); reg &= ~VGE_DMACFG0_BURSTLEN; reg |= sc->vge_dma_burst; CSR_WRITE_1(sc, VGE_DMACFG0, reg); reg = CSR_READ_1(sc, VGE_TXCFG); reg |= VGE_TXCFG_ARB_PRIO | VGE_TXCFG_NONBLK | VGE_TXCFG_SNAPOPT; CSR_WRITE_1(sc, VGE_TXCFG, reg); /* Set collision backoff algorithm */ CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM | VGE_CHIPCFG1_CAP | VGE_CHIPCFG1_MBA | VGE_CHIPCFG1_BAKOPT); CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); /* Disable LPSEL field in priority resolution */ CSR_WRITE_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); /* Initialize Tx pause frame timer. */ CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); /* * Load the addresses of the DMA queues into the chip. * Note that we only use one transmit queue. */ CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); /* Reset TD index. */ CSR_WRITE_2(sc, VGE_TXDESC_CONSIDX0, 0); CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); /* Reset RD index. */ CSR_WRITE_2(sc, VGE_RXDESC_CONSIDX, 0); CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); #if 0 /XXX Should be done at last. */ /* Enable and wake up the RX descriptor queue */ CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); /* Enable the TX descriptor queue */ CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); #endif /* Init the cam filter. */ vge_cam_init(sc); /* Set up receive filter. */ vge_rxfilter(sc); vge_set_vlan(sc); #if 0 /* * Configure one-shot timer for microsecond * resulution and load it for 500 usecs. */ CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); CSR_WRITE_2(sc, VGE_SSTIMER, 400); #endif #if 1 /* Enable interupt suppression. */ vge_intr_holdoff(sc); #endif /* * Configure interrupt moderation for receive. Enable * the holdoff counter and load it, and set the RX * suppression count to the number of descriptors we * want to allow before triggering an interrupt. * The holdoff timer is in units of 20 usecs. */ #ifdef notyet CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); /* Select the interrupt holdoff timer page. */ CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ /* Enable use of the holdoff timer. */ CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); /* Select the RX suppression threshold page. */ CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ /* Restore the page select bits. */ CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); #endif #ifdef DEVICE_POLLING /* * Disable interrupts if we are polling. */ if (ifp->if_capenable & IFCAP_POLLING) { CSR_WRITE_4(sc, VGE_IMR, 0); CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); } else /* otherwise ... */ #endif { /* * Enable interrupts. */ CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); CSR_WRITE_4(sc, VGE_ISR, 0); CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); } sc->vge_flags &= ~VGE_FLAG_LINK; mii_mediachg(mii); /* Start one second timer */ callout_reset(&sc->vge_tick_ch, hz, vge_tick, sc); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; } static void vge_intr_holdoff(struct vge_softc *sc) { uint8_t cam, intctl, page; VGE_LOCK_ASSERT(sc); /* Save current page. */ page = CSR_READ_1(sc, VGE_CAMCTL); /* * Set Tx interrupt supression threshold. * It's possible to use single-shot timer in VGE_CRS1 register * in Tx path such that driver can remove most of Tx completion * interrupts. However this requires additional access to * VGE_CRS1 register to reload the timer in addintion to * activating Tx kick command. Another downside is we don't know * what single-shot timer value should be used in advance so * reclaiming transmitted mbufs could be delayed a lot which in * turn slows down Tx operation. */ cam = page; cam &= ~VGE_CAMCTL_PAGESEL; cam |= VGE_PAGESEL_TXSUPPTHR; CSR_WRITE_1(sc, VGE_CAMCTL, cam); CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt); /* Set Rx interrupt suppresion threshold. */ cam = CSR_READ_1(sc, VGE_CAMCTL); cam &= ~VGE_CAMCTL_PAGESEL; cam |= VGE_PAGESEL_RXSUPPTHR; CSR_WRITE_1(sc, VGE_CAMCTL, cam); CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt); intctl = CSR_READ_1(sc, VGE_INTCTL1); intctl |= VGE_INTCTL_HC_RELOAD; if (sc->vge_tx_coal_pkt == 0) intctl |= VGE_INTCTL_TXINTSUP_DISABLE; else intctl &= ~VGE_INTCTL_TXINTSUP_DISABLE; if (sc->vge_rx_coal_pkt == 0) intctl |= VGE_INTCTL_RXINTSUP_DISABLE; else intctl &= ~VGE_INTCTL_RXINTSUP_DISABLE; CSR_WRITE_1(sc, VGE_INTCTL1, intctl); CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF); if (sc->vge_int_holdoff != 0) { /* Set interrupt holdoff timer. */ cam = CSR_READ_1(sc, VGE_CAMCTL); cam &= ~VGE_CAMCTL_PAGESEL; cam |= VGE_PAGESEL_INTHLDOFF; CSR_WRITE_1(sc, VGE_CAMCTL, cam); CSR_WRITE_1(sc, VGE_INTHOLDOFF, VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff)); /* Enable holdoff timer. */ CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); } /* Restore the page select bits. */ CSR_WRITE_1(sc, VGE_CAMCTL, page); } static void vge_stats_clear(struct vge_softc *sc) { int i; VGE_LOCK_ASSERT(sc); CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE); CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR); for (i = VGE_TIMEOUT; i > 0; i--) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0) break; } if (i == 0) device_printf(sc->vge_dev, "MIB clear timed out!\n"); CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) & ~(VGE_MIBCSR_FREEZE | VGE_MIBCSR_CLR)); } static void vge_stats_update(struct vge_softc *sc) { struct vge_hw_stats *stats; struct ifnet *ifp; uint32_t mib[VGE_MIB_CNT], val; int i; VGE_LOCK_ASSERT(sc); stats = &sc->vge_stats; ifp = sc->vge_ifp; CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH); for (i = VGE_TIMEOUT; i > 0; i--) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0) break; } if (i == 0) { device_printf(sc->vge_dev, "MIB counter dump timed out!\n"); vge_stats_clear(sc); return; } bzero(mib, sizeof(mib)); reset_idx: /* Set MIB read index to 0. */ CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI); for (i = 0; i < VGE_MIB_CNT; i++) { val = CSR_READ_4(sc, VGE_MIBDATA); if (i != VGE_MIB_DATA_IDX(val)) { /* Reading interrupted. */ goto reset_idx; } mib[i] = val & VGE_MIB_DATA_MASK; } /* Rx stats. */ stats->rx_frames += mib[VGE_MIB_RX_FRAMES]; stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES]; stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS]; stats->rx_runts += mib[VGE_MIB_RX_RUNTS]; stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS]; stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64]; stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127]; stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255]; stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511]; stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023]; stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518]; stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX]; stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS]; stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS]; stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS]; stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE]; stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS]; stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS]; stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS]; stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS]; /* Tx stats. */ stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES]; stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64]; stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127]; stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255]; stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511]; stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023]; stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518]; stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS]; stats->tx_colls += mib[VGE_MIB_TX_COLLS]; stats->tx_pause += mib[VGE_MIB_TX_PAUSE]; stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS]; stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS]; /* Update counters in ifnet. */ ifp->if_opackets += mib[VGE_MIB_TX_GOOD_FRAMES]; ifp->if_collisions += mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]; ifp->if_oerrors += mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]; ifp->if_ipackets += mib[VGE_MIB_RX_GOOD_FRAMES]; ifp->if_ierrors += mib[VGE_MIB_RX_FIFO_OVERRUNS] + mib[VGE_MIB_RX_RUNTS] + mib[VGE_MIB_RX_RUNTS_ERRS] + mib[VGE_MIB_RX_CRCERRS] + mib[VGE_MIB_RX_ALIGNERRS] + mib[VGE_MIB_RX_NOBUFS] + mib[VGE_MIB_RX_SYMERRS] + mib[VGE_MIB_RX_LENERRS]; } /* * Set media options. */ static int vge_ifmedia_upd(struct ifnet *ifp) { struct vge_softc *sc; struct mii_data *mii; int error; sc = ifp->if_softc; VGE_LOCK(sc); mii = device_get_softc(sc->vge_miibus); error = mii_mediachg(mii); VGE_UNLOCK(sc); return (error); } /* * Report current media status. */ static void vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct vge_softc *sc; struct mii_data *mii; sc = ifp->if_softc; VGE_LOCK(sc); if ((ifp->if_flags & IFF_UP) == 0) { VGE_UNLOCK(sc); return; } mii = device_get_softc(sc->vge_miibus); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; VGE_UNLOCK(sc); } static void vge_miibus_statchg(device_t dev) { struct vge_softc *sc; struct mii_data *mii; struct ifnet *ifp; sc = device_get_softc(dev); mii = device_get_softc(sc->vge_miibus); ifp = sc->vge_ifp; if (mii == NULL || ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) return; sc->vge_flags &= ~VGE_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: sc->vge_flags |= VGE_FLAG_LINK; break; case IFM_100_TX: sc->vge_flags |= VGE_FLAG_LINK; break; case IFM_1000_T: sc->vge_flags |= VGE_FLAG_LINK; break; default: break; } } /* Stop Rx/Tx MACs. */ vge_stop_mac(sc); /* Program MAC with resolved speed/duplex/flow-control. */ if ((sc->vge_flags & VGE_FLAG_LINK) != 0) { vge_mac_config(sc); /* Clear MIB counters. */ vge_stats_clear(sc); /* Restart receiver/transmitter. */ vge_start_mac(sc); } } static void vge_mac_config(struct vge_softc *sc) { struct mii_data *mii; struct ifmedia_entry *ife; uint8_t fcfg; sc = device_get_softc(sc->vge_dev); VGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->vge_miibus); ife = mii->mii_media.ifm_cur; /* * If the user manually selects a media mode, we need to turn * on the forced MAC mode bit in the DIAGCTL register. If the * user happens to choose a full duplex mode, we also need to * set the 'force full duplex' bit. This applies only to * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC * mode is disabled, and in 1000baseT mode, full duplex is * always implied, so we turn on the forced mode bit but leave * the FDX bit cleared. */ switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_AUTO: CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); break; case IFM_1000_T: CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); break; case IFM_100_TX: case IFM_10_T: CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) { CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); } else { CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); } break; default: device_printf(sc->vge_dev, "unknown media type: %x\n", IFM_SUBTYPE(ife->ifm_media)); break; } /* Clear all flow-control configuration. */ CSR_WRITE_1(sc, VGE_CRC2, 0); /* Set Tx pause threshold. */ fcfg = VGE_CR2_TXPAUSE_THRESH_HI_RD24 | VGE_CR2_TXPAUSE_THRESH_LO_RD24; #ifdef notyet if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) fcfg |= VGE_CR2_FDX_TXFLOWCTL_ENABLE | VGE_CR2_XON_ENABLE; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) fcfg |= VGE_CR2_FDX_RXFLOWCTL_ENABLE; #endif CSR_WRITE_1(sc, VGE_CRS2, fcfg); } static int vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { struct vge_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *) data; struct mii_data *mii; int error = 0, mask; switch (command) { case SIOCSIFMTU: if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > VGE_JUMBO_MTU) { error = EINVAL; break; } ifp->if_mtu = ifr->ifr_mtu; break; case SIOCSIFFLAGS: VGE_LOCK(sc); if ((ifp->if_flags & IFF_UP) != 0) { if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && ((ifp->if_flags ^ sc->vge_if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) vge_rxfilter(sc); else if ((sc->vge_flags & VGE_FLAG_DETACH) == 0) vge_init_locked(sc); } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) vge_stop(sc); sc->vge_if_flags = ifp->if_flags; VGE_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: VGE_LOCK(sc); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) vge_rxfilter(sc); VGE_UNLOCK(sc); break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: mii = device_get_softc(sc->vge_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); break; case SIOCSIFCAP: VGE_LOCK(sc); mask = ifr->ifr_reqcap ^ ifp->if_capenable; #ifdef DEVICE_POLLING if ((mask & IFCAP_POLLING) != 0 && (IFCAP_POLLING & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_POLLING; if ((IFCAP_POLLING & ifp->if_capenable) != 0) { error = ether_poll_register(vge_poll, ifp); if (error != 0) { VGE_UNLOCK(sc); break; } /* Disable interrupts */ CSR_WRITE_4(sc, VGE_IMR, 0); CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); } else { error = ether_poll_deregister(ifp); /* Enable interrupts. */ CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); } } #endif /* DEVICE_POLLING */ if ((mask & IFCAP_TXCSUM) != 0 && (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_TXCSUM; if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) ifp->if_hwassist |= VGE_CSUM_FEATURES; else ifp->if_hwassist &= ~VGE_CSUM_FEATURES; } if ((mask & IFCAP_RXCSUM) != 0 && (IFCAP_RXCSUM & ifp->if_capabilities) != 0) ifp->if_capenable ^= IFCAP_RXCSUM; if ((mask & IFCAP_WOL) != 0 && (ifp->if_capabilities & IFCAP_WOL) != 0) { if ((mask & IFCAP_WOL_UCAST) != 0) ifp->if_capenable ^= IFCAP_WOL_UCAST; if ((mask & IFCAP_WOL_MCAST) != 0) ifp->if_capenable ^= IFCAP_WOL_MCAST; if ((mask & IFCAP_WOL_MAGIC) != 0) ifp->if_capenable ^= IFCAP_WOL_MAGIC; } if ((mask & IFCAP_VLAN_HWCSUM) != 0 && (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; vge_set_vlan(sc); } VGE_UNLOCK(sc); VLAN_CAPABILITIES(ifp); break; default: error = ether_ioctl(ifp, command, data); break; } return (error); } static void vge_watchdog(struct vge_softc *sc) { struct ifnet *ifp; VGE_LOCK_ASSERT(sc); if (sc->vge_watchdog_timer == 0 || --sc->vge_watchdog_timer) return; ifp = sc->vge_ifp; if ((sc->vge_flags & VGE_FLAG_LINK) == 0) { if_printf(sc->vge_ifp, "watchdog timeout (missed link)\n"); ifp->if_oerrors++; ifp->if_drv_flags &= ~IFF_DRV_RUNNING; vge_init_locked(sc); return; } vge_txeof(sc); if (sc->vge_cdata.vge_tx_cnt == 0) { if_printf(sc->vge_ifp, "watchdog timeout (missed Tx interrupts) -- recovering\n"); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) taskqueue_enqueue(sc->vge_tq, &sc->vge_tx_task); return; } if_printf(sc->vge_ifp, "watchdog timeout\n"); ifp->if_oerrors++; ifp->if_drv_flags &= ~IFF_DRV_RUNNING; vge_init_locked(sc); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) taskqueue_enqueue(sc->vge_tq, &sc->vge_tx_task); } static void vge_stop_mac(struct vge_softc *sc) { uint8_t cfg; int i; CSR_WRITE_2(sc, VGE_TXQCSRC, VGE_TXQCSR_RUN0 | VGE_TXQCSR_RUN1 | VGE_TXQCSR_RUN2 | VGE_TXQCSR_RUN3); CSR_WRITE_1(sc, VGE_RXQCSRC, VGE_RXQCSR_RUN); CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_TX_ENABLE | VGE_CR0_RX_ENABLE); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); cfg = CSR_READ_1(sc, VGE_CRS0); if ((cfg & (VGE_CR0_TX_ENABLE | VGE_CR0_RX_ENABLE)) == 0) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "unable to stop Rx/Tx MAC(0x%02x)!\n", cfg); #if 0 /* Stop controller. */ CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_CRS0) & (VGE_CR0_RX_ENABLE | VGE_CR0_TX_ENABLE)) == 0) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "stopping controller timeout!\n"); #endif } static void vge_start_mac(struct vge_softc *sc) { int i; CSR_WRITE_1(sc, VGE_RXQCSRC, VGE_RXQCSR_DEAD); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); CSR_WRITE_2(sc, VGE_TXQCSRC, VGE_TXQCST_DEAD0); CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_RX_ENABLE | VGE_CR0_TX_ENABLE | VGE_CR0_START); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_CRS0) & (VGE_CR0_RX_ENABLE | VGE_CR0_TX_ENABLE)) == (VGE_CR0_RX_ENABLE | VGE_CR0_TX_ENABLE)) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "unable to start Rx/Tx MAC!\n"); } /* * Stop the adapter and free any mbufs allocated to the * RX and TX lists. */ static void vge_stop(struct vge_softc *sc) { struct ifnet *ifp; VGE_LOCK_ASSERT(sc); /* * Mark the interface down and cancel the watchdog timer. */ ifp = sc->vge_ifp; ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->vge_flags &= ~VGE_FLAG_LINK; callout_stop(&sc->vge_tick_ch); sc->vge_watchdog_timer = 0; /* Disable all interrupts. */ CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); CSR_WRITE_4(sc, VGE_IMR, 0); CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); /* Stop transmitter/receiver. */ vge_stop_mac(sc); vge_stats_update(sc); if (sc->vge_cdata.vge_head != NULL) { m_freem(sc->vge_cdata.vge_head); sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; } vge_txeof(sc); vge_freebufs(sc); } /* * Device suspend routine. Stop the interface and save some PCI * settings in case the BIOS doesn't restore them properly on * resume. */ static int vge_suspend(device_t dev) { struct vge_softc *sc; sc = device_get_softc(dev); VGE_LOCK(sc); vge_stop(sc); vge_setwol(sc); sc->vge_flags |= VGE_FLAG_SUSPENDED; VGE_UNLOCK(sc); return (0); } /* * Device resume routine. Restore some PCI settings in case the BIOS * doesn't, re-enable busmastering, and restart the interface if * appropriate. */ static int vge_resume(device_t dev) { struct vge_softc *sc; struct ifnet *ifp; int pmc; uint16_t pmstat; sc = device_get_softc(dev); VGE_LOCK(sc); if (pci_find_extcap(sc->vge_dev, PCIY_PMG, &pmc) == 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->vge_dev, pmc + PCIR_POWER_STATUS, 2); if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { pmstat &= ~PCIM_PSTAT_PMEENABLE; pci_write_config(sc->vge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); } } vge_clrwol(sc); ifp = sc->vge_ifp; /* reinitialize interface if necessary */ if ((ifp->if_flags & IFF_UP) != 0) { ifp->if_drv_flags &= ~IFF_DRV_RUNNING; vge_init_locked(sc); } sc->vge_flags &= ~VGE_FLAG_SUSPENDED; VGE_UNLOCK(sc); return (0); } /* * Stop all chip I/O so that the kernel's probe routines don't * get confused by errant DMAs when rebooting. */ static int vge_shutdown(device_t dev) { return (vge_suspend(dev)); } static void vge_setlinkspeed(struct vge_softc *sc) { struct mii_data *mii; int aneg, i; VGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->vge_miibus); mii_pollstat(mii); aneg = 0; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch IFM_SUBTYPE(mii->mii_media_active) { case IFM_10_T: case IFM_100_TX: return; case IFM_1000_T: aneg++; default: break; } } vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0); vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); DELAY(1000); if (aneg != 0) { /* Poll link state until vge(4) get a 10/100 link. */ for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { mii_pollstat(mii); if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: vge_mac_config(sc); return; default: break; } } VGE_UNLOCK(sc); pause("vgelnk", hz); VGE_LOCK(sc); } if (i == MII_ANEGTICKS_GIGE) device_printf(sc->vge_dev, "establishing link failed, " "WOL may not work!"); } /* * No link, force MAC to have 100Mbps, full-duplex link. * This is the last resort and may/may not work. */ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; vge_mac_config(sc); } static void vge_setwol(struct vge_softc *sc) { struct ifnet *ifp; int pmc; uint16_t pmstat; uint8_t v; VGE_LOCK_ASSERT(sc); if (pci_find_extcap(sc->vge_dev, PCIY_PMG, &pmc) != 0) { /* No PME capability, PHY power down. */ vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, BMCR_PDOWN); return; } ifp = sc->vge_ifp; /* Clear WOL on pattern match. */ CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); /* Disable WOL on magic/unicast packet. */ CSR_WRITE_1(sc, VGE_WOLCR1C, VGE_WOLCR1_ALL); CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_PHYINT_ENB | VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | VGE_WOLCFG_PMEOVR); if ((ifp->if_capenable & IFCAP_WOL) != 0) { vge_setlinkspeed(sc); v = 0; if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) v |= VGE_WOLCR1_UCAST; if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) v |= VGE_WOLCR1_MAGIC; CSR_WRITE_1(sc, VGE_WOLCR1S, v); if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) CSR_WRITE_1(sc, VGE_WOLCFGS, VGE_WOLCFG_SAM | VGE_WOLCFG_SAB); } v = CSR_READ_1(sc, VGE_PWRSTAT); v |= VGE_STICKHW_SWPTAG; CSR_WRITE_1(sc, VGE_PWRSTAT, v); /* Put hardware into sleep. */ v = CSR_READ_1(sc, VGE_PWRSTAT); v |= VGE_STICKHW_DS0 | VGE_STICKHW_DS1; if ((ifp->if_capenable & IFCAP_WOL) != 0) v |= VGE_STICKHW_WOL_ENB; CSR_WRITE_1(sc, VGE_PWRSTAT, v); /* Request PME if WOL is requested. */ pmstat = pci_read_config(sc->vge_dev, pmc + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); if ((ifp->if_capenable & IFCAP_WOL) != 0) pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; pci_write_config(sc->vge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); } static void vge_clrwol(struct vge_softc *sc) { uint8_t v; v = CSR_READ_1(sc, VGE_PWRSTAT); v &= ~VGE_STICKHW_SWPTAG; CSR_WRITE_1(sc, VGE_PWRSTAT, v); /* Disable WOL and clear power state indicator. */ v = CSR_READ_1(sc, VGE_PWRSTAT); v &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1 | VGE_STICKHW_WOL_ENB); CSR_WRITE_1(sc, VGE_PWRSTAT, v); /* Clear WOL on pattern match. */ CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); /* Disable WOL on magic/unicast packet. */ CSR_WRITE_1(sc, VGE_WOLCR1C, VGE_WOLCR1_ALL); CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_PHYINT_ENB | VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | VGE_WOLCFG_PMEOVR); /* Clear WOL status on pattern match. */ CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); } static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) { int error, value; if (arg1 == NULL) return (EINVAL); value = *(int *)arg1; error = sysctl_handle_int(oidp, &value, 0, req); if (error || req->newptr == NULL) return (error); if (value < low || value > high) return (EINVAL); *(int *)arg1 = value; return (0); } static int sysctl_hw_vge_int_holdoff(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, VGE_INT_HOLDOFF_MIN, VGE_INT_HOLDOFF_MAX)); } static int sysctl_hw_vge_proc_limit(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, VGE_PROC_MIN, VGE_PROC_MAX)); } static int sysctl_hw_vge_rx_coal_pkt(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, VGE_RX_COAL_PKT_MIN, VGE_RX_COAL_PKT_MAX)); } static int sysctl_hw_vge_tx_coal_pkt(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, VGE_TX_COAL_PKT_MIN, VGE_TX_COAL_PKT_MAX)); }