--- sys/dev/msk/if_msk.c.orig	2008-02-29 12:38:12.000000000 +0900
+++ sys/dev/msk/if_msk.c	2008-03-04 18:06:31.000000000 +0900
@@ -1203,8 +1203,9 @@
 	case MSK_PEX_BUS:
 		/* Clear all PEX errors. */
 		CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
-		val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
-		if ((val & PEX_RX_OV) != 0) {
+		CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
+		if ((CSR_READ_4(sc, B0_HWE_ISRC) & Y2_IS_PCI_EXP) != 0) {
+			/* Uncorrectable errors not cleared, ignore it. */
 			sc->msk_intrmask &= ~Y2_IS_HW_ERR;
 			sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
 		}
@@ -3177,7 +3178,6 @@
 msk_intr_hwerr(struct msk_softc *sc)
 {
 	uint32_t status;
-	uint32_t tlphead[4];
 
 	status = CSR_READ_4(sc, B0_HWE_ISRC);
 	/* Time Stamp timer overflow. */
@@ -3217,38 +3217,12 @@
 	if ((status & Y2_IS_PCI_EXP) != 0) {
 		uint32_t v32;
 
-		/*
-		 * On PCI Express bus bridges are called root complexes (RC).
-		 * PCI Express errors are recognized by the root complex too,
-		 * which requests the system to handle the problem. After
-		 * error occurence it may be that no access to the adapter
-		 * may be performed any longer.
-		 */
-
 		v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
-		if ((v32 & PEX_UNSUP_REQ) != 0) {
-			/* Ignore unsupported request error. */
-			device_printf(sc->msk_dev,
-			    "Uncorrectable PCI Express error\n");
-		}
-		if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
-			int i;
-
-			/* Get TLP header form Log Registers. */
-			for (i = 0; i < 4; i++)
-				tlphead[i] = CSR_PCI_READ_4(sc,
-				    PEX_HEADER_LOG + i * 4);
-			/* Check for vendor defined broadcast message. */
-			if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
-				sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
-				CSR_WRITE_4(sc, B0_HWE_IMSK,
-				    sc->msk_intrhwemask);
-				CSR_READ_4(sc, B0_HWE_IMSK);
-			}
-		}
+		device_printf(sc->msk_dev, "PCI Express error(0x%08x)\n", v32);
 		/* Clear the interrupt. */
 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 		CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
+		CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 	}