Index: sys/dev/mii/miidevs =================================================================== --- sys/dev/mii/miidevs (revision 192499) +++ sys/dev/mii/miidevs (working copy) @@ -247,6 +247,7 @@ model MARVELL E1116 0x0021 Marvell 88E1116 Gigabit PHY model MARVELL E1116R 0x0024 Marvell 88E1116R Gigabit PHY model MARVELL E1118 0x0022 Marvell 88E1118 Gigabit PHY +model MARVELL E3016 0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY model xxMARVELL E1000 0x0005 Marvell 88E1000 Gigabit PHY model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY Index: sys/dev/mii/e1000phy.c =================================================================== --- sys/dev/mii/e1000phy.c (revision 192499) +++ sys/dev/mii/e1000phy.c (working copy) @@ -107,6 +107,7 @@ MII_PHY_DESC(MARVELL, E1116), MII_PHY_DESC(MARVELL, E1116R), MII_PHY_DESC(MARVELL, E1118), + MII_PHY_DESC(MARVELL, E3016), MII_PHY_DESC(xxMARVELL, E1000), MII_PHY_DESC(xxMARVELL, E1011), MII_PHY_DESC(xxMARVELL, E1000_3), @@ -129,7 +130,6 @@ struct mii_softc *sc; struct mii_attach_args *ma; struct mii_data *mii; - int fast_ether; esc = device_get_softc(dev); sc = &esc->mii_sc; @@ -142,10 +142,8 @@ sc->mii_phy = ma->mii_phyno; sc->mii_service = e1000phy_service; sc->mii_pdata = mii; - sc->mii_anegticks = MII_ANEGTICKS_GIGE; mii->mii_instance++; - fast_ether = 0; esc->mii_model = MII_MODEL(ma->mii_id2); switch (esc->mii_model) { case MII_MODEL_MARVELL_E1011: @@ -167,55 +165,17 @@ */ PHY_WRITE(sc, E1000_EADR, 0); break; - case MII_MODEL_MARVELL_E3082: - /* 88E3082 10/100 Fast Ethernet PHY. */ - sc->mii_anegticks = MII_ANEGTICKS; - fast_ether = 1; - break; } e1000phy_reset(sc); + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); -#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), - E1000_CR_ISOLATE); - if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), - E1000_CR_SPEED_10); - printf("10baseT, "); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst), - E1000_CR_SPEED_10 | E1000_CR_FULL_DUPLEX); - printf("10baseT-FDX, "); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), - E1000_CR_SPEED_100); - printf("100baseTX, "); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst), - E1000_CR_SPEED_100 | E1000_CR_FULL_DUPLEX); - printf("100baseTX-FDX, "); - if (fast_ether == 0) { - /* - * 1000BT-simplex not supported; driver must ignore - * this entry, but it must be present in order to - * manually set full-duplex. - */ - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, - sc->mii_inst), E1000_CR_SPEED_1000); - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, - sc->mii_inst), - E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX); - printf("1000baseTX-FDX, "); - } - } else { - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), - E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX); - printf("1000baseSX-FDX, "); - } - ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); - printf("auto\n"); -#undef ADD - MIIBUS_MEDIAINIT(sc->mii_dev); return (0); } @@ -253,18 +213,29 @@ reg |= E1000_SCR_AUTO_X_MODE; if (esc->mii_model == MII_MODEL_MARVELL_E1116) reg &= ~E1000_SCR_POWER_DOWN; + reg |= E1000_SCR_ASSERT_CRS_ON_TX; break; case MII_MODEL_MARVELL_E3082: reg |= (E1000_SCR_AUTO_X_MODE >> 1); + reg |= E1000_SCR_ASSERT_CRS_ON_TX; break; + case MII_MODEL_MARVELL_E3016: + reg |= E1000_SCR_AUTO_MDIX; + reg &= ~(E1000_SCR_EN_DETECT | + E1000_SCR_SCRAMBLER_DISABLE); + reg |= E1000_SCR_LPNP; + /* XXX Enable class A driver for Yukon FE+ A0. */ + PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); + break; default: reg &= ~E1000_SCR_AUTO_X_MODE; + reg |= E1000_SCR_ASSERT_CRS_ON_TX; break; } - /* Enable CRS on TX. */ - reg |= E1000_SCR_ASSERT_CRS_ON_TX; - /* Auto correction for reversed cable polarity. */ - reg &= ~E1000_SCR_POLARITY_REVERSAL; + if (esc->mii_model != MII_MODEL_MARVELL_E3016) { + /* Auto correction for reversed cable polarity. */ + reg &= ~E1000_SCR_POLARITY_REVERSAL; + } PHY_WRITE(sc, E1000_SCR, reg); if (esc->mii_model == MII_MODEL_MARVELL_E1116) { @@ -283,6 +254,13 @@ case MII_MODEL_MARVELL_E1118: case MII_MODEL_MARVELL_E1149: break; + case MII_MODEL_MARVELL_E3016: + /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ + PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); + /* Integrated register calibration workaround. */ + PHY_WRITE(sc, 0x1D, 17); + PHY_WRITE(sc, 0x1E, 0x3F60); + break; default: /* Force TX_CLK to 25MHz clock. */ reg = PHY_READ(sc, E1000_ESCR); @@ -339,12 +317,14 @@ speed = 0; switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_1000_T: - if (esc->mii_model == MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & + (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) return (EINVAL); speed = E1000_CR_SPEED_1000; break; case IFM_1000_SX: - if (esc->mii_model == MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & + (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) return (EINVAL); speed = E1000_CR_SPEED_1000; break; @@ -390,7 +370,8 @@ PHY_WRITE(sc, E1000_1GCR, gig | E1000_1GCR_MS_ENABLE); } else { - if (esc->mii_model != MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & + (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) PHY_WRITE(sc, E1000_1GCR, 0); } PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); @@ -432,7 +413,7 @@ if (sc->mii_ticks++ == 0) break; if (sc->mii_ticks <= sc->mii_anegticks) - return (0); + break; sc->mii_ticks = 0; e1000phy_reset(sc); @@ -452,18 +433,14 @@ e1000phy_status(struct mii_softc *sc) { struct mii_data *mii = sc->mii_pdata; - int bmsr, bmcr, esr, gsr, ssr, isr, ar, lpar; + int bmcr, bmsr, gsr, ssr, ar, lpar; mii->mii_media_status = IFM_AVALID; mii->mii_media_active = IFM_ETHER; bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); - esr = PHY_READ(sc, E1000_ESR); bmcr = PHY_READ(sc, E1000_CR); ssr = PHY_READ(sc, E1000_SSR); - isr = PHY_READ(sc, E1000_ISR); - ar = PHY_READ(sc, E1000_AR); - lpar = PHY_READ(sc, E1000_LPAR); if (bmsr & E1000_SR_LINK_STATUS) mii->mii_media_status |= IFM_ACTIVE; @@ -471,22 +448,28 @@ if (bmcr & E1000_CR_LOOPBACK) mii->mii_media_active |= IFM_LOOP; - if ((((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0) && - ((bmsr & E1000_SR_AUTO_NEG_COMPLETE) == 0)) || - ((ssr & E1000_SSR_LINK) == 0) || - ((ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0)) { + if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && + (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { /* Erg, still trying, I guess... */ mii->mii_media_active |= IFM_NONE; return; } if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { - if (ssr & E1000_SSR_1000MBS) + switch (ssr & E1000_SSR_SPEED) { + case E1000_SSR_1000MBS: mii->mii_media_active |= IFM_1000_T; - else if (ssr & E1000_SSR_100MBS) + break; + case E1000_SSR_100MBS: mii->mii_media_active |= IFM_100_TX; - else + break; + case E1000_SSR_10MBS: mii->mii_media_active |= IFM_10_T; + break; + default: + mii->mii_media_active |= IFM_NONE; + return; + } } else { if (ssr & E1000_SSR_1000MBS) mii->mii_media_active |= IFM_1000_SX; @@ -498,6 +481,8 @@ mii->mii_media_active |= IFM_HDX; if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + ar = PHY_READ(sc, E1000_AR); + lpar = PHY_READ(sc, E1000_LPAR); /* FLAG0==rx-flow-control FLAG1==tx-flow-control */ if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) { mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1; @@ -524,16 +509,19 @@ e1000phy_mii_phy_auto(struct e1000phy_softc *esc) { struct mii_softc *sc; + uint16_t reg; sc = &esc->mii_sc; - if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) - PHY_WRITE(sc, E1000_AR, E1000_AR_10T | E1000_AR_10T_FD | + if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + reg = PHY_READ(sc, E1000_AR); + reg |= E1000_AR_10T | E1000_AR_10T_FD | E1000_AR_100TX | E1000_AR_100TX_FD | - E1000_AR_PAUSE | E1000_AR_ASM_DIR); - else + E1000_AR_PAUSE | E1000_AR_ASM_DIR; + PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); + } else PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X | E1000_FA_SYM_PAUSE | E1000_FA_ASYM_PAUSE); - if (esc->mii_model != MII_MODEL_MARVELL_E3082) + if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) PHY_WRITE(sc, E1000_1GCR, E1000_1GCR_1000T_FD | E1000_1GCR_1000T); PHY_WRITE(sc, E1000_CR, Index: sys/dev/mii/e1000phyreg.h =================================================================== --- sys/dev/mii/e1000phyreg.h (revision 192499) +++ sys/dev/mii/e1000phyreg.h (working copy) @@ -236,6 +236,16 @@ #define E1000_SCR_TX_FIFO_DEPTH_10 0x8000 #define E1000_SCR_TX_FIFO_DEPTH_12 0xC000 +/* 88E3016 only */ +#define E1000_SCR_AUTO_MDIX 0x0030 +#define E1000_SCR_SIGDET_POLARITY 0x0040 +#define E1000_SCR_EXT_DISTANCE 0x0080 +#define E1000_SCR_FEFI_DISABLE 0x0100 +#define E1000_SCR_NLP_GEN_DISABLE 0x0800 +#define E1000_SCR_LPNP 0x1000 +#define E1000_SCR_NLP_CHK_DISABLE 0x2000 +#define E1000_SCR_EN_DETECT 0x4000 + #define E1000_SCR_EN_DETECT_MASK 0x0300 /* 88E1112 page 2 */ Index: sys/dev/msk/if_msk.c =================================================================== --- sys/dev/msk/if_msk.c (revision 192499) +++ sys/dev/msk/if_msk.c (working copy) @@ -197,6 +197,14 @@ "Marvell Yukon 88E8038 Gigabit Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_8039, "Marvell Yukon 88E8039 Gigabit Ethernet" }, + { VENDORID_MARVELL, DEVICEID_MRVL_8040, + "Marvell Yukon 88E8040 Fast Ethernet" }, + { VENDORID_MARVELL, DEVICEID_MRVL_8040T, + "Marvell Yukon 88E8040T Fast Ethernet" }, + { VENDORID_MARVELL, DEVICEID_MRVL_8048, + "Marvell Yukon 88E8048 Fast Ethernet" }, + { VENDORID_MARVELL, DEVICEID_MRVL_8070, + "Marvell Yukon 88E8070 Fast Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_4361, "Marvell Yukon 88E8050 Gigabit Ethernet" }, { VENDORID_MARVELL, DEVICEID_MRVL_4360, @@ -220,7 +228,8 @@ "Yukon EC Ultra", "Yukon Unknown", "Yukon EC", - "Yukon FE" + "Yukon FE", + "Yukon FE+" }; static int mskc_probe(device_t); @@ -285,7 +294,6 @@ static int msk_miibus_readreg(device_t, int, int); static int msk_miibus_writereg(device_t, int, int, int); static void msk_miibus_statchg(device_t); -static void msk_link_task(void *, int); static void msk_rxfilter(struct msk_if_softc *); static void msk_setvlan(struct msk_if_softc *, struct ifnet *); @@ -459,40 +467,44 @@ static void msk_miibus_statchg(device_t dev) { - struct msk_if_softc *sc_if; - - sc_if = device_get_softc(dev); - taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); -} - -static void -msk_link_task(void *arg, int pending) -{ struct msk_softc *sc; struct msk_if_softc *sc_if; struct mii_data *mii; struct ifnet *ifp; uint32_t gmac; - sc_if = (struct msk_if_softc *)arg; + sc_if = device_get_softc(dev); sc = sc_if->msk_softc; - MSK_IF_LOCK(sc_if); + MSK_IF_LOCK_ASSERT(sc_if); mii = device_get_softc(sc_if->msk_miibus); ifp = sc_if->msk_ifp; - if (mii == NULL || ifp == NULL) { - MSK_IF_UNLOCK(sc_if); + if (mii == NULL || ifp == NULL || + (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) return; + + sc_if->msk_flags &= ~MSK_FLAG_LINK; + if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == + (IFM_AVALID | IFM_ACTIVE)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + sc_if->msk_flags |= MSK_FLAG_LINK; + break; + case IFM_1000_T: + case IFM_1000_SX: + case IFM_1000_LX: + case IFM_1000_CX: + if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) + sc_if->msk_flags |= MSK_FLAG_LINK; + break; + default: + break; + } } - if (mii->mii_media_status & IFM_ACTIVE) { - if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) - sc_if->msk_link = 1; - } else - sc_if->msk_link = 0; - - if (sc_if->msk_link != 0) { + if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { /* Enable Tx FIFO Underrun. */ CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); @@ -549,13 +561,13 @@ msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); /* Disable Rx/Tx MAC. */ gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); - gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); - GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); - /* Read again to ensure writing. */ - GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); + if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { + gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); + GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); + /* Read again to ensure writing. */ + GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); + } } - - MSK_IF_UNLOCK(sc_if); } static void @@ -869,15 +881,16 @@ { struct msk_if_softc *sc_if; struct mii_data *mii; + int error; sc_if = ifp->if_softc; MSK_IF_LOCK(sc_if); mii = device_get_softc(sc_if->msk_miibus); - mii_mediachg(mii); + error = mii_mediachg(mii); MSK_IF_UNLOCK(sc_if); - return (0); + return (error); } /* @@ -913,20 +926,30 @@ switch(command) { case SIOCSIFMTU: + MSK_IF_LOCK(sc_if); if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) error = EINVAL; else if (ifp->if_mtu != ifr->ifr_mtu) { - if ((sc_if->msk_flags & MSK_FLAG_NOJUMBO) != 0 && - ifr->ifr_mtu > ETHERMTU) - error = EINVAL; - else { - MSK_IF_LOCK(sc_if); - ifp->if_mtu = ifr->ifr_mtu; - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) - msk_init_locked(sc_if); - MSK_IF_UNLOCK(sc_if); + if (ifr->ifr_mtu > ETHERMTU) { + if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { + error = EINVAL; + MSK_IF_UNLOCK(sc_if); + break; + } + if ((sc_if->msk_flags & + MSK_FLAG_JUMBO_NOCSUM) != 0) { + ifp->if_hwassist &= + ~(MSK_CSUM_FEATURES | CSUM_TSO); + ifp->if_capenable &= + ~(IFCAP_TSO4 | IFCAP_TXCSUM); + VLAN_CAPABILITIES(ifp); + } } + ifp->if_mtu = ifr->ifr_mtu; + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + msk_init_locked(sc_if); } + MSK_IF_UNLOCK(sc_if); break; case SIOCSIFFLAGS: MSK_IF_LOCK(sc_if); @@ -936,7 +959,7 @@ & (IFF_PROMISC | IFF_ALLMULTI)) != 0) msk_rxfilter(sc_if); } else { - if (sc_if->msk_detach == 0) + if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) msk_init_locked(sc_if); } } else { @@ -961,33 +984,30 @@ case SIOCSIFCAP: MSK_IF_LOCK(sc_if); mask = ifr->ifr_reqcap ^ ifp->if_capenable; - if ((mask & IFCAP_TXCSUM) != 0) { + if ((mask & IFCAP_TXCSUM) != 0 && + (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_TXCSUM; - if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && - (IFCAP_TXCSUM & ifp->if_capabilities) != 0) + if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) ifp->if_hwassist |= MSK_CSUM_FEATURES; else ifp->if_hwassist &= ~MSK_CSUM_FEATURES; } - if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { + if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && + (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; msk_setvlan(sc_if, ifp); } - if ((mask & IFCAP_TSO4) != 0) { + if ((mask & IFCAP_TSO4) != 0 && + (IFCAP_TSO4 & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_TSO4; - if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && - (IFCAP_TSO4 & ifp->if_capabilities) != 0) + if ((IFCAP_TSO4 & ifp->if_capenable) != 0) ifp->if_hwassist |= CSUM_TSO; else ifp->if_hwassist &= ~CSUM_TSO; } if (ifp->if_mtu > ETHERMTU && - sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { - /* - * In Yukon EC Ultra, TSO & checksum offload is not - * supported for jumbo frame. - */ + (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); } @@ -1071,7 +1091,7 @@ static void msk_phy_power(struct msk_softc *sc, int mode) { - uint32_t val; + uint32_t our, val; int i; switch (mode) { @@ -1097,17 +1117,19 @@ val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); - if (sc->msk_hw_id == CHIP_ID_YUKON_XL && - sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { - /* Deassert Low Power for 1st PHY. */ - val |= PCI_Y2_PHY1_COMA; - if (sc->msk_num_port > 1) - val |= PCI_Y2_PHY2_COMA; - } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { - uint32_t our; + switch (sc->msk_hw_id) { + case CHIP_ID_YUKON_XL: + if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { + /* Deassert Low Power for 1st PHY. */ + val |= PCI_Y2_PHY1_COMA; + if (sc->msk_num_port > 1) + val |= PCI_Y2_PHY2_COMA; + } + break; + case CHIP_ID_YUKON_EC_U: + case CHIP_ID_YUKON_FE_P: + CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); - CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); - /* Enable all clocks. */ pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); @@ -1117,6 +1139,9 @@ pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); /* Set to default value. */ pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); + break; + default: + break; } /* Release PHY from PowerDown/COMA mode. */ pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); @@ -1416,13 +1441,8 @@ } callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); - TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); msk_sysctl_node(sc_if); - /* Disable jumbo frame for Yukon FE. */ - if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE) - sc_if->msk_flags |= MSK_FLAG_NOJUMBO; - if ((error = msk_txrx_dma_alloc(sc_if) != 0)) goto fail; msk_rx_dma_jalloc(sc_if); @@ -1483,14 +1503,17 @@ ether_ifattach(ifp, eaddr); MSK_IF_LOCK(sc_if); - /* - * VLAN capability setup - * Due to Tx checksum offload hardware bugs, msk(4) manually - * computes checksum for short frames. For VLAN tagged frames - * this workaround does not work so disable checksum offload - * for VLAN interface. - */ - ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; + /* VLAN capability setup */ + ifp->if_capabilities |= IFCAP_VLAN_MTU; + if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { + /* + * Due to Tx checksum offload hardware bugs, msk(4) manually + * computes checksum for short frames. For VLAN tagged frames + * this workaround does not work so disable checksum offload + * for VLAN interface. + */ + ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; + } ifp->if_capenable = ifp->if_capabilities; /* @@ -1571,7 +1594,7 @@ sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; /* Bail out if chip is not recognized. */ if (sc->msk_hw_id < CHIP_ID_YUKON_XL || - sc->msk_hw_id > CHIP_ID_YUKON_FE) { + sc->msk_hw_id > CHIP_ID_YUKON_FE_P) { device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", sc->msk_hw_id, sc->msk_hw_rev); mtx_destroy(&sc->msk_mtx); @@ -1622,14 +1645,37 @@ switch (sc->msk_hw_id) { case CHIP_ID_YUKON_EC: + sc->msk_clock = 125; /* 125 Mhz */ + sc->msk_pflags |= MSK_FLAG_JUMBO; + break; case CHIP_ID_YUKON_EC_U: sc->msk_clock = 125; /* 125 Mhz */ + sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; break; case CHIP_ID_YUKON_FE: sc->msk_clock = 100; /* 100 Mhz */ + sc->msk_pflags |= MSK_FLAG_FASTETHER; break; + case CHIP_ID_YUKON_FE_P: + sc->msk_clock = 50; /* 50 Mhz */ + sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2; + if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { + /* + * XXX + * FE+ A0 has status LE writeback bug so msk(4) + * does not rely on status word of received frame + * in msk_rxeof() which in turn disables all + * hardware assistance bits reported by the status + * word as well as validity of the recevied frame. + * Just pass received frames to upper stack with + * minimal test and let upper stack handle them. + */ + sc->msk_pflags |= MSK_FLAG_NOHWVLAN | MSK_FLAG_NORXCHK; + } + break; case CHIP_ID_YUKON_XL: sc->msk_clock = 156; /* 156 Mhz */ + sc->msk_pflags |= MSK_FLAG_JUMBO; break; default: sc->msk_clock = 156; /* 156 Mhz */ @@ -1659,7 +1705,7 @@ if (sc->msk_num_port == 1 && pci_alloc_msi(dev, &msir) == 0) { if (msic == msir) { - sc->msk_msi = 1; + sc->msk_pflags |= MSK_FLAG_MSI; sc->msk_irq_spec = msic == 2 ? msk_irq_spec_msi2 : msk_irq_spec_msi; @@ -1785,13 +1831,12 @@ ifp = sc_if->msk_ifp; if (device_is_attached(dev)) { /* XXX */ - sc_if->msk_detach = 1; + sc_if->msk_flags |= MSK_FLAG_DETACH; msk_stop(sc_if); /* Can't hold locks while calling detach. */ MSK_IF_UNLOCK(sc_if); callout_drain(&sc_if->msk_tick_ch); taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); - taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); ether_ifdetach(ifp); MSK_IF_LOCK(sc_if); } @@ -1870,7 +1915,7 @@ sc->msk_intrhand[1] = NULL; } bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); - if (sc->msk_msi) + if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) pci_release_msi(dev); bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); mtx_destroy(&sc->msk_mtx); @@ -2172,11 +2217,10 @@ bus_size_t rxalign; int error, i; - if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_NOJUMBO) != 0) { - sc_if->msk_flags |= MSK_FLAG_NOJUMBO; + if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { + sc_if->msk_flags &= ~MSK_FLAG_JUMBO; device_printf(sc_if->msk_if_dev, "disabling jumbo frame support\n"); - sc_if->msk_flags |= MSK_FLAG_NOJUMBO; return (0); } /* Create tag for jumbo Rx ring. */ @@ -2271,7 +2315,7 @@ msk_rx_dma_jfree(sc_if); device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " "due to resource shortage\n"); - sc_if->msk_flags |= MSK_FLAG_NOJUMBO; + sc_if->msk_flags &= ~MSK_FLAG_JUMBO; return (error); } @@ -2407,7 +2451,8 @@ tcp_offset = offset = 0; m = *m_head; - if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { + if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && + (m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { /* * Since mbuf has no protocol specific structure information * in it we have to inspect protocol information here to @@ -2534,11 +2579,18 @@ /* Check TSO support. */ if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { - tso_mtu = offset + m->m_pkthdr.tso_segsz; + if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) + tso_mtu = m->m_pkthdr.tso_segsz; + else + tso_mtu = offset + m->m_pkthdr.tso_segsz; if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; tx_le->msk_addr = htole32(tso_mtu); - tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); + if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) + tx_le->msk_control = htole32(OP_MSS | HW_OWNER); + else + tx_le->msk_control = + htole32(OP_LRGLEN | HW_OWNER); sc_if->msk_cdata.msk_tx_cnt++; MSK_INC(prod, MSK_TX_RING_CNT); sc_if->msk_cdata.msk_tso_mtu = tso_mtu; @@ -2562,15 +2614,21 @@ } /* Check if we have to handle checksum offload. */ if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { - tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; - tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) - & 0xffff) | ((uint32_t)tcp_offset << 16)); - tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); - control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; - if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) - control |= UDPTCP; - sc_if->msk_cdata.msk_tx_cnt++; - MSK_INC(prod, MSK_TX_RING_CNT); + if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) + control |= CALSUM; + else { + tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; + tx_le->msk_addr = htole32(((tcp_offset + + m->m_pkthdr.csum_data) & 0xffff) | + ((uint32_t)tcp_offset << 16)); + tx_le->msk_control = htole32(1 << 16 | + (OP_TCPLISW | HW_OWNER)); + control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; + if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) + control |= UDPTCP; + sc_if->msk_cdata.msk_tx_cnt++; + MSK_INC(prod, MSK_TX_RING_CNT); + } } si = prod; @@ -2641,7 +2699,7 @@ MSK_IF_LOCK(sc_if); if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != - IFF_DRV_RUNNING || sc_if->msk_link == 0) { + IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) { MSK_IF_UNLOCK(sc_if); return; } @@ -2698,7 +2756,7 @@ if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) return; ifp = sc_if->msk_ifp; - if (sc_if->msk_link == 0) { + if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { if (bootverbose) if_printf(sc_if->msk_ifp, "watchdog timeout " "(missed link)\n"); @@ -2785,7 +2843,7 @@ /* Put hardware reset. */ CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); - sc->msk_suspended = 1; + sc->msk_pflags |= MSK_FLAG_SUSPEND; MSK_UNLOCK(sc); @@ -2808,7 +2866,7 @@ ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) msk_init_locked(sc->msk_if[i]); } - sc->msk_suspended = 0; + sc->msk_pflags &= ~MSK_FLAG_SUSPEND; MSK_UNLOCK(sc); @@ -2850,7 +2908,18 @@ if ((status & GMR_FS_VLAN) != 0 && (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) rxlen -= ETHER_VLAN_ENCAP_LEN; - if (len > sc_if->msk_framesize || + if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { + /* + * For controllers that returns bogus status code + * just do minimal check and let upper stack + * handle this frame. + */ + if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { + ifp->if_ierrors++; + msk_discard_rxbuf(sc_if, cons); + break; + } + } else if (len > sc_if->msk_framesize || ((status & GMR_FS_ANY_ERR) != 0) || ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { /* Don't count flow-control packet as errors. */ @@ -3011,6 +3080,8 @@ mii = device_get_softc(sc_if->msk_miibus); mii_tick(mii); + if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) + msk_miibus_statchg(sc_if->msk_if_dev); msk_watchdog(sc_if); callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); } @@ -3321,7 +3392,8 @@ /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); - if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || + if (status == 0 || status == 0xffffffff || + (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || (status & sc->msk_intrmask) == 0) { CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); return; @@ -3408,7 +3480,8 @@ /* Get interrupt source. */ status = CSR_READ_4(sc, B0_ISRC); - if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || + if (status == 0 || status == 0xffffffff || + (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || (status & sc->msk_intrmask) == 0) goto done; @@ -3484,6 +3557,7 @@ struct mii_data *mii; uint16_t eaddr[ETHER_ADDR_LEN / 2]; uint16_t gmac; + uint32_t reg; int error, i; MSK_IF_LOCK_ASSERT(sc_if); @@ -3502,27 +3576,21 @@ sc_if->msk_framesize = ifp->if_mtu; sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; if (ifp->if_mtu > ETHERMTU && - sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { - /* - * In Yukon EC Ultra, TSO & checksum offload is not - * supported for jumbo frame. - */ + (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); } + /* GMAC Control reset. */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); + /* - * Initialize GMAC first. - * Without this initialization, Rx MAC did not work as expected - * and Rx MAC garbled status LEs and it resulted in out-of-order - * or duplicated frame delivery which in turn showed very poor - * Rx performance.(I had to write a packet analysis code that - * could be embeded in driver to diagnose this issue.) - * I've spent almost 2 months to fix this issue. If I have had - * datasheet for Yukon II I wouldn't have encountered this. :-( + * Initialize GMAC first such that speed/duplex/flow-control + * parameters are renegotiated when interface is brought up. */ - gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; - GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); + GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); /* Dummy read the Interrupt Source Register. */ CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); @@ -3568,8 +3636,10 @@ /* Configure Rx MAC FIFO. */ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); - CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), - GMF_OPER_ON | GMF_RX_F_FL_ON); + reg = GMF_OPER_ON | GMF_RX_F_FL_ON; + if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P) + reg |= GMF_RX_OVER_ON; + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); /* Set receive filter. */ msk_rxfilter(sc_if); @@ -3582,8 +3652,12 @@ * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word * due to hardware hang on receipt of pause frames. */ - CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), - RX_GMF_FL_THR_DEF + 1); + reg = RX_GMF_FL_THR_DEF + 1; + /* Another magic for Yukon FE+ - From Linux. */ + if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && + sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) + reg = 0x178; + CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); /* Configure Tx MAC FIFO. */ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); @@ -3615,6 +3689,14 @@ } } + if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && + sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { + /* Disable dynamic watermark - from Linux. */ + reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); + reg &= ~0x03; + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); + } + /* * Disable Force Sync bit and Alloc bit in Tx RAM interface * arbiter as we don't use Sync Tx queue. @@ -3690,7 +3772,7 @@ CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); CSR_READ_4(sc, B0_IMSK); - sc_if->msk_link = 0; + sc_if->msk_flags &= ~MSK_FLAG_LINK; mii_mediachg(mii); ifp->if_drv_flags |= IFF_DRV_RUNNING; @@ -3925,7 +4007,7 @@ * Mark the interface down. */ ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); - sc_if->msk_link = 0; + sc_if->msk_flags &= ~MSK_FLAG_LINK; } /* Index: sys/dev/msk/if_mskreg.h =================================================================== --- sys/dev/msk/if_mskreg.h (revision 192499) +++ sys/dev/msk/if_mskreg.h (working copy) @@ -130,12 +130,16 @@ #define DEVICEID_MRVL_8035 0x4350 #define DEVICEID_MRVL_8036 0x4351 #define DEVICEID_MRVL_8038 0x4352 -#define DEVICEID_MRVL_8039 0X4353 +#define DEVICEID_MRVL_8039 0x4353 +#define DEVICEID_MRVL_8040 0x4354 +#define DEVICEID_MRVL_8040T 0x4355 +#define DEVICEID_MRVL_8048 0x435A #define DEVICEID_MRVL_4360 0x4360 #define DEVICEID_MRVL_4361 0x4361 #define DEVICEID_MRVL_4362 0x4362 #define DEVICEID_MRVL_4363 0x4363 #define DEVICEID_MRVL_4364 0x4364 +#define DEVICEID_MRVL_8070 0x4365 #define DEVICEID_MRVL_436A 0x436A /* @@ -828,6 +832,7 @@ #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ +#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ @@ -841,6 +846,8 @@ #define CHIP_REV_YU_EC_U_A0 1 #define CHIP_REV_YU_EC_U_A1 2 +#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ + /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ @@ -1855,6 +1862,10 @@ #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ +#define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ +#define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ +#define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ +#define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ #define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ #define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ #define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ @@ -2122,6 +2133,8 @@ #define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) #define OP_LRGLEN 0x24000000 #define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) +#define OP_MSS 0x28000000 +#define OP_MSSVLAN (OP_MSS | OP_VLAN) #define OP_BUFFER 0x40000000 #define OP_PACKET 0x41000000 #define OP_LARGESEND 0x43000000 @@ -2342,9 +2355,7 @@ uint32_t msk_intrmask; uint32_t msk_intrhwemask; uint32_t msk_pflags; - int msk_suspended; int msk_clock; - int msk_msi; struct msk_if_softc *msk_if[2]; device_t msk_devs[2]; int msk_txqsize; @@ -2382,10 +2393,19 @@ int msk_framesize; int msk_phytype; int msk_phyaddr; - int msk_link; uint32_t msk_flags; -#define MSK_FLAG_RAMBUF 0x0010 -#define MSK_FLAG_NOJUMBO 0x0020 +#define MSK_FLAG_MSI 0x0001 +#define MSK_FLAG_MSIX 0x0002 +#define MSK_FLAG_FASTETHER 0x0004 +#define MSK_FLAG_JUMBO 0x0008 +#define MSK_FLAG_JUMBO_NOCSUM 0x0010 +#define MSK_FLAG_RAMBUF 0x0020 +#define MSK_FLAG_DESCV2 0x0040 +#define MSK_FLAG_NOHWVLAN 0x0080 +#define MSK_FLAG_NORXCHK 0x0100 +#define MSK_FLAG_SUSPEND 0x2000 +#define MSK_FLAG_DETACH 0x4000 +#define MSK_FLAG_LINK 0x8000 struct callout msk_tick_ch; int msk_watchdog_timer; uint32_t msk_txq; /* Tx. Async Queue offset */ @@ -2395,10 +2415,8 @@ struct msk_ring_data msk_rdata; struct msk_softc *msk_softc; /* parent controller */ struct msk_hw_stats msk_stats; - struct task msk_link_task; struct task msk_tx_task; int msk_if_flags; - int msk_detach; uint16_t msk_vtag; /* VLAN tag id. */ };