/*- * Copyright (c) 2000-2004 Taku YAMAMOTO * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp */ /* * Credits: * * Part of this code (especially in many magic numbers) was heavily inspired * by the Linux driver originally written by * Alan Cox , modified heavily by * Zach Brown . * * busdma()-ize and buffer size reduction were suggested by * Cameron Grant . * Also he showed me the way to use busdma() suite. * * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500 * were looked at by * Munehiro Matsuda , * who brought patches based on the Linux driver with some simplification. * * Hardware volume controller was implemented by * John Baldwin . */ #include #include #include #include #include SND_DECLARE_FILE("$FreeBSD: src/sys/dev/sound/pci/maestro.c,v 1.28 2005/03/01 08:58:05 imp Exp $"); #define inline __inline /* * PCI IDs of supported chips: * * MAESTRO-1 0x01001285 * MAESTRO-2 0x1968125d * MAESTRO-2E 0x1978125d */ #define MAESTRO_1_PCI_ID 0x01001285 #define MAESTRO_2_PCI_ID 0x1968125d #define MAESTRO_2E_PCI_ID 0x1978125d #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */ #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */ #define AGG_MAXPLAYCH 4 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */ /* ----------------------------- * Data structures. */ struct agg_dma { bus_dma_tag_t dmat; bus_dmamap_t dmam; caddr_t vaddr; /* channel buffer address */ bus_addr_t phys; /* DMA channel buffer address */ bus_addr_t base; /* DMA buffer segment base */ uint32_t size; }; struct agg_chinfo { /* parent softc */ struct agg_info *parent; /* FreeBSD newpcm related */ struct pcm_channel *channel; struct snd_dbuf *buffer; /* OS independent */ struct agg_dma dma; u_int32_t blklen; /* DMA block length in WORDs */ u_int32_t buflen; /* channel buffer length in WORDs */ u_int32_t speed; unsigned num : 3; unsigned stereo : 1; unsigned qs16 : 1; /* quantum size is 16bit */ unsigned us : 1; /* in unsigned format */ }; struct agg_rchinfo { /* parent softc */ struct agg_info *parent; /* FreeBSD newpcm related */ struct pcm_channel *channel; struct snd_dbuf *buffer; /* OS independent */ struct agg_dma dma; u_int32_t blklen; /* DMA block length in WORDs */ u_int32_t buflen; /* channel buffer length in WORDs */ u_int32_t speed; unsigned num : 3; unsigned stereo : 1; bus_addr_t srcphys; int16_t *src; /* stereo peer buffer */ int16_t *sink; /* channel buffer pointer */ u_int32_t hwptr; /* ready point in 16bit sample */ }; struct agg_info { /* FreeBSD newbus related */ device_t dev; /* I wonder whether bus_space_* are in common in *BSD... */ struct resource *reg; int regid; bus_space_tag_t st; bus_space_handle_t sh; struct resource *irq; int irqid; void *ih; bus_dma_tag_t buf_dmat; bus_dma_tag_t stat_dmat; /* FreeBSD SMPng related */ struct mtx *lock; /* mutual exclusion */ /* FreeBSD newpcm related */ struct ac97_info *codec; /* OS independent */ unsigned int bufsz; /* channel buffer size in bytes */ u_int playchns; u_int active; struct agg_chinfo pch[AGG_MAXPLAYCH]; struct agg_rchinfo rch; uint32_t flags; #define AGG_JITTER_CORRECTION 0x01 }; #define AGG_LOCK(_sc) snd_mtxlock((_sc)->lock) #define AGG_UNLOCK(_sc) snd_mtxunlock((_sc)->lock) #define AGG_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->lock) #define AGG_RD(sc, regno, size) \ bus_space_read_##size( \ ((struct agg_info*)(sc))->st, \ ((struct agg_info*)(sc))->sh, (regno)) #define AGG_WR(sc, regno, data, size) \ bus_space_write_##size( \ ((struct agg_info*)(sc))->st, \ ((struct agg_info*)(sc))->sh, (regno), (data)) #define AGG_ACPI_ALL 0xffff #define AGG_ACPI_SLEEP \ (~(ACPI_PART_SPDIF | ACPI_PART_ASSP | ACPI_PART_SB | ACPI_PART_FM | \ ACPI_PART_MIDI | ACPI_PART_GAME_PORT | ACPI_PART_WP)) #define AGG_ACPI_NONE (ACPI_PART_DAA) static uint16_t agg_acpi_state_mask[] = { AGG_ACPI_ALL, AGG_ACPI_SLEEP, AGG_ACPI_SLEEP, AGG_ACPI_NONE }; /* ----------------------------- * Prototypes */ static inline int agg_rdcodec(struct agg_info*, int); static inline int agg_wrcodec(struct agg_info*, int, u_int32_t); static inline u_int16_t wp_rdreg(struct agg_info*, u_int16_t); static inline void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t); static inline u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t); static inline void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t); static inline void wp_settimer(struct agg_info*, u_int); static inline void wp_starttimer(struct agg_info*); static inline void wp_stoptimer(struct agg_info*); static inline u_int16_t wc_rdreg(struct agg_info*, u_int16_t); static inline void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t); static inline u_int16_t wc_rdchctl(struct agg_info*, int); static inline void wc_wrchctl(struct agg_info*, int, u_int16_t); static void agg_acpi(struct agg_info *, int); static inline void agg_initcodec(struct agg_info*); static void agg_init(struct agg_info*); static void agg_pci_power(struct agg_info *, uint8_t); static void agg_power(struct agg_info*, int); static void aggch_start_dac(struct agg_chinfo*); static void aggch_stop_dac(struct agg_chinfo*); static void aggch_start_adc(struct agg_rchinfo*); static void aggch_stop_adc(struct agg_rchinfo*); static void aggch_feed_adc_stereo(struct agg_rchinfo*); static void aggch_feed_adc_mono(struct agg_rchinfo*); static inline void suppress_jitter(struct agg_chinfo*); static inline void suppress_rec_jitter(struct agg_rchinfo*); static void set_timer(struct agg_info*); static void agg_intr(void *); static int agg_probe(device_t); static int agg_attach(device_t); static int agg_detach(device_t); static int agg_suspend(device_t); static int agg_resume(device_t); static int agg_shutdown(device_t); static void *dma_malloc(struct agg_dma *); static void dma_free(struct agg_dma *); /* ----------------------------- * Subsystems. */ /* Codec/Ringbus */ static inline int agg_codec_wait4idle(struct agg_info *ess) { int i, step, to; to = 1000; /* 1ms */ for (i = 0, step = 1; i < to; i += step) { if ((AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) != CODEC_STAT_PROGRESS) return (0); step += step; DELAY(step); } return (EBUSY); } static inline int agg_rdcodec(struct agg_info *ess, int regno) { int ret; /* We have to wait for a SAFE time to write addr/data */ if (agg_codec_wait4idle(ess)) { /* Timed out, force to continue. */ device_printf(ess->dev, "%s: PROGRESS timed out.\n", __func__); } AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1); /*DELAY(21); * AC97 cycle = 20.8usec */ /* Wait for data retrieve */ if (agg_codec_wait4idle(ess)) device_printf(ess->dev, "%s: RW_DONE timed out.\n", __func__); ret = AGG_RD(ess, PORT_CODEC_REG, 2); return ret; } static inline int agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data) { /* We have to wait for a SAFE time to write addr/data */ if (agg_codec_wait4idle(ess)) { /* Timed out, force to continue. */ device_printf(ess->dev, "%s: PROGRESS timed out.\n", __func__); } AGG_WR(ess, PORT_CODEC_REG, data, 2); AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1); return 0; } /* -------------------------------------------------------------------- */ /* Wave Processor */ static inline u_int16_t wp_rdreg(struct agg_info *ess, u_int16_t reg) { AGG_WR(ess, PORT_DSP_INDEX, reg, 2); return AGG_RD(ess, PORT_DSP_DATA, 2); } static inline void wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data) { AGG_WR(ess, PORT_DSP_INDEX, reg, 2); AGG_WR(ess, PORT_DSP_DATA, data, 2); } static inline int wp_wait_data(struct agg_info *ess, u_int16_t data) { unsigned t = 0; while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) { if (++t == 1000) { return EAGAIN; } AGG_WR(ess, PORT_DSP_DATA, data, 2); } return 0; } static inline u_int16_t wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg) { wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4)); if (wp_wait_data(ess, reg | (ch << 4)) != 0) device_printf(ess->dev, "%s: indexing timed out.\n", __func__); return wp_rdreg(ess, WPREG_DATA_PORT); } static inline void wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data) { wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4)); if (wp_wait_data(ess, reg | (ch << 4)) == 0) { wp_wrreg(ess, WPREG_DATA_PORT, data); if (wp_wait_data(ess, data) != 0) device_printf(ess->dev, "%s: write timed out.\n", __func__); } else { device_printf(ess->dev, "%s: indexing timed out.\n", __func__); } } static void apu_setparam(struct agg_info *ess, int apuch, u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv) { wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK); wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa); wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size); wp_wrapu(ess, apuch, APUREG_LOOPLEN, size); wp_wrapu(ess, apuch, APUREG_ROUTING, 0); wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000); wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)) | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT))); wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE, APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8); } static inline void wp_settimer(struct agg_info *ess, u_int divide) { u_int prescale = 0; RANGE(divide, 2, 32 << 7); for (; divide > 32; divide >>= 1) { prescale++; divide++; } for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1) prescale++; wp_wrreg(ess, WPREG_TIMER_ENABLE, 0); wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 | (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1)); wp_wrreg(ess, WPREG_TIMER_ENABLE, 1); } static inline void wp_starttimer(struct agg_info *ess) { AGG_WR(ess, PORT_INT_STAT, 1, 2); AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED | HOSTINT_CTRL_HWVOL_ENABLED | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2); wp_wrreg(ess, WPREG_TIMER_START, 1); } static inline void wp_stoptimer(struct agg_info *ess) { AGG_WR(ess, PORT_HOSTINT_CTRL, ~(HOSTINT_CTRL_DSOUND_INT_ENABLED | HOSTINT_CTRL_HWVOL_ENABLED) & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2); AGG_WR(ess, PORT_INT_STAT, 1, 2); wp_wrreg(ess, WPREG_TIMER_START, 0); } /* -------------------------------------------------------------------- */ /* WaveCache */ static inline u_int16_t wc_rdreg(struct agg_info *ess, u_int16_t reg) { AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2); return AGG_RD(ess, PORT_WAVCACHE_DATA, 2); } static inline void wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data) { AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2); AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2); } static inline u_int16_t wc_rdchctl(struct agg_info *ess, int ch) { return wc_rdreg(ess, ch << 3); } static inline void wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data) { wc_wrreg(ess, ch << 3, data); } /* -------------------------------------------------------------------- */ /* Power management */ static void agg_acpi(struct agg_info *ess, int state) { uint16_t mask; mask = agg_acpi_state_mask[state]; pci_write_config(ess->dev, CONF_ACPI_A, ~mask, 2); pci_write_config(ess->dev, CONF_ACPI_B, ~mask, 2); } /* ----------------------------- * Controller. */ static inline void agg_initcodec(struct agg_info* ess) { uint16_t data, ringbusa, dir; uint32_t vendor; /* save configuration */ ringbusa = AGG_RD(ess, PORT_RINGBUS_CTRL_A, 2); /* set command/status address i/o to 1st codec */ data = AGG_RD(ess, PORT_RINGBUS_SDO, 2) & 0xfffc; AGG_WR(ess, PORT_RINGBUS_SDO, data, 2); data = AGG_RD(ess, 0x3c, 2) & 0xfffc; AGG_WR(ess, 0x3c, data, 2); /* disable ac link */ AGG_WR(ess, PORT_RINGBUS_CTRL_A, 0, 4); dir = AGG_RD(ess, PORT_GPIO_DIR, 2); data = pci_read_config(ess->dev, 0x58, 2); if (data & 0x01) dir |= 0x10; /* unmask gpio 0 */ AGG_WR(ess, PORT_GPIO_MASK, 0xfffe, 2); /* gpio write */ AGG_WR(ess, PORT_GPIO_DIR, 1, 2); /* write 0 to gpio 0 */ AGG_WR(ess, PORT_GPIO_DATA, 0, 2); DELAY(20); /* write 1 to gpio 1 */ AGG_WR(ess, PORT_GPIO_DATA, 1, 2); DELAY(20*1000); /* 20ms */ /* restore */ AGG_WR(ess, PORT_GPIO_DIR, dir | 0x01, 2); data = AGG_RD(ess, PORT_RINGBUS_CTRL_B, 2) & 0xfffc; AGG_WR(ess, PORT_RINGBUS_CTRL_B, data | 0x01, 2); data = AGG_RD(ess, PORT_RINGBUS_SDO, 2) & 0xfffc; AGG_WR(ess, PORT_RINGBUS_SDO, data | 0x01, 2); data = AGG_RD(ess, 0x3c, 2) & 0xfffc; AGG_WR(ess, 0x3c, data | 0x01, 2); /* second codec */ /* disable ac link */ AGG_WR(ess, PORT_RINGBUS_CTRL_A, 0, 2); /* umask gpio 3 */ AGG_WR(ess, PORT_GPIO_MASK, 0xfff7, 2); dir = AGG_RD(ess, PORT_GPIO_DIR, 2); /* gpio write 0 & 3 ?? */ AGG_WR(ess, PORT_GPIO_DIR, 0x09, 2); /* write 1 to gpio */ AGG_WR(ess, PORT_GPIO_DATA, 1, 2); DELAY(20); /* write 9 to gpio */ AGG_WR(ess, PORT_GPIO_DATA, 0x09, 2); DELAY(500*1000); /* 500ms */ data = AGG_RD(ess, PORT_RINGBUS_SDO, 2) & 0xfffc; AGG_WR(ess, PORT_RINGBUS_SDO, data, 2); data = AGG_RD(ess, 0x3c, 2) & 0xfffc; AGG_WR(ess, 0x3c, data, 2); /* * Setup GPIO. * There seems to be speciality with NEC systems. */ vendor = pci_get_subvendor(ess->dev) | (pci_get_subdevice(ess->dev) << 16); if (vendor == NEC_SUBID1 || vendor == NEC_SUBID2) { /* Matthew Braithwaite reported that * NEC Versa LX doesn't need GPIO operation. */ AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2); AGG_WR(ess, PORT_GPIO_DIR, AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2); AGG_WR(ess, PORT_GPIO_DATA, 0x209, 2); } /* restore */ AGG_WR(ess, PORT_RINGBUS_CTRL_A, ringbusa, 2); /* check codec */ if ((AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) != 0) device_printf(ess->dev, "codec not ready!\n"); } static void agg_init(struct agg_info* ess) { uint16_t v; AGG_LOCK_ASSERT(ess); /* start with D0 state */ agg_power(ess, PCI_POWERSTATE_D0); /* maestro config A */ v = pci_read_config(ess->dev, CONF_MAESTRO_A, 2); v &= ~MAESTRO_DMA_CLEAR; v |= MAESTRO_DMA_TDMA; v &= ~(MAESTRO_PIC_SNOOP1 | MAESTRO_PIC_SNOOP2); v &= ~MAESTRO_SAFEGUARD; v |= MAESTRO_POSTEDWRITE; v |= MAESTRO_DMA_PCITIMING; v &= ~MAESTRO_SWAP_LR; v &= ~MAESTRO_SUBTR_DECODE; pci_write_config(ess->dev, CONF_MAESTRO_A, v, 2); /* maestro config B */ v = pci_read_config(ess->dev, CONF_MAESTRO_B, 2); /* turn off internal clock multiplier */ v &= ~(1 << 15); /* select external clock */ v &= ~(1 << 14); v &= ~MAESTRO_SPDIF; v |= (MAESTRO_HWVOL | MAESTRO_HWVOL_DEBOUNCE); /* gpio 4:5 */ v &= ~MAESTRO_GPIO; /* disconnect from the CHI. (Makes Dell inspiron 7500 work?) */ v |= MAESTRO_CHIBUS; v &= ~MAESTRO_IDMA; v &= ~MAESTRO_MIDI_FIX; /* reserved, always write 0 */ v &= ~(1 << 1); /* IRQ to ISA off (undoc) */ v &= ~MAESTRO_IRQ_TO_ISA; pci_write_config(ess->dev, CONF_MAESTRO_B, v, 2); /* DDMA off */ v = pci_read_config(ess->dev, CONF_DDMA, 2); v &= ~MAESTRO_DDMA_ENABLE; pci_write_config(ess->dev, CONF_DDMA, v, 2); /* disable legacy audio */ v = pci_read_config(ess->dev, CONF_LEGACY, 2); v &= ~(MAESTRO_LEGACY_AUDIO | MAESTRO_SERIAL_IRQ | MAESTRO_MPU401_IRQ | MAESTRO_MPU401_IO | MAESTRO_GAME_IO | MAESTRO_FM_IO | MAESTRO_SB_IO); pci_write_config(ess->dev, CONF_LEGACY, v, 2); /* Reset direct sound. */ AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET | HOSTINT_CTRL_DSOUND_RESET, 2); DELAY(1000); AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2); /* Setup Codec/Ringbus. */ v = (RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN) << RINGBUS_SRC_ADC; v |= (RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC) << RINGBUS_SRC_DSOUND; AGG_WR(ess, PORT_RINGBUS_CTRL, v, 2); AGG_WR(ess, PORT_RINGBUS_CTRL_A, RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 2); agg_initcodec(ess); DELAY(20); /* Enable hardware volume control interruption. */ v = pci_read_config(ess->dev, CONF_MAESTRO_B, 2); if (v & MAESTRO_HWVOL) { /* XXX - why not use device flags? */ AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_HWVOL_ENABLED, 2); /* reset hw volume to a known value */ AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1); } /* Enable S/PDIF if necessary. */ if (v & MAESTRO_SPDIF) /* XXX - why not use device flags? */ AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF | AGG_RD(ess, PORT_RINGBUS_CTRL_B, 2), 2); /* Setup Wave Processor. */ /* Enable WaveCache, set DMA base address. */ wp_wrreg(ess, WPREG_WAVE_ROMRAM, WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED); wp_wrreg(ess, WPREG_CRAM_DATA, 0); AGG_WR(ess, PORT_WAVCACHE_CTRL, WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2); /* XXX not ready yet */ for (v = WAVCACHE_PCMBAR; v < WAVCACHE_PCMBAR + 4; v++) wc_wrreg(ess, v, 0); wp_wrreg(ess, 0x08, 0xB004); wp_wrreg(ess, 0x09, 0x001B); wp_wrreg(ess, 0x0A, 0x8000); wp_wrreg(ess, 0x0B, 0x3F37); wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */ wp_wrreg(ess, WPREG_BASE + 1, 0x7632); /* Setup ASSP. Needed for Dell Inspiron 7500? */ AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1); AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1); AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1); } /* Deals power state transition. Must be called with softc->lock held. */ static void agg_pci_power(struct agg_info *ess, uint8_t state) { uint8_t v; switch (state) { case PCI_POWERSTATE_D0: case PCI_POWERSTATE_D3: v = pci_read_config(ess->dev, CONF_PM_PTR, 1); v = pci_read_config(ess->dev, v, 1); if (v == PPMI_CID) { pci_write_config(ess->dev, v + PM_CTRL, state, 1); DELAY(200); } break; } } static void agg_power(struct agg_info *ess, int state) { AGG_LOCK_ASSERT(ess); switch (state) { case PCI_POWERSTATE_D0: agg_acpi(ess, state); agg_pci_power(ess, PCI_POWERSTATE_D0); /* Turn on PCM-related parts. */ #if 0 /* * XXX * I can't sure powering up is needed operation as pcm would * bring it up during AC97_CREATE. In addition, it produced * codec timed out message on my system. */ agg_wrcodec(ess, AC97_REG_POWER, 0); DELAY(100); #endif break; case PCI_POWERSTATE_D3: /* Entirely power down. */ #if 0 /* * XXX * Writing codec with the following value generates a constant * noise when the driver is unloaded. Disable powering down * until we have better understand what it does. */ agg_wrcodec(ess, AC97_REG_POWER, 0xdf00); DELAY(100); #endif AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 2); AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2); AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1); agg_acpi(ess, state); agg_pci_power(ess, PCI_POWERSTATE_D3); break; default: break; } } /* -------------------------------------------------------------------- */ /* Channel controller. */ static void aggch_start_dac(struct agg_chinfo *ch) { bus_addr_t wpwa; u_int32_t speed; u_int16_t size, apuch, wtbar, wcreg, aputype; u_int dv; int pan; AGG_LOCK_ASSERT(ch->parent); speed = ch->speed; wpwa = (ch->dma.phys - ch->dma.base) >> 1; wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2)); wcreg = (ch->dma.phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; size = ch->buflen; apuch = (ch->num << 1) | 32; pan = PAN_RIGHT - PAN_FRONT; if (ch->stereo) { wcreg |= WAVCACHE_CHCTL_STEREO; if (ch->qs16) { aputype = APUTYPE_16BITSTEREO; wpwa >>= 1; size >>= 1; pan = -pan; } else aputype = APUTYPE_8BITSTEREO; } else { pan = 0; if (ch->qs16) aputype = APUTYPE_16BITLINEAR; else { aputype = APUTYPE_8BITLINEAR; speed >>= 1; } } if (ch->us) wcreg |= WAVCACHE_CHCTL_U8; if (wtbar > 8) wtbar = (wtbar >> 1) + 4; dv = (((speed % 48000) << 16) + 24000) / 48000 + ((speed / 48000) << 16); wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar, ch->dma.base >> WAVCACHE_BASEADDR_SHIFT); wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1, ch->dma.base >> WAVCACHE_BASEADDR_SHIFT); if (wtbar < 8) { wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2, ch->dma.base >> WAVCACHE_BASEADDR_SHIFT); wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3, ch->dma.base >> WAVCACHE_BASEADDR_SHIFT); } wc_wrchctl(ch->parent, apuch, wcreg); wc_wrchctl(ch->parent, apuch + 1, wcreg); apu_setparam(ch->parent, apuch, wpwa, size, pan, dv); if (ch->stereo) { if (ch->qs16) wpwa |= (WPWA_STEREO >> 1); apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv); /* XXX needed ? */ #if 0 critical_enter(); #endif wp_wrapu(ch->parent, apuch, APUREG_APUTYPE, (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE, (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); #if 0 critical_exit(); #endif } else { wp_wrapu(ch->parent, apuch, APUREG_APUTYPE, (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); } /* to mark that this channel is ready for intr. */ ch->parent->active |= (1 << ch->num); set_timer(ch->parent); wp_starttimer(ch->parent); } static void aggch_stop_dac(struct agg_chinfo *ch) { AGG_LOCK_ASSERT(ch->parent); /* to mark that this channel no longer needs further intrs. */ ch->parent->active &= ~(1 << ch->num); wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE, APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE, APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); if (ch->parent->active) { set_timer(ch->parent); wp_starttimer(ch->parent); } else wp_stoptimer(ch->parent); } static void aggch_start_adc(struct agg_rchinfo *ch) { bus_addr_t wpwa, wpwa2; u_int16_t wcreg, wcreg2; u_int dv; int pan; AGG_LOCK_ASSERT(ch->parent); /* speed > 48000 not cared */ dv = ((ch->speed << 16) + 24000) / 48000; /* RATECONV doesn't seem to like dv == 0x10000. */ if (dv == 0x10000) dv--; if (ch->stereo) { wpwa = (ch->srcphys - ch->dma.base) >> 1; wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->dma.base) >> 1; wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; wcreg2 = (ch->dma.base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; pan = PAN_LEFT - PAN_FRONT; } else { wpwa = (ch->dma.phys - ch->dma.base) >> 1; wpwa2 = (ch->srcphys - ch->dma.base) >> 1; wcreg = (ch->dma.phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; wcreg2 = (ch->dma.base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; pan = 0; } ch->hwptr = 0; /* Invalidate WaveCache. */ wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO); wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO); wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO); wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO); /* Load APU registers. */ /* APU #0 : Sample rate converter for left/center. */ apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa, ch->buflen >> ch->stereo, 0, dv); wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0); wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT); /* APU #1 : Sample rate converter for right. */ apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2, ch->buflen >> ch->stereo, 0, dv); wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0); wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT); /* APU #2 : Input mixer for left. */ apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0, ch->parent->bufsz >> 2, pan, 0x10000); wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0); wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0); wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT); /* APU #3 : Input mixer for right. */ apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2), ch->parent->bufsz >> 2, -pan, 0x10000); wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0); wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0); wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT); /* to mark this channel ready for intr. */ ch->parent->active |= (1 << ch->parent->playchns); /* start adc */ /* XXX needed? */ #if 0 critical_enter(); #endif wp_wrapu(ch->parent, 0, APUREG_APUTYPE, (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); wp_wrapu(ch->parent, 1, APUREG_APUTYPE, (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); wp_wrapu(ch->parent, 2, APUREG_APUTYPE, (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf); wp_wrapu(ch->parent, 3, APUREG_APUTYPE, (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf); #if 0 critical_exit(); #endif set_timer(ch->parent); wp_starttimer(ch->parent); } static void aggch_stop_adc(struct agg_rchinfo *ch) { int apuch; AGG_LOCK_ASSERT(ch->parent); /* to mark that this channel no longer needs further intrs. */ ch->parent->active &= ~(1 << ch->parent->playchns); for (apuch = 0; apuch < 4; apuch++) wp_wrapu(ch->parent, apuch, APUREG_APUTYPE, APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); if (ch->parent->active) { set_timer(ch->parent); wp_starttimer(ch->parent); } else wp_stoptimer(ch->parent); } /* * Feed from L/R channel of ADC to destination with stereo interleaving. * This function expects n not overwrapping the buffer boundary. * Note that n is measured in sample unit. * * XXX - this function works in 16bit stereo format only. */ static inline void interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n) { int16_t *end; for (end = l + n; l < end; ) { *p++ = *l++; *p++ = *r++; } } static void aggch_feed_adc_stereo(struct agg_rchinfo *ch) { unsigned cur, last; int16_t *src2; AGG_LOCK(ch->parent); cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR); AGG_UNLOCK(ch->parent); cur -= 0xffff & ((ch->srcphys - ch->dma.base) >> 1); last = ch->hwptr; src2 = ch->src + ch->parent->bufsz/4; if (cur < last) { interleave(ch->src + last, src2 + last, ch->sink + 2*last, ch->buflen/2 - last); interleave(ch->src, src2, ch->sink, cur); } else if (cur > last) interleave(ch->src + last, src2 + last, ch->sink + 2*last, cur - last); ch->hwptr = cur; } /* * Feed from R channel of ADC and mixdown to destination L/center. * This function expects n not overwrapping the buffer boundary. * Note that n is measured in sample unit. * * XXX - this function works in 16bit monoral format only. */ static inline void mixdown(int16_t *src, int16_t *dest, unsigned n) { int16_t *end; for (end = dest + n; dest < end; dest++) *dest = (int16_t)(((int)*dest - (int)*src++) / 2); } static void aggch_feed_adc_mono(struct agg_rchinfo *ch) { unsigned cur, last; AGG_LOCK(ch->parent); cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR); AGG_UNLOCK(ch->parent); cur -= 0xffff & ((ch->dma.phys - ch->dma.base) >> 1); last = ch->hwptr; if (cur < last) { mixdown(ch->src + last, ch->sink + last, ch->buflen - last); mixdown(ch->src, ch->sink, cur); } else if (cur > last) mixdown(ch->src + last, ch->sink + last, cur - last); ch->hwptr = cur; } /* * Stereo jitter suppressor. * Sometimes playback pointers differ in stereo-paired channels. * Calling this routine within intr fixes the problem. */ static inline void suppress_jitter(struct agg_chinfo *ch) { if (ch->stereo) { int cp1, cp2, diff /*, halfsize*/ ; /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/ cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR); cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR); if (cp1 != cp2) { diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1); if (diff > 1 /* && diff < halfsize*/ ) AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2); } } } static inline void suppress_rec_jitter(struct agg_rchinfo *ch) { int cp1, cp2, diff /*, halfsize*/ ; /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/ cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1) + wp_rdapu(ch->parent, 0, APUREG_CURPTR); cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR); if (cp1 != cp2) { diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1); if (diff > 1 /* && diff < halfsize*/ ) AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2); } } static inline u_int calc_timer_div(struct agg_chinfo *ch) { u_int speed; speed = ch->speed; if (speed == 0) { device_printf(ch->parent->dev, "pch[%d].speed == 0, which shouldn't\n", ch->num); speed = 1; } return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo)) + speed - 1) / speed; } static inline u_int calc_timer_div_rch(struct agg_rchinfo *ch) { u_int speed; speed = ch->speed; if (speed == 0) { device_printf(ch->parent->dev, "rch.speed == 0, which shouldn't\n"); speed = 1; } return (48000 * (ch->blklen << (!ch->stereo)) + speed - 1) / speed; } static void set_timer(struct agg_info *ess) { int i; u_int dv = 32 << 7, newdv; for (i = 0; i < ess->playchns; i++) if ((ess->active & (1 << i)) && (dv > (newdv = calc_timer_div(ess->pch + i)))) dv = newdv; if ((ess->active & (1 << i)) && (dv > (newdv = calc_timer_div_rch(&ess->rch)))) dv = newdv; wp_settimer(ess, dv); } /* ----------------------------- * Newpcm glue. */ /* AC97 mixer interface. */ static u_int32_t agg_ac97_init(kobj_t obj, void *sc) { struct agg_info *ess = sc; return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1; } static int agg_ac97_read(kobj_t obj, void *sc, int regno) { struct agg_info *ess = sc; return (agg_rdcodec(ess, regno)); } static int agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data) { struct agg_info *ess = sc; return (agg_wrcodec(ess, regno, data)); } static kobj_method_t agg_ac97_methods[] = { KOBJMETHOD(ac97_init, agg_ac97_init), KOBJMETHOD(ac97_read, agg_ac97_read), KOBJMETHOD(ac97_write, agg_ac97_write), { 0, 0 } }; AC97_DECLARE(agg_ac97); /* -------------------------------------------------------------------- */ /* Playback channel. */ static void * aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) { struct agg_info *ess = devinfo; struct agg_chinfo *ch; uint8_t *p; KASSERT((dir == PCMDIR_PLAY), ("aggpch_init() called for RECORDING channel!")); ch = ess->pch + ess->playchns; ch->parent = ess; ch->channel = c; ch->buffer = b; ch->num = ess->playchns; bzero(&ch->dma, sizeof(ch->dma)); ch->dma.dmat = ess->buf_dmat; ch->dma.size = ess->bufsz; p = dma_malloc(&ch->dma); if (p == NULL) return NULL; ch->dma.base = ch->dma.phys & ((~(bus_addr_t)0) <bufsz) != 0) { dma_free(&ch->dma); return NULL; } ch->blklen = sndbuf_getblksz(b) / 2; ch->buflen = sndbuf_getsize(b) / 2; ess->playchns++; return ch; } static void adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size) { struct agg_chinfo *pchs[AGG_MAXPLAYCH]; u_int i, j, k; bus_addr_t base; /* sort pchs by phys address */ for (i = 0; i < n; i++) { for (j = 0; j < i; j++) if (chans[i].dma.phys < pchs[j]->dma.phys) { for (k = i; k > j; k--) pchs[k] = pchs[k - 1]; break; } pchs[j] = chans + i; } /* use new base register if next buffer can not be addressed via current base. */ #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1) base = pchs[0]->dma.base; for (k = 1, i = 1; i < n; i++) { if (pchs[i]->dma.phys + size - base >= 1 << BASE_SHIFT) /* not addressable: assign new base */ base = (pchs[i]->dma.base -= k++ << BASE_SHIFT); else pchs[i]->dma.base = base; } #undef BASE_SHIFT if (bootverbose) { printf("Total of %d bases are assigned.\n", k); for (i = 0; i < n; i++) { printf("ch.%d: phys 0x%llx, wpwa 0x%llx\n", i, (long long)chans[i].dma.phys, (long long)(chans[i].dma.phys - chans[i].dma.base) >> 1); } } } static int aggpch_free(kobj_t obj, void *data) { struct agg_chinfo *ch = data; /* free up buffer - called after channel stopped */ dma_free(&ch->dma); /* return 0 if ok */ return 0; } static int aggpch_setformat(kobj_t obj, void *data, u_int32_t format) { struct agg_chinfo *ch = data; if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE) return EINVAL; ch->stereo = ch->qs16 = ch->us = 0; if (format & AFMT_STEREO) ch->stereo = 1; if (format & AFMT_U8 || format & AFMT_S8) { if (format & AFMT_U8) ch->us = 1; } else ch->qs16 = 1; return 0; } static int aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed) { return ((struct agg_chinfo*)data)->speed = speed; } static int aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) { struct agg_chinfo *ch = data; int blkcnt; /* try to keep at least 20msec DMA space */ blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize); RANGE(blkcnt, 2, ch->parent->bufsz / blocksize); if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) { sndbuf_resize(ch->buffer, blkcnt, blocksize); blkcnt = sndbuf_getblkcnt(ch->buffer); blocksize = sndbuf_getblksz(ch->buffer); } else { sndbuf_setblkcnt(ch->buffer, blkcnt); sndbuf_setblksz(ch->buffer, blocksize); } ch->blklen = blocksize / 2; ch->buflen = blkcnt * blocksize / 2; return blocksize; } static int aggpch_trigger(kobj_t obj, void *data, int go) { struct agg_chinfo *ch = data; switch (go) { case PCMTRIG_EMLDMAWR: break; case PCMTRIG_START: AGG_LOCK(ch->parent); aggch_start_dac(ch); AGG_UNLOCK(ch->parent); break; case PCMTRIG_ABORT: case PCMTRIG_STOP: AGG_LOCK(ch->parent); aggch_stop_dac(ch); AGG_UNLOCK(ch->parent); break; } return 0; } static int aggpch_getptr(kobj_t obj, void *data) { struct agg_chinfo *ch = data; u_int cp; AGG_LOCK(ch->parent); cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR); AGG_UNLOCK(ch->parent); return ch->qs16 && ch->stereo ? (cp << 2) - ((0xffff << 2) & (ch->dma.phys - ch->dma.base)) : (cp << 1) - ((0xffff << 1) & (ch->dma.phys - ch->dma.base)); } static struct pcmchan_caps * aggpch_getcaps(kobj_t obj, void *data) { static u_int32_t playfmt[] = { AFMT_U8, AFMT_STEREO | AFMT_U8, AFMT_S8, AFMT_STEREO | AFMT_S8, AFMT_S16_LE, AFMT_STEREO | AFMT_S16_LE, 0 }; static struct pcmchan_caps playcaps = {2000, 767999, playfmt, 0}; return &playcaps; } static kobj_method_t aggpch_methods[] = { KOBJMETHOD(channel_init, aggpch_init), KOBJMETHOD(channel_free, aggpch_free), KOBJMETHOD(channel_setformat, aggpch_setformat), KOBJMETHOD(channel_setspeed, aggpch_setspeed), KOBJMETHOD(channel_setblocksize, aggpch_setblocksize), KOBJMETHOD(channel_trigger, aggpch_trigger), KOBJMETHOD(channel_getptr, aggpch_getptr), KOBJMETHOD(channel_getcaps, aggpch_getcaps), { 0, 0 } }; CHANNEL_DECLARE(aggpch); /* -------------------------------------------------------------------- */ /* Recording channel. */ static void * aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) { struct agg_info *ess = devinfo; struct agg_rchinfo *ch; u_int8_t *p; KASSERT((dir == PCMDIR_REC), ("aggrch_init() called for PLAYBACK channel!")); ch = &ess->rch; ch->parent = ess; ch->channel = c; ch->buffer = b; bzero(&ch->dma, sizeof(ch->dma)); ch->dma.dmat = ess->stat_dmat; ch->dma.size = 3 * ess->bufsz; p = dma_malloc(&ch->dma); if (p == NULL) return NULL; /* Uses the bottom-half of the status buffer. */ p = ch->dma.vaddr + ess->bufsz; ch->dma.phys = ch->dma.phys + ess->bufsz; ch->dma.base = ch->dma.phys; ch->src = (int16_t *)(p + ess->bufsz); ch->srcphys = ch->dma.phys + ess->bufsz; ch->sink = (int16_t *)p; if (sndbuf_setup(b, p, ess->bufsz) != 0) { dma_free(&ch->dma); return NULL; } ch->blklen = sndbuf_getblksz(b) / 2; ch->buflen = sndbuf_getsize(b) / 2; return ch; } static int aggrch_free(kobj_t obj, void *data) { struct agg_chinfo *ch = data; dma_free(&ch->dma); return (0); } static int aggrch_setformat(kobj_t obj, void *data, u_int32_t format) { struct agg_rchinfo *ch = data; if (!(format & AFMT_S16_LE)) return EINVAL; if (format & AFMT_STEREO) ch->stereo = 1; else ch->stereo = 0; return 0; } static int aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed) { return ((struct agg_rchinfo*)data)->speed = speed; } static int aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) { struct agg_rchinfo *ch = data; int blkcnt; /* try to keep at least 20msec DMA space */ blkcnt = (ch->speed << ch->stereo) / (25 * blocksize); RANGE(blkcnt, 2, ch->parent->bufsz / blocksize); if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) { sndbuf_resize(ch->buffer, blkcnt, blocksize); blkcnt = sndbuf_getblkcnt(ch->buffer); blocksize = sndbuf_getblksz(ch->buffer); } else { sndbuf_setblkcnt(ch->buffer, blkcnt); sndbuf_setblksz(ch->buffer, blocksize); } ch->blklen = blocksize / 2; ch->buflen = blkcnt * blocksize / 2; return blocksize; } static int aggrch_trigger(kobj_t obj, void *sc, int go) { struct agg_rchinfo *ch = sc; switch (go) { case PCMTRIG_EMLDMARD: if (ch->stereo) aggch_feed_adc_stereo(ch); else aggch_feed_adc_mono(ch); break; case PCMTRIG_START: AGG_LOCK(ch->parent); aggch_start_adc(ch); AGG_UNLOCK(ch->parent); break; case PCMTRIG_ABORT: case PCMTRIG_STOP: AGG_LOCK(ch->parent); aggch_stop_adc(ch); AGG_UNLOCK(ch->parent); break; } return 0; } static int aggrch_getptr(kobj_t obj, void *sc) { struct agg_rchinfo *ch = sc; return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1; } static struct pcmchan_caps * aggrch_getcaps(kobj_t obj, void *sc) { static u_int32_t recfmt[] = { AFMT_S16_LE, AFMT_STEREO | AFMT_S16_LE, 0 }; static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0}; return &reccaps; } static kobj_method_t aggrch_methods[] = { KOBJMETHOD(channel_init, aggrch_init), KOBJMETHOD(channel_free, aggrch_free), KOBJMETHOD(channel_setformat, aggrch_setformat), KOBJMETHOD(channel_setspeed, aggrch_setspeed), KOBJMETHOD(channel_setblocksize, aggrch_setblocksize), KOBJMETHOD(channel_trigger, aggrch_trigger), KOBJMETHOD(channel_getptr, aggrch_getptr), KOBJMETHOD(channel_getcaps, aggrch_getcaps), { 0, 0 } }; CHANNEL_DECLARE(aggrch); /* ----------------------------- * Bus space. */ static void agg_intr(void *sc) { struct agg_info* ess = sc; u_int8_t status; int i; u_int m; AGG_LOCK(ess); status = AGG_RD(ess, PORT_HOSTINT_STAT, 1); if (!status) { AGG_UNLOCK(ess); return; } /* Acknowledge intr. */ AGG_WR(ess, PORT_HOSTINT_STAT, status, 1); if (status & HOSTINT_STAT_DSOUND) { AGG_WR(ess, PORT_INT_STAT, 1, 2); if ((ess->flags & AGG_JITTER_CORRECTION) != 0) { for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) { if (ess->active & m) suppress_jitter(ess->pch + i); } if (ess->active & m) suppress_rec_jitter(&ess->rch); } for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) { if (ess->active & m) { AGG_UNLOCK(ess); chn_intr(ess->pch[i].channel); AGG_LOCK(ess); } } if (ess->active & m) { AGG_UNLOCK(ess); chn_intr(ess->rch.channel); AGG_LOCK(ess); } } if (status & HOSTINT_STAT_HWVOL) { u_int8_t event; event = AGG_RD(ess, PORT_HWVOL_MASTER, 1); AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1); switch (event) { case HWVOL_UP: mixer_hwvol_step(ess->dev, 1, 1); break; case HWVOL_DOWN: mixer_hwvol_step(ess->dev, -1, -1); break; case HWVOL_NOP: break; default: if (event & HWVOL_MUTE) { mixer_hwvol_mute(ess->dev); break; } device_printf(ess->dev, "unknown HWVOL event 0x%x\n", event); } } AGG_UNLOCK(ess); } static void setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error) { if (error != 0) return; *(bus_addr_t *)arg = segs[0].ds_addr; if (bootverbose) { printf("setmap (%lx, %lx), nseg=%d, error=%d\n", (u_long)segs[0].ds_addr, (u_long)segs[0].ds_len, nseg, error); } } static void * dma_malloc(struct agg_dma *dma) { int error; error = bus_dmamem_alloc(dma->dmat, (void **)&dma->vaddr, BUS_DMA_NOWAIT, &dma->dmam); if (error != 0) return NULL; dma->phys = 0; error = bus_dmamap_load(dma->dmat, dma->dmam, dma->vaddr, dma->size, setmap, &dma->phys, 0); if (error != 0 || dma->phys == 0) { bus_dmamem_free(dma->dmat, dma->vaddr, dma->dmam); dma->vaddr = NULL; dma->dmam = NULL; } return dma->vaddr; } static void dma_free(struct agg_dma *dma) { if (dma->dmam) bus_dmamap_unload(dma->dmat, dma->dmam); if (dma->dmam && dma->vaddr) bus_dmamem_free(dma->dmat, dma->vaddr, dma->dmam); dma->vaddr = NULL; dma->dmam = NULL; } static int agg_probe(device_t dev) { char *s = NULL; switch (pci_get_devid(dev)) { case MAESTRO_1_PCI_ID: s = "ESS Technology Maestro-1"; break; case MAESTRO_2_PCI_ID: s = "ESS Technology Maestro-2"; break; case MAESTRO_2E_PCI_ID: s = "ESS Technology Maestro-2E"; break; } if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) { device_set_desc(dev, s); return BUS_PROBE_DEFAULT; } return ENXIO; } static int agg_attach(device_t dev) { struct agg_info *ess; u_int32_t data; char status[SND_STATUSLEN]; int hint, ret = 0; if ((ess = malloc(sizeof *ess, M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { device_printf(dev, "cannot allocate softc\n"); ret = ENOMEM; goto bad; } ess->dev = dev; ess->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); if (ess->lock == NULL) { device_printf(dev, "failed to create a mutex.\n"); ret = ENOMEM; goto bad; } ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536); if (bus_dma_tag_create(/*parent*/ NULL, /*align */ 4, 1 << (16+1), /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR, /*filter*/ NULL, NULL, /*size */ ess->bufsz, 1, 0x3ffff, /*flags */ 0, /*lock */ NULL, NULL, &ess->buf_dmat) != 0) { device_printf(dev, "unable to create dma tag\n"); ret = ENOMEM; goto bad; } if (bus_dma_tag_create(/*parent*/NULL, /*align */ 1 << WAVCACHE_BASEADDR_SHIFT, 1 << (16+1), /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR, /*filter*/ NULL, NULL, /*size */ 3*ess->bufsz, 1, 0x3ffff, /*flags */ 0, /*lock */ NULL, NULL, &ess->stat_dmat) != 0) { device_printf(dev, "unable to create dma tag\n"); ret = ENOMEM; goto bad; } pci_enable_busmaster(dev); data = pci_read_config(dev, PCIR_COMMAND, 2); data |= PCIM_CMD_PORTEN; pci_write_config(dev, PCIR_COMMAND, data, 2); data = pci_read_config(dev, PCIR_COMMAND, 2); /* Allocate resources. */ ess->regid = PCIR_BAR(0); if (data & PCIM_CMD_PORTEN) ess->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &ess->regid, RF_ACTIVE); if (ess->reg == NULL) { device_printf(dev, "unable to map register space\n"); ret = ENXIO; goto bad; } ess->st = rman_get_bustag(ess->reg); ess->sh = rman_get_bushandle(ess->reg); ess->irqid = 0; ess->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &ess->irqid, RF_ACTIVE | RF_SHAREABLE); if (ess->irq == NULL) { device_printf(dev, "unable to map interrupt\n"); ret = ENXIO; goto bad; } /* Setup resources. */ if (snd_setup_intr(dev, ess->irq, INTR_MPSAFE, agg_intr, ess, &ess->ih)) { device_printf(dev, "unable to setup interrupt\n"); ret = ENXIO; goto bad; } AGG_LOCK(ess); agg_init(ess); AGG_UNLOCK(ess); if (resource_int_value(device_get_name(dev), device_get_unit(dev), "jitter_correction", &hint) == 0) ess->flags |= (hint > 0) ? AGG_JITTER_CORRECTION : 0; if (agg_rdcodec(ess, 0) == 0x80) { /* XXX - TODO: PT101 */ device_printf(dev, "PT101 codec detected!\n"); ret = ENXIO; goto bad; } ess->codec = AC97_CREATE(dev, ess, agg_ac97); if (ess->codec == NULL) { device_printf(dev, "failed to create AC97 codec softc!\n"); ret = ENOMEM; goto bad; } if (mixer_init(dev, ac97_getmixerclass(), ess->codec) == -1) { device_printf(dev, "mixer initialization failed!\n"); ret = ENXIO; goto bad; } ret = pcm_register(dev, ess, AGG_MAXPLAYCH, 1); if (ret) goto bad; mixer_hwvol_init(dev); for (data = 0; data < AGG_MAXPLAYCH; data++) pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess); pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess); adjust_pchbase(ess->pch, ess->playchns, ess->bufsz); snprintf(status, SND_STATUSLEN, "port 0x%lx-0x%lx irq %ld at device %d.%d on pci%d", rman_get_start(ess->reg), rman_get_end(ess->reg), rman_get_start(ess->irq), pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev)); pcm_setstatus(dev, status); return 0; bad: if (ess->codec != NULL) ac97_destroy(ess->codec); if (ess->ih != NULL) bus_teardown_intr(dev, ess->irq, ess->ih); if (ess->irq != NULL) bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq); if (ess->reg != NULL) bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg); if (ess->stat_dmat != NULL) bus_dma_tag_destroy(ess->stat_dmat); if (ess->buf_dmat != NULL) bus_dma_tag_destroy(ess->buf_dmat); if (ess->lock) snd_mtxfree(ess->lock); if (ess != NULL) free(ess, M_DEVBUF); return ret; } static int agg_detach(device_t dev) { struct agg_info *ess = pcm_getdevinfo(dev); int r; AGG_LOCK(ess); if (ess->active) { AGG_UNLOCK(ess); return EBUSY; } AGG_UNLOCK(ess); r = pcm_unregister(dev); if (r) return r; /* disable interrupts and power down */ AGG_LOCK(ess); AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2); agg_power(ess, PCI_POWERSTATE_D3); AGG_UNLOCK(ess); bus_teardown_intr(dev, ess->irq, ess->ih); bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq); bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg); bus_dma_tag_destroy(ess->stat_dmat); bus_dma_tag_destroy(ess->buf_dmat); snd_mtxfree(ess->lock); free(ess, M_DEVBUF); return 0; } static int agg_suspend(device_t dev) { struct agg_info *ess; ess = pcm_getdevinfo(dev); AGG_LOCK(ess); AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2); agg_power(ess, PCI_POWERSTATE_D3); AGG_UNLOCK(ess); return 0; } static int agg_resume(device_t dev) { struct agg_info *ess; int i; ess = pcm_getdevinfo(dev); AGG_LOCK(ess); agg_power(ess, PCI_POWERSTATE_D0); agg_init(ess); if (mixer_reinit(dev)) device_printf(dev, "unable to reinitialize the mixer\n"); for (i = 0; i < ess->playchns; i++) if (ess->active & (1 << i)) aggch_start_dac(ess->pch + i); if (ess->active & (i << i)) aggch_start_adc(&ess->rch); AGG_UNLOCK(ess); return 0; } static int agg_shutdown(device_t dev) { struct agg_info *ess = pcm_getdevinfo(dev); AGG_LOCK(ess); AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2); agg_power(ess, PCI_POWERSTATE_D3); AGG_UNLOCK(ess); return 0; } static device_method_t agg_methods[] = { DEVMETHOD(device_probe, agg_probe), DEVMETHOD(device_attach, agg_attach), DEVMETHOD(device_detach, agg_detach), DEVMETHOD(device_suspend, agg_suspend), DEVMETHOD(device_resume, agg_resume), DEVMETHOD(device_shutdown, agg_shutdown), { 0, 0 } }; static driver_t agg_driver = { "pcm", agg_methods, PCM_SOFTC_SIZE, }; /*static devclass_t pcm_devclass;*/ DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0); MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); MODULE_VERSION(snd_maestro, 1);